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ipv6: use ip6_flowinfo helper
[deliverable/linux.git] / drivers / net / ethernet / mellanox / mlx4 / en_rx.c
1 /*
2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 *
32 */
33
34 #include <net/busy_poll.h>
35 #include <linux/mlx4/cq.h>
36 #include <linux/slab.h>
37 #include <linux/mlx4/qp.h>
38 #include <linux/skbuff.h>
39 #include <linux/rculist.h>
40 #include <linux/if_ether.h>
41 #include <linux/if_vlan.h>
42 #include <linux/vmalloc.h>
43
44 #include "mlx4_en.h"
45
46 static int mlx4_alloc_pages(struct mlx4_en_priv *priv,
47 struct mlx4_en_rx_alloc *page_alloc,
48 const struct mlx4_en_frag_info *frag_info,
49 gfp_t _gfp)
50 {
51 int order;
52 struct page *page;
53 dma_addr_t dma;
54
55 for (order = MLX4_EN_ALLOC_PREFER_ORDER; ;) {
56 gfp_t gfp = _gfp;
57
58 if (order)
59 gfp |= __GFP_COMP | __GFP_NOWARN;
60 page = alloc_pages(gfp, order);
61 if (likely(page))
62 break;
63 if (--order < 0 ||
64 ((PAGE_SIZE << order) < frag_info->frag_size))
65 return -ENOMEM;
66 }
67 dma = dma_map_page(priv->ddev, page, 0, PAGE_SIZE << order,
68 PCI_DMA_FROMDEVICE);
69 if (dma_mapping_error(priv->ddev, dma)) {
70 put_page(page);
71 return -ENOMEM;
72 }
73 page_alloc->page_size = PAGE_SIZE << order;
74 page_alloc->page = page;
75 page_alloc->dma = dma;
76 page_alloc->page_offset = frag_info->frag_align;
77 /* Not doing get_page() for each frag is a big win
78 * on asymetric workloads.
79 */
80 atomic_set(&page->_count,
81 page_alloc->page_size / frag_info->frag_stride);
82 return 0;
83 }
84
85 static int mlx4_en_alloc_frags(struct mlx4_en_priv *priv,
86 struct mlx4_en_rx_desc *rx_desc,
87 struct mlx4_en_rx_alloc *frags,
88 struct mlx4_en_rx_alloc *ring_alloc,
89 gfp_t gfp)
90 {
91 struct mlx4_en_rx_alloc page_alloc[MLX4_EN_MAX_RX_FRAGS];
92 const struct mlx4_en_frag_info *frag_info;
93 struct page *page;
94 dma_addr_t dma;
95 int i;
96
97 for (i = 0; i < priv->num_frags; i++) {
98 frag_info = &priv->frag_info[i];
99 page_alloc[i] = ring_alloc[i];
100 page_alloc[i].page_offset += frag_info->frag_stride;
101
102 if (page_alloc[i].page_offset + frag_info->frag_stride <=
103 ring_alloc[i].page_size)
104 continue;
105
106 if (mlx4_alloc_pages(priv, &page_alloc[i], frag_info, gfp))
107 goto out;
108 }
109
110 for (i = 0; i < priv->num_frags; i++) {
111 frags[i] = ring_alloc[i];
112 dma = ring_alloc[i].dma + ring_alloc[i].page_offset;
113 ring_alloc[i] = page_alloc[i];
114 rx_desc->data[i].addr = cpu_to_be64(dma);
115 }
116
117 return 0;
118
119 out:
120 while (i--) {
121 frag_info = &priv->frag_info[i];
122 if (page_alloc[i].page != ring_alloc[i].page) {
123 dma_unmap_page(priv->ddev, page_alloc[i].dma,
124 page_alloc[i].page_size, PCI_DMA_FROMDEVICE);
125 page = page_alloc[i].page;
126 atomic_set(&page->_count, 1);
127 put_page(page);
128 }
129 }
130 return -ENOMEM;
131 }
132
133 static void mlx4_en_free_frag(struct mlx4_en_priv *priv,
134 struct mlx4_en_rx_alloc *frags,
135 int i)
136 {
137 const struct mlx4_en_frag_info *frag_info = &priv->frag_info[i];
138 u32 next_frag_end = frags[i].page_offset + 2 * frag_info->frag_stride;
139
140
141 if (next_frag_end > frags[i].page_size)
142 dma_unmap_page(priv->ddev, frags[i].dma, frags[i].page_size,
143 PCI_DMA_FROMDEVICE);
144
145 if (frags[i].page)
146 put_page(frags[i].page);
147 }
148
149 static int mlx4_en_init_allocator(struct mlx4_en_priv *priv,
150 struct mlx4_en_rx_ring *ring)
151 {
152 int i;
153 struct mlx4_en_rx_alloc *page_alloc;
154
155 for (i = 0; i < priv->num_frags; i++) {
156 const struct mlx4_en_frag_info *frag_info = &priv->frag_info[i];
157
158 if (mlx4_alloc_pages(priv, &ring->page_alloc[i],
159 frag_info, GFP_KERNEL))
160 goto out;
161 }
162 return 0;
163
164 out:
165 while (i--) {
166 struct page *page;
167
168 page_alloc = &ring->page_alloc[i];
169 dma_unmap_page(priv->ddev, page_alloc->dma,
170 page_alloc->page_size, PCI_DMA_FROMDEVICE);
171 page = page_alloc->page;
172 atomic_set(&page->_count, 1);
173 put_page(page);
174 page_alloc->page = NULL;
175 }
176 return -ENOMEM;
177 }
178
179 static void mlx4_en_destroy_allocator(struct mlx4_en_priv *priv,
180 struct mlx4_en_rx_ring *ring)
181 {
182 struct mlx4_en_rx_alloc *page_alloc;
183 int i;
184
185 for (i = 0; i < priv->num_frags; i++) {
186 const struct mlx4_en_frag_info *frag_info = &priv->frag_info[i];
187
188 page_alloc = &ring->page_alloc[i];
189 en_dbg(DRV, priv, "Freeing allocator:%d count:%d\n",
190 i, page_count(page_alloc->page));
191
192 dma_unmap_page(priv->ddev, page_alloc->dma,
193 page_alloc->page_size, PCI_DMA_FROMDEVICE);
194 while (page_alloc->page_offset + frag_info->frag_stride <
195 page_alloc->page_size) {
196 put_page(page_alloc->page);
197 page_alloc->page_offset += frag_info->frag_stride;
198 }
199 page_alloc->page = NULL;
200 }
201 }
202
203 static void mlx4_en_init_rx_desc(struct mlx4_en_priv *priv,
204 struct mlx4_en_rx_ring *ring, int index)
205 {
206 struct mlx4_en_rx_desc *rx_desc = ring->buf + ring->stride * index;
207 int possible_frags;
208 int i;
209
210 /* Set size and memtype fields */
211 for (i = 0; i < priv->num_frags; i++) {
212 rx_desc->data[i].byte_count =
213 cpu_to_be32(priv->frag_info[i].frag_size);
214 rx_desc->data[i].lkey = cpu_to_be32(priv->mdev->mr.key);
215 }
216
217 /* If the number of used fragments does not fill up the ring stride,
218 * remaining (unused) fragments must be padded with null address/size
219 * and a special memory key */
220 possible_frags = (ring->stride - sizeof(struct mlx4_en_rx_desc)) / DS_SIZE;
221 for (i = priv->num_frags; i < possible_frags; i++) {
222 rx_desc->data[i].byte_count = 0;
223 rx_desc->data[i].lkey = cpu_to_be32(MLX4_EN_MEMTYPE_PAD);
224 rx_desc->data[i].addr = 0;
225 }
226 }
227
228 static int mlx4_en_prepare_rx_desc(struct mlx4_en_priv *priv,
229 struct mlx4_en_rx_ring *ring, int index,
230 gfp_t gfp)
231 {
232 struct mlx4_en_rx_desc *rx_desc = ring->buf + (index * ring->stride);
233 struct mlx4_en_rx_alloc *frags = ring->rx_info +
234 (index << priv->log_rx_info);
235
236 return mlx4_en_alloc_frags(priv, rx_desc, frags, ring->page_alloc, gfp);
237 }
238
239 static inline void mlx4_en_update_rx_prod_db(struct mlx4_en_rx_ring *ring)
240 {
241 *ring->wqres.db.db = cpu_to_be32(ring->prod & 0xffff);
242 }
243
244 static void mlx4_en_free_rx_desc(struct mlx4_en_priv *priv,
245 struct mlx4_en_rx_ring *ring,
246 int index)
247 {
248 struct mlx4_en_rx_alloc *frags;
249 int nr;
250
251 frags = ring->rx_info + (index << priv->log_rx_info);
252 for (nr = 0; nr < priv->num_frags; nr++) {
253 en_dbg(DRV, priv, "Freeing fragment:%d\n", nr);
254 mlx4_en_free_frag(priv, frags, nr);
255 }
256 }
257
258 static int mlx4_en_fill_rx_buffers(struct mlx4_en_priv *priv)
259 {
260 struct mlx4_en_rx_ring *ring;
261 int ring_ind;
262 int buf_ind;
263 int new_size;
264
265 for (buf_ind = 0; buf_ind < priv->prof->rx_ring_size; buf_ind++) {
266 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
267 ring = priv->rx_ring[ring_ind];
268
269 if (mlx4_en_prepare_rx_desc(priv, ring,
270 ring->actual_size,
271 GFP_KERNEL)) {
272 if (ring->actual_size < MLX4_EN_MIN_RX_SIZE) {
273 en_err(priv, "Failed to allocate "
274 "enough rx buffers\n");
275 return -ENOMEM;
276 } else {
277 new_size = rounddown_pow_of_two(ring->actual_size);
278 en_warn(priv, "Only %d buffers allocated "
279 "reducing ring size to %d",
280 ring->actual_size, new_size);
281 goto reduce_rings;
282 }
283 }
284 ring->actual_size++;
285 ring->prod++;
286 }
287 }
288 return 0;
289
290 reduce_rings:
291 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
292 ring = priv->rx_ring[ring_ind];
293 while (ring->actual_size > new_size) {
294 ring->actual_size--;
295 ring->prod--;
296 mlx4_en_free_rx_desc(priv, ring, ring->actual_size);
297 }
298 }
299
300 return 0;
301 }
302
303 static void mlx4_en_free_rx_buf(struct mlx4_en_priv *priv,
304 struct mlx4_en_rx_ring *ring)
305 {
306 int index;
307
308 en_dbg(DRV, priv, "Freeing Rx buf - cons:%d prod:%d\n",
309 ring->cons, ring->prod);
310
311 /* Unmap and free Rx buffers */
312 BUG_ON((u32) (ring->prod - ring->cons) > ring->actual_size);
313 while (ring->cons != ring->prod) {
314 index = ring->cons & ring->size_mask;
315 en_dbg(DRV, priv, "Processing descriptor:%d\n", index);
316 mlx4_en_free_rx_desc(priv, ring, index);
317 ++ring->cons;
318 }
319 }
320
321 int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv,
322 struct mlx4_en_rx_ring **pring,
323 u32 size, u16 stride, int node)
324 {
325 struct mlx4_en_dev *mdev = priv->mdev;
326 struct mlx4_en_rx_ring *ring;
327 int err = -ENOMEM;
328 int tmp;
329
330 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, node);
331 if (!ring) {
332 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
333 if (!ring) {
334 en_err(priv, "Failed to allocate RX ring structure\n");
335 return -ENOMEM;
336 }
337 }
338
339 ring->prod = 0;
340 ring->cons = 0;
341 ring->size = size;
342 ring->size_mask = size - 1;
343 ring->stride = stride;
344 ring->log_stride = ffs(ring->stride) - 1;
345 ring->buf_size = ring->size * ring->stride + TXBB_SIZE;
346
347 tmp = size * roundup_pow_of_two(MLX4_EN_MAX_RX_FRAGS *
348 sizeof(struct mlx4_en_rx_alloc));
349 ring->rx_info = vmalloc_node(tmp, node);
350 if (!ring->rx_info) {
351 ring->rx_info = vmalloc(tmp);
352 if (!ring->rx_info) {
353 err = -ENOMEM;
354 goto err_ring;
355 }
356 }
357
358 en_dbg(DRV, priv, "Allocated rx_info ring at addr:%p size:%d\n",
359 ring->rx_info, tmp);
360
361 /* Allocate HW buffers on provided NUMA node */
362 set_dev_node(&mdev->dev->pdev->dev, node);
363 err = mlx4_alloc_hwq_res(mdev->dev, &ring->wqres,
364 ring->buf_size, 2 * PAGE_SIZE);
365 set_dev_node(&mdev->dev->pdev->dev, mdev->dev->numa_node);
366 if (err)
367 goto err_info;
368
369 err = mlx4_en_map_buffer(&ring->wqres.buf);
370 if (err) {
371 en_err(priv, "Failed to map RX buffer\n");
372 goto err_hwq;
373 }
374 ring->buf = ring->wqres.buf.direct.buf;
375
376 ring->hwtstamp_rx_filter = priv->hwtstamp_config.rx_filter;
377
378 *pring = ring;
379 return 0;
380
381 err_hwq:
382 mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size);
383 err_info:
384 vfree(ring->rx_info);
385 ring->rx_info = NULL;
386 err_ring:
387 kfree(ring);
388 *pring = NULL;
389
390 return err;
391 }
392
393 int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv)
394 {
395 struct mlx4_en_rx_ring *ring;
396 int i;
397 int ring_ind;
398 int err;
399 int stride = roundup_pow_of_two(sizeof(struct mlx4_en_rx_desc) +
400 DS_SIZE * priv->num_frags);
401
402 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
403 ring = priv->rx_ring[ring_ind];
404
405 ring->prod = 0;
406 ring->cons = 0;
407 ring->actual_size = 0;
408 ring->cqn = priv->rx_cq[ring_ind]->mcq.cqn;
409
410 ring->stride = stride;
411 if (ring->stride <= TXBB_SIZE)
412 ring->buf += TXBB_SIZE;
413
414 ring->log_stride = ffs(ring->stride) - 1;
415 ring->buf_size = ring->size * ring->stride;
416
417 memset(ring->buf, 0, ring->buf_size);
418 mlx4_en_update_rx_prod_db(ring);
419
420 /* Initialize all descriptors */
421 for (i = 0; i < ring->size; i++)
422 mlx4_en_init_rx_desc(priv, ring, i);
423
424 /* Initialize page allocators */
425 err = mlx4_en_init_allocator(priv, ring);
426 if (err) {
427 en_err(priv, "Failed initializing ring allocator\n");
428 if (ring->stride <= TXBB_SIZE)
429 ring->buf -= TXBB_SIZE;
430 ring_ind--;
431 goto err_allocator;
432 }
433 }
434 err = mlx4_en_fill_rx_buffers(priv);
435 if (err)
436 goto err_buffers;
437
438 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
439 ring = priv->rx_ring[ring_ind];
440
441 ring->size_mask = ring->actual_size - 1;
442 mlx4_en_update_rx_prod_db(ring);
443 }
444
445 return 0;
446
447 err_buffers:
448 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++)
449 mlx4_en_free_rx_buf(priv, priv->rx_ring[ring_ind]);
450
451 ring_ind = priv->rx_ring_num - 1;
452 err_allocator:
453 while (ring_ind >= 0) {
454 if (priv->rx_ring[ring_ind]->stride <= TXBB_SIZE)
455 priv->rx_ring[ring_ind]->buf -= TXBB_SIZE;
456 mlx4_en_destroy_allocator(priv, priv->rx_ring[ring_ind]);
457 ring_ind--;
458 }
459 return err;
460 }
461
462 void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv,
463 struct mlx4_en_rx_ring **pring,
464 u32 size, u16 stride)
465 {
466 struct mlx4_en_dev *mdev = priv->mdev;
467 struct mlx4_en_rx_ring *ring = *pring;
468
469 mlx4_en_unmap_buffer(&ring->wqres.buf);
470 mlx4_free_hwq_res(mdev->dev, &ring->wqres, size * stride + TXBB_SIZE);
471 vfree(ring->rx_info);
472 ring->rx_info = NULL;
473 kfree(ring);
474 *pring = NULL;
475 #ifdef CONFIG_RFS_ACCEL
476 mlx4_en_cleanup_filters(priv);
477 #endif
478 }
479
480 void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv,
481 struct mlx4_en_rx_ring *ring)
482 {
483 mlx4_en_free_rx_buf(priv, ring);
484 if (ring->stride <= TXBB_SIZE)
485 ring->buf -= TXBB_SIZE;
486 mlx4_en_destroy_allocator(priv, ring);
487 }
488
489
490 static int mlx4_en_complete_rx_desc(struct mlx4_en_priv *priv,
491 struct mlx4_en_rx_desc *rx_desc,
492 struct mlx4_en_rx_alloc *frags,
493 struct sk_buff *skb,
494 int length)
495 {
496 struct skb_frag_struct *skb_frags_rx = skb_shinfo(skb)->frags;
497 struct mlx4_en_frag_info *frag_info;
498 int nr;
499 dma_addr_t dma;
500
501 /* Collect used fragments while replacing them in the HW descriptors */
502 for (nr = 0; nr < priv->num_frags; nr++) {
503 frag_info = &priv->frag_info[nr];
504 if (length <= frag_info->frag_prefix_size)
505 break;
506 if (!frags[nr].page)
507 goto fail;
508
509 dma = be64_to_cpu(rx_desc->data[nr].addr);
510 dma_sync_single_for_cpu(priv->ddev, dma, frag_info->frag_size,
511 DMA_FROM_DEVICE);
512
513 /* Save page reference in skb */
514 __skb_frag_set_page(&skb_frags_rx[nr], frags[nr].page);
515 skb_frag_size_set(&skb_frags_rx[nr], frag_info->frag_size);
516 skb_frags_rx[nr].page_offset = frags[nr].page_offset;
517 skb->truesize += frag_info->frag_stride;
518 frags[nr].page = NULL;
519 }
520 /* Adjust size of last fragment to match actual length */
521 if (nr > 0)
522 skb_frag_size_set(&skb_frags_rx[nr - 1],
523 length - priv->frag_info[nr - 1].frag_prefix_size);
524 return nr;
525
526 fail:
527 while (nr > 0) {
528 nr--;
529 __skb_frag_unref(&skb_frags_rx[nr]);
530 }
531 return 0;
532 }
533
534
535 static struct sk_buff *mlx4_en_rx_skb(struct mlx4_en_priv *priv,
536 struct mlx4_en_rx_desc *rx_desc,
537 struct mlx4_en_rx_alloc *frags,
538 unsigned int length)
539 {
540 struct sk_buff *skb;
541 void *va;
542 int used_frags;
543 dma_addr_t dma;
544
545 skb = netdev_alloc_skb(priv->dev, SMALL_PACKET_SIZE + NET_IP_ALIGN);
546 if (!skb) {
547 en_dbg(RX_ERR, priv, "Failed allocating skb\n");
548 return NULL;
549 }
550 skb_reserve(skb, NET_IP_ALIGN);
551 skb->len = length;
552
553 /* Get pointer to first fragment so we could copy the headers into the
554 * (linear part of the) skb */
555 va = page_address(frags[0].page) + frags[0].page_offset;
556
557 if (length <= SMALL_PACKET_SIZE) {
558 /* We are copying all relevant data to the skb - temporarily
559 * sync buffers for the copy */
560 dma = be64_to_cpu(rx_desc->data[0].addr);
561 dma_sync_single_for_cpu(priv->ddev, dma, length,
562 DMA_FROM_DEVICE);
563 skb_copy_to_linear_data(skb, va, length);
564 skb->tail += length;
565 } else {
566 /* Move relevant fragments to skb */
567 used_frags = mlx4_en_complete_rx_desc(priv, rx_desc, frags,
568 skb, length);
569 if (unlikely(!used_frags)) {
570 kfree_skb(skb);
571 return NULL;
572 }
573 skb_shinfo(skb)->nr_frags = used_frags;
574
575 /* Copy headers into the skb linear buffer */
576 memcpy(skb->data, va, HEADER_COPY_SIZE);
577 skb->tail += HEADER_COPY_SIZE;
578
579 /* Skip headers in first fragment */
580 skb_shinfo(skb)->frags[0].page_offset += HEADER_COPY_SIZE;
581
582 /* Adjust size of first fragment */
583 skb_frag_size_sub(&skb_shinfo(skb)->frags[0], HEADER_COPY_SIZE);
584 skb->data_len = length - HEADER_COPY_SIZE;
585 }
586 return skb;
587 }
588
589 static void validate_loopback(struct mlx4_en_priv *priv, struct sk_buff *skb)
590 {
591 int i;
592 int offset = ETH_HLEN;
593
594 for (i = 0; i < MLX4_LOOPBACK_TEST_PAYLOAD; i++, offset++) {
595 if (*(skb->data + offset) != (unsigned char) (i & 0xff))
596 goto out_loopback;
597 }
598 /* Loopback found */
599 priv->loopback_ok = 1;
600
601 out_loopback:
602 dev_kfree_skb_any(skb);
603 }
604
605 static void mlx4_en_refill_rx_buffers(struct mlx4_en_priv *priv,
606 struct mlx4_en_rx_ring *ring)
607 {
608 int index = ring->prod & ring->size_mask;
609
610 while ((u32) (ring->prod - ring->cons) < ring->actual_size) {
611 if (mlx4_en_prepare_rx_desc(priv, ring, index, GFP_ATOMIC))
612 break;
613 ring->prod++;
614 index = ring->prod & ring->size_mask;
615 }
616 }
617
618 int mlx4_en_process_rx_cq(struct net_device *dev, struct mlx4_en_cq *cq, int budget)
619 {
620 struct mlx4_en_priv *priv = netdev_priv(dev);
621 struct mlx4_en_dev *mdev = priv->mdev;
622 struct mlx4_cqe *cqe;
623 struct mlx4_en_rx_ring *ring = priv->rx_ring[cq->ring];
624 struct mlx4_en_rx_alloc *frags;
625 struct mlx4_en_rx_desc *rx_desc;
626 struct sk_buff *skb;
627 int index;
628 int nr;
629 unsigned int length;
630 int polled = 0;
631 int ip_summed;
632 int factor = priv->cqe_factor;
633 u64 timestamp;
634
635 if (!priv->port_up)
636 return 0;
637
638 /* We assume a 1:1 mapping between CQEs and Rx descriptors, so Rx
639 * descriptor offset can be deduced from the CQE index instead of
640 * reading 'cqe->index' */
641 index = cq->mcq.cons_index & ring->size_mask;
642 cqe = &cq->buf[(index << factor) + factor];
643
644 /* Process all completed CQEs */
645 while (XNOR(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK,
646 cq->mcq.cons_index & cq->size)) {
647
648 frags = ring->rx_info + (index << priv->log_rx_info);
649 rx_desc = ring->buf + (index << ring->log_stride);
650
651 /*
652 * make sure we read the CQE after we read the ownership bit
653 */
654 rmb();
655
656 /* Drop packet on bad receive or bad checksum */
657 if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) ==
658 MLX4_CQE_OPCODE_ERROR)) {
659 en_err(priv, "CQE completed in error - vendor "
660 "syndrom:%d syndrom:%d\n",
661 ((struct mlx4_err_cqe *) cqe)->vendor_err_syndrome,
662 ((struct mlx4_err_cqe *) cqe)->syndrome);
663 goto next;
664 }
665 if (unlikely(cqe->badfcs_enc & MLX4_CQE_BAD_FCS)) {
666 en_dbg(RX_ERR, priv, "Accepted frame with bad FCS\n");
667 goto next;
668 }
669
670 /* Check if we need to drop the packet if SRIOV is not enabled
671 * and not performing the selftest or flb disabled
672 */
673 if (priv->flags & MLX4_EN_FLAG_RX_FILTER_NEEDED) {
674 struct ethhdr *ethh;
675 dma_addr_t dma;
676 /* Get pointer to first fragment since we haven't
677 * skb yet and cast it to ethhdr struct
678 */
679 dma = be64_to_cpu(rx_desc->data[0].addr);
680 dma_sync_single_for_cpu(priv->ddev, dma, sizeof(*ethh),
681 DMA_FROM_DEVICE);
682 ethh = (struct ethhdr *)(page_address(frags[0].page) +
683 frags[0].page_offset);
684
685 if (is_multicast_ether_addr(ethh->h_dest)) {
686 struct mlx4_mac_entry *entry;
687 struct hlist_head *bucket;
688 unsigned int mac_hash;
689
690 /* Drop the packet, since HW loopback-ed it */
691 mac_hash = ethh->h_source[MLX4_EN_MAC_HASH_IDX];
692 bucket = &priv->mac_hash[mac_hash];
693 rcu_read_lock();
694 hlist_for_each_entry_rcu(entry, bucket, hlist) {
695 if (ether_addr_equal_64bits(entry->mac,
696 ethh->h_source)) {
697 rcu_read_unlock();
698 goto next;
699 }
700 }
701 rcu_read_unlock();
702 }
703 }
704
705 /*
706 * Packet is OK - process it.
707 */
708 length = be32_to_cpu(cqe->byte_cnt);
709 length -= ring->fcs_del;
710 ring->bytes += length;
711 ring->packets++;
712
713 if (likely(dev->features & NETIF_F_RXCSUM)) {
714 if ((cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPOK)) &&
715 (cqe->checksum == cpu_to_be16(0xffff))) {
716 ring->csum_ok++;
717 /* This packet is eligible for GRO if it is:
718 * - DIX Ethernet (type interpretation)
719 * - TCP/IP (v4)
720 * - without IP options
721 * - not an IP fragment
722 * - no LLS polling in progress
723 */
724 if (!mlx4_en_cq_ll_polling(cq) &&
725 (dev->features & NETIF_F_GRO)) {
726 struct sk_buff *gro_skb = napi_get_frags(&cq->napi);
727 if (!gro_skb)
728 goto next;
729
730 nr = mlx4_en_complete_rx_desc(priv,
731 rx_desc, frags, gro_skb,
732 length);
733 if (!nr)
734 goto next;
735
736 skb_shinfo(gro_skb)->nr_frags = nr;
737 gro_skb->len = length;
738 gro_skb->data_len = length;
739 gro_skb->ip_summed = CHECKSUM_UNNECESSARY;
740
741 if ((cqe->vlan_my_qpn &
742 cpu_to_be32(MLX4_CQE_VLAN_PRESENT_MASK)) &&
743 (dev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
744 u16 vid = be16_to_cpu(cqe->sl_vid);
745
746 __vlan_hwaccel_put_tag(gro_skb, htons(ETH_P_8021Q), vid);
747 }
748
749 if (dev->features & NETIF_F_RXHASH)
750 gro_skb->rxhash = be32_to_cpu(cqe->immed_rss_invalid);
751
752 skb_record_rx_queue(gro_skb, cq->ring);
753
754 if (ring->hwtstamp_rx_filter == HWTSTAMP_FILTER_ALL) {
755 timestamp = mlx4_en_get_cqe_ts(cqe);
756 mlx4_en_fill_hwtstamps(mdev,
757 skb_hwtstamps(gro_skb),
758 timestamp);
759 }
760
761 napi_gro_frags(&cq->napi);
762 goto next;
763 }
764
765 /* GRO not possible, complete processing here */
766 ip_summed = CHECKSUM_UNNECESSARY;
767 } else {
768 ip_summed = CHECKSUM_NONE;
769 ring->csum_none++;
770 }
771 } else {
772 ip_summed = CHECKSUM_NONE;
773 ring->csum_none++;
774 }
775
776 skb = mlx4_en_rx_skb(priv, rx_desc, frags, length);
777 if (!skb) {
778 priv->stats.rx_dropped++;
779 goto next;
780 }
781
782 if (unlikely(priv->validate_loopback)) {
783 validate_loopback(priv, skb);
784 goto next;
785 }
786
787 skb->ip_summed = ip_summed;
788 skb->protocol = eth_type_trans(skb, dev);
789 skb_record_rx_queue(skb, cq->ring);
790
791 if (dev->features & NETIF_F_RXHASH)
792 skb->rxhash = be32_to_cpu(cqe->immed_rss_invalid);
793
794 if ((be32_to_cpu(cqe->vlan_my_qpn) &
795 MLX4_CQE_VLAN_PRESENT_MASK) &&
796 (dev->features & NETIF_F_HW_VLAN_CTAG_RX))
797 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), be16_to_cpu(cqe->sl_vid));
798
799 if (ring->hwtstamp_rx_filter == HWTSTAMP_FILTER_ALL) {
800 timestamp = mlx4_en_get_cqe_ts(cqe);
801 mlx4_en_fill_hwtstamps(mdev, skb_hwtstamps(skb),
802 timestamp);
803 }
804
805 skb_mark_napi_id(skb, &cq->napi);
806
807 /* Push it up the stack */
808 netif_receive_skb(skb);
809
810 next:
811 for (nr = 0; nr < priv->num_frags; nr++)
812 mlx4_en_free_frag(priv, frags, nr);
813
814 ++cq->mcq.cons_index;
815 index = (cq->mcq.cons_index) & ring->size_mask;
816 cqe = &cq->buf[(index << factor) + factor];
817 if (++polled == budget)
818 goto out;
819 }
820
821 out:
822 AVG_PERF_COUNTER(priv->pstats.rx_coal_avg, polled);
823 mlx4_cq_set_ci(&cq->mcq);
824 wmb(); /* ensure HW sees CQ consumer before we post new buffers */
825 ring->cons = cq->mcq.cons_index;
826 mlx4_en_refill_rx_buffers(priv, ring);
827 mlx4_en_update_rx_prod_db(ring);
828 return polled;
829 }
830
831
832 void mlx4_en_rx_irq(struct mlx4_cq *mcq)
833 {
834 struct mlx4_en_cq *cq = container_of(mcq, struct mlx4_en_cq, mcq);
835 struct mlx4_en_priv *priv = netdev_priv(cq->dev);
836
837 if (priv->port_up)
838 napi_schedule(&cq->napi);
839 else
840 mlx4_en_arm_cq(priv, cq);
841 }
842
843 /* Rx CQ polling - called by NAPI */
844 int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget)
845 {
846 struct mlx4_en_cq *cq = container_of(napi, struct mlx4_en_cq, napi);
847 struct net_device *dev = cq->dev;
848 struct mlx4_en_priv *priv = netdev_priv(dev);
849 int done;
850
851 if (!mlx4_en_cq_lock_napi(cq))
852 return budget;
853
854 done = mlx4_en_process_rx_cq(dev, cq, budget);
855
856 mlx4_en_cq_unlock_napi(cq);
857
858 /* If we used up all the quota - we're probably not done yet... */
859 if (done == budget)
860 INC_PERF_COUNTER(priv->pstats.napi_quota);
861 else {
862 /* Done for now */
863 napi_complete(napi);
864 mlx4_en_arm_cq(priv, cq);
865 }
866 return done;
867 }
868
869 static const int frag_sizes[] = {
870 FRAG_SZ0,
871 FRAG_SZ1,
872 FRAG_SZ2,
873 FRAG_SZ3
874 };
875
876 void mlx4_en_calc_rx_buf(struct net_device *dev)
877 {
878 struct mlx4_en_priv *priv = netdev_priv(dev);
879 int eff_mtu = dev->mtu + ETH_HLEN + VLAN_HLEN + ETH_LLC_SNAP_SIZE;
880 int buf_size = 0;
881 int i = 0;
882
883 while (buf_size < eff_mtu) {
884 priv->frag_info[i].frag_size =
885 (eff_mtu > buf_size + frag_sizes[i]) ?
886 frag_sizes[i] : eff_mtu - buf_size;
887 priv->frag_info[i].frag_prefix_size = buf_size;
888 if (!i) {
889 priv->frag_info[i].frag_align = NET_IP_ALIGN;
890 priv->frag_info[i].frag_stride =
891 ALIGN(frag_sizes[i] + NET_IP_ALIGN, SMP_CACHE_BYTES);
892 } else {
893 priv->frag_info[i].frag_align = 0;
894 priv->frag_info[i].frag_stride =
895 ALIGN(frag_sizes[i], SMP_CACHE_BYTES);
896 }
897 buf_size += priv->frag_info[i].frag_size;
898 i++;
899 }
900
901 priv->num_frags = i;
902 priv->rx_skb_size = eff_mtu;
903 priv->log_rx_info = ROUNDUP_LOG2(i * sizeof(struct mlx4_en_rx_alloc));
904
905 en_dbg(DRV, priv, "Rx buffer scatter-list (effective-mtu:%d "
906 "num_frags:%d):\n", eff_mtu, priv->num_frags);
907 for (i = 0; i < priv->num_frags; i++) {
908 en_err(priv,
909 " frag:%d - size:%d prefix:%d align:%d stride:%d\n",
910 i,
911 priv->frag_info[i].frag_size,
912 priv->frag_info[i].frag_prefix_size,
913 priv->frag_info[i].frag_align,
914 priv->frag_info[i].frag_stride);
915 }
916 }
917
918 /* RSS related functions */
919
920 static int mlx4_en_config_rss_qp(struct mlx4_en_priv *priv, int qpn,
921 struct mlx4_en_rx_ring *ring,
922 enum mlx4_qp_state *state,
923 struct mlx4_qp *qp)
924 {
925 struct mlx4_en_dev *mdev = priv->mdev;
926 struct mlx4_qp_context *context;
927 int err = 0;
928
929 context = kmalloc(sizeof(*context), GFP_KERNEL);
930 if (!context)
931 return -ENOMEM;
932
933 err = mlx4_qp_alloc(mdev->dev, qpn, qp);
934 if (err) {
935 en_err(priv, "Failed to allocate qp #%x\n", qpn);
936 goto out;
937 }
938 qp->event = mlx4_en_sqp_event;
939
940 memset(context, 0, sizeof *context);
941 mlx4_en_fill_qp_context(priv, ring->actual_size, ring->stride, 0, 0,
942 qpn, ring->cqn, -1, context);
943 context->db_rec_addr = cpu_to_be64(ring->wqres.db.dma);
944
945 /* Cancel FCS removal if FW allows */
946 if (mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_FCS_KEEP) {
947 context->param3 |= cpu_to_be32(1 << 29);
948 ring->fcs_del = ETH_FCS_LEN;
949 } else
950 ring->fcs_del = 0;
951
952 err = mlx4_qp_to_ready(mdev->dev, &ring->wqres.mtt, context, qp, state);
953 if (err) {
954 mlx4_qp_remove(mdev->dev, qp);
955 mlx4_qp_free(mdev->dev, qp);
956 }
957 mlx4_en_update_rx_prod_db(ring);
958 out:
959 kfree(context);
960 return err;
961 }
962
963 int mlx4_en_create_drop_qp(struct mlx4_en_priv *priv)
964 {
965 int err;
966 u32 qpn;
967
968 err = mlx4_qp_reserve_range(priv->mdev->dev, 1, 1, &qpn);
969 if (err) {
970 en_err(priv, "Failed reserving drop qpn\n");
971 return err;
972 }
973 err = mlx4_qp_alloc(priv->mdev->dev, qpn, &priv->drop_qp);
974 if (err) {
975 en_err(priv, "Failed allocating drop qp\n");
976 mlx4_qp_release_range(priv->mdev->dev, qpn, 1);
977 return err;
978 }
979
980 return 0;
981 }
982
983 void mlx4_en_destroy_drop_qp(struct mlx4_en_priv *priv)
984 {
985 u32 qpn;
986
987 qpn = priv->drop_qp.qpn;
988 mlx4_qp_remove(priv->mdev->dev, &priv->drop_qp);
989 mlx4_qp_free(priv->mdev->dev, &priv->drop_qp);
990 mlx4_qp_release_range(priv->mdev->dev, qpn, 1);
991 }
992
993 /* Allocate rx qp's and configure them according to rss map */
994 int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv)
995 {
996 struct mlx4_en_dev *mdev = priv->mdev;
997 struct mlx4_en_rss_map *rss_map = &priv->rss_map;
998 struct mlx4_qp_context context;
999 struct mlx4_rss_context *rss_context;
1000 int rss_rings;
1001 void *ptr;
1002 u8 rss_mask = (MLX4_RSS_IPV4 | MLX4_RSS_TCP_IPV4 | MLX4_RSS_IPV6 |
1003 MLX4_RSS_TCP_IPV6);
1004 int i, qpn;
1005 int err = 0;
1006 int good_qps = 0;
1007 static const u32 rsskey[10] = { 0xD181C62C, 0xF7F4DB5B, 0x1983A2FC,
1008 0x943E1ADB, 0xD9389E6B, 0xD1039C2C, 0xA74499AD,
1009 0x593D56D9, 0xF3253C06, 0x2ADC1FFC};
1010
1011 en_dbg(DRV, priv, "Configuring rss steering\n");
1012 err = mlx4_qp_reserve_range(mdev->dev, priv->rx_ring_num,
1013 priv->rx_ring_num,
1014 &rss_map->base_qpn);
1015 if (err) {
1016 en_err(priv, "Failed reserving %d qps\n", priv->rx_ring_num);
1017 return err;
1018 }
1019
1020 for (i = 0; i < priv->rx_ring_num; i++) {
1021 qpn = rss_map->base_qpn + i;
1022 err = mlx4_en_config_rss_qp(priv, qpn, priv->rx_ring[i],
1023 &rss_map->state[i],
1024 &rss_map->qps[i]);
1025 if (err)
1026 goto rss_err;
1027
1028 ++good_qps;
1029 }
1030
1031 /* Configure RSS indirection qp */
1032 err = mlx4_qp_alloc(mdev->dev, priv->base_qpn, &rss_map->indir_qp);
1033 if (err) {
1034 en_err(priv, "Failed to allocate RSS indirection QP\n");
1035 goto rss_err;
1036 }
1037 rss_map->indir_qp.event = mlx4_en_sqp_event;
1038 mlx4_en_fill_qp_context(priv, 0, 0, 0, 1, priv->base_qpn,
1039 priv->rx_ring[0]->cqn, -1, &context);
1040
1041 if (!priv->prof->rss_rings || priv->prof->rss_rings > priv->rx_ring_num)
1042 rss_rings = priv->rx_ring_num;
1043 else
1044 rss_rings = priv->prof->rss_rings;
1045
1046 ptr = ((void *) &context) + offsetof(struct mlx4_qp_context, pri_path)
1047 + MLX4_RSS_OFFSET_IN_QPC_PRI_PATH;
1048 rss_context = ptr;
1049 rss_context->base_qpn = cpu_to_be32(ilog2(rss_rings) << 24 |
1050 (rss_map->base_qpn));
1051 rss_context->default_qpn = cpu_to_be32(rss_map->base_qpn);
1052 if (priv->mdev->profile.udp_rss) {
1053 rss_mask |= MLX4_RSS_UDP_IPV4 | MLX4_RSS_UDP_IPV6;
1054 rss_context->base_qpn_udp = rss_context->default_qpn;
1055 }
1056 rss_context->flags = rss_mask;
1057 rss_context->hash_fn = MLX4_RSS_HASH_TOP;
1058 for (i = 0; i < 10; i++)
1059 rss_context->rss_key[i] = cpu_to_be32(rsskey[i]);
1060
1061 err = mlx4_qp_to_ready(mdev->dev, &priv->res.mtt, &context,
1062 &rss_map->indir_qp, &rss_map->indir_state);
1063 if (err)
1064 goto indir_err;
1065
1066 return 0;
1067
1068 indir_err:
1069 mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state,
1070 MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->indir_qp);
1071 mlx4_qp_remove(mdev->dev, &rss_map->indir_qp);
1072 mlx4_qp_free(mdev->dev, &rss_map->indir_qp);
1073 rss_err:
1074 for (i = 0; i < good_qps; i++) {
1075 mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i],
1076 MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]);
1077 mlx4_qp_remove(mdev->dev, &rss_map->qps[i]);
1078 mlx4_qp_free(mdev->dev, &rss_map->qps[i]);
1079 }
1080 mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, priv->rx_ring_num);
1081 return err;
1082 }
1083
1084 void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv)
1085 {
1086 struct mlx4_en_dev *mdev = priv->mdev;
1087 struct mlx4_en_rss_map *rss_map = &priv->rss_map;
1088 int i;
1089
1090 mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state,
1091 MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->indir_qp);
1092 mlx4_qp_remove(mdev->dev, &rss_map->indir_qp);
1093 mlx4_qp_free(mdev->dev, &rss_map->indir_qp);
1094
1095 for (i = 0; i < priv->rx_ring_num; i++) {
1096 mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i],
1097 MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]);
1098 mlx4_qp_remove(mdev->dev, &rss_map->qps[i]);
1099 mlx4_qp_free(mdev->dev, &rss_map->qps[i]);
1100 }
1101 mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, priv->rx_ring_num);
1102 }
Linux kernel - Deliverables
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