2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 #include <net/busy_poll.h>
35 #include <linux/mlx4/cq.h>
36 #include <linux/slab.h>
37 #include <linux/mlx4/qp.h>
38 #include <linux/skbuff.h>
39 #include <linux/rculist.h>
40 #include <linux/if_ether.h>
41 #include <linux/if_vlan.h>
42 #include <linux/vmalloc.h>
43 #include <linux/irq.h>
45 #if IS_ENABLED(CONFIG_IPV6)
46 #include <net/ip6_checksum.h>
51 static int mlx4_alloc_pages(struct mlx4_en_priv
*priv
,
52 struct mlx4_en_rx_alloc
*page_alloc
,
53 const struct mlx4_en_frag_info
*frag_info
,
60 for (order
= MLX4_EN_ALLOC_PREFER_ORDER
; ;) {
64 gfp
|= __GFP_COMP
| __GFP_NOWARN
| __GFP_NOMEMALLOC
;
65 page
= alloc_pages(gfp
, order
);
69 ((PAGE_SIZE
<< order
) < frag_info
->frag_size
))
72 dma
= dma_map_page(priv
->ddev
, page
, 0, PAGE_SIZE
<< order
,
74 if (dma_mapping_error(priv
->ddev
, dma
)) {
78 page_alloc
->page_size
= PAGE_SIZE
<< order
;
79 page_alloc
->page
= page
;
80 page_alloc
->dma
= dma
;
81 page_alloc
->page_offset
= 0;
82 /* Not doing get_page() for each frag is a big win
83 * on asymetric workloads. Note we can not use atomic_set().
85 page_ref_add(page
, page_alloc
->page_size
/ frag_info
->frag_stride
- 1);
89 static int mlx4_en_alloc_frags(struct mlx4_en_priv
*priv
,
90 struct mlx4_en_rx_desc
*rx_desc
,
91 struct mlx4_en_rx_alloc
*frags
,
92 struct mlx4_en_rx_alloc
*ring_alloc
,
95 struct mlx4_en_rx_alloc page_alloc
[MLX4_EN_MAX_RX_FRAGS
];
96 const struct mlx4_en_frag_info
*frag_info
;
101 for (i
= 0; i
< priv
->num_frags
; i
++) {
102 frag_info
= &priv
->frag_info
[i
];
103 page_alloc
[i
] = ring_alloc
[i
];
104 page_alloc
[i
].page_offset
+= frag_info
->frag_stride
;
106 if (page_alloc
[i
].page_offset
+ frag_info
->frag_stride
<=
107 ring_alloc
[i
].page_size
)
110 if (mlx4_alloc_pages(priv
, &page_alloc
[i
], frag_info
, gfp
))
114 for (i
= 0; i
< priv
->num_frags
; i
++) {
115 frags
[i
] = ring_alloc
[i
];
116 dma
= ring_alloc
[i
].dma
+ ring_alloc
[i
].page_offset
;
117 ring_alloc
[i
] = page_alloc
[i
];
118 rx_desc
->data
[i
].addr
= cpu_to_be64(dma
);
125 if (page_alloc
[i
].page
!= ring_alloc
[i
].page
) {
126 dma_unmap_page(priv
->ddev
, page_alloc
[i
].dma
,
127 page_alloc
[i
].page_size
, PCI_DMA_FROMDEVICE
);
128 page
= page_alloc
[i
].page
;
129 /* Revert changes done by mlx4_alloc_pages */
130 page_ref_sub(page
, page_alloc
[i
].page_size
/
131 priv
->frag_info
[i
].frag_stride
- 1);
138 static void mlx4_en_free_frag(struct mlx4_en_priv
*priv
,
139 struct mlx4_en_rx_alloc
*frags
,
142 const struct mlx4_en_frag_info
*frag_info
= &priv
->frag_info
[i
];
143 u32 next_frag_end
= frags
[i
].page_offset
+ 2 * frag_info
->frag_stride
;
146 if (next_frag_end
> frags
[i
].page_size
)
147 dma_unmap_page(priv
->ddev
, frags
[i
].dma
, frags
[i
].page_size
,
151 put_page(frags
[i
].page
);
154 static int mlx4_en_init_allocator(struct mlx4_en_priv
*priv
,
155 struct mlx4_en_rx_ring
*ring
)
158 struct mlx4_en_rx_alloc
*page_alloc
;
160 for (i
= 0; i
< priv
->num_frags
; i
++) {
161 const struct mlx4_en_frag_info
*frag_info
= &priv
->frag_info
[i
];
163 if (mlx4_alloc_pages(priv
, &ring
->page_alloc
[i
],
164 frag_info
, GFP_KERNEL
| __GFP_COLD
))
167 en_dbg(DRV
, priv
, " frag %d allocator: - size:%d frags:%d\n",
168 i
, ring
->page_alloc
[i
].page_size
,
169 page_ref_count(ring
->page_alloc
[i
].page
));
177 page_alloc
= &ring
->page_alloc
[i
];
178 dma_unmap_page(priv
->ddev
, page_alloc
->dma
,
179 page_alloc
->page_size
, PCI_DMA_FROMDEVICE
);
180 page
= page_alloc
->page
;
181 /* Revert changes done by mlx4_alloc_pages */
182 page_ref_sub(page
, page_alloc
->page_size
/
183 priv
->frag_info
[i
].frag_stride
- 1);
185 page_alloc
->page
= NULL
;
190 static void mlx4_en_destroy_allocator(struct mlx4_en_priv
*priv
,
191 struct mlx4_en_rx_ring
*ring
)
193 struct mlx4_en_rx_alloc
*page_alloc
;
196 for (i
= 0; i
< priv
->num_frags
; i
++) {
197 const struct mlx4_en_frag_info
*frag_info
= &priv
->frag_info
[i
];
199 page_alloc
= &ring
->page_alloc
[i
];
200 en_dbg(DRV
, priv
, "Freeing allocator:%d count:%d\n",
201 i
, page_count(page_alloc
->page
));
203 dma_unmap_page(priv
->ddev
, page_alloc
->dma
,
204 page_alloc
->page_size
, PCI_DMA_FROMDEVICE
);
205 while (page_alloc
->page_offset
+ frag_info
->frag_stride
<
206 page_alloc
->page_size
) {
207 put_page(page_alloc
->page
);
208 page_alloc
->page_offset
+= frag_info
->frag_stride
;
210 page_alloc
->page
= NULL
;
214 static void mlx4_en_init_rx_desc(struct mlx4_en_priv
*priv
,
215 struct mlx4_en_rx_ring
*ring
, int index
)
217 struct mlx4_en_rx_desc
*rx_desc
= ring
->buf
+ ring
->stride
* index
;
221 /* Set size and memtype fields */
222 for (i
= 0; i
< priv
->num_frags
; i
++) {
223 rx_desc
->data
[i
].byte_count
=
224 cpu_to_be32(priv
->frag_info
[i
].frag_size
);
225 rx_desc
->data
[i
].lkey
= cpu_to_be32(priv
->mdev
->mr
.key
);
228 /* If the number of used fragments does not fill up the ring stride,
229 * remaining (unused) fragments must be padded with null address/size
230 * and a special memory key */
231 possible_frags
= (ring
->stride
- sizeof(struct mlx4_en_rx_desc
)) / DS_SIZE
;
232 for (i
= priv
->num_frags
; i
< possible_frags
; i
++) {
233 rx_desc
->data
[i
].byte_count
= 0;
234 rx_desc
->data
[i
].lkey
= cpu_to_be32(MLX4_EN_MEMTYPE_PAD
);
235 rx_desc
->data
[i
].addr
= 0;
239 static int mlx4_en_prepare_rx_desc(struct mlx4_en_priv
*priv
,
240 struct mlx4_en_rx_ring
*ring
, int index
,
243 struct mlx4_en_rx_desc
*rx_desc
= ring
->buf
+ (index
* ring
->stride
);
244 struct mlx4_en_rx_alloc
*frags
= ring
->rx_info
+
245 (index
<< priv
->log_rx_info
);
247 return mlx4_en_alloc_frags(priv
, rx_desc
, frags
, ring
->page_alloc
, gfp
);
250 static inline bool mlx4_en_is_ring_empty(struct mlx4_en_rx_ring
*ring
)
252 return ring
->prod
== ring
->cons
;
255 static inline void mlx4_en_update_rx_prod_db(struct mlx4_en_rx_ring
*ring
)
257 *ring
->wqres
.db
.db
= cpu_to_be32(ring
->prod
& 0xffff);
260 static void mlx4_en_free_rx_desc(struct mlx4_en_priv
*priv
,
261 struct mlx4_en_rx_ring
*ring
,
264 struct mlx4_en_rx_alloc
*frags
;
267 frags
= ring
->rx_info
+ (index
<< priv
->log_rx_info
);
268 for (nr
= 0; nr
< priv
->num_frags
; nr
++) {
269 en_dbg(DRV
, priv
, "Freeing fragment:%d\n", nr
);
270 mlx4_en_free_frag(priv
, frags
, nr
);
274 static int mlx4_en_fill_rx_buffers(struct mlx4_en_priv
*priv
)
276 struct mlx4_en_rx_ring
*ring
;
281 for (buf_ind
= 0; buf_ind
< priv
->prof
->rx_ring_size
; buf_ind
++) {
282 for (ring_ind
= 0; ring_ind
< priv
->rx_ring_num
; ring_ind
++) {
283 ring
= priv
->rx_ring
[ring_ind
];
285 if (mlx4_en_prepare_rx_desc(priv
, ring
,
287 GFP_KERNEL
| __GFP_COLD
)) {
288 if (ring
->actual_size
< MLX4_EN_MIN_RX_SIZE
) {
289 en_err(priv
, "Failed to allocate enough rx buffers\n");
292 new_size
= rounddown_pow_of_two(ring
->actual_size
);
293 en_warn(priv
, "Only %d buffers allocated reducing ring size to %d\n",
294 ring
->actual_size
, new_size
);
305 for (ring_ind
= 0; ring_ind
< priv
->rx_ring_num
; ring_ind
++) {
306 ring
= priv
->rx_ring
[ring_ind
];
307 while (ring
->actual_size
> new_size
) {
310 mlx4_en_free_rx_desc(priv
, ring
, ring
->actual_size
);
317 static void mlx4_en_free_rx_buf(struct mlx4_en_priv
*priv
,
318 struct mlx4_en_rx_ring
*ring
)
322 en_dbg(DRV
, priv
, "Freeing Rx buf - cons:%d prod:%d\n",
323 ring
->cons
, ring
->prod
);
325 /* Unmap and free Rx buffers */
326 while (!mlx4_en_is_ring_empty(ring
)) {
327 index
= ring
->cons
& ring
->size_mask
;
328 en_dbg(DRV
, priv
, "Processing descriptor:%d\n", index
);
329 mlx4_en_free_rx_desc(priv
, ring
, index
);
334 void mlx4_en_set_num_rx_rings(struct mlx4_en_dev
*mdev
)
339 struct mlx4_dev
*dev
= mdev
->dev
;
341 mlx4_foreach_port(i
, dev
, MLX4_PORT_TYPE_ETH
) {
342 num_of_eqs
= max_t(int, MIN_RX_RINGS
,
344 mlx4_get_eqs_per_port(mdev
->dev
, i
),
347 num_rx_rings
= mlx4_low_memory_profile() ? MIN_RX_RINGS
:
348 min_t(int, num_of_eqs
,
349 netif_get_num_default_rss_queues());
350 mdev
->profile
.prof
[i
].rx_ring_num
=
351 rounddown_pow_of_two(num_rx_rings
);
355 int mlx4_en_create_rx_ring(struct mlx4_en_priv
*priv
,
356 struct mlx4_en_rx_ring
**pring
,
357 u32 size
, u16 stride
, int node
)
359 struct mlx4_en_dev
*mdev
= priv
->mdev
;
360 struct mlx4_en_rx_ring
*ring
;
364 ring
= kzalloc_node(sizeof(*ring
), GFP_KERNEL
, node
);
366 ring
= kzalloc(sizeof(*ring
), GFP_KERNEL
);
368 en_err(priv
, "Failed to allocate RX ring structure\n");
376 ring
->size_mask
= size
- 1;
377 ring
->stride
= stride
;
378 ring
->log_stride
= ffs(ring
->stride
) - 1;
379 ring
->buf_size
= ring
->size
* ring
->stride
+ TXBB_SIZE
;
381 tmp
= size
* roundup_pow_of_two(MLX4_EN_MAX_RX_FRAGS
*
382 sizeof(struct mlx4_en_rx_alloc
));
383 ring
->rx_info
= vmalloc_node(tmp
, node
);
384 if (!ring
->rx_info
) {
385 ring
->rx_info
= vmalloc(tmp
);
386 if (!ring
->rx_info
) {
392 en_dbg(DRV
, priv
, "Allocated rx_info ring at addr:%p size:%d\n",
395 /* Allocate HW buffers on provided NUMA node */
396 set_dev_node(&mdev
->dev
->persist
->pdev
->dev
, node
);
397 err
= mlx4_alloc_hwq_res(mdev
->dev
, &ring
->wqres
, ring
->buf_size
);
398 set_dev_node(&mdev
->dev
->persist
->pdev
->dev
, mdev
->dev
->numa_node
);
402 ring
->buf
= ring
->wqres
.buf
.direct
.buf
;
404 ring
->hwtstamp_rx_filter
= priv
->hwtstamp_config
.rx_filter
;
410 vfree(ring
->rx_info
);
411 ring
->rx_info
= NULL
;
419 int mlx4_en_activate_rx_rings(struct mlx4_en_priv
*priv
)
421 struct mlx4_en_rx_ring
*ring
;
425 int stride
= roundup_pow_of_two(sizeof(struct mlx4_en_rx_desc
) +
426 DS_SIZE
* priv
->num_frags
);
428 for (ring_ind
= 0; ring_ind
< priv
->rx_ring_num
; ring_ind
++) {
429 ring
= priv
->rx_ring
[ring_ind
];
433 ring
->actual_size
= 0;
434 ring
->cqn
= priv
->rx_cq
[ring_ind
]->mcq
.cqn
;
436 ring
->stride
= stride
;
437 if (ring
->stride
<= TXBB_SIZE
)
438 ring
->buf
+= TXBB_SIZE
;
440 ring
->log_stride
= ffs(ring
->stride
) - 1;
441 ring
->buf_size
= ring
->size
* ring
->stride
;
443 memset(ring
->buf
, 0, ring
->buf_size
);
444 mlx4_en_update_rx_prod_db(ring
);
446 /* Initialize all descriptors */
447 for (i
= 0; i
< ring
->size
; i
++)
448 mlx4_en_init_rx_desc(priv
, ring
, i
);
450 /* Initialize page allocators */
451 err
= mlx4_en_init_allocator(priv
, ring
);
453 en_err(priv
, "Failed initializing ring allocator\n");
454 if (ring
->stride
<= TXBB_SIZE
)
455 ring
->buf
-= TXBB_SIZE
;
460 err
= mlx4_en_fill_rx_buffers(priv
);
464 for (ring_ind
= 0; ring_ind
< priv
->rx_ring_num
; ring_ind
++) {
465 ring
= priv
->rx_ring
[ring_ind
];
467 ring
->size_mask
= ring
->actual_size
- 1;
468 mlx4_en_update_rx_prod_db(ring
);
474 for (ring_ind
= 0; ring_ind
< priv
->rx_ring_num
; ring_ind
++)
475 mlx4_en_free_rx_buf(priv
, priv
->rx_ring
[ring_ind
]);
477 ring_ind
= priv
->rx_ring_num
- 1;
479 while (ring_ind
>= 0) {
480 if (priv
->rx_ring
[ring_ind
]->stride
<= TXBB_SIZE
)
481 priv
->rx_ring
[ring_ind
]->buf
-= TXBB_SIZE
;
482 mlx4_en_destroy_allocator(priv
, priv
->rx_ring
[ring_ind
]);
488 /* We recover from out of memory by scheduling our napi poll
489 * function (mlx4_en_process_cq), which tries to allocate
490 * all missing RX buffers (call to mlx4_en_refill_rx_buffers).
492 void mlx4_en_recover_from_oom(struct mlx4_en_priv
*priv
)
499 for (ring
= 0; ring
< priv
->rx_ring_num
; ring
++) {
500 if (mlx4_en_is_ring_empty(priv
->rx_ring
[ring
]))
501 napi_reschedule(&priv
->rx_cq
[ring
]->napi
);
505 void mlx4_en_destroy_rx_ring(struct mlx4_en_priv
*priv
,
506 struct mlx4_en_rx_ring
**pring
,
507 u32 size
, u16 stride
)
509 struct mlx4_en_dev
*mdev
= priv
->mdev
;
510 struct mlx4_en_rx_ring
*ring
= *pring
;
512 mlx4_free_hwq_res(mdev
->dev
, &ring
->wqres
, size
* stride
+ TXBB_SIZE
);
513 vfree(ring
->rx_info
);
514 ring
->rx_info
= NULL
;
519 void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv
*priv
,
520 struct mlx4_en_rx_ring
*ring
)
522 mlx4_en_free_rx_buf(priv
, ring
);
523 if (ring
->stride
<= TXBB_SIZE
)
524 ring
->buf
-= TXBB_SIZE
;
525 mlx4_en_destroy_allocator(priv
, ring
);
529 static int mlx4_en_complete_rx_desc(struct mlx4_en_priv
*priv
,
530 struct mlx4_en_rx_desc
*rx_desc
,
531 struct mlx4_en_rx_alloc
*frags
,
535 struct skb_frag_struct
*skb_frags_rx
= skb_shinfo(skb
)->frags
;
536 struct mlx4_en_frag_info
*frag_info
;
540 /* Collect used fragments while replacing them in the HW descriptors */
541 for (nr
= 0; nr
< priv
->num_frags
; nr
++) {
542 frag_info
= &priv
->frag_info
[nr
];
543 if (length
<= frag_info
->frag_prefix_size
)
548 dma
= be64_to_cpu(rx_desc
->data
[nr
].addr
);
549 dma_sync_single_for_cpu(priv
->ddev
, dma
, frag_info
->frag_size
,
552 /* Save page reference in skb */
553 __skb_frag_set_page(&skb_frags_rx
[nr
], frags
[nr
].page
);
554 skb_frag_size_set(&skb_frags_rx
[nr
], frag_info
->frag_size
);
555 skb_frags_rx
[nr
].page_offset
= frags
[nr
].page_offset
;
556 skb
->truesize
+= frag_info
->frag_stride
;
557 frags
[nr
].page
= NULL
;
559 /* Adjust size of last fragment to match actual length */
561 skb_frag_size_set(&skb_frags_rx
[nr
- 1],
562 length
- priv
->frag_info
[nr
- 1].frag_prefix_size
);
568 __skb_frag_unref(&skb_frags_rx
[nr
]);
574 static struct sk_buff
*mlx4_en_rx_skb(struct mlx4_en_priv
*priv
,
575 struct mlx4_en_rx_desc
*rx_desc
,
576 struct mlx4_en_rx_alloc
*frags
,
584 skb
= netdev_alloc_skb(priv
->dev
, SMALL_PACKET_SIZE
+ NET_IP_ALIGN
);
586 en_dbg(RX_ERR
, priv
, "Failed allocating skb\n");
589 skb_reserve(skb
, NET_IP_ALIGN
);
592 /* Get pointer to first fragment so we could copy the headers into the
593 * (linear part of the) skb */
594 va
= page_address(frags
[0].page
) + frags
[0].page_offset
;
596 if (length
<= SMALL_PACKET_SIZE
) {
597 /* We are copying all relevant data to the skb - temporarily
598 * sync buffers for the copy */
599 dma
= be64_to_cpu(rx_desc
->data
[0].addr
);
600 dma_sync_single_for_cpu(priv
->ddev
, dma
, length
,
602 skb_copy_to_linear_data(skb
, va
, length
);
605 unsigned int pull_len
;
607 /* Move relevant fragments to skb */
608 used_frags
= mlx4_en_complete_rx_desc(priv
, rx_desc
, frags
,
610 if (unlikely(!used_frags
)) {
614 skb_shinfo(skb
)->nr_frags
= used_frags
;
616 pull_len
= eth_get_headlen(va
, SMALL_PACKET_SIZE
);
617 /* Copy headers into the skb linear buffer */
618 memcpy(skb
->data
, va
, pull_len
);
619 skb
->tail
+= pull_len
;
621 /* Skip headers in first fragment */
622 skb_shinfo(skb
)->frags
[0].page_offset
+= pull_len
;
624 /* Adjust size of first fragment */
625 skb_frag_size_sub(&skb_shinfo(skb
)->frags
[0], pull_len
);
626 skb
->data_len
= length
- pull_len
;
631 static void validate_loopback(struct mlx4_en_priv
*priv
, struct sk_buff
*skb
)
634 int offset
= ETH_HLEN
;
636 for (i
= 0; i
< MLX4_LOOPBACK_TEST_PAYLOAD
; i
++, offset
++) {
637 if (*(skb
->data
+ offset
) != (unsigned char) (i
& 0xff))
641 priv
->loopback_ok
= 1;
644 dev_kfree_skb_any(skb
);
647 static void mlx4_en_refill_rx_buffers(struct mlx4_en_priv
*priv
,
648 struct mlx4_en_rx_ring
*ring
)
650 int index
= ring
->prod
& ring
->size_mask
;
652 while ((u32
) (ring
->prod
- ring
->cons
) < ring
->actual_size
) {
653 if (mlx4_en_prepare_rx_desc(priv
, ring
, index
,
654 GFP_ATOMIC
| __GFP_COLD
))
657 index
= ring
->prod
& ring
->size_mask
;
661 /* When hardware doesn't strip the vlan, we need to calculate the checksum
662 * over it and add it to the hardware's checksum calculation
664 static inline __wsum
get_fixed_vlan_csum(__wsum hw_checksum
,
665 struct vlan_hdr
*vlanh
)
667 return csum_add(hw_checksum
, *(__wsum
*)vlanh
);
670 /* Although the stack expects checksum which doesn't include the pseudo
671 * header, the HW adds it. To address that, we are subtracting the pseudo
672 * header checksum from the checksum value provided by the HW.
674 static void get_fixed_ipv4_csum(__wsum hw_checksum
, struct sk_buff
*skb
,
677 __u16 length_for_csum
= 0;
678 __wsum csum_pseudo_header
= 0;
680 length_for_csum
= (be16_to_cpu(iph
->tot_len
) - (iph
->ihl
<< 2));
681 csum_pseudo_header
= csum_tcpudp_nofold(iph
->saddr
, iph
->daddr
,
682 length_for_csum
, iph
->protocol
, 0);
683 skb
->csum
= csum_sub(hw_checksum
, csum_pseudo_header
);
686 #if IS_ENABLED(CONFIG_IPV6)
687 /* In IPv6 packets, besides subtracting the pseudo header checksum,
688 * we also compute/add the IP header checksum which
689 * is not added by the HW.
691 static int get_fixed_ipv6_csum(__wsum hw_checksum
, struct sk_buff
*skb
,
692 struct ipv6hdr
*ipv6h
)
694 __wsum csum_pseudo_hdr
= 0;
696 if (ipv6h
->nexthdr
== IPPROTO_FRAGMENT
|| ipv6h
->nexthdr
== IPPROTO_HOPOPTS
)
698 hw_checksum
= csum_add(hw_checksum
, (__force __wsum
)htons(ipv6h
->nexthdr
));
700 csum_pseudo_hdr
= csum_partial(&ipv6h
->saddr
,
701 sizeof(ipv6h
->saddr
) + sizeof(ipv6h
->daddr
), 0);
702 csum_pseudo_hdr
= csum_add(csum_pseudo_hdr
, (__force __wsum
)ipv6h
->payload_len
);
703 csum_pseudo_hdr
= csum_add(csum_pseudo_hdr
, (__force __wsum
)ntohs(ipv6h
->nexthdr
));
705 skb
->csum
= csum_sub(hw_checksum
, csum_pseudo_hdr
);
706 skb
->csum
= csum_add(skb
->csum
, csum_partial(ipv6h
, sizeof(struct ipv6hdr
), 0));
710 static int check_csum(struct mlx4_cqe
*cqe
, struct sk_buff
*skb
, void *va
,
711 netdev_features_t dev_features
)
713 __wsum hw_checksum
= 0;
715 void *hdr
= (u8
*)va
+ sizeof(struct ethhdr
);
717 hw_checksum
= csum_unfold((__force __sum16
)cqe
->checksum
);
719 if (cqe
->vlan_my_qpn
& cpu_to_be32(MLX4_CQE_CVLAN_PRESENT_MASK
) &&
720 !(dev_features
& NETIF_F_HW_VLAN_CTAG_RX
)) {
721 hw_checksum
= get_fixed_vlan_csum(hw_checksum
, hdr
);
722 hdr
+= sizeof(struct vlan_hdr
);
725 if (cqe
->status
& cpu_to_be16(MLX4_CQE_STATUS_IPV4
))
726 get_fixed_ipv4_csum(hw_checksum
, skb
, hdr
);
727 #if IS_ENABLED(CONFIG_IPV6)
728 else if (cqe
->status
& cpu_to_be16(MLX4_CQE_STATUS_IPV6
))
729 if (get_fixed_ipv6_csum(hw_checksum
, skb
, hdr
))
735 int mlx4_en_process_rx_cq(struct net_device
*dev
, struct mlx4_en_cq
*cq
, int budget
)
737 struct mlx4_en_priv
*priv
= netdev_priv(dev
);
738 struct mlx4_en_dev
*mdev
= priv
->mdev
;
739 struct mlx4_cqe
*cqe
;
740 struct mlx4_en_rx_ring
*ring
= priv
->rx_ring
[cq
->ring
];
741 struct mlx4_en_rx_alloc
*frags
;
742 struct mlx4_en_rx_desc
*rx_desc
;
749 int factor
= priv
->cqe_factor
;
759 /* We assume a 1:1 mapping between CQEs and Rx descriptors, so Rx
760 * descriptor offset can be deduced from the CQE index instead of
761 * reading 'cqe->index' */
762 index
= cq
->mcq
.cons_index
& ring
->size_mask
;
763 cqe
= mlx4_en_get_cqe(cq
->buf
, index
, priv
->cqe_size
) + factor
;
765 /* Process all completed CQEs */
766 while (XNOR(cqe
->owner_sr_opcode
& MLX4_CQE_OWNER_MASK
,
767 cq
->mcq
.cons_index
& cq
->size
)) {
769 frags
= ring
->rx_info
+ (index
<< priv
->log_rx_info
);
770 rx_desc
= ring
->buf
+ (index
<< ring
->log_stride
);
773 * make sure we read the CQE after we read the ownership bit
777 /* Drop packet on bad receive or bad checksum */
778 if (unlikely((cqe
->owner_sr_opcode
& MLX4_CQE_OPCODE_MASK
) ==
779 MLX4_CQE_OPCODE_ERROR
)) {
780 en_err(priv
, "CQE completed in error - vendor syndrom:%d syndrom:%d\n",
781 ((struct mlx4_err_cqe
*)cqe
)->vendor_err_syndrome
,
782 ((struct mlx4_err_cqe
*)cqe
)->syndrome
);
785 if (unlikely(cqe
->badfcs_enc
& MLX4_CQE_BAD_FCS
)) {
786 en_dbg(RX_ERR
, priv
, "Accepted frame with bad FCS\n");
790 /* Check if we need to drop the packet if SRIOV is not enabled
791 * and not performing the selftest or flb disabled
793 if (priv
->flags
& MLX4_EN_FLAG_RX_FILTER_NEEDED
) {
796 /* Get pointer to first fragment since we haven't
797 * skb yet and cast it to ethhdr struct
799 dma
= be64_to_cpu(rx_desc
->data
[0].addr
);
800 dma_sync_single_for_cpu(priv
->ddev
, dma
, sizeof(*ethh
),
802 ethh
= (struct ethhdr
*)(page_address(frags
[0].page
) +
803 frags
[0].page_offset
);
805 if (is_multicast_ether_addr(ethh
->h_dest
)) {
806 struct mlx4_mac_entry
*entry
;
807 struct hlist_head
*bucket
;
808 unsigned int mac_hash
;
810 /* Drop the packet, since HW loopback-ed it */
811 mac_hash
= ethh
->h_source
[MLX4_EN_MAC_HASH_IDX
];
812 bucket
= &priv
->mac_hash
[mac_hash
];
814 hlist_for_each_entry_rcu(entry
, bucket
, hlist
) {
815 if (ether_addr_equal_64bits(entry
->mac
,
826 * Packet is OK - process it.
828 length
= be32_to_cpu(cqe
->byte_cnt
);
829 length
-= ring
->fcs_del
;
830 ring
->bytes
+= length
;
832 l2_tunnel
= (dev
->hw_enc_features
& NETIF_F_RXCSUM
) &&
833 (cqe
->vlan_my_qpn
& cpu_to_be32(MLX4_CQE_L2_TUNNEL
));
835 if (likely(dev
->features
& NETIF_F_RXCSUM
)) {
836 if (cqe
->status
& cpu_to_be16(MLX4_CQE_STATUS_TCP
|
837 MLX4_CQE_STATUS_UDP
)) {
838 if ((cqe
->status
& cpu_to_be16(MLX4_CQE_STATUS_IPOK
)) &&
839 cqe
->checksum
== cpu_to_be16(0xffff)) {
840 ip_summed
= CHECKSUM_UNNECESSARY
;
843 ip_summed
= CHECKSUM_NONE
;
847 if (priv
->flags
& MLX4_EN_FLAG_RX_CSUM_NON_TCP_UDP
&&
848 (cqe
->status
& cpu_to_be16(MLX4_CQE_STATUS_IPV4
|
849 MLX4_CQE_STATUS_IPV6
))) {
850 ip_summed
= CHECKSUM_COMPLETE
;
851 ring
->csum_complete
++;
853 ip_summed
= CHECKSUM_NONE
;
858 ip_summed
= CHECKSUM_NONE
;
862 /* This packet is eligible for GRO if it is:
863 * - DIX Ethernet (type interpretation)
865 * - without IP options
866 * - not an IP fragment
868 if (dev
->features
& NETIF_F_GRO
) {
869 struct sk_buff
*gro_skb
= napi_get_frags(&cq
->napi
);
873 nr
= mlx4_en_complete_rx_desc(priv
,
874 rx_desc
, frags
, gro_skb
,
879 if (ip_summed
== CHECKSUM_COMPLETE
) {
880 void *va
= skb_frag_address(skb_shinfo(gro_skb
)->frags
);
881 if (check_csum(cqe
, gro_skb
, va
,
883 ip_summed
= CHECKSUM_NONE
;
885 ring
->csum_complete
--;
889 skb_shinfo(gro_skb
)->nr_frags
= nr
;
890 gro_skb
->len
= length
;
891 gro_skb
->data_len
= length
;
892 gro_skb
->ip_summed
= ip_summed
;
894 if (l2_tunnel
&& ip_summed
== CHECKSUM_UNNECESSARY
)
895 gro_skb
->csum_level
= 1;
897 if ((cqe
->vlan_my_qpn
&
898 cpu_to_be32(MLX4_CQE_CVLAN_PRESENT_MASK
)) &&
899 (dev
->features
& NETIF_F_HW_VLAN_CTAG_RX
)) {
900 u16 vid
= be16_to_cpu(cqe
->sl_vid
);
902 __vlan_hwaccel_put_tag(gro_skb
, htons(ETH_P_8021Q
), vid
);
903 } else if ((be32_to_cpu(cqe
->vlan_my_qpn
) &
904 MLX4_CQE_SVLAN_PRESENT_MASK
) &&
905 (dev
->features
& NETIF_F_HW_VLAN_STAG_RX
)) {
906 __vlan_hwaccel_put_tag(gro_skb
,
908 be16_to_cpu(cqe
->sl_vid
));
911 if (dev
->features
& NETIF_F_RXHASH
)
912 skb_set_hash(gro_skb
,
913 be32_to_cpu(cqe
->immed_rss_invalid
),
914 (ip_summed
== CHECKSUM_UNNECESSARY
) ?
918 skb_record_rx_queue(gro_skb
, cq
->ring
);
920 if (ring
->hwtstamp_rx_filter
== HWTSTAMP_FILTER_ALL
) {
921 timestamp
= mlx4_en_get_cqe_ts(cqe
);
922 mlx4_en_fill_hwtstamps(mdev
,
923 skb_hwtstamps(gro_skb
),
927 napi_gro_frags(&cq
->napi
);
931 /* GRO not possible, complete processing here */
932 skb
= mlx4_en_rx_skb(priv
, rx_desc
, frags
, length
);
938 if (unlikely(priv
->validate_loopback
)) {
939 validate_loopback(priv
, skb
);
943 if (ip_summed
== CHECKSUM_COMPLETE
) {
944 if (check_csum(cqe
, skb
, skb
->data
, dev
->features
)) {
945 ip_summed
= CHECKSUM_NONE
;
946 ring
->csum_complete
--;
951 skb
->ip_summed
= ip_summed
;
952 skb
->protocol
= eth_type_trans(skb
, dev
);
953 skb_record_rx_queue(skb
, cq
->ring
);
955 if (l2_tunnel
&& ip_summed
== CHECKSUM_UNNECESSARY
)
958 if (dev
->features
& NETIF_F_RXHASH
)
960 be32_to_cpu(cqe
->immed_rss_invalid
),
961 (ip_summed
== CHECKSUM_UNNECESSARY
) ?
965 if ((be32_to_cpu(cqe
->vlan_my_qpn
) &
966 MLX4_CQE_CVLAN_PRESENT_MASK
) &&
967 (dev
->features
& NETIF_F_HW_VLAN_CTAG_RX
))
968 __vlan_hwaccel_put_tag(skb
, htons(ETH_P_8021Q
), be16_to_cpu(cqe
->sl_vid
));
969 else if ((be32_to_cpu(cqe
->vlan_my_qpn
) &
970 MLX4_CQE_SVLAN_PRESENT_MASK
) &&
971 (dev
->features
& NETIF_F_HW_VLAN_STAG_RX
))
972 __vlan_hwaccel_put_tag(skb
, htons(ETH_P_8021AD
),
973 be16_to_cpu(cqe
->sl_vid
));
975 if (ring
->hwtstamp_rx_filter
== HWTSTAMP_FILTER_ALL
) {
976 timestamp
= mlx4_en_get_cqe_ts(cqe
);
977 mlx4_en_fill_hwtstamps(mdev
, skb_hwtstamps(skb
),
981 napi_gro_receive(&cq
->napi
, skb
);
983 for (nr
= 0; nr
< priv
->num_frags
; nr
++)
984 mlx4_en_free_frag(priv
, frags
, nr
);
986 ++cq
->mcq
.cons_index
;
987 index
= (cq
->mcq
.cons_index
) & ring
->size_mask
;
988 cqe
= mlx4_en_get_cqe(cq
->buf
, index
, priv
->cqe_size
) + factor
;
989 if (++polled
== budget
)
994 AVG_PERF_COUNTER(priv
->pstats
.rx_coal_avg
, polled
);
995 mlx4_cq_set_ci(&cq
->mcq
);
996 wmb(); /* ensure HW sees CQ consumer before we post new buffers */
997 ring
->cons
= cq
->mcq
.cons_index
;
998 mlx4_en_refill_rx_buffers(priv
, ring
);
999 mlx4_en_update_rx_prod_db(ring
);
1004 void mlx4_en_rx_irq(struct mlx4_cq
*mcq
)
1006 struct mlx4_en_cq
*cq
= container_of(mcq
, struct mlx4_en_cq
, mcq
);
1007 struct mlx4_en_priv
*priv
= netdev_priv(cq
->dev
);
1009 if (likely(priv
->port_up
))
1010 napi_schedule_irqoff(&cq
->napi
);
1012 mlx4_en_arm_cq(priv
, cq
);
1015 /* Rx CQ polling - called by NAPI */
1016 int mlx4_en_poll_rx_cq(struct napi_struct
*napi
, int budget
)
1018 struct mlx4_en_cq
*cq
= container_of(napi
, struct mlx4_en_cq
, napi
);
1019 struct net_device
*dev
= cq
->dev
;
1020 struct mlx4_en_priv
*priv
= netdev_priv(dev
);
1023 done
= mlx4_en_process_rx_cq(dev
, cq
, budget
);
1025 /* If we used up all the quota - we're probably not done yet... */
1026 if (done
== budget
) {
1027 const struct cpumask
*aff
;
1028 struct irq_data
*idata
;
1031 INC_PERF_COUNTER(priv
->pstats
.napi_quota
);
1033 cpu_curr
= smp_processor_id();
1034 idata
= irq_desc_get_irq_data(cq
->irq_desc
);
1035 aff
= irq_data_get_affinity_mask(idata
);
1037 if (likely(cpumask_test_cpu(cpu_curr
, aff
)))
1040 /* Current cpu is not according to smp_irq_affinity -
1041 * probably affinity changed. need to stop this NAPI
1042 * poll, and restart it on the right CPU
1047 napi_complete_done(napi
, done
);
1048 mlx4_en_arm_cq(priv
, cq
);
1052 static const int frag_sizes
[] = {
1059 void mlx4_en_calc_rx_buf(struct net_device
*dev
)
1061 struct mlx4_en_priv
*priv
= netdev_priv(dev
);
1062 /* VLAN_HLEN is added twice,to support skb vlan tagged with multiple
1063 * headers. (For example: ETH_P_8021Q and ETH_P_8021AD).
1065 int eff_mtu
= dev
->mtu
+ ETH_HLEN
+ (2 * VLAN_HLEN
);
1069 while (buf_size
< eff_mtu
) {
1070 priv
->frag_info
[i
].frag_size
=
1071 (eff_mtu
> buf_size
+ frag_sizes
[i
]) ?
1072 frag_sizes
[i
] : eff_mtu
- buf_size
;
1073 priv
->frag_info
[i
].frag_prefix_size
= buf_size
;
1074 priv
->frag_info
[i
].frag_stride
=
1075 ALIGN(priv
->frag_info
[i
].frag_size
,
1077 buf_size
+= priv
->frag_info
[i
].frag_size
;
1081 priv
->num_frags
= i
;
1082 priv
->rx_skb_size
= eff_mtu
;
1083 priv
->log_rx_info
= ROUNDUP_LOG2(i
* sizeof(struct mlx4_en_rx_alloc
));
1085 en_dbg(DRV
, priv
, "Rx buffer scatter-list (effective-mtu:%d num_frags:%d):\n",
1086 eff_mtu
, priv
->num_frags
);
1087 for (i
= 0; i
< priv
->num_frags
; i
++) {
1089 " frag:%d - size:%d prefix:%d stride:%d\n",
1091 priv
->frag_info
[i
].frag_size
,
1092 priv
->frag_info
[i
].frag_prefix_size
,
1093 priv
->frag_info
[i
].frag_stride
);
1097 /* RSS related functions */
1099 static int mlx4_en_config_rss_qp(struct mlx4_en_priv
*priv
, int qpn
,
1100 struct mlx4_en_rx_ring
*ring
,
1101 enum mlx4_qp_state
*state
,
1104 struct mlx4_en_dev
*mdev
= priv
->mdev
;
1105 struct mlx4_qp_context
*context
;
1108 context
= kmalloc(sizeof(*context
), GFP_KERNEL
);
1112 err
= mlx4_qp_alloc(mdev
->dev
, qpn
, qp
, GFP_KERNEL
);
1114 en_err(priv
, "Failed to allocate qp #%x\n", qpn
);
1117 qp
->event
= mlx4_en_sqp_event
;
1119 memset(context
, 0, sizeof *context
);
1120 mlx4_en_fill_qp_context(priv
, ring
->actual_size
, ring
->stride
, 0, 0,
1121 qpn
, ring
->cqn
, -1, context
);
1122 context
->db_rec_addr
= cpu_to_be64(ring
->wqres
.db
.dma
);
1124 /* Cancel FCS removal if FW allows */
1125 if (mdev
->dev
->caps
.flags
& MLX4_DEV_CAP_FLAG_FCS_KEEP
) {
1126 context
->param3
|= cpu_to_be32(1 << 29);
1127 if (priv
->dev
->features
& NETIF_F_RXFCS
)
1130 ring
->fcs_del
= ETH_FCS_LEN
;
1134 err
= mlx4_qp_to_ready(mdev
->dev
, &ring
->wqres
.mtt
, context
, qp
, state
);
1136 mlx4_qp_remove(mdev
->dev
, qp
);
1137 mlx4_qp_free(mdev
->dev
, qp
);
1139 mlx4_en_update_rx_prod_db(ring
);
1145 int mlx4_en_create_drop_qp(struct mlx4_en_priv
*priv
)
1150 err
= mlx4_qp_reserve_range(priv
->mdev
->dev
, 1, 1, &qpn
,
1151 MLX4_RESERVE_A0_QP
);
1153 en_err(priv
, "Failed reserving drop qpn\n");
1156 err
= mlx4_qp_alloc(priv
->mdev
->dev
, qpn
, &priv
->drop_qp
, GFP_KERNEL
);
1158 en_err(priv
, "Failed allocating drop qp\n");
1159 mlx4_qp_release_range(priv
->mdev
->dev
, qpn
, 1);
1166 void mlx4_en_destroy_drop_qp(struct mlx4_en_priv
*priv
)
1170 qpn
= priv
->drop_qp
.qpn
;
1171 mlx4_qp_remove(priv
->mdev
->dev
, &priv
->drop_qp
);
1172 mlx4_qp_free(priv
->mdev
->dev
, &priv
->drop_qp
);
1173 mlx4_qp_release_range(priv
->mdev
->dev
, qpn
, 1);
1176 /* Allocate rx qp's and configure them according to rss map */
1177 int mlx4_en_config_rss_steer(struct mlx4_en_priv
*priv
)
1179 struct mlx4_en_dev
*mdev
= priv
->mdev
;
1180 struct mlx4_en_rss_map
*rss_map
= &priv
->rss_map
;
1181 struct mlx4_qp_context context
;
1182 struct mlx4_rss_context
*rss_context
;
1185 u8 rss_mask
= (MLX4_RSS_IPV4
| MLX4_RSS_TCP_IPV4
| MLX4_RSS_IPV6
|
1191 en_dbg(DRV
, priv
, "Configuring rss steering\n");
1192 err
= mlx4_qp_reserve_range(mdev
->dev
, priv
->rx_ring_num
,
1194 &rss_map
->base_qpn
, 0);
1196 en_err(priv
, "Failed reserving %d qps\n", priv
->rx_ring_num
);
1200 for (i
= 0; i
< priv
->rx_ring_num
; i
++) {
1201 qpn
= rss_map
->base_qpn
+ i
;
1202 err
= mlx4_en_config_rss_qp(priv
, qpn
, priv
->rx_ring
[i
],
1211 /* Configure RSS indirection qp */
1212 err
= mlx4_qp_alloc(mdev
->dev
, priv
->base_qpn
, &rss_map
->indir_qp
, GFP_KERNEL
);
1214 en_err(priv
, "Failed to allocate RSS indirection QP\n");
1217 rss_map
->indir_qp
.event
= mlx4_en_sqp_event
;
1218 mlx4_en_fill_qp_context(priv
, 0, 0, 0, 1, priv
->base_qpn
,
1219 priv
->rx_ring
[0]->cqn
, -1, &context
);
1221 if (!priv
->prof
->rss_rings
|| priv
->prof
->rss_rings
> priv
->rx_ring_num
)
1222 rss_rings
= priv
->rx_ring_num
;
1224 rss_rings
= priv
->prof
->rss_rings
;
1226 ptr
= ((void *) &context
) + offsetof(struct mlx4_qp_context
, pri_path
)
1227 + MLX4_RSS_OFFSET_IN_QPC_PRI_PATH
;
1229 rss_context
->base_qpn
= cpu_to_be32(ilog2(rss_rings
) << 24 |
1230 (rss_map
->base_qpn
));
1231 rss_context
->default_qpn
= cpu_to_be32(rss_map
->base_qpn
);
1232 if (priv
->mdev
->profile
.udp_rss
) {
1233 rss_mask
|= MLX4_RSS_UDP_IPV4
| MLX4_RSS_UDP_IPV6
;
1234 rss_context
->base_qpn_udp
= rss_context
->default_qpn
;
1237 if (mdev
->dev
->caps
.tunnel_offload_mode
== MLX4_TUNNEL_OFFLOAD_MODE_VXLAN
) {
1238 en_info(priv
, "Setting RSS context tunnel type to RSS on inner headers\n");
1239 rss_mask
|= MLX4_RSS_BY_INNER_HEADERS
;
1242 rss_context
->flags
= rss_mask
;
1243 rss_context
->hash_fn
= MLX4_RSS_HASH_TOP
;
1244 if (priv
->rss_hash_fn
== ETH_RSS_HASH_XOR
) {
1245 rss_context
->hash_fn
= MLX4_RSS_HASH_XOR
;
1246 } else if (priv
->rss_hash_fn
== ETH_RSS_HASH_TOP
) {
1247 rss_context
->hash_fn
= MLX4_RSS_HASH_TOP
;
1248 memcpy(rss_context
->rss_key
, priv
->rss_key
,
1249 MLX4_EN_RSS_KEY_SIZE
);
1251 en_err(priv
, "Unknown RSS hash function requested\n");
1255 err
= mlx4_qp_to_ready(mdev
->dev
, &priv
->res
.mtt
, &context
,
1256 &rss_map
->indir_qp
, &rss_map
->indir_state
);
1263 mlx4_qp_modify(mdev
->dev
, NULL
, rss_map
->indir_state
,
1264 MLX4_QP_STATE_RST
, NULL
, 0, 0, &rss_map
->indir_qp
);
1265 mlx4_qp_remove(mdev
->dev
, &rss_map
->indir_qp
);
1266 mlx4_qp_free(mdev
->dev
, &rss_map
->indir_qp
);
1268 for (i
= 0; i
< good_qps
; i
++) {
1269 mlx4_qp_modify(mdev
->dev
, NULL
, rss_map
->state
[i
],
1270 MLX4_QP_STATE_RST
, NULL
, 0, 0, &rss_map
->qps
[i
]);
1271 mlx4_qp_remove(mdev
->dev
, &rss_map
->qps
[i
]);
1272 mlx4_qp_free(mdev
->dev
, &rss_map
->qps
[i
]);
1274 mlx4_qp_release_range(mdev
->dev
, rss_map
->base_qpn
, priv
->rx_ring_num
);
1278 void mlx4_en_release_rss_steer(struct mlx4_en_priv
*priv
)
1280 struct mlx4_en_dev
*mdev
= priv
->mdev
;
1281 struct mlx4_en_rss_map
*rss_map
= &priv
->rss_map
;
1284 mlx4_qp_modify(mdev
->dev
, NULL
, rss_map
->indir_state
,
1285 MLX4_QP_STATE_RST
, NULL
, 0, 0, &rss_map
->indir_qp
);
1286 mlx4_qp_remove(mdev
->dev
, &rss_map
->indir_qp
);
1287 mlx4_qp_free(mdev
->dev
, &rss_map
->indir_qp
);
1289 for (i
= 0; i
< priv
->rx_ring_num
; i
++) {
1290 mlx4_qp_modify(mdev
->dev
, NULL
, rss_map
->state
[i
],
1291 MLX4_QP_STATE_RST
, NULL
, 0, 0, &rss_map
->qps
[i
]);
1292 mlx4_qp_remove(mdev
->dev
, &rss_map
->qps
[i
]);
1293 mlx4_qp_free(mdev
->dev
, &rss_map
->qps
[i
]);
1295 mlx4_qp_release_range(mdev
->dev
, rss_map
->base_qpn
, priv
->rx_ring_num
);