2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <linux/mlx4/cq.h>
36 #include <linux/slab.h>
37 #include <linux/mlx4/qp.h>
38 #include <linux/skbuff.h>
39 #include <linux/if_vlan.h>
40 #include <linux/prefetch.h>
41 #include <linux/vmalloc.h>
42 #include <linux/tcp.h>
44 #include <linux/ipv6.h>
45 #include <linux/moduleparam.h>
49 int mlx4_en_create_tx_ring(struct mlx4_en_priv
*priv
,
50 struct mlx4_en_tx_ring
**pring
, u32 size
,
51 u16 stride
, int node
, int queue_index
)
53 struct mlx4_en_dev
*mdev
= priv
->mdev
;
54 struct mlx4_en_tx_ring
*ring
;
58 ring
= kzalloc_node(sizeof(*ring
), GFP_KERNEL
, node
);
60 ring
= kzalloc(sizeof(*ring
), GFP_KERNEL
);
62 en_err(priv
, "Failed allocating TX ring\n");
68 ring
->size_mask
= size
- 1;
69 ring
->stride
= stride
;
70 ring
->full_size
= ring
->size
- HEADROOM
- MAX_DESC_TXBBS
;
72 tmp
= size
* sizeof(struct mlx4_en_tx_info
);
73 ring
->tx_info
= kmalloc_node(tmp
, GFP_KERNEL
| __GFP_NOWARN
, node
);
75 ring
->tx_info
= vmalloc(tmp
);
82 en_dbg(DRV
, priv
, "Allocated tx_info ring at addr:%p size:%d\n",
85 ring
->bounce_buf
= kmalloc_node(MAX_DESC_SIZE
, GFP_KERNEL
, node
);
86 if (!ring
->bounce_buf
) {
87 ring
->bounce_buf
= kmalloc(MAX_DESC_SIZE
, GFP_KERNEL
);
88 if (!ring
->bounce_buf
) {
93 ring
->buf_size
= ALIGN(size
* ring
->stride
, MLX4_EN_PAGE_SIZE
);
95 /* Allocate HW buffers on provided NUMA node */
96 set_dev_node(&mdev
->dev
->persist
->pdev
->dev
, node
);
97 err
= mlx4_alloc_hwq_res(mdev
->dev
, &ring
->wqres
, ring
->buf_size
);
98 set_dev_node(&mdev
->dev
->persist
->pdev
->dev
, mdev
->dev
->numa_node
);
100 en_err(priv
, "Failed allocating hwq resources\n");
104 ring
->buf
= ring
->wqres
.buf
.direct
.buf
;
106 en_dbg(DRV
, priv
, "Allocated TX ring (addr:%p) - buf:%p size:%d buf_size:%d dma:%llx\n",
107 ring
, ring
->buf
, ring
->size
, ring
->buf_size
,
108 (unsigned long long) ring
->wqres
.buf
.direct
.map
);
110 err
= mlx4_qp_reserve_range(mdev
->dev
, 1, 1, &ring
->qpn
,
111 MLX4_RESERVE_ETH_BF_QP
);
113 en_err(priv
, "failed reserving qp for TX ring\n");
117 err
= mlx4_qp_alloc(mdev
->dev
, ring
->qpn
, &ring
->qp
, GFP_KERNEL
);
119 en_err(priv
, "Failed allocating qp %d\n", ring
->qpn
);
122 ring
->qp
.event
= mlx4_en_sqp_event
;
124 err
= mlx4_bf_alloc(mdev
->dev
, &ring
->bf
, node
);
126 en_dbg(DRV
, priv
, "working without blueflame (%d)\n", err
);
127 ring
->bf
.uar
= &mdev
->priv_uar
;
128 ring
->bf
.uar
->map
= mdev
->uar_map
;
129 ring
->bf_enabled
= false;
130 ring
->bf_alloced
= false;
131 priv
->pflags
&= ~MLX4_EN_PRIV_FLAGS_BLUEFLAME
;
133 ring
->bf_alloced
= true;
134 ring
->bf_enabled
= !!(priv
->pflags
&
135 MLX4_EN_PRIV_FLAGS_BLUEFLAME
);
138 ring
->hwtstamp_tx_type
= priv
->hwtstamp_config
.tx_type
;
139 ring
->queue_index
= queue_index
;
141 if (queue_index
< priv
->num_tx_rings_p_up
)
142 cpumask_set_cpu(cpumask_local_spread(queue_index
,
143 priv
->mdev
->dev
->numa_node
),
144 &ring
->affinity_mask
);
150 mlx4_qp_release_range(mdev
->dev
, ring
->qpn
, 1);
152 mlx4_free_hwq_res(mdev
->dev
, &ring
->wqres
, ring
->buf_size
);
154 kfree(ring
->bounce_buf
);
155 ring
->bounce_buf
= NULL
;
157 kvfree(ring
->tx_info
);
158 ring
->tx_info
= NULL
;
165 void mlx4_en_destroy_tx_ring(struct mlx4_en_priv
*priv
,
166 struct mlx4_en_tx_ring
**pring
)
168 struct mlx4_en_dev
*mdev
= priv
->mdev
;
169 struct mlx4_en_tx_ring
*ring
= *pring
;
170 en_dbg(DRV
, priv
, "Destroying tx ring, qpn: %d\n", ring
->qpn
);
172 if (ring
->bf_alloced
)
173 mlx4_bf_free(mdev
->dev
, &ring
->bf
);
174 mlx4_qp_remove(mdev
->dev
, &ring
->qp
);
175 mlx4_qp_free(mdev
->dev
, &ring
->qp
);
176 mlx4_qp_release_range(priv
->mdev
->dev
, ring
->qpn
, 1);
177 mlx4_free_hwq_res(mdev
->dev
, &ring
->wqres
, ring
->buf_size
);
178 kfree(ring
->bounce_buf
);
179 ring
->bounce_buf
= NULL
;
180 kvfree(ring
->tx_info
);
181 ring
->tx_info
= NULL
;
186 int mlx4_en_activate_tx_ring(struct mlx4_en_priv
*priv
,
187 struct mlx4_en_tx_ring
*ring
,
188 int cq
, int user_prio
)
190 struct mlx4_en_dev
*mdev
= priv
->mdev
;
195 ring
->cons
= 0xffffffff;
196 ring
->last_nr_txbb
= 1;
197 memset(ring
->tx_info
, 0, ring
->size
* sizeof(struct mlx4_en_tx_info
));
198 memset(ring
->buf
, 0, ring
->buf_size
);
200 ring
->qp_state
= MLX4_QP_STATE_RST
;
201 ring
->doorbell_qpn
= cpu_to_be32(ring
->qp
.qpn
<< 8);
202 ring
->mr_key
= cpu_to_be32(mdev
->mr
.key
);
204 mlx4_en_fill_qp_context(priv
, ring
->size
, ring
->stride
, 1, 0, ring
->qpn
,
205 ring
->cqn
, user_prio
, &ring
->context
);
206 if (ring
->bf_alloced
)
207 ring
->context
.usr_page
=
208 cpu_to_be32(mlx4_to_hw_uar_index(mdev
->dev
,
209 ring
->bf
.uar
->index
));
211 err
= mlx4_qp_to_ready(mdev
->dev
, &ring
->wqres
.mtt
, &ring
->context
,
212 &ring
->qp
, &ring
->qp_state
);
213 if (!cpumask_empty(&ring
->affinity_mask
))
214 netif_set_xps_queue(priv
->dev
, &ring
->affinity_mask
,
220 void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv
*priv
,
221 struct mlx4_en_tx_ring
*ring
)
223 struct mlx4_en_dev
*mdev
= priv
->mdev
;
225 mlx4_qp_modify(mdev
->dev
, NULL
, ring
->qp_state
,
226 MLX4_QP_STATE_RST
, NULL
, 0, 0, &ring
->qp
);
229 static inline bool mlx4_en_is_tx_ring_full(struct mlx4_en_tx_ring
*ring
)
231 return ring
->prod
- ring
->cons
> ring
->full_size
;
234 static void mlx4_en_stamp_wqe(struct mlx4_en_priv
*priv
,
235 struct mlx4_en_tx_ring
*ring
, int index
,
238 __be32 stamp
= cpu_to_be32(STAMP_VAL
| (!!owner
<< STAMP_SHIFT
));
239 struct mlx4_en_tx_desc
*tx_desc
= ring
->buf
+ index
* TXBB_SIZE
;
240 struct mlx4_en_tx_info
*tx_info
= &ring
->tx_info
[index
];
241 void *end
= ring
->buf
+ ring
->buf_size
;
242 __be32
*ptr
= (__be32
*)tx_desc
;
245 /* Optimize the common case when there are no wraparounds */
246 if (likely((void *)tx_desc
+ tx_info
->nr_txbb
* TXBB_SIZE
<= end
)) {
247 /* Stamp the freed descriptor */
248 for (i
= 0; i
< tx_info
->nr_txbb
* TXBB_SIZE
;
254 /* Stamp the freed descriptor */
255 for (i
= 0; i
< tx_info
->nr_txbb
* TXBB_SIZE
;
259 if ((void *)ptr
>= end
) {
261 stamp
^= cpu_to_be32(0x80000000);
268 static u32
mlx4_en_free_tx_desc(struct mlx4_en_priv
*priv
,
269 struct mlx4_en_tx_ring
*ring
,
270 int index
, u8 owner
, u64 timestamp
,
273 struct mlx4_en_tx_info
*tx_info
= &ring
->tx_info
[index
];
274 struct mlx4_en_tx_desc
*tx_desc
= ring
->buf
+ index
* TXBB_SIZE
;
275 struct mlx4_wqe_data_seg
*data
= (void *) tx_desc
+ tx_info
->data_offset
;
276 void *end
= ring
->buf
+ ring
->buf_size
;
277 struct sk_buff
*skb
= tx_info
->skb
;
278 int nr_maps
= tx_info
->nr_maps
;
281 /* We do not touch skb here, so prefetch skb->users location
282 * to speedup consume_skb()
284 prefetchw(&skb
->users
);
286 if (unlikely(timestamp
)) {
287 struct skb_shared_hwtstamps hwts
;
289 mlx4_en_fill_hwtstamps(priv
->mdev
, &hwts
, timestamp
);
290 skb_tstamp_tx(skb
, &hwts
);
293 /* Optimize the common case when there are no wraparounds */
294 if (likely((void *) tx_desc
+ tx_info
->nr_txbb
* TXBB_SIZE
<= end
)) {
297 dma_unmap_single(priv
->ddev
,
299 tx_info
->map0_byte_count
,
302 dma_unmap_page(priv
->ddev
,
304 tx_info
->map0_byte_count
,
306 for (i
= 1; i
< nr_maps
; i
++) {
308 dma_unmap_page(priv
->ddev
,
309 (dma_addr_t
)be64_to_cpu(data
->addr
),
310 be32_to_cpu(data
->byte_count
),
316 if ((void *) data
>= end
) {
317 data
= ring
->buf
+ ((void *)data
- end
);
321 dma_unmap_single(priv
->ddev
,
323 tx_info
->map0_byte_count
,
326 dma_unmap_page(priv
->ddev
,
328 tx_info
->map0_byte_count
,
330 for (i
= 1; i
< nr_maps
; i
++) {
332 /* Check for wraparound before unmapping */
333 if ((void *) data
>= end
)
335 dma_unmap_page(priv
->ddev
,
336 (dma_addr_t
)be64_to_cpu(data
->addr
),
337 be32_to_cpu(data
->byte_count
),
342 napi_consume_skb(skb
, napi_mode
);
344 return tx_info
->nr_txbb
;
348 int mlx4_en_free_tx_buf(struct net_device
*dev
, struct mlx4_en_tx_ring
*ring
)
350 struct mlx4_en_priv
*priv
= netdev_priv(dev
);
353 /* Skip last polled descriptor */
354 ring
->cons
+= ring
->last_nr_txbb
;
355 en_dbg(DRV
, priv
, "Freeing Tx buf - cons:0x%x prod:0x%x\n",
356 ring
->cons
, ring
->prod
);
358 if ((u32
) (ring
->prod
- ring
->cons
) > ring
->size
) {
359 if (netif_msg_tx_err(priv
))
360 en_warn(priv
, "Tx consumer passed producer!\n");
364 while (ring
->cons
!= ring
->prod
) {
365 ring
->last_nr_txbb
= mlx4_en_free_tx_desc(priv
, ring
,
366 ring
->cons
& ring
->size_mask
,
367 !!(ring
->cons
& ring
->size
), 0,
368 0 /* Non-NAPI caller */);
369 ring
->cons
+= ring
->last_nr_txbb
;
373 netdev_tx_reset_queue(ring
->tx_queue
);
376 en_dbg(DRV
, priv
, "Freed %d uncompleted tx descriptors\n", cnt
);
381 static bool mlx4_en_process_tx_cq(struct net_device
*dev
,
382 struct mlx4_en_cq
*cq
, int napi_budget
)
384 struct mlx4_en_priv
*priv
= netdev_priv(dev
);
385 struct mlx4_cq
*mcq
= &cq
->mcq
;
386 struct mlx4_en_tx_ring
*ring
= priv
->tx_ring
[cq
->ring
];
387 struct mlx4_cqe
*cqe
;
389 u16 new_index
, ring_index
, stamp_index
;
390 u32 txbbs_skipped
= 0;
392 u32 cons_index
= mcq
->cons_index
;
394 u32 size_mask
= ring
->size_mask
;
395 struct mlx4_cqe
*buf
= cq
->buf
;
398 int factor
= priv
->cqe_factor
;
400 int budget
= priv
->tx_work_limit
;
407 netdev_txq_bql_complete_prefetchw(ring
->tx_queue
);
409 index
= cons_index
& size_mask
;
410 cqe
= mlx4_en_get_cqe(buf
, index
, priv
->cqe_size
) + factor
;
411 last_nr_txbb
= ACCESS_ONCE(ring
->last_nr_txbb
);
412 ring_cons
= ACCESS_ONCE(ring
->cons
);
413 ring_index
= ring_cons
& size_mask
;
414 stamp_index
= ring_index
;
416 /* Process all completed CQEs */
417 while (XNOR(cqe
->owner_sr_opcode
& MLX4_CQE_OWNER_MASK
,
418 cons_index
& size
) && (done
< budget
)) {
420 * make sure we read the CQE after we read the
425 if (unlikely((cqe
->owner_sr_opcode
& MLX4_CQE_OPCODE_MASK
) ==
426 MLX4_CQE_OPCODE_ERROR
)) {
427 struct mlx4_err_cqe
*cqe_err
= (struct mlx4_err_cqe
*)cqe
;
429 en_err(priv
, "CQE error - vendor syndrome: 0x%x syndrome: 0x%x\n",
430 cqe_err
->vendor_err_syndrome
,
434 /* Skip over last polled CQE */
435 new_index
= be16_to_cpu(cqe
->wqe_index
) & size_mask
;
440 txbbs_skipped
+= last_nr_txbb
;
441 ring_index
= (ring_index
+ last_nr_txbb
) & size_mask
;
443 if (unlikely(ring
->tx_info
[ring_index
].ts_requested
))
444 timestamp
= mlx4_en_get_cqe_ts(cqe
);
446 /* free next descriptor */
447 last_nr_txbb
= mlx4_en_free_tx_desc(
448 priv
, ring
, ring_index
,
449 !!((ring_cons
+ txbbs_skipped
) &
450 ring
->size
), timestamp
, napi_budget
);
452 mlx4_en_stamp_wqe(priv
, ring
, stamp_index
,
453 !!((ring_cons
+ txbbs_stamp
) &
455 stamp_index
= ring_index
;
456 txbbs_stamp
= txbbs_skipped
;
458 bytes
+= ring
->tx_info
[ring_index
].nr_bytes
;
459 } while ((++done
< budget
) && (ring_index
!= new_index
));
462 index
= cons_index
& size_mask
;
463 cqe
= mlx4_en_get_cqe(buf
, index
, priv
->cqe_size
) + factor
;
468 * To prevent CQ overflow we first update CQ consumer and only then
471 mcq
->cons_index
= cons_index
;
475 /* we want to dirty this cache line once */
476 ACCESS_ONCE(ring
->last_nr_txbb
) = last_nr_txbb
;
477 ACCESS_ONCE(ring
->cons
) = ring_cons
+ txbbs_skipped
;
479 netdev_tx_completed_queue(ring
->tx_queue
, packets
, bytes
);
481 /* Wakeup Tx queue if this stopped, and ring is not full.
483 if (netif_tx_queue_stopped(ring
->tx_queue
) &&
484 !mlx4_en_is_tx_ring_full(ring
)) {
485 netif_tx_wake_queue(ring
->tx_queue
);
488 return done
< budget
;
491 void mlx4_en_tx_irq(struct mlx4_cq
*mcq
)
493 struct mlx4_en_cq
*cq
= container_of(mcq
, struct mlx4_en_cq
, mcq
);
494 struct mlx4_en_priv
*priv
= netdev_priv(cq
->dev
);
496 if (likely(priv
->port_up
))
497 napi_schedule_irqoff(&cq
->napi
);
499 mlx4_en_arm_cq(priv
, cq
);
502 /* TX CQ polling - called by NAPI */
503 int mlx4_en_poll_tx_cq(struct napi_struct
*napi
, int budget
)
505 struct mlx4_en_cq
*cq
= container_of(napi
, struct mlx4_en_cq
, napi
);
506 struct net_device
*dev
= cq
->dev
;
507 struct mlx4_en_priv
*priv
= netdev_priv(dev
);
510 clean_complete
= mlx4_en_process_tx_cq(dev
, cq
, budget
);
515 mlx4_en_arm_cq(priv
, cq
);
520 static struct mlx4_en_tx_desc
*mlx4_en_bounce_to_desc(struct mlx4_en_priv
*priv
,
521 struct mlx4_en_tx_ring
*ring
,
523 unsigned int desc_size
)
525 u32 copy
= (ring
->size
- index
) * TXBB_SIZE
;
528 for (i
= desc_size
- copy
- 4; i
>= 0; i
-= 4) {
529 if ((i
& (TXBB_SIZE
- 1)) == 0)
532 *((u32
*) (ring
->buf
+ i
)) =
533 *((u32
*) (ring
->bounce_buf
+ copy
+ i
));
536 for (i
= copy
- 4; i
>= 4 ; i
-= 4) {
537 if ((i
& (TXBB_SIZE
- 1)) == 0)
540 *((u32
*) (ring
->buf
+ index
* TXBB_SIZE
+ i
)) =
541 *((u32
*) (ring
->bounce_buf
+ i
));
544 /* Return real descriptor location */
545 return ring
->buf
+ index
* TXBB_SIZE
;
548 /* Decide if skb can be inlined in tx descriptor to avoid dma mapping
550 * It seems strange we do not simply use skb_copy_bits().
551 * This would allow to inline all skbs iff skb->len <= inline_thold
553 * Note that caller already checked skb was not a gso packet
555 static bool is_inline(int inline_thold
, const struct sk_buff
*skb
,
556 const struct skb_shared_info
*shinfo
,
561 if (skb
->len
> inline_thold
|| !inline_thold
)
564 if (shinfo
->nr_frags
== 1) {
565 ptr
= skb_frag_address_safe(&shinfo
->frags
[0]);
571 if (shinfo
->nr_frags
)
576 static int inline_size(const struct sk_buff
*skb
)
578 if (skb
->len
+ CTRL_SIZE
+ sizeof(struct mlx4_wqe_inline_seg
)
579 <= MLX4_INLINE_ALIGN
)
580 return ALIGN(skb
->len
+ CTRL_SIZE
+
581 sizeof(struct mlx4_wqe_inline_seg
), 16);
583 return ALIGN(skb
->len
+ CTRL_SIZE
+ 2 *
584 sizeof(struct mlx4_wqe_inline_seg
), 16);
587 static int get_real_size(const struct sk_buff
*skb
,
588 const struct skb_shared_info
*shinfo
,
589 struct net_device
*dev
,
590 int *lso_header_size
,
594 struct mlx4_en_priv
*priv
= netdev_priv(dev
);
597 if (shinfo
->gso_size
) {
599 if (skb
->encapsulation
)
600 *lso_header_size
= (skb_inner_transport_header(skb
) - skb
->data
) + inner_tcp_hdrlen(skb
);
602 *lso_header_size
= skb_transport_offset(skb
) + tcp_hdrlen(skb
);
603 real_size
= CTRL_SIZE
+ shinfo
->nr_frags
* DS_SIZE
+
604 ALIGN(*lso_header_size
+ 4, DS_SIZE
);
605 if (unlikely(*lso_header_size
!= skb_headlen(skb
))) {
606 /* We add a segment for the skb linear buffer only if
607 * it contains data */
608 if (*lso_header_size
< skb_headlen(skb
))
609 real_size
+= DS_SIZE
;
611 if (netif_msg_tx_err(priv
))
612 en_warn(priv
, "Non-linear headers\n");
617 *lso_header_size
= 0;
618 *inline_ok
= is_inline(priv
->prof
->inline_thold
, skb
,
622 real_size
= inline_size(skb
);
624 real_size
= CTRL_SIZE
+
625 (shinfo
->nr_frags
+ 1) * DS_SIZE
;
631 static void build_inline_wqe(struct mlx4_en_tx_desc
*tx_desc
,
632 const struct sk_buff
*skb
,
633 const struct skb_shared_info
*shinfo
,
634 int real_size
, u16
*vlan_tag
,
635 int tx_ind
, void *fragptr
)
637 struct mlx4_wqe_inline_seg
*inl
= &tx_desc
->inl
;
638 int spc
= MLX4_INLINE_ALIGN
- CTRL_SIZE
- sizeof *inl
;
639 unsigned int hlen
= skb_headlen(skb
);
641 if (skb
->len
<= spc
) {
642 if (likely(skb
->len
>= MIN_PKT_LEN
)) {
643 inl
->byte_count
= cpu_to_be32(1 << 31 | skb
->len
);
645 inl
->byte_count
= cpu_to_be32(1 << 31 | MIN_PKT_LEN
);
646 memset(((void *)(inl
+ 1)) + skb
->len
, 0,
647 MIN_PKT_LEN
- skb
->len
);
649 skb_copy_from_linear_data(skb
, inl
+ 1, hlen
);
650 if (shinfo
->nr_frags
)
651 memcpy(((void *)(inl
+ 1)) + hlen
, fragptr
,
652 skb_frag_size(&shinfo
->frags
[0]));
655 inl
->byte_count
= cpu_to_be32(1 << 31 | spc
);
657 skb_copy_from_linear_data(skb
, inl
+ 1, hlen
);
659 memcpy(((void *)(inl
+ 1)) + hlen
,
660 fragptr
, spc
- hlen
);
661 fragptr
+= spc
- hlen
;
663 inl
= (void *) (inl
+ 1) + spc
;
664 memcpy(((void *)(inl
+ 1)), fragptr
, skb
->len
- spc
);
666 skb_copy_from_linear_data(skb
, inl
+ 1, spc
);
667 inl
= (void *) (inl
+ 1) + spc
;
668 skb_copy_from_linear_data_offset(skb
, spc
, inl
+ 1,
670 if (shinfo
->nr_frags
)
671 memcpy(((void *)(inl
+ 1)) + hlen
- spc
,
673 skb_frag_size(&shinfo
->frags
[0]));
677 inl
->byte_count
= cpu_to_be32(1 << 31 | (skb
->len
- spc
));
681 u16
mlx4_en_select_queue(struct net_device
*dev
, struct sk_buff
*skb
,
682 void *accel_priv
, select_queue_fallback_t fallback
)
684 struct mlx4_en_priv
*priv
= netdev_priv(dev
);
685 u16 rings_p_up
= priv
->num_tx_rings_p_up
;
689 return skb_tx_hash(dev
, skb
);
691 if (skb_vlan_tag_present(skb
))
692 up
= skb_vlan_tag_get(skb
) >> VLAN_PRIO_SHIFT
;
694 return fallback(dev
, skb
) % rings_p_up
+ up
* rings_p_up
;
697 static void mlx4_bf_copy(void __iomem
*dst
, const void *src
,
698 unsigned int bytecnt
)
700 __iowrite64_copy(dst
, src
, bytecnt
/ 8);
703 netdev_tx_t
mlx4_en_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
705 struct skb_shared_info
*shinfo
= skb_shinfo(skb
);
706 struct mlx4_en_priv
*priv
= netdev_priv(dev
);
707 struct device
*ddev
= priv
->ddev
;
708 struct mlx4_en_tx_ring
*ring
;
709 struct mlx4_en_tx_desc
*tx_desc
;
710 struct mlx4_wqe_data_seg
*data
;
711 struct mlx4_en_tx_info
*tx_info
;
722 void *fragptr
= NULL
;
729 tx_ind
= skb_get_queue_mapping(skb
);
730 ring
= priv
->tx_ring
[tx_ind
];
735 /* fetch ring->cons far ahead before needing it to avoid stall */
736 ring_cons
= ACCESS_ONCE(ring
->cons
);
738 real_size
= get_real_size(skb
, shinfo
, dev
, &lso_header_size
,
739 &inline_ok
, &fragptr
);
740 if (unlikely(!real_size
))
743 /* Align descriptor to TXBB size */
744 desc_size
= ALIGN(real_size
, TXBB_SIZE
);
745 nr_txbb
= desc_size
/ TXBB_SIZE
;
746 if (unlikely(nr_txbb
> MAX_DESC_TXBBS
)) {
747 if (netif_msg_tx_err(priv
))
748 en_warn(priv
, "Oversized header or SG list\n");
752 if (skb_vlan_tag_present(skb
)) {
753 vlan_tag
= skb_vlan_tag_get(skb
);
754 vlan_proto
= be16_to_cpu(skb
->vlan_proto
);
757 netdev_txq_bql_enqueue_prefetchw(ring
->tx_queue
);
759 /* Track current inflight packets for performance analysis */
760 AVG_PERF_COUNTER(priv
->pstats
.inflight_avg
,
761 (u32
)(ring
->prod
- ring_cons
- 1));
763 /* Packet is good - grab an index and transmit it */
764 index
= ring
->prod
& ring
->size_mask
;
765 bf_index
= ring
->prod
;
767 /* See if we have enough space for whole descriptor TXBB for setting
768 * SW ownership on next descriptor; if not, use a bounce buffer. */
769 if (likely(index
+ nr_txbb
<= ring
->size
))
770 tx_desc
= ring
->buf
+ index
* TXBB_SIZE
;
772 tx_desc
= (struct mlx4_en_tx_desc
*) ring
->bounce_buf
;
776 /* Save skb in tx_info ring */
777 tx_info
= &ring
->tx_info
[index
];
779 tx_info
->nr_txbb
= nr_txbb
;
781 data
= &tx_desc
->data
;
783 data
= ((void *)&tx_desc
->lso
+ ALIGN(lso_header_size
+ 4,
786 /* valid only for none inline segments */
787 tx_info
->data_offset
= (void *)data
- (void *)tx_desc
;
789 tx_info
->inl
= inline_ok
;
791 tx_info
->linear
= (lso_header_size
< skb_headlen(skb
) &&
794 tx_info
->nr_maps
= shinfo
->nr_frags
+ tx_info
->linear
;
795 data
+= tx_info
->nr_maps
- 1;
801 /* Map fragments if any */
802 for (i_frag
= shinfo
->nr_frags
- 1; i_frag
>= 0; i_frag
--) {
803 const struct skb_frag_struct
*frag
;
805 frag
= &shinfo
->frags
[i_frag
];
806 byte_count
= skb_frag_size(frag
);
807 dma
= skb_frag_dma_map(ddev
, frag
,
810 if (dma_mapping_error(ddev
, dma
))
813 data
->addr
= cpu_to_be64(dma
);
814 data
->lkey
= ring
->mr_key
;
816 data
->byte_count
= cpu_to_be32(byte_count
);
820 /* Map linear part if needed */
821 if (tx_info
->linear
) {
822 byte_count
= skb_headlen(skb
) - lso_header_size
;
824 dma
= dma_map_single(ddev
, skb
->data
+
825 lso_header_size
, byte_count
,
827 if (dma_mapping_error(ddev
, dma
))
830 data
->addr
= cpu_to_be64(dma
);
831 data
->lkey
= ring
->mr_key
;
833 data
->byte_count
= cpu_to_be32(byte_count
);
835 /* tx completion can avoid cache line miss for common cases */
836 tx_info
->map0_dma
= dma
;
837 tx_info
->map0_byte_count
= byte_count
;
841 * For timestamping add flag to skb_shinfo and
842 * set flag for further reference
844 tx_info
->ts_requested
= 0;
845 if (unlikely(ring
->hwtstamp_tx_type
== HWTSTAMP_TX_ON
&&
846 shinfo
->tx_flags
& SKBTX_HW_TSTAMP
)) {
847 shinfo
->tx_flags
|= SKBTX_IN_PROGRESS
;
848 tx_info
->ts_requested
= 1;
851 /* Prepare ctrl segement apart opcode+ownership, which depends on
852 * whether LSO is used */
853 tx_desc
->ctrl
.srcrb_flags
= priv
->ctrl_flags
;
854 if (likely(skb
->ip_summed
== CHECKSUM_PARTIAL
)) {
855 if (!skb
->encapsulation
)
856 tx_desc
->ctrl
.srcrb_flags
|= cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM
|
857 MLX4_WQE_CTRL_TCP_UDP_CSUM
);
859 tx_desc
->ctrl
.srcrb_flags
|= cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM
);
863 if (priv
->flags
& MLX4_EN_FLAG_ENABLE_HW_LOOPBACK
) {
866 /* Copy dst mac address to wqe. This allows loopback in eSwitch,
867 * so that VFs and PF can communicate with each other
869 ethh
= (struct ethhdr
*)skb
->data
;
870 tx_desc
->ctrl
.srcrb_flags16
[0] = get_unaligned((__be16
*)ethh
->h_dest
);
871 tx_desc
->ctrl
.imm
= get_unaligned((__be32
*)(ethh
->h_dest
+ 2));
874 /* Handle LSO (TSO) packets */
875 if (lso_header_size
) {
878 /* Mark opcode as LSO */
879 op_own
= cpu_to_be32(MLX4_OPCODE_LSO
| (1 << 6)) |
880 ((ring
->prod
& ring
->size
) ?
881 cpu_to_be32(MLX4_EN_BIT_DESC_OWN
) : 0);
883 /* Fill in the LSO prefix */
884 tx_desc
->lso
.mss_hdr_size
= cpu_to_be32(
885 shinfo
->gso_size
<< 16 | lso_header_size
);
888 * note that we already verified that it is linear */
889 memcpy(tx_desc
->lso
.header
, skb
->data
, lso_header_size
);
893 i
= ((skb
->len
- lso_header_size
) / shinfo
->gso_size
) +
894 !!((skb
->len
- lso_header_size
) % shinfo
->gso_size
);
895 tx_info
->nr_bytes
= skb
->len
+ (i
- 1) * lso_header_size
;
898 /* Normal (Non LSO) packet */
899 op_own
= cpu_to_be32(MLX4_OPCODE_SEND
) |
900 ((ring
->prod
& ring
->size
) ?
901 cpu_to_be32(MLX4_EN_BIT_DESC_OWN
) : 0);
902 tx_info
->nr_bytes
= max_t(unsigned int, skb
->len
, ETH_ZLEN
);
905 ring
->bytes
+= tx_info
->nr_bytes
;
906 netdev_tx_sent_queue(ring
->tx_queue
, tx_info
->nr_bytes
);
907 AVG_PERF_COUNTER(priv
->pstats
.tx_pktsz_avg
, skb
->len
);
910 build_inline_wqe(tx_desc
, skb
, shinfo
, real_size
, &vlan_tag
,
913 if (skb
->encapsulation
) {
921 ip
.hdr
= skb_inner_network_header(skb
);
922 proto
= (ip
.v4
->version
== 4) ? ip
.v4
->protocol
:
925 if (proto
== IPPROTO_TCP
|| proto
== IPPROTO_UDP
)
926 op_own
|= cpu_to_be32(MLX4_WQE_CTRL_IIP
| MLX4_WQE_CTRL_ILP
);
928 op_own
|= cpu_to_be32(MLX4_WQE_CTRL_IIP
);
931 ring
->prod
+= nr_txbb
;
933 /* If we used a bounce buffer then copy descriptor back into place */
934 if (unlikely(bounce
))
935 tx_desc
= mlx4_en_bounce_to_desc(priv
, ring
, index
, desc_size
);
937 skb_tx_timestamp(skb
);
939 /* Check available TXBBs And 2K spare for prefetch */
940 stop_queue
= mlx4_en_is_tx_ring_full(ring
);
941 if (unlikely(stop_queue
)) {
942 netif_tx_stop_queue(ring
->tx_queue
);
943 ring
->queue_stopped
++;
945 send_doorbell
= !skb
->xmit_more
|| netif_xmit_stopped(ring
->tx_queue
);
947 real_size
= (real_size
/ 16) & 0x3f;
949 if (ring
->bf_enabled
&& desc_size
<= MAX_BF
&& !bounce
&&
950 !skb_vlan_tag_present(skb
) && send_doorbell
) {
951 tx_desc
->ctrl
.bf_qpn
= ring
->doorbell_qpn
|
952 cpu_to_be32(real_size
);
954 op_own
|= htonl((bf_index
& 0xffff) << 8);
955 /* Ensure new descriptor hits memory
956 * before setting ownership of this descriptor to HW
959 tx_desc
->ctrl
.owner_opcode
= op_own
;
963 mlx4_bf_copy(ring
->bf
.reg
+ ring
->bf
.offset
, &tx_desc
->ctrl
,
968 ring
->bf
.offset
^= ring
->bf
.buf_size
;
970 tx_desc
->ctrl
.vlan_tag
= cpu_to_be16(vlan_tag
);
971 if (vlan_proto
== ETH_P_8021AD
)
972 tx_desc
->ctrl
.ins_vlan
= MLX4_WQE_CTRL_INS_SVLAN
;
973 else if (vlan_proto
== ETH_P_8021Q
)
974 tx_desc
->ctrl
.ins_vlan
= MLX4_WQE_CTRL_INS_CVLAN
;
976 tx_desc
->ctrl
.ins_vlan
= 0;
978 tx_desc
->ctrl
.fence_size
= real_size
;
980 /* Ensure new descriptor hits memory
981 * before setting ownership of this descriptor to HW
984 tx_desc
->ctrl
.owner_opcode
= op_own
;
987 /* Since there is no iowrite*_native() that writes the
988 * value as is, without byteswapping - using the one
989 * the doesn't do byteswapping in the relevant arch
992 #if defined(__LITTLE_ENDIAN)
998 ring
->bf
.uar
->map
+ MLX4_SEND_DOORBELL
);
1004 if (unlikely(stop_queue
)) {
1005 /* If queue was emptied after the if (stop_queue) , and before
1006 * the netif_tx_stop_queue() - need to wake the queue,
1007 * or else it will remain stopped forever.
1008 * Need a memory barrier to make sure ring->cons was not
1009 * updated before queue was stopped.
1013 ring_cons
= ACCESS_ONCE(ring
->cons
);
1014 if (unlikely(!mlx4_en_is_tx_ring_full(ring
))) {
1015 netif_tx_wake_queue(ring
->tx_queue
);
1019 return NETDEV_TX_OK
;
1022 en_err(priv
, "DMA mapping error\n");
1024 while (++i_frag
< shinfo
->nr_frags
) {
1026 dma_unmap_page(ddev
, (dma_addr_t
) be64_to_cpu(data
->addr
),
1027 be32_to_cpu(data
->byte_count
),
1032 dev_kfree_skb_any(skb
);
1034 return NETDEV_TX_OK
;