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Merge tag 'for-4.1' of git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux...
[deliverable/linux.git] / drivers / net / ethernet / mellanox / mlx4 / eq.c
1 /*
2 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
3 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
10 *
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
13 * conditions are met:
14 *
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
17 * disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 */
33
34 #include <linux/interrupt.h>
35 #include <linux/slab.h>
36 #include <linux/export.h>
37 #include <linux/mm.h>
38 #include <linux/dma-mapping.h>
39
40 #include <linux/mlx4/cmd.h>
41 #include <linux/cpu_rmap.h>
42
43 #include "mlx4.h"
44 #include "fw.h"
45
46 enum {
47 MLX4_IRQNAME_SIZE = 32
48 };
49
50 enum {
51 MLX4_NUM_ASYNC_EQE = 0x100,
52 MLX4_NUM_SPARE_EQE = 0x80,
53 MLX4_EQ_ENTRY_SIZE = 0x20
54 };
55
56 #define MLX4_EQ_STATUS_OK ( 0 << 28)
57 #define MLX4_EQ_STATUS_WRITE_FAIL (10 << 28)
58 #define MLX4_EQ_OWNER_SW ( 0 << 24)
59 #define MLX4_EQ_OWNER_HW ( 1 << 24)
60 #define MLX4_EQ_FLAG_EC ( 1 << 18)
61 #define MLX4_EQ_FLAG_OI ( 1 << 17)
62 #define MLX4_EQ_STATE_ARMED ( 9 << 8)
63 #define MLX4_EQ_STATE_FIRED (10 << 8)
64 #define MLX4_EQ_STATE_ALWAYS_ARMED (11 << 8)
65
66 #define MLX4_ASYNC_EVENT_MASK ((1ull << MLX4_EVENT_TYPE_PATH_MIG) | \
67 (1ull << MLX4_EVENT_TYPE_COMM_EST) | \
68 (1ull << MLX4_EVENT_TYPE_SQ_DRAINED) | \
69 (1ull << MLX4_EVENT_TYPE_CQ_ERROR) | \
70 (1ull << MLX4_EVENT_TYPE_WQ_CATAS_ERROR) | \
71 (1ull << MLX4_EVENT_TYPE_EEC_CATAS_ERROR) | \
72 (1ull << MLX4_EVENT_TYPE_PATH_MIG_FAILED) | \
73 (1ull << MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR) | \
74 (1ull << MLX4_EVENT_TYPE_WQ_ACCESS_ERROR) | \
75 (1ull << MLX4_EVENT_TYPE_PORT_CHANGE) | \
76 (1ull << MLX4_EVENT_TYPE_ECC_DETECT) | \
77 (1ull << MLX4_EVENT_TYPE_SRQ_CATAS_ERROR) | \
78 (1ull << MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE) | \
79 (1ull << MLX4_EVENT_TYPE_SRQ_LIMIT) | \
80 (1ull << MLX4_EVENT_TYPE_CMD) | \
81 (1ull << MLX4_EVENT_TYPE_OP_REQUIRED) | \
82 (1ull << MLX4_EVENT_TYPE_COMM_CHANNEL) | \
83 (1ull << MLX4_EVENT_TYPE_FLR_EVENT) | \
84 (1ull << MLX4_EVENT_TYPE_FATAL_WARNING))
85
86 static u64 get_async_ev_mask(struct mlx4_dev *dev)
87 {
88 u64 async_ev_mask = MLX4_ASYNC_EVENT_MASK;
89 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV)
90 async_ev_mask |= (1ull << MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT);
91 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RECOVERABLE_ERROR_EVENT)
92 async_ev_mask |= (1ull << MLX4_EVENT_TYPE_RECOVERABLE_ERROR_EVENT);
93
94 return async_ev_mask;
95 }
96
97 static void eq_set_ci(struct mlx4_eq *eq, int req_not)
98 {
99 __raw_writel((__force u32) cpu_to_be32((eq->cons_index & 0xffffff) |
100 req_not << 31),
101 eq->doorbell);
102 /* We still want ordering, just not swabbing, so add a barrier */
103 mb();
104 }
105
106 static struct mlx4_eqe *get_eqe(struct mlx4_eq *eq, u32 entry, u8 eqe_factor,
107 u8 eqe_size)
108 {
109 /* (entry & (eq->nent - 1)) gives us a cyclic array */
110 unsigned long offset = (entry & (eq->nent - 1)) * eqe_size;
111 /* CX3 is capable of extending the EQE from 32 to 64 bytes with
112 * strides of 64B,128B and 256B.
113 * When 64B EQE is used, the first (in the lower addresses)
114 * 32 bytes in the 64 byte EQE are reserved and the next 32 bytes
115 * contain the legacy EQE information.
116 * In all other cases, the first 32B contains the legacy EQE info.
117 */
118 return eq->page_list[offset / PAGE_SIZE].buf + (offset + (eqe_factor ? MLX4_EQ_ENTRY_SIZE : 0)) % PAGE_SIZE;
119 }
120
121 static struct mlx4_eqe *next_eqe_sw(struct mlx4_eq *eq, u8 eqe_factor, u8 size)
122 {
123 struct mlx4_eqe *eqe = get_eqe(eq, eq->cons_index, eqe_factor, size);
124 return !!(eqe->owner & 0x80) ^ !!(eq->cons_index & eq->nent) ? NULL : eqe;
125 }
126
127 static struct mlx4_eqe *next_slave_event_eqe(struct mlx4_slave_event_eq *slave_eq)
128 {
129 struct mlx4_eqe *eqe =
130 &slave_eq->event_eqe[slave_eq->cons & (SLAVE_EVENT_EQ_SIZE - 1)];
131 return (!!(eqe->owner & 0x80) ^
132 !!(slave_eq->cons & SLAVE_EVENT_EQ_SIZE)) ?
133 eqe : NULL;
134 }
135
136 void mlx4_gen_slave_eqe(struct work_struct *work)
137 {
138 struct mlx4_mfunc_master_ctx *master =
139 container_of(work, struct mlx4_mfunc_master_ctx,
140 slave_event_work);
141 struct mlx4_mfunc *mfunc =
142 container_of(master, struct mlx4_mfunc, master);
143 struct mlx4_priv *priv = container_of(mfunc, struct mlx4_priv, mfunc);
144 struct mlx4_dev *dev = &priv->dev;
145 struct mlx4_slave_event_eq *slave_eq = &mfunc->master.slave_eq;
146 struct mlx4_eqe *eqe;
147 u8 slave;
148 int i;
149
150 for (eqe = next_slave_event_eqe(slave_eq); eqe;
151 eqe = next_slave_event_eqe(slave_eq)) {
152 slave = eqe->slave_id;
153
154 /* All active slaves need to receive the event */
155 if (slave == ALL_SLAVES) {
156 for (i = 0; i <= dev->persist->num_vfs; i++) {
157 if (mlx4_GEN_EQE(dev, i, eqe))
158 mlx4_warn(dev, "Failed to generate event for slave %d\n",
159 i);
160 }
161 } else {
162 if (mlx4_GEN_EQE(dev, slave, eqe))
163 mlx4_warn(dev, "Failed to generate event for slave %d\n",
164 slave);
165 }
166 ++slave_eq->cons;
167 }
168 }
169
170
171 static void slave_event(struct mlx4_dev *dev, u8 slave, struct mlx4_eqe *eqe)
172 {
173 struct mlx4_priv *priv = mlx4_priv(dev);
174 struct mlx4_slave_event_eq *slave_eq = &priv->mfunc.master.slave_eq;
175 struct mlx4_eqe *s_eqe;
176 unsigned long flags;
177
178 spin_lock_irqsave(&slave_eq->event_lock, flags);
179 s_eqe = &slave_eq->event_eqe[slave_eq->prod & (SLAVE_EVENT_EQ_SIZE - 1)];
180 if ((!!(s_eqe->owner & 0x80)) ^
181 (!!(slave_eq->prod & SLAVE_EVENT_EQ_SIZE))) {
182 mlx4_warn(dev, "Master failed to generate an EQE for slave: %d. No free EQE on slave events queue\n",
183 slave);
184 spin_unlock_irqrestore(&slave_eq->event_lock, flags);
185 return;
186 }
187
188 memcpy(s_eqe, eqe, dev->caps.eqe_size - 1);
189 s_eqe->slave_id = slave;
190 /* ensure all information is written before setting the ownersip bit */
191 wmb();
192 s_eqe->owner = !!(slave_eq->prod & SLAVE_EVENT_EQ_SIZE) ? 0x0 : 0x80;
193 ++slave_eq->prod;
194
195 queue_work(priv->mfunc.master.comm_wq,
196 &priv->mfunc.master.slave_event_work);
197 spin_unlock_irqrestore(&slave_eq->event_lock, flags);
198 }
199
200 static void mlx4_slave_event(struct mlx4_dev *dev, int slave,
201 struct mlx4_eqe *eqe)
202 {
203 struct mlx4_priv *priv = mlx4_priv(dev);
204
205 if (slave < 0 || slave > dev->persist->num_vfs ||
206 slave == dev->caps.function ||
207 !priv->mfunc.master.slave_state[slave].active)
208 return;
209
210 slave_event(dev, slave, eqe);
211 }
212
213 int mlx4_gen_pkey_eqe(struct mlx4_dev *dev, int slave, u8 port)
214 {
215 struct mlx4_eqe eqe;
216
217 struct mlx4_priv *priv = mlx4_priv(dev);
218 struct mlx4_slave_state *s_slave = &priv->mfunc.master.slave_state[slave];
219
220 if (!s_slave->active)
221 return 0;
222
223 memset(&eqe, 0, sizeof eqe);
224
225 eqe.type = MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT;
226 eqe.subtype = MLX4_DEV_PMC_SUBTYPE_PKEY_TABLE;
227 eqe.event.port_mgmt_change.port = port;
228
229 return mlx4_GEN_EQE(dev, slave, &eqe);
230 }
231 EXPORT_SYMBOL(mlx4_gen_pkey_eqe);
232
233 int mlx4_gen_guid_change_eqe(struct mlx4_dev *dev, int slave, u8 port)
234 {
235 struct mlx4_eqe eqe;
236
237 /*don't send if we don't have the that slave */
238 if (dev->persist->num_vfs < slave)
239 return 0;
240 memset(&eqe, 0, sizeof eqe);
241
242 eqe.type = MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT;
243 eqe.subtype = MLX4_DEV_PMC_SUBTYPE_GUID_INFO;
244 eqe.event.port_mgmt_change.port = port;
245
246 return mlx4_GEN_EQE(dev, slave, &eqe);
247 }
248 EXPORT_SYMBOL(mlx4_gen_guid_change_eqe);
249
250 int mlx4_gen_port_state_change_eqe(struct mlx4_dev *dev, int slave, u8 port,
251 u8 port_subtype_change)
252 {
253 struct mlx4_eqe eqe;
254
255 /*don't send if we don't have the that slave */
256 if (dev->persist->num_vfs < slave)
257 return 0;
258 memset(&eqe, 0, sizeof eqe);
259
260 eqe.type = MLX4_EVENT_TYPE_PORT_CHANGE;
261 eqe.subtype = port_subtype_change;
262 eqe.event.port_change.port = cpu_to_be32(port << 28);
263
264 mlx4_dbg(dev, "%s: sending: %d to slave: %d on port: %d\n", __func__,
265 port_subtype_change, slave, port);
266 return mlx4_GEN_EQE(dev, slave, &eqe);
267 }
268 EXPORT_SYMBOL(mlx4_gen_port_state_change_eqe);
269
270 enum slave_port_state mlx4_get_slave_port_state(struct mlx4_dev *dev, int slave, u8 port)
271 {
272 struct mlx4_priv *priv = mlx4_priv(dev);
273 struct mlx4_slave_state *s_state = priv->mfunc.master.slave_state;
274 struct mlx4_active_ports actv_ports = mlx4_get_active_ports(dev, slave);
275
276 if (slave >= dev->num_slaves || port > dev->caps.num_ports ||
277 port <= 0 || !test_bit(port - 1, actv_ports.ports)) {
278 pr_err("%s: Error: asking for slave:%d, port:%d\n",
279 __func__, slave, port);
280 return SLAVE_PORT_DOWN;
281 }
282 return s_state[slave].port_state[port];
283 }
284 EXPORT_SYMBOL(mlx4_get_slave_port_state);
285
286 static int mlx4_set_slave_port_state(struct mlx4_dev *dev, int slave, u8 port,
287 enum slave_port_state state)
288 {
289 struct mlx4_priv *priv = mlx4_priv(dev);
290 struct mlx4_slave_state *s_state = priv->mfunc.master.slave_state;
291 struct mlx4_active_ports actv_ports = mlx4_get_active_ports(dev, slave);
292
293 if (slave >= dev->num_slaves || port > dev->caps.num_ports ||
294 port <= 0 || !test_bit(port - 1, actv_ports.ports)) {
295 pr_err("%s: Error: asking for slave:%d, port:%d\n",
296 __func__, slave, port);
297 return -1;
298 }
299 s_state[slave].port_state[port] = state;
300
301 return 0;
302 }
303
304 static void set_all_slave_state(struct mlx4_dev *dev, u8 port, int event)
305 {
306 int i;
307 enum slave_port_gen_event gen_event;
308 struct mlx4_slaves_pport slaves_pport = mlx4_phys_to_slaves_pport(dev,
309 port);
310
311 for (i = 0; i < dev->persist->num_vfs + 1; i++)
312 if (test_bit(i, slaves_pport.slaves))
313 set_and_calc_slave_port_state(dev, i, port,
314 event, &gen_event);
315 }
316 /**************************************************************************
317 The function get as input the new event to that port,
318 and according to the prev state change the slave's port state.
319 The events are:
320 MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN,
321 MLX4_PORT_STATE_DEV_EVENT_PORT_UP
322 MLX4_PORT_STATE_IB_EVENT_GID_VALID
323 MLX4_PORT_STATE_IB_EVENT_GID_INVALID
324 ***************************************************************************/
325 int set_and_calc_slave_port_state(struct mlx4_dev *dev, int slave,
326 u8 port, int event,
327 enum slave_port_gen_event *gen_event)
328 {
329 struct mlx4_priv *priv = mlx4_priv(dev);
330 struct mlx4_slave_state *ctx = NULL;
331 unsigned long flags;
332 int ret = -1;
333 struct mlx4_active_ports actv_ports = mlx4_get_active_ports(dev, slave);
334 enum slave_port_state cur_state =
335 mlx4_get_slave_port_state(dev, slave, port);
336
337 *gen_event = SLAVE_PORT_GEN_EVENT_NONE;
338
339 if (slave >= dev->num_slaves || port > dev->caps.num_ports ||
340 port <= 0 || !test_bit(port - 1, actv_ports.ports)) {
341 pr_err("%s: Error: asking for slave:%d, port:%d\n",
342 __func__, slave, port);
343 return ret;
344 }
345
346 ctx = &priv->mfunc.master.slave_state[slave];
347 spin_lock_irqsave(&ctx->lock, flags);
348
349 switch (cur_state) {
350 case SLAVE_PORT_DOWN:
351 if (MLX4_PORT_STATE_DEV_EVENT_PORT_UP == event)
352 mlx4_set_slave_port_state(dev, slave, port,
353 SLAVE_PENDING_UP);
354 break;
355 case SLAVE_PENDING_UP:
356 if (MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN == event)
357 mlx4_set_slave_port_state(dev, slave, port,
358 SLAVE_PORT_DOWN);
359 else if (MLX4_PORT_STATE_IB_PORT_STATE_EVENT_GID_VALID == event) {
360 mlx4_set_slave_port_state(dev, slave, port,
361 SLAVE_PORT_UP);
362 *gen_event = SLAVE_PORT_GEN_EVENT_UP;
363 }
364 break;
365 case SLAVE_PORT_UP:
366 if (MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN == event) {
367 mlx4_set_slave_port_state(dev, slave, port,
368 SLAVE_PORT_DOWN);
369 *gen_event = SLAVE_PORT_GEN_EVENT_DOWN;
370 } else if (MLX4_PORT_STATE_IB_EVENT_GID_INVALID ==
371 event) {
372 mlx4_set_slave_port_state(dev, slave, port,
373 SLAVE_PENDING_UP);
374 *gen_event = SLAVE_PORT_GEN_EVENT_DOWN;
375 }
376 break;
377 default:
378 pr_err("%s: BUG!!! UNKNOWN state: slave:%d, port:%d\n",
379 __func__, slave, port);
380 goto out;
381 }
382 ret = mlx4_get_slave_port_state(dev, slave, port);
383
384 out:
385 spin_unlock_irqrestore(&ctx->lock, flags);
386 return ret;
387 }
388
389 EXPORT_SYMBOL(set_and_calc_slave_port_state);
390
391 int mlx4_gen_slaves_port_mgt_ev(struct mlx4_dev *dev, u8 port, int attr)
392 {
393 struct mlx4_eqe eqe;
394
395 memset(&eqe, 0, sizeof eqe);
396
397 eqe.type = MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT;
398 eqe.subtype = MLX4_DEV_PMC_SUBTYPE_PORT_INFO;
399 eqe.event.port_mgmt_change.port = port;
400 eqe.event.port_mgmt_change.params.port_info.changed_attr =
401 cpu_to_be32((u32) attr);
402
403 slave_event(dev, ALL_SLAVES, &eqe);
404 return 0;
405 }
406 EXPORT_SYMBOL(mlx4_gen_slaves_port_mgt_ev);
407
408 void mlx4_master_handle_slave_flr(struct work_struct *work)
409 {
410 struct mlx4_mfunc_master_ctx *master =
411 container_of(work, struct mlx4_mfunc_master_ctx,
412 slave_flr_event_work);
413 struct mlx4_mfunc *mfunc =
414 container_of(master, struct mlx4_mfunc, master);
415 struct mlx4_priv *priv =
416 container_of(mfunc, struct mlx4_priv, mfunc);
417 struct mlx4_dev *dev = &priv->dev;
418 struct mlx4_slave_state *slave_state = priv->mfunc.master.slave_state;
419 int i;
420 int err;
421 unsigned long flags;
422
423 mlx4_dbg(dev, "mlx4_handle_slave_flr\n");
424
425 for (i = 0 ; i < dev->num_slaves; i++) {
426
427 if (MLX4_COMM_CMD_FLR == slave_state[i].last_cmd) {
428 mlx4_dbg(dev, "mlx4_handle_slave_flr: clean slave: %d\n",
429 i);
430 /* In case of 'Reset flow' FLR can be generated for
431 * a slave before mlx4_load_one is done.
432 * make sure interface is up before trying to delete
433 * slave resources which weren't allocated yet.
434 */
435 if (dev->persist->interface_state &
436 MLX4_INTERFACE_STATE_UP)
437 mlx4_delete_all_resources_for_slave(dev, i);
438 /*return the slave to running mode*/
439 spin_lock_irqsave(&priv->mfunc.master.slave_state_lock, flags);
440 slave_state[i].last_cmd = MLX4_COMM_CMD_RESET;
441 slave_state[i].is_slave_going_down = 0;
442 spin_unlock_irqrestore(&priv->mfunc.master.slave_state_lock, flags);
443 /*notify the FW:*/
444 err = mlx4_cmd(dev, 0, i, 0, MLX4_CMD_INFORM_FLR_DONE,
445 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
446 if (err)
447 mlx4_warn(dev, "Failed to notify FW on FLR done (slave:%d)\n",
448 i);
449 }
450 }
451 }
452
453 static int mlx4_eq_int(struct mlx4_dev *dev, struct mlx4_eq *eq)
454 {
455 struct mlx4_priv *priv = mlx4_priv(dev);
456 struct mlx4_eqe *eqe;
457 int cqn = -1;
458 int eqes_found = 0;
459 int set_ci = 0;
460 int port;
461 int slave = 0;
462 int ret;
463 u32 flr_slave;
464 u8 update_slave_state;
465 int i;
466 enum slave_port_gen_event gen_event;
467 unsigned long flags;
468 struct mlx4_vport_state *s_info;
469 int eqe_size = dev->caps.eqe_size;
470
471 while ((eqe = next_eqe_sw(eq, dev->caps.eqe_factor, eqe_size))) {
472 /*
473 * Make sure we read EQ entry contents after we've
474 * checked the ownership bit.
475 */
476 rmb();
477
478 switch (eqe->type) {
479 case MLX4_EVENT_TYPE_COMP:
480 cqn = be32_to_cpu(eqe->event.comp.cqn) & 0xffffff;
481 mlx4_cq_completion(dev, cqn);
482 break;
483
484 case MLX4_EVENT_TYPE_PATH_MIG:
485 case MLX4_EVENT_TYPE_COMM_EST:
486 case MLX4_EVENT_TYPE_SQ_DRAINED:
487 case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE:
488 case MLX4_EVENT_TYPE_WQ_CATAS_ERROR:
489 case MLX4_EVENT_TYPE_PATH_MIG_FAILED:
490 case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
491 case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR:
492 mlx4_dbg(dev, "event %d arrived\n", eqe->type);
493 if (mlx4_is_master(dev)) {
494 /* forward only to slave owning the QP */
495 ret = mlx4_get_slave_from_resource_id(dev,
496 RES_QP,
497 be32_to_cpu(eqe->event.qp.qpn)
498 & 0xffffff, &slave);
499 if (ret && ret != -ENOENT) {
500 mlx4_dbg(dev, "QP event %02x(%02x) on EQ %d at index %u: could not get slave id (%d)\n",
501 eqe->type, eqe->subtype,
502 eq->eqn, eq->cons_index, ret);
503 break;
504 }
505
506 if (!ret && slave != dev->caps.function) {
507 mlx4_slave_event(dev, slave, eqe);
508 break;
509 }
510
511 }
512 mlx4_qp_event(dev, be32_to_cpu(eqe->event.qp.qpn) &
513 0xffffff, eqe->type);
514 break;
515
516 case MLX4_EVENT_TYPE_SRQ_LIMIT:
517 mlx4_dbg(dev, "%s: MLX4_EVENT_TYPE_SRQ_LIMIT\n",
518 __func__);
519 case MLX4_EVENT_TYPE_SRQ_CATAS_ERROR:
520 if (mlx4_is_master(dev)) {
521 /* forward only to slave owning the SRQ */
522 ret = mlx4_get_slave_from_resource_id(dev,
523 RES_SRQ,
524 be32_to_cpu(eqe->event.srq.srqn)
525 & 0xffffff,
526 &slave);
527 if (ret && ret != -ENOENT) {
528 mlx4_warn(dev, "SRQ event %02x(%02x) on EQ %d at index %u: could not get slave id (%d)\n",
529 eqe->type, eqe->subtype,
530 eq->eqn, eq->cons_index, ret);
531 break;
532 }
533 mlx4_warn(dev, "%s: slave:%d, srq_no:0x%x, event: %02x(%02x)\n",
534 __func__, slave,
535 be32_to_cpu(eqe->event.srq.srqn),
536 eqe->type, eqe->subtype);
537
538 if (!ret && slave != dev->caps.function) {
539 mlx4_warn(dev, "%s: sending event %02x(%02x) to slave:%d\n",
540 __func__, eqe->type,
541 eqe->subtype, slave);
542 mlx4_slave_event(dev, slave, eqe);
543 break;
544 }
545 }
546 mlx4_srq_event(dev, be32_to_cpu(eqe->event.srq.srqn) &
547 0xffffff, eqe->type);
548 break;
549
550 case MLX4_EVENT_TYPE_CMD:
551 mlx4_cmd_event(dev,
552 be16_to_cpu(eqe->event.cmd.token),
553 eqe->event.cmd.status,
554 be64_to_cpu(eqe->event.cmd.out_param));
555 break;
556
557 case MLX4_EVENT_TYPE_PORT_CHANGE: {
558 struct mlx4_slaves_pport slaves_port;
559 port = be32_to_cpu(eqe->event.port_change.port) >> 28;
560 slaves_port = mlx4_phys_to_slaves_pport(dev, port);
561 if (eqe->subtype == MLX4_PORT_CHANGE_SUBTYPE_DOWN) {
562 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_PORT_DOWN,
563 port);
564 mlx4_priv(dev)->sense.do_sense_port[port] = 1;
565 if (!mlx4_is_master(dev))
566 break;
567 for (i = 0; i < dev->persist->num_vfs + 1;
568 i++) {
569 if (!test_bit(i, slaves_port.slaves))
570 continue;
571 if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH) {
572 if (i == mlx4_master_func_num(dev))
573 continue;
574 mlx4_dbg(dev, "%s: Sending MLX4_PORT_CHANGE_SUBTYPE_DOWN to slave: %d, port:%d\n",
575 __func__, i, port);
576 s_info = &priv->mfunc.master.vf_oper[slave].vport[port].state;
577 if (IFLA_VF_LINK_STATE_AUTO == s_info->link_state) {
578 eqe->event.port_change.port =
579 cpu_to_be32(
580 (be32_to_cpu(eqe->event.port_change.port) & 0xFFFFFFF)
581 | (mlx4_phys_to_slave_port(dev, i, port) << 28));
582 mlx4_slave_event(dev, i, eqe);
583 }
584 } else { /* IB port */
585 set_and_calc_slave_port_state(dev, i, port,
586 MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN,
587 &gen_event);
588 /*we can be in pending state, then do not send port_down event*/
589 if (SLAVE_PORT_GEN_EVENT_DOWN == gen_event) {
590 if (i == mlx4_master_func_num(dev))
591 continue;
592 mlx4_slave_event(dev, i, eqe);
593 }
594 }
595 }
596 } else {
597 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_PORT_UP, port);
598
599 mlx4_priv(dev)->sense.do_sense_port[port] = 0;
600
601 if (!mlx4_is_master(dev))
602 break;
603 if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH)
604 for (i = 0;
605 i < dev->persist->num_vfs + 1;
606 i++) {
607 if (!test_bit(i, slaves_port.slaves))
608 continue;
609 if (i == mlx4_master_func_num(dev))
610 continue;
611 s_info = &priv->mfunc.master.vf_oper[slave].vport[port].state;
612 if (IFLA_VF_LINK_STATE_AUTO == s_info->link_state) {
613 eqe->event.port_change.port =
614 cpu_to_be32(
615 (be32_to_cpu(eqe->event.port_change.port) & 0xFFFFFFF)
616 | (mlx4_phys_to_slave_port(dev, i, port) << 28));
617 mlx4_slave_event(dev, i, eqe);
618 }
619 }
620 else /* IB port */
621 /* port-up event will be sent to a slave when the
622 * slave's alias-guid is set. This is done in alias_GUID.c
623 */
624 set_all_slave_state(dev, port, MLX4_DEV_EVENT_PORT_UP);
625 }
626 break;
627 }
628
629 case MLX4_EVENT_TYPE_CQ_ERROR:
630 mlx4_warn(dev, "CQ %s on CQN %06x\n",
631 eqe->event.cq_err.syndrome == 1 ?
632 "overrun" : "access violation",
633 be32_to_cpu(eqe->event.cq_err.cqn) & 0xffffff);
634 if (mlx4_is_master(dev)) {
635 ret = mlx4_get_slave_from_resource_id(dev,
636 RES_CQ,
637 be32_to_cpu(eqe->event.cq_err.cqn)
638 & 0xffffff, &slave);
639 if (ret && ret != -ENOENT) {
640 mlx4_dbg(dev, "CQ event %02x(%02x) on EQ %d at index %u: could not get slave id (%d)\n",
641 eqe->type, eqe->subtype,
642 eq->eqn, eq->cons_index, ret);
643 break;
644 }
645
646 if (!ret && slave != dev->caps.function) {
647 mlx4_slave_event(dev, slave, eqe);
648 break;
649 }
650 }
651 mlx4_cq_event(dev,
652 be32_to_cpu(eqe->event.cq_err.cqn)
653 & 0xffffff,
654 eqe->type);
655 break;
656
657 case MLX4_EVENT_TYPE_EQ_OVERFLOW:
658 mlx4_warn(dev, "EQ overrun on EQN %d\n", eq->eqn);
659 break;
660
661 case MLX4_EVENT_TYPE_OP_REQUIRED:
662 atomic_inc(&priv->opreq_count);
663 /* FW commands can't be executed from interrupt context
664 * working in deferred task
665 */
666 queue_work(mlx4_wq, &priv->opreq_task);
667 break;
668
669 case MLX4_EVENT_TYPE_COMM_CHANNEL:
670 if (!mlx4_is_master(dev)) {
671 mlx4_warn(dev, "Received comm channel event for non master device\n");
672 break;
673 }
674 memcpy(&priv->mfunc.master.comm_arm_bit_vector,
675 eqe->event.comm_channel_arm.bit_vec,
676 sizeof eqe->event.comm_channel_arm.bit_vec);
677 queue_work(priv->mfunc.master.comm_wq,
678 &priv->mfunc.master.comm_work);
679 break;
680
681 case MLX4_EVENT_TYPE_FLR_EVENT:
682 flr_slave = be32_to_cpu(eqe->event.flr_event.slave_id);
683 if (!mlx4_is_master(dev)) {
684 mlx4_warn(dev, "Non-master function received FLR event\n");
685 break;
686 }
687
688 mlx4_dbg(dev, "FLR event for slave: %d\n", flr_slave);
689
690 if (flr_slave >= dev->num_slaves) {
691 mlx4_warn(dev,
692 "Got FLR for unknown function: %d\n",
693 flr_slave);
694 update_slave_state = 0;
695 } else
696 update_slave_state = 1;
697
698 spin_lock_irqsave(&priv->mfunc.master.slave_state_lock, flags);
699 if (update_slave_state) {
700 priv->mfunc.master.slave_state[flr_slave].active = false;
701 priv->mfunc.master.slave_state[flr_slave].last_cmd = MLX4_COMM_CMD_FLR;
702 priv->mfunc.master.slave_state[flr_slave].is_slave_going_down = 1;
703 }
704 spin_unlock_irqrestore(&priv->mfunc.master.slave_state_lock, flags);
705 queue_work(priv->mfunc.master.comm_wq,
706 &priv->mfunc.master.slave_flr_event_work);
707 break;
708
709 case MLX4_EVENT_TYPE_FATAL_WARNING:
710 if (eqe->subtype == MLX4_FATAL_WARNING_SUBTYPE_WARMING) {
711 if (mlx4_is_master(dev))
712 for (i = 0; i < dev->num_slaves; i++) {
713 mlx4_dbg(dev, "%s: Sending MLX4_FATAL_WARNING_SUBTYPE_WARMING to slave: %d\n",
714 __func__, i);
715 if (i == dev->caps.function)
716 continue;
717 mlx4_slave_event(dev, i, eqe);
718 }
719 mlx4_err(dev, "Temperature Threshold was reached! Threshold: %d celsius degrees; Current Temperature: %d\n",
720 be16_to_cpu(eqe->event.warming.warning_threshold),
721 be16_to_cpu(eqe->event.warming.current_temperature));
722 } else
723 mlx4_warn(dev, "Unhandled event FATAL WARNING (%02x), subtype %02x on EQ %d at index %u. owner=%x, nent=0x%x, slave=%x, ownership=%s\n",
724 eqe->type, eqe->subtype, eq->eqn,
725 eq->cons_index, eqe->owner, eq->nent,
726 eqe->slave_id,
727 !!(eqe->owner & 0x80) ^
728 !!(eq->cons_index & eq->nent) ? "HW" : "SW");
729
730 break;
731
732 case MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT:
733 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_PORT_MGMT_CHANGE,
734 (unsigned long) eqe);
735 break;
736
737 case MLX4_EVENT_TYPE_RECOVERABLE_ERROR_EVENT:
738 switch (eqe->subtype) {
739 case MLX4_RECOVERABLE_ERROR_EVENT_SUBTYPE_BAD_CABLE:
740 mlx4_warn(dev, "Bad cable detected on port %u\n",
741 eqe->event.bad_cable.port);
742 break;
743 case MLX4_RECOVERABLE_ERROR_EVENT_SUBTYPE_UNSUPPORTED_CABLE:
744 mlx4_warn(dev, "Unsupported cable detected\n");
745 break;
746 default:
747 mlx4_dbg(dev,
748 "Unhandled recoverable error event detected: %02x(%02x) on EQ %d at index %u. owner=%x, nent=0x%x, ownership=%s\n",
749 eqe->type, eqe->subtype, eq->eqn,
750 eq->cons_index, eqe->owner, eq->nent,
751 !!(eqe->owner & 0x80) ^
752 !!(eq->cons_index & eq->nent) ? "HW" : "SW");
753 break;
754 }
755 break;
756
757 case MLX4_EVENT_TYPE_EEC_CATAS_ERROR:
758 case MLX4_EVENT_TYPE_ECC_DETECT:
759 default:
760 mlx4_warn(dev, "Unhandled event %02x(%02x) on EQ %d at index %u. owner=%x, nent=0x%x, slave=%x, ownership=%s\n",
761 eqe->type, eqe->subtype, eq->eqn,
762 eq->cons_index, eqe->owner, eq->nent,
763 eqe->slave_id,
764 !!(eqe->owner & 0x80) ^
765 !!(eq->cons_index & eq->nent) ? "HW" : "SW");
766 break;
767 };
768
769 ++eq->cons_index;
770 eqes_found = 1;
771 ++set_ci;
772
773 /*
774 * The HCA will think the queue has overflowed if we
775 * don't tell it we've been processing events. We
776 * create our EQs with MLX4_NUM_SPARE_EQE extra
777 * entries, so we must update our consumer index at
778 * least that often.
779 */
780 if (unlikely(set_ci >= MLX4_NUM_SPARE_EQE)) {
781 eq_set_ci(eq, 0);
782 set_ci = 0;
783 }
784 }
785
786 eq_set_ci(eq, 1);
787
788 /* cqn is 24bit wide but is initialized such that its higher bits
789 * are ones too. Thus, if we got any event, cqn's high bits should be off
790 * and we need to schedule the tasklet.
791 */
792 if (!(cqn & ~0xffffff))
793 tasklet_schedule(&eq->tasklet_ctx.task);
794
795 return eqes_found;
796 }
797
798 static irqreturn_t mlx4_interrupt(int irq, void *dev_ptr)
799 {
800 struct mlx4_dev *dev = dev_ptr;
801 struct mlx4_priv *priv = mlx4_priv(dev);
802 int work = 0;
803 int i;
804
805 writel(priv->eq_table.clr_mask, priv->eq_table.clr_int);
806
807 for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i)
808 work |= mlx4_eq_int(dev, &priv->eq_table.eq[i]);
809
810 return IRQ_RETVAL(work);
811 }
812
813 static irqreturn_t mlx4_msi_x_interrupt(int irq, void *eq_ptr)
814 {
815 struct mlx4_eq *eq = eq_ptr;
816 struct mlx4_dev *dev = eq->dev;
817
818 mlx4_eq_int(dev, eq);
819
820 /* MSI-X vectors always belong to us */
821 return IRQ_HANDLED;
822 }
823
824 int mlx4_MAP_EQ_wrapper(struct mlx4_dev *dev, int slave,
825 struct mlx4_vhcr *vhcr,
826 struct mlx4_cmd_mailbox *inbox,
827 struct mlx4_cmd_mailbox *outbox,
828 struct mlx4_cmd_info *cmd)
829 {
830 struct mlx4_priv *priv = mlx4_priv(dev);
831 struct mlx4_slave_event_eq_info *event_eq =
832 priv->mfunc.master.slave_state[slave].event_eq;
833 u32 in_modifier = vhcr->in_modifier;
834 u32 eqn = in_modifier & 0x3FF;
835 u64 in_param = vhcr->in_param;
836 int err = 0;
837 int i;
838
839 if (slave == dev->caps.function)
840 err = mlx4_cmd(dev, in_param, (in_modifier & 0x80000000) | eqn,
841 0, MLX4_CMD_MAP_EQ, MLX4_CMD_TIME_CLASS_B,
842 MLX4_CMD_NATIVE);
843 if (!err)
844 for (i = 0; i < MLX4_EVENT_TYPES_NUM; ++i)
845 if (in_param & (1LL << i))
846 event_eq[i].eqn = in_modifier >> 31 ? -1 : eqn;
847
848 return err;
849 }
850
851 static int mlx4_MAP_EQ(struct mlx4_dev *dev, u64 event_mask, int unmap,
852 int eq_num)
853 {
854 return mlx4_cmd(dev, event_mask, (unmap << 31) | eq_num,
855 0, MLX4_CMD_MAP_EQ, MLX4_CMD_TIME_CLASS_B,
856 MLX4_CMD_WRAPPED);
857 }
858
859 static int mlx4_SW2HW_EQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
860 int eq_num)
861 {
862 return mlx4_cmd(dev, mailbox->dma, eq_num, 0,
863 MLX4_CMD_SW2HW_EQ, MLX4_CMD_TIME_CLASS_A,
864 MLX4_CMD_WRAPPED);
865 }
866
867 static int mlx4_HW2SW_EQ(struct mlx4_dev *dev, int eq_num)
868 {
869 return mlx4_cmd(dev, 0, eq_num, 1, MLX4_CMD_HW2SW_EQ,
870 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
871 }
872
873 static int mlx4_num_eq_uar(struct mlx4_dev *dev)
874 {
875 /*
876 * Each UAR holds 4 EQ doorbells. To figure out how many UARs
877 * we need to map, take the difference of highest index and
878 * the lowest index we'll use and add 1.
879 */
880 return (dev->caps.num_comp_vectors + 1 + dev->caps.reserved_eqs +
881 dev->caps.comp_pool)/4 - dev->caps.reserved_eqs/4 + 1;
882 }
883
884 static void __iomem *mlx4_get_eq_uar(struct mlx4_dev *dev, struct mlx4_eq *eq)
885 {
886 struct mlx4_priv *priv = mlx4_priv(dev);
887 int index;
888
889 index = eq->eqn / 4 - dev->caps.reserved_eqs / 4;
890
891 if (!priv->eq_table.uar_map[index]) {
892 priv->eq_table.uar_map[index] =
893 ioremap(pci_resource_start(dev->persist->pdev, 2) +
894 ((eq->eqn / 4) << PAGE_SHIFT),
895 PAGE_SIZE);
896 if (!priv->eq_table.uar_map[index]) {
897 mlx4_err(dev, "Couldn't map EQ doorbell for EQN 0x%06x\n",
898 eq->eqn);
899 return NULL;
900 }
901 }
902
903 return priv->eq_table.uar_map[index] + 0x800 + 8 * (eq->eqn % 4);
904 }
905
906 static void mlx4_unmap_uar(struct mlx4_dev *dev)
907 {
908 struct mlx4_priv *priv = mlx4_priv(dev);
909 int i;
910
911 for (i = 0; i < mlx4_num_eq_uar(dev); ++i)
912 if (priv->eq_table.uar_map[i]) {
913 iounmap(priv->eq_table.uar_map[i]);
914 priv->eq_table.uar_map[i] = NULL;
915 }
916 }
917
918 static int mlx4_create_eq(struct mlx4_dev *dev, int nent,
919 u8 intr, struct mlx4_eq *eq)
920 {
921 struct mlx4_priv *priv = mlx4_priv(dev);
922 struct mlx4_cmd_mailbox *mailbox;
923 struct mlx4_eq_context *eq_context;
924 int npages;
925 u64 *dma_list = NULL;
926 dma_addr_t t;
927 u64 mtt_addr;
928 int err = -ENOMEM;
929 int i;
930
931 eq->dev = dev;
932 eq->nent = roundup_pow_of_two(max(nent, 2));
933 /* CX3 is capable of extending the CQE/EQE from 32 to 64 bytes, with
934 * strides of 64B,128B and 256B.
935 */
936 npages = PAGE_ALIGN(eq->nent * dev->caps.eqe_size) / PAGE_SIZE;
937
938 eq->page_list = kmalloc(npages * sizeof *eq->page_list,
939 GFP_KERNEL);
940 if (!eq->page_list)
941 goto err_out;
942
943 for (i = 0; i < npages; ++i)
944 eq->page_list[i].buf = NULL;
945
946 dma_list = kmalloc(npages * sizeof *dma_list, GFP_KERNEL);
947 if (!dma_list)
948 goto err_out_free;
949
950 mailbox = mlx4_alloc_cmd_mailbox(dev);
951 if (IS_ERR(mailbox))
952 goto err_out_free;
953 eq_context = mailbox->buf;
954
955 for (i = 0; i < npages; ++i) {
956 eq->page_list[i].buf = dma_alloc_coherent(&dev->persist->
957 pdev->dev,
958 PAGE_SIZE, &t,
959 GFP_KERNEL);
960 if (!eq->page_list[i].buf)
961 goto err_out_free_pages;
962
963 dma_list[i] = t;
964 eq->page_list[i].map = t;
965
966 memset(eq->page_list[i].buf, 0, PAGE_SIZE);
967 }
968
969 eq->eqn = mlx4_bitmap_alloc(&priv->eq_table.bitmap);
970 if (eq->eqn == -1)
971 goto err_out_free_pages;
972
973 eq->doorbell = mlx4_get_eq_uar(dev, eq);
974 if (!eq->doorbell) {
975 err = -ENOMEM;
976 goto err_out_free_eq;
977 }
978
979 err = mlx4_mtt_init(dev, npages, PAGE_SHIFT, &eq->mtt);
980 if (err)
981 goto err_out_free_eq;
982
983 err = mlx4_write_mtt(dev, &eq->mtt, 0, npages, dma_list);
984 if (err)
985 goto err_out_free_mtt;
986
987 eq_context->flags = cpu_to_be32(MLX4_EQ_STATUS_OK |
988 MLX4_EQ_STATE_ARMED);
989 eq_context->log_eq_size = ilog2(eq->nent);
990 eq_context->intr = intr;
991 eq_context->log_page_size = PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT;
992
993 mtt_addr = mlx4_mtt_addr(dev, &eq->mtt);
994 eq_context->mtt_base_addr_h = mtt_addr >> 32;
995 eq_context->mtt_base_addr_l = cpu_to_be32(mtt_addr & 0xffffffff);
996
997 err = mlx4_SW2HW_EQ(dev, mailbox, eq->eqn);
998 if (err) {
999 mlx4_warn(dev, "SW2HW_EQ failed (%d)\n", err);
1000 goto err_out_free_mtt;
1001 }
1002
1003 kfree(dma_list);
1004 mlx4_free_cmd_mailbox(dev, mailbox);
1005
1006 eq->cons_index = 0;
1007
1008 INIT_LIST_HEAD(&eq->tasklet_ctx.list);
1009 INIT_LIST_HEAD(&eq->tasklet_ctx.process_list);
1010 spin_lock_init(&eq->tasklet_ctx.lock);
1011 tasklet_init(&eq->tasklet_ctx.task, mlx4_cq_tasklet_cb,
1012 (unsigned long)&eq->tasklet_ctx);
1013
1014 return err;
1015
1016 err_out_free_mtt:
1017 mlx4_mtt_cleanup(dev, &eq->mtt);
1018
1019 err_out_free_eq:
1020 mlx4_bitmap_free(&priv->eq_table.bitmap, eq->eqn, MLX4_USE_RR);
1021
1022 err_out_free_pages:
1023 for (i = 0; i < npages; ++i)
1024 if (eq->page_list[i].buf)
1025 dma_free_coherent(&dev->persist->pdev->dev, PAGE_SIZE,
1026 eq->page_list[i].buf,
1027 eq->page_list[i].map);
1028
1029 mlx4_free_cmd_mailbox(dev, mailbox);
1030
1031 err_out_free:
1032 kfree(eq->page_list);
1033 kfree(dma_list);
1034
1035 err_out:
1036 return err;
1037 }
1038
1039 static void mlx4_free_eq(struct mlx4_dev *dev,
1040 struct mlx4_eq *eq)
1041 {
1042 struct mlx4_priv *priv = mlx4_priv(dev);
1043 int err;
1044 int i;
1045 /* CX3 is capable of extending the CQE/EQE from 32 to 64 bytes, with
1046 * strides of 64B,128B and 256B
1047 */
1048 int npages = PAGE_ALIGN(dev->caps.eqe_size * eq->nent) / PAGE_SIZE;
1049
1050 err = mlx4_HW2SW_EQ(dev, eq->eqn);
1051 if (err)
1052 mlx4_warn(dev, "HW2SW_EQ failed (%d)\n", err);
1053
1054 synchronize_irq(eq->irq);
1055 tasklet_disable(&eq->tasklet_ctx.task);
1056
1057 mlx4_mtt_cleanup(dev, &eq->mtt);
1058 for (i = 0; i < npages; ++i)
1059 dma_free_coherent(&dev->persist->pdev->dev, PAGE_SIZE,
1060 eq->page_list[i].buf,
1061 eq->page_list[i].map);
1062
1063 kfree(eq->page_list);
1064 mlx4_bitmap_free(&priv->eq_table.bitmap, eq->eqn, MLX4_USE_RR);
1065 }
1066
1067 static void mlx4_free_irqs(struct mlx4_dev *dev)
1068 {
1069 struct mlx4_eq_table *eq_table = &mlx4_priv(dev)->eq_table;
1070 struct mlx4_priv *priv = mlx4_priv(dev);
1071 int i, vec;
1072
1073 if (eq_table->have_irq)
1074 free_irq(dev->persist->pdev->irq, dev);
1075
1076 for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i)
1077 if (eq_table->eq[i].have_irq) {
1078 free_irq(eq_table->eq[i].irq, eq_table->eq + i);
1079 eq_table->eq[i].have_irq = 0;
1080 }
1081
1082 for (i = 0; i < dev->caps.comp_pool; i++) {
1083 /*
1084 * Freeing the assigned irq's
1085 * all bits should be 0, but we need to validate
1086 */
1087 if (priv->msix_ctl.pool_bm & 1ULL << i) {
1088 /* NO need protecting*/
1089 vec = dev->caps.num_comp_vectors + 1 + i;
1090 free_irq(priv->eq_table.eq[vec].irq,
1091 &priv->eq_table.eq[vec]);
1092 }
1093 }
1094
1095
1096 kfree(eq_table->irq_names);
1097 }
1098
1099 static int mlx4_map_clr_int(struct mlx4_dev *dev)
1100 {
1101 struct mlx4_priv *priv = mlx4_priv(dev);
1102
1103 priv->clr_base = ioremap(pci_resource_start(dev->persist->pdev,
1104 priv->fw.clr_int_bar) +
1105 priv->fw.clr_int_base, MLX4_CLR_INT_SIZE);
1106 if (!priv->clr_base) {
1107 mlx4_err(dev, "Couldn't map interrupt clear register, aborting\n");
1108 return -ENOMEM;
1109 }
1110
1111 return 0;
1112 }
1113
1114 static void mlx4_unmap_clr_int(struct mlx4_dev *dev)
1115 {
1116 struct mlx4_priv *priv = mlx4_priv(dev);
1117
1118 iounmap(priv->clr_base);
1119 }
1120
1121 int mlx4_alloc_eq_table(struct mlx4_dev *dev)
1122 {
1123 struct mlx4_priv *priv = mlx4_priv(dev);
1124
1125 priv->eq_table.eq = kcalloc(dev->caps.num_eqs - dev->caps.reserved_eqs,
1126 sizeof *priv->eq_table.eq, GFP_KERNEL);
1127 if (!priv->eq_table.eq)
1128 return -ENOMEM;
1129
1130 return 0;
1131 }
1132
1133 void mlx4_free_eq_table(struct mlx4_dev *dev)
1134 {
1135 kfree(mlx4_priv(dev)->eq_table.eq);
1136 }
1137
1138 int mlx4_init_eq_table(struct mlx4_dev *dev)
1139 {
1140 struct mlx4_priv *priv = mlx4_priv(dev);
1141 int err;
1142 int i;
1143
1144 priv->eq_table.uar_map = kcalloc(mlx4_num_eq_uar(dev),
1145 sizeof *priv->eq_table.uar_map,
1146 GFP_KERNEL);
1147 if (!priv->eq_table.uar_map) {
1148 err = -ENOMEM;
1149 goto err_out_free;
1150 }
1151
1152 err = mlx4_bitmap_init(&priv->eq_table.bitmap,
1153 roundup_pow_of_two(dev->caps.num_eqs),
1154 dev->caps.num_eqs - 1,
1155 dev->caps.reserved_eqs,
1156 roundup_pow_of_two(dev->caps.num_eqs) -
1157 dev->caps.num_eqs);
1158 if (err)
1159 goto err_out_free;
1160
1161 for (i = 0; i < mlx4_num_eq_uar(dev); ++i)
1162 priv->eq_table.uar_map[i] = NULL;
1163
1164 if (!mlx4_is_slave(dev)) {
1165 err = mlx4_map_clr_int(dev);
1166 if (err)
1167 goto err_out_bitmap;
1168
1169 priv->eq_table.clr_mask =
1170 swab32(1 << (priv->eq_table.inta_pin & 31));
1171 priv->eq_table.clr_int = priv->clr_base +
1172 (priv->eq_table.inta_pin < 32 ? 4 : 0);
1173 }
1174
1175 priv->eq_table.irq_names =
1176 kmalloc(MLX4_IRQNAME_SIZE * (dev->caps.num_comp_vectors + 1 +
1177 dev->caps.comp_pool),
1178 GFP_KERNEL);
1179 if (!priv->eq_table.irq_names) {
1180 err = -ENOMEM;
1181 goto err_out_bitmap;
1182 }
1183
1184 for (i = 0; i < dev->caps.num_comp_vectors; ++i) {
1185 err = mlx4_create_eq(dev, dev->caps.num_cqs -
1186 dev->caps.reserved_cqs +
1187 MLX4_NUM_SPARE_EQE,
1188 (dev->flags & MLX4_FLAG_MSI_X) ? i : 0,
1189 &priv->eq_table.eq[i]);
1190 if (err) {
1191 --i;
1192 goto err_out_unmap;
1193 }
1194 }
1195
1196 err = mlx4_create_eq(dev, MLX4_NUM_ASYNC_EQE + MLX4_NUM_SPARE_EQE,
1197 (dev->flags & MLX4_FLAG_MSI_X) ? dev->caps.num_comp_vectors : 0,
1198 &priv->eq_table.eq[dev->caps.num_comp_vectors]);
1199 if (err)
1200 goto err_out_comp;
1201
1202 /*if additional completion vectors poolsize is 0 this loop will not run*/
1203 for (i = dev->caps.num_comp_vectors + 1;
1204 i < dev->caps.num_comp_vectors + dev->caps.comp_pool + 1; ++i) {
1205
1206 err = mlx4_create_eq(dev, dev->caps.num_cqs -
1207 dev->caps.reserved_cqs +
1208 MLX4_NUM_SPARE_EQE,
1209 (dev->flags & MLX4_FLAG_MSI_X) ? i : 0,
1210 &priv->eq_table.eq[i]);
1211 if (err) {
1212 --i;
1213 goto err_out_unmap;
1214 }
1215 }
1216
1217
1218 if (dev->flags & MLX4_FLAG_MSI_X) {
1219 const char *eq_name;
1220
1221 for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i) {
1222 if (i < dev->caps.num_comp_vectors) {
1223 snprintf(priv->eq_table.irq_names +
1224 i * MLX4_IRQNAME_SIZE,
1225 MLX4_IRQNAME_SIZE,
1226 "mlx4-comp-%d@pci:%s", i,
1227 pci_name(dev->persist->pdev));
1228 } else {
1229 snprintf(priv->eq_table.irq_names +
1230 i * MLX4_IRQNAME_SIZE,
1231 MLX4_IRQNAME_SIZE,
1232 "mlx4-async@pci:%s",
1233 pci_name(dev->persist->pdev));
1234 }
1235
1236 eq_name = priv->eq_table.irq_names +
1237 i * MLX4_IRQNAME_SIZE;
1238 err = request_irq(priv->eq_table.eq[i].irq,
1239 mlx4_msi_x_interrupt, 0, eq_name,
1240 priv->eq_table.eq + i);
1241 if (err)
1242 goto err_out_async;
1243
1244 priv->eq_table.eq[i].have_irq = 1;
1245 }
1246 } else {
1247 snprintf(priv->eq_table.irq_names,
1248 MLX4_IRQNAME_SIZE,
1249 DRV_NAME "@pci:%s",
1250 pci_name(dev->persist->pdev));
1251 err = request_irq(dev->persist->pdev->irq, mlx4_interrupt,
1252 IRQF_SHARED, priv->eq_table.irq_names, dev);
1253 if (err)
1254 goto err_out_async;
1255
1256 priv->eq_table.have_irq = 1;
1257 }
1258
1259 err = mlx4_MAP_EQ(dev, get_async_ev_mask(dev), 0,
1260 priv->eq_table.eq[dev->caps.num_comp_vectors].eqn);
1261 if (err)
1262 mlx4_warn(dev, "MAP_EQ for async EQ %d failed (%d)\n",
1263 priv->eq_table.eq[dev->caps.num_comp_vectors].eqn, err);
1264
1265 for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i)
1266 eq_set_ci(&priv->eq_table.eq[i], 1);
1267
1268 return 0;
1269
1270 err_out_async:
1271 mlx4_free_eq(dev, &priv->eq_table.eq[dev->caps.num_comp_vectors]);
1272
1273 err_out_comp:
1274 i = dev->caps.num_comp_vectors - 1;
1275
1276 err_out_unmap:
1277 while (i >= 0) {
1278 mlx4_free_eq(dev, &priv->eq_table.eq[i]);
1279 --i;
1280 }
1281 if (!mlx4_is_slave(dev))
1282 mlx4_unmap_clr_int(dev);
1283 mlx4_free_irqs(dev);
1284
1285 err_out_bitmap:
1286 mlx4_unmap_uar(dev);
1287 mlx4_bitmap_cleanup(&priv->eq_table.bitmap);
1288
1289 err_out_free:
1290 kfree(priv->eq_table.uar_map);
1291
1292 return err;
1293 }
1294
1295 void mlx4_cleanup_eq_table(struct mlx4_dev *dev)
1296 {
1297 struct mlx4_priv *priv = mlx4_priv(dev);
1298 int i;
1299
1300 mlx4_MAP_EQ(dev, get_async_ev_mask(dev), 1,
1301 priv->eq_table.eq[dev->caps.num_comp_vectors].eqn);
1302
1303 mlx4_free_irqs(dev);
1304
1305 for (i = 0; i < dev->caps.num_comp_vectors + dev->caps.comp_pool + 1; ++i)
1306 mlx4_free_eq(dev, &priv->eq_table.eq[i]);
1307
1308 if (!mlx4_is_slave(dev))
1309 mlx4_unmap_clr_int(dev);
1310
1311 mlx4_unmap_uar(dev);
1312 mlx4_bitmap_cleanup(&priv->eq_table.bitmap);
1313
1314 kfree(priv->eq_table.uar_map);
1315 }
1316
1317 /* A test that verifies that we can accept interrupts on all
1318 * the irq vectors of the device.
1319 * Interrupts are checked using the NOP command.
1320 */
1321 int mlx4_test_interrupts(struct mlx4_dev *dev)
1322 {
1323 struct mlx4_priv *priv = mlx4_priv(dev);
1324 int i;
1325 int err;
1326
1327 err = mlx4_NOP(dev);
1328 /* When not in MSI_X, there is only one irq to check */
1329 if (!(dev->flags & MLX4_FLAG_MSI_X) || mlx4_is_slave(dev))
1330 return err;
1331
1332 /* A loop over all completion vectors, for each vector we will check
1333 * whether it works by mapping command completions to that vector
1334 * and performing a NOP command
1335 */
1336 for(i = 0; !err && (i < dev->caps.num_comp_vectors); ++i) {
1337 /* Temporary use polling for command completions */
1338 mlx4_cmd_use_polling(dev);
1339
1340 /* Map the new eq to handle all asynchronous events */
1341 err = mlx4_MAP_EQ(dev, get_async_ev_mask(dev), 0,
1342 priv->eq_table.eq[i].eqn);
1343 if (err) {
1344 mlx4_warn(dev, "Failed mapping eq for interrupt test\n");
1345 mlx4_cmd_use_events(dev);
1346 break;
1347 }
1348
1349 /* Go back to using events */
1350 mlx4_cmd_use_events(dev);
1351 err = mlx4_NOP(dev);
1352 }
1353
1354 /* Return to default */
1355 mlx4_MAP_EQ(dev, get_async_ev_mask(dev), 0,
1356 priv->eq_table.eq[dev->caps.num_comp_vectors].eqn);
1357 return err;
1358 }
1359 EXPORT_SYMBOL(mlx4_test_interrupts);
1360
1361 int mlx4_assign_eq(struct mlx4_dev *dev, char *name, struct cpu_rmap *rmap,
1362 int *vector)
1363 {
1364
1365 struct mlx4_priv *priv = mlx4_priv(dev);
1366 int vec = 0, err = 0, i;
1367
1368 mutex_lock(&priv->msix_ctl.pool_lock);
1369 for (i = 0; !vec && i < dev->caps.comp_pool; i++) {
1370 if (~priv->msix_ctl.pool_bm & 1ULL << i) {
1371 priv->msix_ctl.pool_bm |= 1ULL << i;
1372 vec = dev->caps.num_comp_vectors + 1 + i;
1373 snprintf(priv->eq_table.irq_names +
1374 vec * MLX4_IRQNAME_SIZE,
1375 MLX4_IRQNAME_SIZE, "%s", name);
1376 #ifdef CONFIG_RFS_ACCEL
1377 if (rmap) {
1378 err = irq_cpu_rmap_add(rmap,
1379 priv->eq_table.eq[vec].irq);
1380 if (err)
1381 mlx4_warn(dev, "Failed adding irq rmap\n");
1382 }
1383 #endif
1384 err = request_irq(priv->eq_table.eq[vec].irq,
1385 mlx4_msi_x_interrupt, 0,
1386 &priv->eq_table.irq_names[vec<<5],
1387 priv->eq_table.eq + vec);
1388 if (err) {
1389 /*zero out bit by fliping it*/
1390 priv->msix_ctl.pool_bm ^= 1 << i;
1391 vec = 0;
1392 continue;
1393 /*we dont want to break here*/
1394 }
1395
1396 eq_set_ci(&priv->eq_table.eq[vec], 1);
1397 }
1398 }
1399 mutex_unlock(&priv->msix_ctl.pool_lock);
1400
1401 if (vec) {
1402 *vector = vec;
1403 } else {
1404 *vector = 0;
1405 err = (i == dev->caps.comp_pool) ? -ENOSPC : err;
1406 }
1407 return err;
1408 }
1409 EXPORT_SYMBOL(mlx4_assign_eq);
1410
1411 int mlx4_eq_get_irq(struct mlx4_dev *dev, int vec)
1412 {
1413 struct mlx4_priv *priv = mlx4_priv(dev);
1414
1415 return priv->eq_table.eq[vec].irq;
1416 }
1417 EXPORT_SYMBOL(mlx4_eq_get_irq);
1418
1419 void mlx4_release_eq(struct mlx4_dev *dev, int vec)
1420 {
1421 struct mlx4_priv *priv = mlx4_priv(dev);
1422 /*bm index*/
1423 int i = vec - dev->caps.num_comp_vectors - 1;
1424
1425 if (likely(i >= 0)) {
1426 /*sanity check , making sure were not trying to free irq's
1427 Belonging to a legacy EQ*/
1428 mutex_lock(&priv->msix_ctl.pool_lock);
1429 if (priv->msix_ctl.pool_bm & 1ULL << i) {
1430 free_irq(priv->eq_table.eq[vec].irq,
1431 &priv->eq_table.eq[vec]);
1432 priv->msix_ctl.pool_bm &= ~(1ULL << i);
1433 }
1434 mutex_unlock(&priv->msix_ctl.pool_lock);
1435 }
1436
1437 }
1438 EXPORT_SYMBOL(mlx4_release_eq);
1439
Linux kernel - Deliverables
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