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mlx4: 64-byte CQE/EQE support
[deliverable/linux.git] / drivers / net / ethernet / mellanox / mlx4 / eq.c
1 /*
2 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
3 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
10 *
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
13 * conditions are met:
14 *
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
17 * disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 */
33
34 #include <linux/init.h>
35 #include <linux/interrupt.h>
36 #include <linux/slab.h>
37 #include <linux/export.h>
38 #include <linux/mm.h>
39 #include <linux/dma-mapping.h>
40
41 #include <linux/mlx4/cmd.h>
42 #include <linux/cpu_rmap.h>
43
44 #include "mlx4.h"
45 #include "fw.h"
46
47 enum {
48 MLX4_IRQNAME_SIZE = 32
49 };
50
51 enum {
52 MLX4_NUM_ASYNC_EQE = 0x100,
53 MLX4_NUM_SPARE_EQE = 0x80,
54 MLX4_EQ_ENTRY_SIZE = 0x20
55 };
56
57 #define MLX4_EQ_STATUS_OK ( 0 << 28)
58 #define MLX4_EQ_STATUS_WRITE_FAIL (10 << 28)
59 #define MLX4_EQ_OWNER_SW ( 0 << 24)
60 #define MLX4_EQ_OWNER_HW ( 1 << 24)
61 #define MLX4_EQ_FLAG_EC ( 1 << 18)
62 #define MLX4_EQ_FLAG_OI ( 1 << 17)
63 #define MLX4_EQ_STATE_ARMED ( 9 << 8)
64 #define MLX4_EQ_STATE_FIRED (10 << 8)
65 #define MLX4_EQ_STATE_ALWAYS_ARMED (11 << 8)
66
67 #define MLX4_ASYNC_EVENT_MASK ((1ull << MLX4_EVENT_TYPE_PATH_MIG) | \
68 (1ull << MLX4_EVENT_TYPE_COMM_EST) | \
69 (1ull << MLX4_EVENT_TYPE_SQ_DRAINED) | \
70 (1ull << MLX4_EVENT_TYPE_CQ_ERROR) | \
71 (1ull << MLX4_EVENT_TYPE_WQ_CATAS_ERROR) | \
72 (1ull << MLX4_EVENT_TYPE_EEC_CATAS_ERROR) | \
73 (1ull << MLX4_EVENT_TYPE_PATH_MIG_FAILED) | \
74 (1ull << MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR) | \
75 (1ull << MLX4_EVENT_TYPE_WQ_ACCESS_ERROR) | \
76 (1ull << MLX4_EVENT_TYPE_PORT_CHANGE) | \
77 (1ull << MLX4_EVENT_TYPE_ECC_DETECT) | \
78 (1ull << MLX4_EVENT_TYPE_SRQ_CATAS_ERROR) | \
79 (1ull << MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE) | \
80 (1ull << MLX4_EVENT_TYPE_SRQ_LIMIT) | \
81 (1ull << MLX4_EVENT_TYPE_CMD) | \
82 (1ull << MLX4_EVENT_TYPE_COMM_CHANNEL) | \
83 (1ull << MLX4_EVENT_TYPE_FLR_EVENT) | \
84 (1ull << MLX4_EVENT_TYPE_FATAL_WARNING))
85
86 static u64 get_async_ev_mask(struct mlx4_dev *dev)
87 {
88 u64 async_ev_mask = MLX4_ASYNC_EVENT_MASK;
89 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV)
90 async_ev_mask |= (1ull << MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT);
91
92 return async_ev_mask;
93 }
94
95 static void eq_set_ci(struct mlx4_eq *eq, int req_not)
96 {
97 __raw_writel((__force u32) cpu_to_be32((eq->cons_index & 0xffffff) |
98 req_not << 31),
99 eq->doorbell);
100 /* We still want ordering, just not swabbing, so add a barrier */
101 mb();
102 }
103
104 static struct mlx4_eqe *get_eqe(struct mlx4_eq *eq, u32 entry, u8 eqe_factor)
105 {
106 /* (entry & (eq->nent - 1)) gives us a cyclic array */
107 unsigned long offset = (entry & (eq->nent - 1)) * (MLX4_EQ_ENTRY_SIZE << eqe_factor);
108 /* CX3 is capable of extending the EQE from 32 to 64 bytes.
109 * When this feature is enabled, the first (in the lower addresses)
110 * 32 bytes in the 64 byte EQE are reserved and the next 32 bytes
111 * contain the legacy EQE information.
112 */
113 return eq->page_list[offset / PAGE_SIZE].buf + (offset + (eqe_factor ? MLX4_EQ_ENTRY_SIZE : 0)) % PAGE_SIZE;
114 }
115
116 static struct mlx4_eqe *next_eqe_sw(struct mlx4_eq *eq, u8 eqe_factor)
117 {
118 struct mlx4_eqe *eqe = get_eqe(eq, eq->cons_index, eqe_factor);
119 return !!(eqe->owner & 0x80) ^ !!(eq->cons_index & eq->nent) ? NULL : eqe;
120 }
121
122 static struct mlx4_eqe *next_slave_event_eqe(struct mlx4_slave_event_eq *slave_eq)
123 {
124 struct mlx4_eqe *eqe =
125 &slave_eq->event_eqe[slave_eq->cons & (SLAVE_EVENT_EQ_SIZE - 1)];
126 return (!!(eqe->owner & 0x80) ^
127 !!(slave_eq->cons & SLAVE_EVENT_EQ_SIZE)) ?
128 eqe : NULL;
129 }
130
131 void mlx4_gen_slave_eqe(struct work_struct *work)
132 {
133 struct mlx4_mfunc_master_ctx *master =
134 container_of(work, struct mlx4_mfunc_master_ctx,
135 slave_event_work);
136 struct mlx4_mfunc *mfunc =
137 container_of(master, struct mlx4_mfunc, master);
138 struct mlx4_priv *priv = container_of(mfunc, struct mlx4_priv, mfunc);
139 struct mlx4_dev *dev = &priv->dev;
140 struct mlx4_slave_event_eq *slave_eq = &mfunc->master.slave_eq;
141 struct mlx4_eqe *eqe;
142 u8 slave;
143 int i;
144
145 for (eqe = next_slave_event_eqe(slave_eq); eqe;
146 eqe = next_slave_event_eqe(slave_eq)) {
147 slave = eqe->slave_id;
148
149 /* All active slaves need to receive the event */
150 if (slave == ALL_SLAVES) {
151 for (i = 0; i < dev->num_slaves; i++) {
152 if (i != dev->caps.function &&
153 master->slave_state[i].active)
154 if (mlx4_GEN_EQE(dev, i, eqe))
155 mlx4_warn(dev, "Failed to "
156 " generate event "
157 "for slave %d\n", i);
158 }
159 } else {
160 if (mlx4_GEN_EQE(dev, slave, eqe))
161 mlx4_warn(dev, "Failed to generate event "
162 "for slave %d\n", slave);
163 }
164 ++slave_eq->cons;
165 }
166 }
167
168
169 static void slave_event(struct mlx4_dev *dev, u8 slave, struct mlx4_eqe *eqe)
170 {
171 struct mlx4_priv *priv = mlx4_priv(dev);
172 struct mlx4_slave_event_eq *slave_eq = &priv->mfunc.master.slave_eq;
173 struct mlx4_eqe *s_eqe;
174 unsigned long flags;
175
176 spin_lock_irqsave(&slave_eq->event_lock, flags);
177 s_eqe = &slave_eq->event_eqe[slave_eq->prod & (SLAVE_EVENT_EQ_SIZE - 1)];
178 if ((!!(s_eqe->owner & 0x80)) ^
179 (!!(slave_eq->prod & SLAVE_EVENT_EQ_SIZE))) {
180 mlx4_warn(dev, "Master failed to generate an EQE for slave: %d. "
181 "No free EQE on slave events queue\n", slave);
182 spin_unlock_irqrestore(&slave_eq->event_lock, flags);
183 return;
184 }
185
186 memcpy(s_eqe, eqe, dev->caps.eqe_size - 1);
187 s_eqe->slave_id = slave;
188 /* ensure all information is written before setting the ownersip bit */
189 wmb();
190 s_eqe->owner = !!(slave_eq->prod & SLAVE_EVENT_EQ_SIZE) ? 0x0 : 0x80;
191 ++slave_eq->prod;
192
193 queue_work(priv->mfunc.master.comm_wq,
194 &priv->mfunc.master.slave_event_work);
195 spin_unlock_irqrestore(&slave_eq->event_lock, flags);
196 }
197
198 static void mlx4_slave_event(struct mlx4_dev *dev, int slave,
199 struct mlx4_eqe *eqe)
200 {
201 struct mlx4_priv *priv = mlx4_priv(dev);
202 struct mlx4_slave_state *s_slave =
203 &priv->mfunc.master.slave_state[slave];
204
205 if (!s_slave->active) {
206 /*mlx4_warn(dev, "Trying to pass event to inactive slave\n");*/
207 return;
208 }
209
210 slave_event(dev, slave, eqe);
211 }
212
213 int mlx4_gen_pkey_eqe(struct mlx4_dev *dev, int slave, u8 port)
214 {
215 struct mlx4_eqe eqe;
216
217 struct mlx4_priv *priv = mlx4_priv(dev);
218 struct mlx4_slave_state *s_slave = &priv->mfunc.master.slave_state[slave];
219
220 if (!s_slave->active)
221 return 0;
222
223 memset(&eqe, 0, sizeof eqe);
224
225 eqe.type = MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT;
226 eqe.subtype = MLX4_DEV_PMC_SUBTYPE_PKEY_TABLE;
227 eqe.event.port_mgmt_change.port = port;
228
229 return mlx4_GEN_EQE(dev, slave, &eqe);
230 }
231 EXPORT_SYMBOL(mlx4_gen_pkey_eqe);
232
233 int mlx4_gen_guid_change_eqe(struct mlx4_dev *dev, int slave, u8 port)
234 {
235 struct mlx4_eqe eqe;
236
237 /*don't send if we don't have the that slave */
238 if (dev->num_vfs < slave)
239 return 0;
240 memset(&eqe, 0, sizeof eqe);
241
242 eqe.type = MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT;
243 eqe.subtype = MLX4_DEV_PMC_SUBTYPE_GUID_INFO;
244 eqe.event.port_mgmt_change.port = port;
245
246 return mlx4_GEN_EQE(dev, slave, &eqe);
247 }
248 EXPORT_SYMBOL(mlx4_gen_guid_change_eqe);
249
250 int mlx4_gen_port_state_change_eqe(struct mlx4_dev *dev, int slave, u8 port,
251 u8 port_subtype_change)
252 {
253 struct mlx4_eqe eqe;
254
255 /*don't send if we don't have the that slave */
256 if (dev->num_vfs < slave)
257 return 0;
258 memset(&eqe, 0, sizeof eqe);
259
260 eqe.type = MLX4_EVENT_TYPE_PORT_CHANGE;
261 eqe.subtype = port_subtype_change;
262 eqe.event.port_change.port = cpu_to_be32(port << 28);
263
264 mlx4_dbg(dev, "%s: sending: %d to slave: %d on port: %d\n", __func__,
265 port_subtype_change, slave, port);
266 return mlx4_GEN_EQE(dev, slave, &eqe);
267 }
268 EXPORT_SYMBOL(mlx4_gen_port_state_change_eqe);
269
270 enum slave_port_state mlx4_get_slave_port_state(struct mlx4_dev *dev, int slave, u8 port)
271 {
272 struct mlx4_priv *priv = mlx4_priv(dev);
273 struct mlx4_slave_state *s_state = priv->mfunc.master.slave_state;
274 if (slave >= dev->num_slaves || port > MLX4_MAX_PORTS) {
275 pr_err("%s: Error: asking for slave:%d, port:%d\n",
276 __func__, slave, port);
277 return SLAVE_PORT_DOWN;
278 }
279 return s_state[slave].port_state[port];
280 }
281 EXPORT_SYMBOL(mlx4_get_slave_port_state);
282
283 static int mlx4_set_slave_port_state(struct mlx4_dev *dev, int slave, u8 port,
284 enum slave_port_state state)
285 {
286 struct mlx4_priv *priv = mlx4_priv(dev);
287 struct mlx4_slave_state *s_state = priv->mfunc.master.slave_state;
288
289 if (slave >= dev->num_slaves || port > MLX4_MAX_PORTS || port == 0) {
290 pr_err("%s: Error: asking for slave:%d, port:%d\n",
291 __func__, slave, port);
292 return -1;
293 }
294 s_state[slave].port_state[port] = state;
295
296 return 0;
297 }
298
299 static void set_all_slave_state(struct mlx4_dev *dev, u8 port, int event)
300 {
301 int i;
302 enum slave_port_gen_event gen_event;
303
304 for (i = 0; i < dev->num_slaves; i++)
305 set_and_calc_slave_port_state(dev, i, port, event, &gen_event);
306 }
307 /**************************************************************************
308 The function get as input the new event to that port,
309 and according to the prev state change the slave's port state.
310 The events are:
311 MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN,
312 MLX4_PORT_STATE_DEV_EVENT_PORT_UP
313 MLX4_PORT_STATE_IB_EVENT_GID_VALID
314 MLX4_PORT_STATE_IB_EVENT_GID_INVALID
315 ***************************************************************************/
316 int set_and_calc_slave_port_state(struct mlx4_dev *dev, int slave,
317 u8 port, int event,
318 enum slave_port_gen_event *gen_event)
319 {
320 struct mlx4_priv *priv = mlx4_priv(dev);
321 struct mlx4_slave_state *ctx = NULL;
322 unsigned long flags;
323 int ret = -1;
324 enum slave_port_state cur_state =
325 mlx4_get_slave_port_state(dev, slave, port);
326
327 *gen_event = SLAVE_PORT_GEN_EVENT_NONE;
328
329 if (slave >= dev->num_slaves || port > MLX4_MAX_PORTS || port == 0) {
330 pr_err("%s: Error: asking for slave:%d, port:%d\n",
331 __func__, slave, port);
332 return ret;
333 }
334
335 ctx = &priv->mfunc.master.slave_state[slave];
336 spin_lock_irqsave(&ctx->lock, flags);
337
338 switch (cur_state) {
339 case SLAVE_PORT_DOWN:
340 if (MLX4_PORT_STATE_DEV_EVENT_PORT_UP == event)
341 mlx4_set_slave_port_state(dev, slave, port,
342 SLAVE_PENDING_UP);
343 break;
344 case SLAVE_PENDING_UP:
345 if (MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN == event)
346 mlx4_set_slave_port_state(dev, slave, port,
347 SLAVE_PORT_DOWN);
348 else if (MLX4_PORT_STATE_IB_PORT_STATE_EVENT_GID_VALID == event) {
349 mlx4_set_slave_port_state(dev, slave, port,
350 SLAVE_PORT_UP);
351 *gen_event = SLAVE_PORT_GEN_EVENT_UP;
352 }
353 break;
354 case SLAVE_PORT_UP:
355 if (MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN == event) {
356 mlx4_set_slave_port_state(dev, slave, port,
357 SLAVE_PORT_DOWN);
358 *gen_event = SLAVE_PORT_GEN_EVENT_DOWN;
359 } else if (MLX4_PORT_STATE_IB_EVENT_GID_INVALID ==
360 event) {
361 mlx4_set_slave_port_state(dev, slave, port,
362 SLAVE_PENDING_UP);
363 *gen_event = SLAVE_PORT_GEN_EVENT_DOWN;
364 }
365 break;
366 default:
367 pr_err("%s: BUG!!! UNKNOWN state: "
368 "slave:%d, port:%d\n", __func__, slave, port);
369 goto out;
370 }
371 ret = mlx4_get_slave_port_state(dev, slave, port);
372
373 out:
374 spin_unlock_irqrestore(&ctx->lock, flags);
375 return ret;
376 }
377
378 EXPORT_SYMBOL(set_and_calc_slave_port_state);
379
380 int mlx4_gen_slaves_port_mgt_ev(struct mlx4_dev *dev, u8 port, int attr)
381 {
382 struct mlx4_eqe eqe;
383
384 memset(&eqe, 0, sizeof eqe);
385
386 eqe.type = MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT;
387 eqe.subtype = MLX4_DEV_PMC_SUBTYPE_PORT_INFO;
388 eqe.event.port_mgmt_change.port = port;
389 eqe.event.port_mgmt_change.params.port_info.changed_attr =
390 cpu_to_be32((u32) attr);
391
392 slave_event(dev, ALL_SLAVES, &eqe);
393 return 0;
394 }
395 EXPORT_SYMBOL(mlx4_gen_slaves_port_mgt_ev);
396
397 void mlx4_master_handle_slave_flr(struct work_struct *work)
398 {
399 struct mlx4_mfunc_master_ctx *master =
400 container_of(work, struct mlx4_mfunc_master_ctx,
401 slave_flr_event_work);
402 struct mlx4_mfunc *mfunc =
403 container_of(master, struct mlx4_mfunc, master);
404 struct mlx4_priv *priv =
405 container_of(mfunc, struct mlx4_priv, mfunc);
406 struct mlx4_dev *dev = &priv->dev;
407 struct mlx4_slave_state *slave_state = priv->mfunc.master.slave_state;
408 int i;
409 int err;
410
411 mlx4_dbg(dev, "mlx4_handle_slave_flr\n");
412
413 for (i = 0 ; i < dev->num_slaves; i++) {
414
415 if (MLX4_COMM_CMD_FLR == slave_state[i].last_cmd) {
416 mlx4_dbg(dev, "mlx4_handle_slave_flr: "
417 "clean slave: %d\n", i);
418
419 mlx4_delete_all_resources_for_slave(dev, i);
420 /*return the slave to running mode*/
421 spin_lock(&priv->mfunc.master.slave_state_lock);
422 slave_state[i].last_cmd = MLX4_COMM_CMD_RESET;
423 slave_state[i].is_slave_going_down = 0;
424 spin_unlock(&priv->mfunc.master.slave_state_lock);
425 /*notify the FW:*/
426 err = mlx4_cmd(dev, 0, i, 0, MLX4_CMD_INFORM_FLR_DONE,
427 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
428 if (err)
429 mlx4_warn(dev, "Failed to notify FW on "
430 "FLR done (slave:%d)\n", i);
431 }
432 }
433 }
434
435 static int mlx4_eq_int(struct mlx4_dev *dev, struct mlx4_eq *eq)
436 {
437 struct mlx4_priv *priv = mlx4_priv(dev);
438 struct mlx4_eqe *eqe;
439 int cqn;
440 int eqes_found = 0;
441 int set_ci = 0;
442 int port;
443 int slave = 0;
444 int ret;
445 u32 flr_slave;
446 u8 update_slave_state;
447 int i;
448 enum slave_port_gen_event gen_event;
449
450 while ((eqe = next_eqe_sw(eq, dev->caps.eqe_factor))) {
451 /*
452 * Make sure we read EQ entry contents after we've
453 * checked the ownership bit.
454 */
455 rmb();
456
457 switch (eqe->type) {
458 case MLX4_EVENT_TYPE_COMP:
459 cqn = be32_to_cpu(eqe->event.comp.cqn) & 0xffffff;
460 mlx4_cq_completion(dev, cqn);
461 break;
462
463 case MLX4_EVENT_TYPE_PATH_MIG:
464 case MLX4_EVENT_TYPE_COMM_EST:
465 case MLX4_EVENT_TYPE_SQ_DRAINED:
466 case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE:
467 case MLX4_EVENT_TYPE_WQ_CATAS_ERROR:
468 case MLX4_EVENT_TYPE_PATH_MIG_FAILED:
469 case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
470 case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR:
471 mlx4_dbg(dev, "event %d arrived\n", eqe->type);
472 if (mlx4_is_master(dev)) {
473 /* forward only to slave owning the QP */
474 ret = mlx4_get_slave_from_resource_id(dev,
475 RES_QP,
476 be32_to_cpu(eqe->event.qp.qpn)
477 & 0xffffff, &slave);
478 if (ret && ret != -ENOENT) {
479 mlx4_dbg(dev, "QP event %02x(%02x) on "
480 "EQ %d at index %u: could "
481 "not get slave id (%d)\n",
482 eqe->type, eqe->subtype,
483 eq->eqn, eq->cons_index, ret);
484 break;
485 }
486
487 if (!ret && slave != dev->caps.function) {
488 mlx4_slave_event(dev, slave, eqe);
489 break;
490 }
491
492 }
493 mlx4_qp_event(dev, be32_to_cpu(eqe->event.qp.qpn) &
494 0xffffff, eqe->type);
495 break;
496
497 case MLX4_EVENT_TYPE_SRQ_LIMIT:
498 mlx4_warn(dev, "%s: MLX4_EVENT_TYPE_SRQ_LIMIT\n",
499 __func__);
500 case MLX4_EVENT_TYPE_SRQ_CATAS_ERROR:
501 if (mlx4_is_master(dev)) {
502 /* forward only to slave owning the SRQ */
503 ret = mlx4_get_slave_from_resource_id(dev,
504 RES_SRQ,
505 be32_to_cpu(eqe->event.srq.srqn)
506 & 0xffffff,
507 &slave);
508 if (ret && ret != -ENOENT) {
509 mlx4_warn(dev, "SRQ event %02x(%02x) "
510 "on EQ %d at index %u: could"
511 " not get slave id (%d)\n",
512 eqe->type, eqe->subtype,
513 eq->eqn, eq->cons_index, ret);
514 break;
515 }
516 mlx4_warn(dev, "%s: slave:%d, srq_no:0x%x,"
517 " event: %02x(%02x)\n", __func__,
518 slave,
519 be32_to_cpu(eqe->event.srq.srqn),
520 eqe->type, eqe->subtype);
521
522 if (!ret && slave != dev->caps.function) {
523 mlx4_warn(dev, "%s: sending event "
524 "%02x(%02x) to slave:%d\n",
525 __func__, eqe->type,
526 eqe->subtype, slave);
527 mlx4_slave_event(dev, slave, eqe);
528 break;
529 }
530 }
531 mlx4_srq_event(dev, be32_to_cpu(eqe->event.srq.srqn) &
532 0xffffff, eqe->type);
533 break;
534
535 case MLX4_EVENT_TYPE_CMD:
536 mlx4_cmd_event(dev,
537 be16_to_cpu(eqe->event.cmd.token),
538 eqe->event.cmd.status,
539 be64_to_cpu(eqe->event.cmd.out_param));
540 break;
541
542 case MLX4_EVENT_TYPE_PORT_CHANGE:
543 port = be32_to_cpu(eqe->event.port_change.port) >> 28;
544 if (eqe->subtype == MLX4_PORT_CHANGE_SUBTYPE_DOWN) {
545 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_PORT_DOWN,
546 port);
547 mlx4_priv(dev)->sense.do_sense_port[port] = 1;
548 if (!mlx4_is_master(dev))
549 break;
550 for (i = 0; i < dev->num_slaves; i++) {
551 if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH) {
552 if (i == mlx4_master_func_num(dev))
553 continue;
554 mlx4_dbg(dev, "%s: Sending MLX4_PORT_CHANGE_SUBTYPE_DOWN"
555 " to slave: %d, port:%d\n",
556 __func__, i, port);
557 mlx4_slave_event(dev, i, eqe);
558 } else { /* IB port */
559 set_and_calc_slave_port_state(dev, i, port,
560 MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN,
561 &gen_event);
562 /*we can be in pending state, then do not send port_down event*/
563 if (SLAVE_PORT_GEN_EVENT_DOWN == gen_event) {
564 if (i == mlx4_master_func_num(dev))
565 continue;
566 mlx4_slave_event(dev, i, eqe);
567 }
568 }
569 }
570 } else {
571 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_PORT_UP, port);
572
573 mlx4_priv(dev)->sense.do_sense_port[port] = 0;
574
575 if (!mlx4_is_master(dev))
576 break;
577 if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH)
578 for (i = 0; i < dev->num_slaves; i++) {
579 if (i == mlx4_master_func_num(dev))
580 continue;
581 mlx4_slave_event(dev, i, eqe);
582 }
583 else /* IB port */
584 /* port-up event will be sent to a slave when the
585 * slave's alias-guid is set. This is done in alias_GUID.c
586 */
587 set_all_slave_state(dev, port, MLX4_DEV_EVENT_PORT_UP);
588 }
589 break;
590
591 case MLX4_EVENT_TYPE_CQ_ERROR:
592 mlx4_warn(dev, "CQ %s on CQN %06x\n",
593 eqe->event.cq_err.syndrome == 1 ?
594 "overrun" : "access violation",
595 be32_to_cpu(eqe->event.cq_err.cqn) & 0xffffff);
596 if (mlx4_is_master(dev)) {
597 ret = mlx4_get_slave_from_resource_id(dev,
598 RES_CQ,
599 be32_to_cpu(eqe->event.cq_err.cqn)
600 & 0xffffff, &slave);
601 if (ret && ret != -ENOENT) {
602 mlx4_dbg(dev, "CQ event %02x(%02x) on "
603 "EQ %d at index %u: could "
604 "not get slave id (%d)\n",
605 eqe->type, eqe->subtype,
606 eq->eqn, eq->cons_index, ret);
607 break;
608 }
609
610 if (!ret && slave != dev->caps.function) {
611 mlx4_slave_event(dev, slave, eqe);
612 break;
613 }
614 }
615 mlx4_cq_event(dev,
616 be32_to_cpu(eqe->event.cq_err.cqn)
617 & 0xffffff,
618 eqe->type);
619 break;
620
621 case MLX4_EVENT_TYPE_EQ_OVERFLOW:
622 mlx4_warn(dev, "EQ overrun on EQN %d\n", eq->eqn);
623 break;
624
625 case MLX4_EVENT_TYPE_COMM_CHANNEL:
626 if (!mlx4_is_master(dev)) {
627 mlx4_warn(dev, "Received comm channel event "
628 "for non master device\n");
629 break;
630 }
631 memcpy(&priv->mfunc.master.comm_arm_bit_vector,
632 eqe->event.comm_channel_arm.bit_vec,
633 sizeof eqe->event.comm_channel_arm.bit_vec);
634 queue_work(priv->mfunc.master.comm_wq,
635 &priv->mfunc.master.comm_work);
636 break;
637
638 case MLX4_EVENT_TYPE_FLR_EVENT:
639 flr_slave = be32_to_cpu(eqe->event.flr_event.slave_id);
640 if (!mlx4_is_master(dev)) {
641 mlx4_warn(dev, "Non-master function received"
642 "FLR event\n");
643 break;
644 }
645
646 mlx4_dbg(dev, "FLR event for slave: %d\n", flr_slave);
647
648 if (flr_slave >= dev->num_slaves) {
649 mlx4_warn(dev,
650 "Got FLR for unknown function: %d\n",
651 flr_slave);
652 update_slave_state = 0;
653 } else
654 update_slave_state = 1;
655
656 spin_lock(&priv->mfunc.master.slave_state_lock);
657 if (update_slave_state) {
658 priv->mfunc.master.slave_state[flr_slave].active = false;
659 priv->mfunc.master.slave_state[flr_slave].last_cmd = MLX4_COMM_CMD_FLR;
660 priv->mfunc.master.slave_state[flr_slave].is_slave_going_down = 1;
661 }
662 spin_unlock(&priv->mfunc.master.slave_state_lock);
663 queue_work(priv->mfunc.master.comm_wq,
664 &priv->mfunc.master.slave_flr_event_work);
665 break;
666
667 case MLX4_EVENT_TYPE_FATAL_WARNING:
668 if (eqe->subtype == MLX4_FATAL_WARNING_SUBTYPE_WARMING) {
669 if (mlx4_is_master(dev))
670 for (i = 0; i < dev->num_slaves; i++) {
671 mlx4_dbg(dev, "%s: Sending "
672 "MLX4_FATAL_WARNING_SUBTYPE_WARMING"
673 " to slave: %d\n", __func__, i);
674 if (i == dev->caps.function)
675 continue;
676 mlx4_slave_event(dev, i, eqe);
677 }
678 mlx4_err(dev, "Temperature Threshold was reached! "
679 "Threshold: %d celsius degrees; "
680 "Current Temperature: %d\n",
681 be16_to_cpu(eqe->event.warming.warning_threshold),
682 be16_to_cpu(eqe->event.warming.current_temperature));
683 } else
684 mlx4_warn(dev, "Unhandled event FATAL WARNING (%02x), "
685 "subtype %02x on EQ %d at index %u. owner=%x, "
686 "nent=0x%x, slave=%x, ownership=%s\n",
687 eqe->type, eqe->subtype, eq->eqn,
688 eq->cons_index, eqe->owner, eq->nent,
689 eqe->slave_id,
690 !!(eqe->owner & 0x80) ^
691 !!(eq->cons_index & eq->nent) ? "HW" : "SW");
692
693 break;
694
695 case MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT:
696 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_PORT_MGMT_CHANGE,
697 (unsigned long) eqe);
698 break;
699
700 case MLX4_EVENT_TYPE_EEC_CATAS_ERROR:
701 case MLX4_EVENT_TYPE_ECC_DETECT:
702 default:
703 mlx4_warn(dev, "Unhandled event %02x(%02x) on EQ %d at "
704 "index %u. owner=%x, nent=0x%x, slave=%x, "
705 "ownership=%s\n",
706 eqe->type, eqe->subtype, eq->eqn,
707 eq->cons_index, eqe->owner, eq->nent,
708 eqe->slave_id,
709 !!(eqe->owner & 0x80) ^
710 !!(eq->cons_index & eq->nent) ? "HW" : "SW");
711 break;
712 };
713
714 ++eq->cons_index;
715 eqes_found = 1;
716 ++set_ci;
717
718 /*
719 * The HCA will think the queue has overflowed if we
720 * don't tell it we've been processing events. We
721 * create our EQs with MLX4_NUM_SPARE_EQE extra
722 * entries, so we must update our consumer index at
723 * least that often.
724 */
725 if (unlikely(set_ci >= MLX4_NUM_SPARE_EQE)) {
726 eq_set_ci(eq, 0);
727 set_ci = 0;
728 }
729 }
730
731 eq_set_ci(eq, 1);
732
733 return eqes_found;
734 }
735
736 static irqreturn_t mlx4_interrupt(int irq, void *dev_ptr)
737 {
738 struct mlx4_dev *dev = dev_ptr;
739 struct mlx4_priv *priv = mlx4_priv(dev);
740 int work = 0;
741 int i;
742
743 writel(priv->eq_table.clr_mask, priv->eq_table.clr_int);
744
745 for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i)
746 work |= mlx4_eq_int(dev, &priv->eq_table.eq[i]);
747
748 return IRQ_RETVAL(work);
749 }
750
751 static irqreturn_t mlx4_msi_x_interrupt(int irq, void *eq_ptr)
752 {
753 struct mlx4_eq *eq = eq_ptr;
754 struct mlx4_dev *dev = eq->dev;
755
756 mlx4_eq_int(dev, eq);
757
758 /* MSI-X vectors always belong to us */
759 return IRQ_HANDLED;
760 }
761
762 int mlx4_MAP_EQ_wrapper(struct mlx4_dev *dev, int slave,
763 struct mlx4_vhcr *vhcr,
764 struct mlx4_cmd_mailbox *inbox,
765 struct mlx4_cmd_mailbox *outbox,
766 struct mlx4_cmd_info *cmd)
767 {
768 struct mlx4_priv *priv = mlx4_priv(dev);
769 struct mlx4_slave_event_eq_info *event_eq =
770 priv->mfunc.master.slave_state[slave].event_eq;
771 u32 in_modifier = vhcr->in_modifier;
772 u32 eqn = in_modifier & 0x1FF;
773 u64 in_param = vhcr->in_param;
774 int err = 0;
775 int i;
776
777 if (slave == dev->caps.function)
778 err = mlx4_cmd(dev, in_param, (in_modifier & 0x80000000) | eqn,
779 0, MLX4_CMD_MAP_EQ, MLX4_CMD_TIME_CLASS_B,
780 MLX4_CMD_NATIVE);
781 if (!err)
782 for (i = 0; i < MLX4_EVENT_TYPES_NUM; ++i)
783 if (in_param & (1LL << i))
784 event_eq[i].eqn = in_modifier >> 31 ? -1 : eqn;
785
786 return err;
787 }
788
789 static int mlx4_MAP_EQ(struct mlx4_dev *dev, u64 event_mask, int unmap,
790 int eq_num)
791 {
792 return mlx4_cmd(dev, event_mask, (unmap << 31) | eq_num,
793 0, MLX4_CMD_MAP_EQ, MLX4_CMD_TIME_CLASS_B,
794 MLX4_CMD_WRAPPED);
795 }
796
797 static int mlx4_SW2HW_EQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
798 int eq_num)
799 {
800 return mlx4_cmd(dev, mailbox->dma, eq_num, 0,
801 MLX4_CMD_SW2HW_EQ, MLX4_CMD_TIME_CLASS_A,
802 MLX4_CMD_WRAPPED);
803 }
804
805 static int mlx4_HW2SW_EQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
806 int eq_num)
807 {
808 return mlx4_cmd_box(dev, 0, mailbox->dma, eq_num,
809 0, MLX4_CMD_HW2SW_EQ, MLX4_CMD_TIME_CLASS_A,
810 MLX4_CMD_WRAPPED);
811 }
812
813 static int mlx4_num_eq_uar(struct mlx4_dev *dev)
814 {
815 /*
816 * Each UAR holds 4 EQ doorbells. To figure out how many UARs
817 * we need to map, take the difference of highest index and
818 * the lowest index we'll use and add 1.
819 */
820 return (dev->caps.num_comp_vectors + 1 + dev->caps.reserved_eqs +
821 dev->caps.comp_pool)/4 - dev->caps.reserved_eqs/4 + 1;
822 }
823
824 static void __iomem *mlx4_get_eq_uar(struct mlx4_dev *dev, struct mlx4_eq *eq)
825 {
826 struct mlx4_priv *priv = mlx4_priv(dev);
827 int index;
828
829 index = eq->eqn / 4 - dev->caps.reserved_eqs / 4;
830
831 if (!priv->eq_table.uar_map[index]) {
832 priv->eq_table.uar_map[index] =
833 ioremap(pci_resource_start(dev->pdev, 2) +
834 ((eq->eqn / 4) << PAGE_SHIFT),
835 PAGE_SIZE);
836 if (!priv->eq_table.uar_map[index]) {
837 mlx4_err(dev, "Couldn't map EQ doorbell for EQN 0x%06x\n",
838 eq->eqn);
839 return NULL;
840 }
841 }
842
843 return priv->eq_table.uar_map[index] + 0x800 + 8 * (eq->eqn % 4);
844 }
845
846 static void mlx4_unmap_uar(struct mlx4_dev *dev)
847 {
848 struct mlx4_priv *priv = mlx4_priv(dev);
849 int i;
850
851 for (i = 0; i < mlx4_num_eq_uar(dev); ++i)
852 if (priv->eq_table.uar_map[i]) {
853 iounmap(priv->eq_table.uar_map[i]);
854 priv->eq_table.uar_map[i] = NULL;
855 }
856 }
857
858 static int mlx4_create_eq(struct mlx4_dev *dev, int nent,
859 u8 intr, struct mlx4_eq *eq)
860 {
861 struct mlx4_priv *priv = mlx4_priv(dev);
862 struct mlx4_cmd_mailbox *mailbox;
863 struct mlx4_eq_context *eq_context;
864 int npages;
865 u64 *dma_list = NULL;
866 dma_addr_t t;
867 u64 mtt_addr;
868 int err = -ENOMEM;
869 int i;
870
871 eq->dev = dev;
872 eq->nent = roundup_pow_of_two(max(nent, 2));
873 /* CX3 is capable of extending the CQE/EQE from 32 to 64 bytes */
874 npages = PAGE_ALIGN(eq->nent * (MLX4_EQ_ENTRY_SIZE << dev->caps.eqe_factor)) / PAGE_SIZE;
875
876 eq->page_list = kmalloc(npages * sizeof *eq->page_list,
877 GFP_KERNEL);
878 if (!eq->page_list)
879 goto err_out;
880
881 for (i = 0; i < npages; ++i)
882 eq->page_list[i].buf = NULL;
883
884 dma_list = kmalloc(npages * sizeof *dma_list, GFP_KERNEL);
885 if (!dma_list)
886 goto err_out_free;
887
888 mailbox = mlx4_alloc_cmd_mailbox(dev);
889 if (IS_ERR(mailbox))
890 goto err_out_free;
891 eq_context = mailbox->buf;
892
893 for (i = 0; i < npages; ++i) {
894 eq->page_list[i].buf = dma_alloc_coherent(&dev->pdev->dev,
895 PAGE_SIZE, &t, GFP_KERNEL);
896 if (!eq->page_list[i].buf)
897 goto err_out_free_pages;
898
899 dma_list[i] = t;
900 eq->page_list[i].map = t;
901
902 memset(eq->page_list[i].buf, 0, PAGE_SIZE);
903 }
904
905 eq->eqn = mlx4_bitmap_alloc(&priv->eq_table.bitmap);
906 if (eq->eqn == -1)
907 goto err_out_free_pages;
908
909 eq->doorbell = mlx4_get_eq_uar(dev, eq);
910 if (!eq->doorbell) {
911 err = -ENOMEM;
912 goto err_out_free_eq;
913 }
914
915 err = mlx4_mtt_init(dev, npages, PAGE_SHIFT, &eq->mtt);
916 if (err)
917 goto err_out_free_eq;
918
919 err = mlx4_write_mtt(dev, &eq->mtt, 0, npages, dma_list);
920 if (err)
921 goto err_out_free_mtt;
922
923 memset(eq_context, 0, sizeof *eq_context);
924 eq_context->flags = cpu_to_be32(MLX4_EQ_STATUS_OK |
925 MLX4_EQ_STATE_ARMED);
926 eq_context->log_eq_size = ilog2(eq->nent);
927 eq_context->intr = intr;
928 eq_context->log_page_size = PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT;
929
930 mtt_addr = mlx4_mtt_addr(dev, &eq->mtt);
931 eq_context->mtt_base_addr_h = mtt_addr >> 32;
932 eq_context->mtt_base_addr_l = cpu_to_be32(mtt_addr & 0xffffffff);
933
934 err = mlx4_SW2HW_EQ(dev, mailbox, eq->eqn);
935 if (err) {
936 mlx4_warn(dev, "SW2HW_EQ failed (%d)\n", err);
937 goto err_out_free_mtt;
938 }
939
940 kfree(dma_list);
941 mlx4_free_cmd_mailbox(dev, mailbox);
942
943 eq->cons_index = 0;
944
945 return err;
946
947 err_out_free_mtt:
948 mlx4_mtt_cleanup(dev, &eq->mtt);
949
950 err_out_free_eq:
951 mlx4_bitmap_free(&priv->eq_table.bitmap, eq->eqn);
952
953 err_out_free_pages:
954 for (i = 0; i < npages; ++i)
955 if (eq->page_list[i].buf)
956 dma_free_coherent(&dev->pdev->dev, PAGE_SIZE,
957 eq->page_list[i].buf,
958 eq->page_list[i].map);
959
960 mlx4_free_cmd_mailbox(dev, mailbox);
961
962 err_out_free:
963 kfree(eq->page_list);
964 kfree(dma_list);
965
966 err_out:
967 return err;
968 }
969
970 static void mlx4_free_eq(struct mlx4_dev *dev,
971 struct mlx4_eq *eq)
972 {
973 struct mlx4_priv *priv = mlx4_priv(dev);
974 struct mlx4_cmd_mailbox *mailbox;
975 int err;
976 int i;
977 /* CX3 is capable of extending the CQE/EQE from 32 to 64 bytes */
978 int npages = PAGE_ALIGN((MLX4_EQ_ENTRY_SIZE << dev->caps.eqe_factor) * eq->nent) / PAGE_SIZE;
979
980 mailbox = mlx4_alloc_cmd_mailbox(dev);
981 if (IS_ERR(mailbox))
982 return;
983
984 err = mlx4_HW2SW_EQ(dev, mailbox, eq->eqn);
985 if (err)
986 mlx4_warn(dev, "HW2SW_EQ failed (%d)\n", err);
987
988 if (0) {
989 mlx4_dbg(dev, "Dumping EQ context %02x:\n", eq->eqn);
990 for (i = 0; i < sizeof (struct mlx4_eq_context) / 4; ++i) {
991 if (i % 4 == 0)
992 pr_cont("[%02x] ", i * 4);
993 pr_cont(" %08x", be32_to_cpup(mailbox->buf + i * 4));
994 if ((i + 1) % 4 == 0)
995 pr_cont("\n");
996 }
997 }
998
999 mlx4_mtt_cleanup(dev, &eq->mtt);
1000 for (i = 0; i < npages; ++i)
1001 dma_free_coherent(&dev->pdev->dev, PAGE_SIZE,
1002 eq->page_list[i].buf,
1003 eq->page_list[i].map);
1004
1005 kfree(eq->page_list);
1006 mlx4_bitmap_free(&priv->eq_table.bitmap, eq->eqn);
1007 mlx4_free_cmd_mailbox(dev, mailbox);
1008 }
1009
1010 static void mlx4_free_irqs(struct mlx4_dev *dev)
1011 {
1012 struct mlx4_eq_table *eq_table = &mlx4_priv(dev)->eq_table;
1013 struct mlx4_priv *priv = mlx4_priv(dev);
1014 int i, vec;
1015
1016 if (eq_table->have_irq)
1017 free_irq(dev->pdev->irq, dev);
1018
1019 for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i)
1020 if (eq_table->eq[i].have_irq) {
1021 free_irq(eq_table->eq[i].irq, eq_table->eq + i);
1022 eq_table->eq[i].have_irq = 0;
1023 }
1024
1025 for (i = 0; i < dev->caps.comp_pool; i++) {
1026 /*
1027 * Freeing the assigned irq's
1028 * all bits should be 0, but we need to validate
1029 */
1030 if (priv->msix_ctl.pool_bm & 1ULL << i) {
1031 /* NO need protecting*/
1032 vec = dev->caps.num_comp_vectors + 1 + i;
1033 free_irq(priv->eq_table.eq[vec].irq,
1034 &priv->eq_table.eq[vec]);
1035 }
1036 }
1037
1038
1039 kfree(eq_table->irq_names);
1040 }
1041
1042 static int mlx4_map_clr_int(struct mlx4_dev *dev)
1043 {
1044 struct mlx4_priv *priv = mlx4_priv(dev);
1045
1046 priv->clr_base = ioremap(pci_resource_start(dev->pdev, priv->fw.clr_int_bar) +
1047 priv->fw.clr_int_base, MLX4_CLR_INT_SIZE);
1048 if (!priv->clr_base) {
1049 mlx4_err(dev, "Couldn't map interrupt clear register, aborting.\n");
1050 return -ENOMEM;
1051 }
1052
1053 return 0;
1054 }
1055
1056 static void mlx4_unmap_clr_int(struct mlx4_dev *dev)
1057 {
1058 struct mlx4_priv *priv = mlx4_priv(dev);
1059
1060 iounmap(priv->clr_base);
1061 }
1062
1063 int mlx4_alloc_eq_table(struct mlx4_dev *dev)
1064 {
1065 struct mlx4_priv *priv = mlx4_priv(dev);
1066
1067 priv->eq_table.eq = kcalloc(dev->caps.num_eqs - dev->caps.reserved_eqs,
1068 sizeof *priv->eq_table.eq, GFP_KERNEL);
1069 if (!priv->eq_table.eq)
1070 return -ENOMEM;
1071
1072 return 0;
1073 }
1074
1075 void mlx4_free_eq_table(struct mlx4_dev *dev)
1076 {
1077 kfree(mlx4_priv(dev)->eq_table.eq);
1078 }
1079
1080 int mlx4_init_eq_table(struct mlx4_dev *dev)
1081 {
1082 struct mlx4_priv *priv = mlx4_priv(dev);
1083 int err;
1084 int i;
1085
1086 priv->eq_table.uar_map = kcalloc(mlx4_num_eq_uar(dev),
1087 sizeof *priv->eq_table.uar_map,
1088 GFP_KERNEL);
1089 if (!priv->eq_table.uar_map) {
1090 err = -ENOMEM;
1091 goto err_out_free;
1092 }
1093
1094 err = mlx4_bitmap_init(&priv->eq_table.bitmap, dev->caps.num_eqs,
1095 dev->caps.num_eqs - 1, dev->caps.reserved_eqs, 0);
1096 if (err)
1097 goto err_out_free;
1098
1099 for (i = 0; i < mlx4_num_eq_uar(dev); ++i)
1100 priv->eq_table.uar_map[i] = NULL;
1101
1102 if (!mlx4_is_slave(dev)) {
1103 err = mlx4_map_clr_int(dev);
1104 if (err)
1105 goto err_out_bitmap;
1106
1107 priv->eq_table.clr_mask =
1108 swab32(1 << (priv->eq_table.inta_pin & 31));
1109 priv->eq_table.clr_int = priv->clr_base +
1110 (priv->eq_table.inta_pin < 32 ? 4 : 0);
1111 }
1112
1113 priv->eq_table.irq_names =
1114 kmalloc(MLX4_IRQNAME_SIZE * (dev->caps.num_comp_vectors + 1 +
1115 dev->caps.comp_pool),
1116 GFP_KERNEL);
1117 if (!priv->eq_table.irq_names) {
1118 err = -ENOMEM;
1119 goto err_out_bitmap;
1120 }
1121
1122 for (i = 0; i < dev->caps.num_comp_vectors; ++i) {
1123 err = mlx4_create_eq(dev, dev->caps.num_cqs -
1124 dev->caps.reserved_cqs +
1125 MLX4_NUM_SPARE_EQE,
1126 (dev->flags & MLX4_FLAG_MSI_X) ? i : 0,
1127 &priv->eq_table.eq[i]);
1128 if (err) {
1129 --i;
1130 goto err_out_unmap;
1131 }
1132 }
1133
1134 err = mlx4_create_eq(dev, MLX4_NUM_ASYNC_EQE + MLX4_NUM_SPARE_EQE,
1135 (dev->flags & MLX4_FLAG_MSI_X) ? dev->caps.num_comp_vectors : 0,
1136 &priv->eq_table.eq[dev->caps.num_comp_vectors]);
1137 if (err)
1138 goto err_out_comp;
1139
1140 /*if additional completion vectors poolsize is 0 this loop will not run*/
1141 for (i = dev->caps.num_comp_vectors + 1;
1142 i < dev->caps.num_comp_vectors + dev->caps.comp_pool + 1; ++i) {
1143
1144 err = mlx4_create_eq(dev, dev->caps.num_cqs -
1145 dev->caps.reserved_cqs +
1146 MLX4_NUM_SPARE_EQE,
1147 (dev->flags & MLX4_FLAG_MSI_X) ? i : 0,
1148 &priv->eq_table.eq[i]);
1149 if (err) {
1150 --i;
1151 goto err_out_unmap;
1152 }
1153 }
1154
1155
1156 if (dev->flags & MLX4_FLAG_MSI_X) {
1157 const char *eq_name;
1158
1159 for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i) {
1160 if (i < dev->caps.num_comp_vectors) {
1161 snprintf(priv->eq_table.irq_names +
1162 i * MLX4_IRQNAME_SIZE,
1163 MLX4_IRQNAME_SIZE,
1164 "mlx4-comp-%d@pci:%s", i,
1165 pci_name(dev->pdev));
1166 } else {
1167 snprintf(priv->eq_table.irq_names +
1168 i * MLX4_IRQNAME_SIZE,
1169 MLX4_IRQNAME_SIZE,
1170 "mlx4-async@pci:%s",
1171 pci_name(dev->pdev));
1172 }
1173
1174 eq_name = priv->eq_table.irq_names +
1175 i * MLX4_IRQNAME_SIZE;
1176 err = request_irq(priv->eq_table.eq[i].irq,
1177 mlx4_msi_x_interrupt, 0, eq_name,
1178 priv->eq_table.eq + i);
1179 if (err)
1180 goto err_out_async;
1181
1182 priv->eq_table.eq[i].have_irq = 1;
1183 }
1184 } else {
1185 snprintf(priv->eq_table.irq_names,
1186 MLX4_IRQNAME_SIZE,
1187 DRV_NAME "@pci:%s",
1188 pci_name(dev->pdev));
1189 err = request_irq(dev->pdev->irq, mlx4_interrupt,
1190 IRQF_SHARED, priv->eq_table.irq_names, dev);
1191 if (err)
1192 goto err_out_async;
1193
1194 priv->eq_table.have_irq = 1;
1195 }
1196
1197 err = mlx4_MAP_EQ(dev, get_async_ev_mask(dev), 0,
1198 priv->eq_table.eq[dev->caps.num_comp_vectors].eqn);
1199 if (err)
1200 mlx4_warn(dev, "MAP_EQ for async EQ %d failed (%d)\n",
1201 priv->eq_table.eq[dev->caps.num_comp_vectors].eqn, err);
1202
1203 for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i)
1204 eq_set_ci(&priv->eq_table.eq[i], 1);
1205
1206 return 0;
1207
1208 err_out_async:
1209 mlx4_free_eq(dev, &priv->eq_table.eq[dev->caps.num_comp_vectors]);
1210
1211 err_out_comp:
1212 i = dev->caps.num_comp_vectors - 1;
1213
1214 err_out_unmap:
1215 while (i >= 0) {
1216 mlx4_free_eq(dev, &priv->eq_table.eq[i]);
1217 --i;
1218 }
1219 if (!mlx4_is_slave(dev))
1220 mlx4_unmap_clr_int(dev);
1221 mlx4_free_irqs(dev);
1222
1223 err_out_bitmap:
1224 mlx4_unmap_uar(dev);
1225 mlx4_bitmap_cleanup(&priv->eq_table.bitmap);
1226
1227 err_out_free:
1228 kfree(priv->eq_table.uar_map);
1229
1230 return err;
1231 }
1232
1233 void mlx4_cleanup_eq_table(struct mlx4_dev *dev)
1234 {
1235 struct mlx4_priv *priv = mlx4_priv(dev);
1236 int i;
1237
1238 mlx4_MAP_EQ(dev, get_async_ev_mask(dev), 1,
1239 priv->eq_table.eq[dev->caps.num_comp_vectors].eqn);
1240
1241 mlx4_free_irqs(dev);
1242
1243 for (i = 0; i < dev->caps.num_comp_vectors + dev->caps.comp_pool + 1; ++i)
1244 mlx4_free_eq(dev, &priv->eq_table.eq[i]);
1245
1246 if (!mlx4_is_slave(dev))
1247 mlx4_unmap_clr_int(dev);
1248
1249 mlx4_unmap_uar(dev);
1250 mlx4_bitmap_cleanup(&priv->eq_table.bitmap);
1251
1252 kfree(priv->eq_table.uar_map);
1253 }
1254
1255 /* A test that verifies that we can accept interrupts on all
1256 * the irq vectors of the device.
1257 * Interrupts are checked using the NOP command.
1258 */
1259 int mlx4_test_interrupts(struct mlx4_dev *dev)
1260 {
1261 struct mlx4_priv *priv = mlx4_priv(dev);
1262 int i;
1263 int err;
1264
1265 err = mlx4_NOP(dev);
1266 /* When not in MSI_X, there is only one irq to check */
1267 if (!(dev->flags & MLX4_FLAG_MSI_X) || mlx4_is_slave(dev))
1268 return err;
1269
1270 /* A loop over all completion vectors, for each vector we will check
1271 * whether it works by mapping command completions to that vector
1272 * and performing a NOP command
1273 */
1274 for(i = 0; !err && (i < dev->caps.num_comp_vectors); ++i) {
1275 /* Temporary use polling for command completions */
1276 mlx4_cmd_use_polling(dev);
1277
1278 /* Map the new eq to handle all asyncronous events */
1279 err = mlx4_MAP_EQ(dev, get_async_ev_mask(dev), 0,
1280 priv->eq_table.eq[i].eqn);
1281 if (err) {
1282 mlx4_warn(dev, "Failed mapping eq for interrupt test\n");
1283 mlx4_cmd_use_events(dev);
1284 break;
1285 }
1286
1287 /* Go back to using events */
1288 mlx4_cmd_use_events(dev);
1289 err = mlx4_NOP(dev);
1290 }
1291
1292 /* Return to default */
1293 mlx4_MAP_EQ(dev, get_async_ev_mask(dev), 0,
1294 priv->eq_table.eq[dev->caps.num_comp_vectors].eqn);
1295 return err;
1296 }
1297 EXPORT_SYMBOL(mlx4_test_interrupts);
1298
1299 int mlx4_assign_eq(struct mlx4_dev *dev, char *name, struct cpu_rmap *rmap,
1300 int *vector)
1301 {
1302
1303 struct mlx4_priv *priv = mlx4_priv(dev);
1304 int vec = 0, err = 0, i;
1305
1306 mutex_lock(&priv->msix_ctl.pool_lock);
1307 for (i = 0; !vec && i < dev->caps.comp_pool; i++) {
1308 if (~priv->msix_ctl.pool_bm & 1ULL << i) {
1309 priv->msix_ctl.pool_bm |= 1ULL << i;
1310 vec = dev->caps.num_comp_vectors + 1 + i;
1311 snprintf(priv->eq_table.irq_names +
1312 vec * MLX4_IRQNAME_SIZE,
1313 MLX4_IRQNAME_SIZE, "%s", name);
1314 #ifdef CONFIG_RFS_ACCEL
1315 if (rmap) {
1316 err = irq_cpu_rmap_add(rmap,
1317 priv->eq_table.eq[vec].irq);
1318 if (err)
1319 mlx4_warn(dev, "Failed adding irq rmap\n");
1320 }
1321 #endif
1322 err = request_irq(priv->eq_table.eq[vec].irq,
1323 mlx4_msi_x_interrupt, 0,
1324 &priv->eq_table.irq_names[vec<<5],
1325 priv->eq_table.eq + vec);
1326 if (err) {
1327 /*zero out bit by fliping it*/
1328 priv->msix_ctl.pool_bm ^= 1 << i;
1329 vec = 0;
1330 continue;
1331 /*we dont want to break here*/
1332 }
1333 eq_set_ci(&priv->eq_table.eq[vec], 1);
1334 }
1335 }
1336 mutex_unlock(&priv->msix_ctl.pool_lock);
1337
1338 if (vec) {
1339 *vector = vec;
1340 } else {
1341 *vector = 0;
1342 err = (i == dev->caps.comp_pool) ? -ENOSPC : err;
1343 }
1344 return err;
1345 }
1346 EXPORT_SYMBOL(mlx4_assign_eq);
1347
1348 void mlx4_release_eq(struct mlx4_dev *dev, int vec)
1349 {
1350 struct mlx4_priv *priv = mlx4_priv(dev);
1351 /*bm index*/
1352 int i = vec - dev->caps.num_comp_vectors - 1;
1353
1354 if (likely(i >= 0)) {
1355 /*sanity check , making sure were not trying to free irq's
1356 Belonging to a legacy EQ*/
1357 mutex_lock(&priv->msix_ctl.pool_lock);
1358 if (priv->msix_ctl.pool_bm & 1ULL << i) {
1359 free_irq(priv->eq_table.eq[vec].irq,
1360 &priv->eq_table.eq[vec]);
1361 priv->msix_ctl.pool_bm &= ~(1ULL << i);
1362 }
1363 mutex_unlock(&priv->msix_ctl.pool_lock);
1364 }
1365
1366 }
1367 EXPORT_SYMBOL(mlx4_release_eq);
1368
Linux kernel - Deliverables
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