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Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus
[deliverable/linux.git] / drivers / net / ethernet / mellanox / mlx4 / fw.c
1 /*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35 #include <linux/etherdevice.h>
36 #include <linux/mlx4/cmd.h>
37 #include <linux/module.h>
38 #include <linux/cache.h>
39
40 #include "fw.h"
41 #include "icm.h"
42
43 enum {
44 MLX4_COMMAND_INTERFACE_MIN_REV = 2,
45 MLX4_COMMAND_INTERFACE_MAX_REV = 3,
46 MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS = 3,
47 };
48
49 extern void __buggy_use_of_MLX4_GET(void);
50 extern void __buggy_use_of_MLX4_PUT(void);
51
52 static bool enable_qos;
53 module_param(enable_qos, bool, 0444);
54 MODULE_PARM_DESC(enable_qos, "Enable Quality of Service support in the HCA (default: off)");
55
56 #define MLX4_GET(dest, source, offset) \
57 do { \
58 void *__p = (char *) (source) + (offset); \
59 switch (sizeof (dest)) { \
60 case 1: (dest) = *(u8 *) __p; break; \
61 case 2: (dest) = be16_to_cpup(__p); break; \
62 case 4: (dest) = be32_to_cpup(__p); break; \
63 case 8: (dest) = be64_to_cpup(__p); break; \
64 default: __buggy_use_of_MLX4_GET(); \
65 } \
66 } while (0)
67
68 #define MLX4_PUT(dest, source, offset) \
69 do { \
70 void *__d = ((char *) (dest) + (offset)); \
71 switch (sizeof(source)) { \
72 case 1: *(u8 *) __d = (source); break; \
73 case 2: *(__be16 *) __d = cpu_to_be16(source); break; \
74 case 4: *(__be32 *) __d = cpu_to_be32(source); break; \
75 case 8: *(__be64 *) __d = cpu_to_be64(source); break; \
76 default: __buggy_use_of_MLX4_PUT(); \
77 } \
78 } while (0)
79
80 static void dump_dev_cap_flags(struct mlx4_dev *dev, u64 flags)
81 {
82 static const char *fname[] = {
83 [ 0] = "RC transport",
84 [ 1] = "UC transport",
85 [ 2] = "UD transport",
86 [ 3] = "XRC transport",
87 [ 4] = "reliable multicast",
88 [ 5] = "FCoIB support",
89 [ 6] = "SRQ support",
90 [ 7] = "IPoIB checksum offload",
91 [ 8] = "P_Key violation counter",
92 [ 9] = "Q_Key violation counter",
93 [10] = "VMM",
94 [12] = "Dual Port Different Protocol (DPDP) support",
95 [15] = "Big LSO headers",
96 [16] = "MW support",
97 [17] = "APM support",
98 [18] = "Atomic ops support",
99 [19] = "Raw multicast support",
100 [20] = "Address vector port checking support",
101 [21] = "UD multicast support",
102 [24] = "Demand paging support",
103 [25] = "Router support",
104 [30] = "IBoE support",
105 [32] = "Unicast loopback support",
106 [34] = "FCS header control",
107 [38] = "Wake On LAN support",
108 [40] = "UDP RSS support",
109 [41] = "Unicast VEP steering support",
110 [42] = "Multicast VEP steering support",
111 [48] = "Counters support",
112 [53] = "Port ETS Scheduler support",
113 [55] = "Port link type sensing support",
114 [59] = "Port management change event support",
115 [61] = "64 byte EQE support",
116 [62] = "64 byte CQE support",
117 };
118 int i;
119
120 mlx4_dbg(dev, "DEV_CAP flags:\n");
121 for (i = 0; i < ARRAY_SIZE(fname); ++i)
122 if (fname[i] && (flags & (1LL << i)))
123 mlx4_dbg(dev, " %s\n", fname[i]);
124 }
125
126 static void dump_dev_cap_flags2(struct mlx4_dev *dev, u64 flags)
127 {
128 static const char * const fname[] = {
129 [0] = "RSS support",
130 [1] = "RSS Toeplitz Hash Function support",
131 [2] = "RSS XOR Hash Function support",
132 [3] = "Device managed flow steering support",
133 [4] = "Automatic MAC reassignment support",
134 [5] = "Time stamping support",
135 [6] = "VST (control vlan insertion/stripping) support",
136 [7] = "FSM (MAC anti-spoofing) support",
137 [8] = "Dynamic QP updates support",
138 [9] = "Device managed flow steering IPoIB support",
139 [10] = "TCP/IP offloads/flow-steering for VXLAN support",
140 [11] = "MAD DEMUX (Secure-Host) support",
141 [12] = "Large cache line (>64B) CQE stride support",
142 [13] = "Large cache line (>64B) EQE stride support"
143 };
144 int i;
145
146 for (i = 0; i < ARRAY_SIZE(fname); ++i)
147 if (fname[i] && (flags & (1LL << i)))
148 mlx4_dbg(dev, " %s\n", fname[i]);
149 }
150
151 int mlx4_MOD_STAT_CFG(struct mlx4_dev *dev, struct mlx4_mod_stat_cfg *cfg)
152 {
153 struct mlx4_cmd_mailbox *mailbox;
154 u32 *inbox;
155 int err = 0;
156
157 #define MOD_STAT_CFG_IN_SIZE 0x100
158
159 #define MOD_STAT_CFG_PG_SZ_M_OFFSET 0x002
160 #define MOD_STAT_CFG_PG_SZ_OFFSET 0x003
161
162 mailbox = mlx4_alloc_cmd_mailbox(dev);
163 if (IS_ERR(mailbox))
164 return PTR_ERR(mailbox);
165 inbox = mailbox->buf;
166
167 MLX4_PUT(inbox, cfg->log_pg_sz, MOD_STAT_CFG_PG_SZ_OFFSET);
168 MLX4_PUT(inbox, cfg->log_pg_sz_m, MOD_STAT_CFG_PG_SZ_M_OFFSET);
169
170 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_MOD_STAT_CFG,
171 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
172
173 mlx4_free_cmd_mailbox(dev, mailbox);
174 return err;
175 }
176
177 int mlx4_QUERY_FUNC_CAP_wrapper(struct mlx4_dev *dev, int slave,
178 struct mlx4_vhcr *vhcr,
179 struct mlx4_cmd_mailbox *inbox,
180 struct mlx4_cmd_mailbox *outbox,
181 struct mlx4_cmd_info *cmd)
182 {
183 struct mlx4_priv *priv = mlx4_priv(dev);
184 u8 field, port;
185 u32 size, proxy_qp, qkey;
186 int err = 0;
187
188 #define QUERY_FUNC_CAP_FLAGS_OFFSET 0x0
189 #define QUERY_FUNC_CAP_NUM_PORTS_OFFSET 0x1
190 #define QUERY_FUNC_CAP_PF_BHVR_OFFSET 0x4
191 #define QUERY_FUNC_CAP_FMR_OFFSET 0x8
192 #define QUERY_FUNC_CAP_QP_QUOTA_OFFSET_DEP 0x10
193 #define QUERY_FUNC_CAP_CQ_QUOTA_OFFSET_DEP 0x14
194 #define QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET_DEP 0x18
195 #define QUERY_FUNC_CAP_MPT_QUOTA_OFFSET_DEP 0x20
196 #define QUERY_FUNC_CAP_MTT_QUOTA_OFFSET_DEP 0x24
197 #define QUERY_FUNC_CAP_MCG_QUOTA_OFFSET_DEP 0x28
198 #define QUERY_FUNC_CAP_MAX_EQ_OFFSET 0x2c
199 #define QUERY_FUNC_CAP_RESERVED_EQ_OFFSET 0x30
200
201 #define QUERY_FUNC_CAP_QP_QUOTA_OFFSET 0x50
202 #define QUERY_FUNC_CAP_CQ_QUOTA_OFFSET 0x54
203 #define QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET 0x58
204 #define QUERY_FUNC_CAP_MPT_QUOTA_OFFSET 0x60
205 #define QUERY_FUNC_CAP_MTT_QUOTA_OFFSET 0x64
206 #define QUERY_FUNC_CAP_MCG_QUOTA_OFFSET 0x68
207
208 #define QUERY_FUNC_CAP_FMR_FLAG 0x80
209 #define QUERY_FUNC_CAP_FLAG_RDMA 0x40
210 #define QUERY_FUNC_CAP_FLAG_ETH 0x80
211 #define QUERY_FUNC_CAP_FLAG_QUOTAS 0x10
212
213 /* when opcode modifier = 1 */
214 #define QUERY_FUNC_CAP_PHYS_PORT_OFFSET 0x3
215 #define QUERY_FUNC_CAP_PRIV_VF_QKEY_OFFSET 0x4
216 #define QUERY_FUNC_CAP_FLAGS0_OFFSET 0x8
217 #define QUERY_FUNC_CAP_FLAGS1_OFFSET 0xc
218
219 #define QUERY_FUNC_CAP_QP0_TUNNEL 0x10
220 #define QUERY_FUNC_CAP_QP0_PROXY 0x14
221 #define QUERY_FUNC_CAP_QP1_TUNNEL 0x18
222 #define QUERY_FUNC_CAP_QP1_PROXY 0x1c
223 #define QUERY_FUNC_CAP_PHYS_PORT_ID 0x28
224
225 #define QUERY_FUNC_CAP_FLAGS1_FORCE_MAC 0x40
226 #define QUERY_FUNC_CAP_FLAGS1_FORCE_VLAN 0x80
227 #define QUERY_FUNC_CAP_FLAGS1_NIC_INFO 0x10
228 #define QUERY_FUNC_CAP_VF_ENABLE_QP0 0x08
229
230 #define QUERY_FUNC_CAP_FLAGS0_FORCE_PHY_WQE_GID 0x80
231
232 if (vhcr->op_modifier == 1) {
233 struct mlx4_active_ports actv_ports =
234 mlx4_get_active_ports(dev, slave);
235 int converted_port = mlx4_slave_convert_port(
236 dev, slave, vhcr->in_modifier);
237
238 if (converted_port < 0)
239 return -EINVAL;
240
241 vhcr->in_modifier = converted_port;
242 /* phys-port = logical-port */
243 field = vhcr->in_modifier -
244 find_first_bit(actv_ports.ports, dev->caps.num_ports);
245 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_PHYS_PORT_OFFSET);
246
247 port = vhcr->in_modifier;
248 proxy_qp = dev->phys_caps.base_proxy_sqpn + 8 * slave + port - 1;
249
250 /* Set nic_info bit to mark new fields support */
251 field = QUERY_FUNC_CAP_FLAGS1_NIC_INFO;
252
253 if (mlx4_vf_smi_enabled(dev, slave, port) &&
254 !mlx4_get_parav_qkey(dev, proxy_qp, &qkey)) {
255 field |= QUERY_FUNC_CAP_VF_ENABLE_QP0;
256 MLX4_PUT(outbox->buf, qkey,
257 QUERY_FUNC_CAP_PRIV_VF_QKEY_OFFSET);
258 }
259 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FLAGS1_OFFSET);
260
261 /* size is now the QP number */
262 size = dev->phys_caps.base_tunnel_sqpn + 8 * slave + port - 1;
263 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP0_TUNNEL);
264
265 size += 2;
266 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP1_TUNNEL);
267
268 MLX4_PUT(outbox->buf, proxy_qp, QUERY_FUNC_CAP_QP0_PROXY);
269 proxy_qp += 2;
270 MLX4_PUT(outbox->buf, proxy_qp, QUERY_FUNC_CAP_QP1_PROXY);
271
272 MLX4_PUT(outbox->buf, dev->caps.phys_port_id[vhcr->in_modifier],
273 QUERY_FUNC_CAP_PHYS_PORT_ID);
274
275 } else if (vhcr->op_modifier == 0) {
276 struct mlx4_active_ports actv_ports =
277 mlx4_get_active_ports(dev, slave);
278 /* enable rdma and ethernet interfaces, and new quota locations */
279 field = (QUERY_FUNC_CAP_FLAG_ETH | QUERY_FUNC_CAP_FLAG_RDMA |
280 QUERY_FUNC_CAP_FLAG_QUOTAS);
281 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FLAGS_OFFSET);
282
283 field = min(
284 bitmap_weight(actv_ports.ports, dev->caps.num_ports),
285 dev->caps.num_ports);
286 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_NUM_PORTS_OFFSET);
287
288 size = dev->caps.function_caps; /* set PF behaviours */
289 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_PF_BHVR_OFFSET);
290
291 field = 0; /* protected FMR support not available as yet */
292 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FMR_OFFSET);
293
294 size = priv->mfunc.master.res_tracker.res_alloc[RES_QP].quota[slave];
295 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP_QUOTA_OFFSET);
296 size = dev->caps.num_qps;
297 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP_QUOTA_OFFSET_DEP);
298
299 size = priv->mfunc.master.res_tracker.res_alloc[RES_SRQ].quota[slave];
300 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET);
301 size = dev->caps.num_srqs;
302 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET_DEP);
303
304 size = priv->mfunc.master.res_tracker.res_alloc[RES_CQ].quota[slave];
305 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET);
306 size = dev->caps.num_cqs;
307 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET_DEP);
308
309 size = dev->caps.num_eqs;
310 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MAX_EQ_OFFSET);
311
312 size = dev->caps.reserved_eqs;
313 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET);
314
315 size = priv->mfunc.master.res_tracker.res_alloc[RES_MPT].quota[slave];
316 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET);
317 size = dev->caps.num_mpts;
318 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET_DEP);
319
320 size = priv->mfunc.master.res_tracker.res_alloc[RES_MTT].quota[slave];
321 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET);
322 size = dev->caps.num_mtts;
323 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET_DEP);
324
325 size = dev->caps.num_mgms + dev->caps.num_amgms;
326 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET);
327 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET_DEP);
328
329 } else
330 err = -EINVAL;
331
332 return err;
333 }
334
335 int mlx4_QUERY_FUNC_CAP(struct mlx4_dev *dev, u32 gen_or_port,
336 struct mlx4_func_cap *func_cap)
337 {
338 struct mlx4_cmd_mailbox *mailbox;
339 u32 *outbox;
340 u8 field, op_modifier;
341 u32 size, qkey;
342 int err = 0, quotas = 0;
343
344 op_modifier = !!gen_or_port; /* 0 = general, 1 = logical port */
345
346 mailbox = mlx4_alloc_cmd_mailbox(dev);
347 if (IS_ERR(mailbox))
348 return PTR_ERR(mailbox);
349
350 err = mlx4_cmd_box(dev, 0, mailbox->dma, gen_or_port, op_modifier,
351 MLX4_CMD_QUERY_FUNC_CAP,
352 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
353 if (err)
354 goto out;
355
356 outbox = mailbox->buf;
357
358 if (!op_modifier) {
359 MLX4_GET(field, outbox, QUERY_FUNC_CAP_FLAGS_OFFSET);
360 if (!(field & (QUERY_FUNC_CAP_FLAG_ETH | QUERY_FUNC_CAP_FLAG_RDMA))) {
361 mlx4_err(dev, "The host supports neither eth nor rdma interfaces\n");
362 err = -EPROTONOSUPPORT;
363 goto out;
364 }
365 func_cap->flags = field;
366 quotas = !!(func_cap->flags & QUERY_FUNC_CAP_FLAG_QUOTAS);
367
368 MLX4_GET(field, outbox, QUERY_FUNC_CAP_NUM_PORTS_OFFSET);
369 func_cap->num_ports = field;
370
371 MLX4_GET(size, outbox, QUERY_FUNC_CAP_PF_BHVR_OFFSET);
372 func_cap->pf_context_behaviour = size;
373
374 if (quotas) {
375 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP_QUOTA_OFFSET);
376 func_cap->qp_quota = size & 0xFFFFFF;
377
378 MLX4_GET(size, outbox, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET);
379 func_cap->srq_quota = size & 0xFFFFFF;
380
381 MLX4_GET(size, outbox, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET);
382 func_cap->cq_quota = size & 0xFFFFFF;
383
384 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET);
385 func_cap->mpt_quota = size & 0xFFFFFF;
386
387 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET);
388 func_cap->mtt_quota = size & 0xFFFFFF;
389
390 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET);
391 func_cap->mcg_quota = size & 0xFFFFFF;
392
393 } else {
394 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP_QUOTA_OFFSET_DEP);
395 func_cap->qp_quota = size & 0xFFFFFF;
396
397 MLX4_GET(size, outbox, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET_DEP);
398 func_cap->srq_quota = size & 0xFFFFFF;
399
400 MLX4_GET(size, outbox, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET_DEP);
401 func_cap->cq_quota = size & 0xFFFFFF;
402
403 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET_DEP);
404 func_cap->mpt_quota = size & 0xFFFFFF;
405
406 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET_DEP);
407 func_cap->mtt_quota = size & 0xFFFFFF;
408
409 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET_DEP);
410 func_cap->mcg_quota = size & 0xFFFFFF;
411 }
412 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MAX_EQ_OFFSET);
413 func_cap->max_eq = size & 0xFFFFFF;
414
415 MLX4_GET(size, outbox, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET);
416 func_cap->reserved_eq = size & 0xFFFFFF;
417
418 goto out;
419 }
420
421 /* logical port query */
422 if (gen_or_port > dev->caps.num_ports) {
423 err = -EINVAL;
424 goto out;
425 }
426
427 MLX4_GET(func_cap->flags1, outbox, QUERY_FUNC_CAP_FLAGS1_OFFSET);
428 if (dev->caps.port_type[gen_or_port] == MLX4_PORT_TYPE_ETH) {
429 if (func_cap->flags1 & QUERY_FUNC_CAP_FLAGS1_FORCE_VLAN) {
430 mlx4_err(dev, "VLAN is enforced on this port\n");
431 err = -EPROTONOSUPPORT;
432 goto out;
433 }
434
435 if (func_cap->flags1 & QUERY_FUNC_CAP_FLAGS1_FORCE_MAC) {
436 mlx4_err(dev, "Force mac is enabled on this port\n");
437 err = -EPROTONOSUPPORT;
438 goto out;
439 }
440 } else if (dev->caps.port_type[gen_or_port] == MLX4_PORT_TYPE_IB) {
441 MLX4_GET(field, outbox, QUERY_FUNC_CAP_FLAGS0_OFFSET);
442 if (field & QUERY_FUNC_CAP_FLAGS0_FORCE_PHY_WQE_GID) {
443 mlx4_err(dev, "phy_wqe_gid is enforced on this ib port\n");
444 err = -EPROTONOSUPPORT;
445 goto out;
446 }
447 }
448
449 MLX4_GET(field, outbox, QUERY_FUNC_CAP_PHYS_PORT_OFFSET);
450 func_cap->physical_port = field;
451 if (func_cap->physical_port != gen_or_port) {
452 err = -ENOSYS;
453 goto out;
454 }
455
456 if (func_cap->flags1 & QUERY_FUNC_CAP_VF_ENABLE_QP0) {
457 MLX4_GET(qkey, outbox, QUERY_FUNC_CAP_PRIV_VF_QKEY_OFFSET);
458 func_cap->qp0_qkey = qkey;
459 } else {
460 func_cap->qp0_qkey = 0;
461 }
462
463 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP0_TUNNEL);
464 func_cap->qp0_tunnel_qpn = size & 0xFFFFFF;
465
466 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP0_PROXY);
467 func_cap->qp0_proxy_qpn = size & 0xFFFFFF;
468
469 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP1_TUNNEL);
470 func_cap->qp1_tunnel_qpn = size & 0xFFFFFF;
471
472 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP1_PROXY);
473 func_cap->qp1_proxy_qpn = size & 0xFFFFFF;
474
475 if (func_cap->flags1 & QUERY_FUNC_CAP_FLAGS1_NIC_INFO)
476 MLX4_GET(func_cap->phys_port_id, outbox,
477 QUERY_FUNC_CAP_PHYS_PORT_ID);
478
479 /* All other resources are allocated by the master, but we still report
480 * 'num' and 'reserved' capabilities as follows:
481 * - num remains the maximum resource index
482 * - 'num - reserved' is the total available objects of a resource, but
483 * resource indices may be less than 'reserved'
484 * TODO: set per-resource quotas */
485
486 out:
487 mlx4_free_cmd_mailbox(dev, mailbox);
488
489 return err;
490 }
491
492 int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
493 {
494 struct mlx4_cmd_mailbox *mailbox;
495 u32 *outbox;
496 u8 field;
497 u32 field32, flags, ext_flags;
498 u16 size;
499 u16 stat_rate;
500 int err;
501 int i;
502
503 #define QUERY_DEV_CAP_OUT_SIZE 0x100
504 #define QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET 0x10
505 #define QUERY_DEV_CAP_MAX_QP_SZ_OFFSET 0x11
506 #define QUERY_DEV_CAP_RSVD_QP_OFFSET 0x12
507 #define QUERY_DEV_CAP_MAX_QP_OFFSET 0x13
508 #define QUERY_DEV_CAP_RSVD_SRQ_OFFSET 0x14
509 #define QUERY_DEV_CAP_MAX_SRQ_OFFSET 0x15
510 #define QUERY_DEV_CAP_RSVD_EEC_OFFSET 0x16
511 #define QUERY_DEV_CAP_MAX_EEC_OFFSET 0x17
512 #define QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET 0x19
513 #define QUERY_DEV_CAP_RSVD_CQ_OFFSET 0x1a
514 #define QUERY_DEV_CAP_MAX_CQ_OFFSET 0x1b
515 #define QUERY_DEV_CAP_MAX_MPT_OFFSET 0x1d
516 #define QUERY_DEV_CAP_RSVD_EQ_OFFSET 0x1e
517 #define QUERY_DEV_CAP_MAX_EQ_OFFSET 0x1f
518 #define QUERY_DEV_CAP_RSVD_MTT_OFFSET 0x20
519 #define QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET 0x21
520 #define QUERY_DEV_CAP_RSVD_MRW_OFFSET 0x22
521 #define QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET 0x23
522 #define QUERY_DEV_CAP_MAX_AV_OFFSET 0x27
523 #define QUERY_DEV_CAP_MAX_REQ_QP_OFFSET 0x29
524 #define QUERY_DEV_CAP_MAX_RES_QP_OFFSET 0x2b
525 #define QUERY_DEV_CAP_MAX_GSO_OFFSET 0x2d
526 #define QUERY_DEV_CAP_RSS_OFFSET 0x2e
527 #define QUERY_DEV_CAP_MAX_RDMA_OFFSET 0x2f
528 #define QUERY_DEV_CAP_RSZ_SRQ_OFFSET 0x33
529 #define QUERY_DEV_CAP_ACK_DELAY_OFFSET 0x35
530 #define QUERY_DEV_CAP_MTU_WIDTH_OFFSET 0x36
531 #define QUERY_DEV_CAP_VL_PORT_OFFSET 0x37
532 #define QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET 0x38
533 #define QUERY_DEV_CAP_MAX_GID_OFFSET 0x3b
534 #define QUERY_DEV_CAP_RATE_SUPPORT_OFFSET 0x3c
535 #define QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET 0x3e
536 #define QUERY_DEV_CAP_MAX_PKEY_OFFSET 0x3f
537 #define QUERY_DEV_CAP_EXT_FLAGS_OFFSET 0x40
538 #define QUERY_DEV_CAP_FLAGS_OFFSET 0x44
539 #define QUERY_DEV_CAP_RSVD_UAR_OFFSET 0x48
540 #define QUERY_DEV_CAP_UAR_SZ_OFFSET 0x49
541 #define QUERY_DEV_CAP_PAGE_SZ_OFFSET 0x4b
542 #define QUERY_DEV_CAP_BF_OFFSET 0x4c
543 #define QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET 0x4d
544 #define QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET 0x4e
545 #define QUERY_DEV_CAP_LOG_MAX_BF_PAGES_OFFSET 0x4f
546 #define QUERY_DEV_CAP_MAX_SG_SQ_OFFSET 0x51
547 #define QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET 0x52
548 #define QUERY_DEV_CAP_MAX_SG_RQ_OFFSET 0x55
549 #define QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET 0x56
550 #define QUERY_DEV_CAP_MAX_QP_MCG_OFFSET 0x61
551 #define QUERY_DEV_CAP_RSVD_MCG_OFFSET 0x62
552 #define QUERY_DEV_CAP_MAX_MCG_OFFSET 0x63
553 #define QUERY_DEV_CAP_RSVD_PD_OFFSET 0x64
554 #define QUERY_DEV_CAP_MAX_PD_OFFSET 0x65
555 #define QUERY_DEV_CAP_RSVD_XRC_OFFSET 0x66
556 #define QUERY_DEV_CAP_MAX_XRC_OFFSET 0x67
557 #define QUERY_DEV_CAP_MAX_COUNTERS_OFFSET 0x68
558 #define QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET 0x70
559 #define QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET 0x74
560 #define QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET 0x76
561 #define QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET 0x77
562 #define QUERY_DEV_CAP_CQ_EQ_CACHE_LINE_STRIDE 0x7a
563 #define QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET 0x80
564 #define QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET 0x82
565 #define QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET 0x84
566 #define QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET 0x86
567 #define QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET 0x88
568 #define QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET 0x8a
569 #define QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET 0x8c
570 #define QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET 0x8e
571 #define QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET 0x90
572 #define QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET 0x92
573 #define QUERY_DEV_CAP_BMME_FLAGS_OFFSET 0x94
574 #define QUERY_DEV_CAP_RSVD_LKEY_OFFSET 0x98
575 #define QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET 0xa0
576 #define QUERY_DEV_CAP_FW_REASSIGN_MAC 0x9d
577 #define QUERY_DEV_CAP_VXLAN 0x9e
578 #define QUERY_DEV_CAP_MAD_DEMUX_OFFSET 0xb0
579
580 dev_cap->flags2 = 0;
581 mailbox = mlx4_alloc_cmd_mailbox(dev);
582 if (IS_ERR(mailbox))
583 return PTR_ERR(mailbox);
584 outbox = mailbox->buf;
585
586 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP,
587 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
588 if (err)
589 goto out;
590
591 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_QP_OFFSET);
592 dev_cap->reserved_qps = 1 << (field & 0xf);
593 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_OFFSET);
594 dev_cap->max_qps = 1 << (field & 0x1f);
595 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_SRQ_OFFSET);
596 dev_cap->reserved_srqs = 1 << (field >> 4);
597 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_OFFSET);
598 dev_cap->max_srqs = 1 << (field & 0x1f);
599 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET);
600 dev_cap->max_cq_sz = 1 << field;
601 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_CQ_OFFSET);
602 dev_cap->reserved_cqs = 1 << (field & 0xf);
603 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_OFFSET);
604 dev_cap->max_cqs = 1 << (field & 0x1f);
605 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MPT_OFFSET);
606 dev_cap->max_mpts = 1 << (field & 0x3f);
607 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_EQ_OFFSET);
608 dev_cap->reserved_eqs = field & 0xf;
609 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_EQ_OFFSET);
610 dev_cap->max_eqs = 1 << (field & 0xf);
611 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MTT_OFFSET);
612 dev_cap->reserved_mtts = 1 << (field >> 4);
613 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET);
614 dev_cap->max_mrw_sz = 1 << field;
615 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MRW_OFFSET);
616 dev_cap->reserved_mrws = 1 << (field & 0xf);
617 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET);
618 dev_cap->max_mtt_seg = 1 << (field & 0x3f);
619 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_REQ_QP_OFFSET);
620 dev_cap->max_requester_per_qp = 1 << (field & 0x3f);
621 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RES_QP_OFFSET);
622 dev_cap->max_responder_per_qp = 1 << (field & 0x3f);
623 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GSO_OFFSET);
624 field &= 0x1f;
625 if (!field)
626 dev_cap->max_gso_sz = 0;
627 else
628 dev_cap->max_gso_sz = 1 << field;
629
630 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSS_OFFSET);
631 if (field & 0x20)
632 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_XOR;
633 if (field & 0x10)
634 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_TOP;
635 field &= 0xf;
636 if (field) {
637 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS;
638 dev_cap->max_rss_tbl_sz = 1 << field;
639 } else
640 dev_cap->max_rss_tbl_sz = 0;
641 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RDMA_OFFSET);
642 dev_cap->max_rdma_global = 1 << (field & 0x3f);
643 MLX4_GET(field, outbox, QUERY_DEV_CAP_ACK_DELAY_OFFSET);
644 dev_cap->local_ca_ack_delay = field & 0x1f;
645 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET);
646 dev_cap->num_ports = field & 0xf;
647 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET);
648 dev_cap->max_msg_sz = 1 << (field & 0x1f);
649 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET);
650 if (field & 0x80)
651 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FS_EN;
652 dev_cap->fs_log_max_ucast_qp_range_size = field & 0x1f;
653 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET);
654 if (field & 0x80)
655 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_DMFS_IPOIB;
656 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET);
657 dev_cap->fs_max_num_qp_per_entry = field;
658 MLX4_GET(stat_rate, outbox, QUERY_DEV_CAP_RATE_SUPPORT_OFFSET);
659 dev_cap->stat_rate_support = stat_rate;
660 MLX4_GET(field, outbox, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET);
661 if (field & 0x80)
662 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_TS;
663 MLX4_GET(ext_flags, outbox, QUERY_DEV_CAP_EXT_FLAGS_OFFSET);
664 MLX4_GET(flags, outbox, QUERY_DEV_CAP_FLAGS_OFFSET);
665 dev_cap->flags = flags | (u64)ext_flags << 32;
666 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_UAR_OFFSET);
667 dev_cap->reserved_uars = field >> 4;
668 MLX4_GET(field, outbox, QUERY_DEV_CAP_UAR_SZ_OFFSET);
669 dev_cap->uar_size = 1 << ((field & 0x3f) + 20);
670 MLX4_GET(field, outbox, QUERY_DEV_CAP_PAGE_SZ_OFFSET);
671 dev_cap->min_page_sz = 1 << field;
672
673 MLX4_GET(field, outbox, QUERY_DEV_CAP_BF_OFFSET);
674 if (field & 0x80) {
675 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET);
676 dev_cap->bf_reg_size = 1 << (field & 0x1f);
677 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET);
678 if ((1 << (field & 0x3f)) > (PAGE_SIZE / dev_cap->bf_reg_size))
679 field = 3;
680 dev_cap->bf_regs_per_page = 1 << (field & 0x3f);
681 mlx4_dbg(dev, "BlueFlame available (reg size %d, regs/page %d)\n",
682 dev_cap->bf_reg_size, dev_cap->bf_regs_per_page);
683 } else {
684 dev_cap->bf_reg_size = 0;
685 mlx4_dbg(dev, "BlueFlame not available\n");
686 }
687
688 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_SQ_OFFSET);
689 dev_cap->max_sq_sg = field;
690 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET);
691 dev_cap->max_sq_desc_sz = size;
692
693 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_MCG_OFFSET);
694 dev_cap->max_qp_per_mcg = 1 << field;
695 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MCG_OFFSET);
696 dev_cap->reserved_mgms = field & 0xf;
697 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MCG_OFFSET);
698 dev_cap->max_mcgs = 1 << field;
699 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_PD_OFFSET);
700 dev_cap->reserved_pds = field >> 4;
701 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PD_OFFSET);
702 dev_cap->max_pds = 1 << (field & 0x3f);
703 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_XRC_OFFSET);
704 dev_cap->reserved_xrcds = field >> 4;
705 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_XRC_OFFSET);
706 dev_cap->max_xrcds = 1 << (field & 0x1f);
707
708 MLX4_GET(size, outbox, QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET);
709 dev_cap->rdmarc_entry_sz = size;
710 MLX4_GET(size, outbox, QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET);
711 dev_cap->qpc_entry_sz = size;
712 MLX4_GET(size, outbox, QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET);
713 dev_cap->aux_entry_sz = size;
714 MLX4_GET(size, outbox, QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET);
715 dev_cap->altc_entry_sz = size;
716 MLX4_GET(size, outbox, QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET);
717 dev_cap->eqc_entry_sz = size;
718 MLX4_GET(size, outbox, QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET);
719 dev_cap->cqc_entry_sz = size;
720 MLX4_GET(size, outbox, QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET);
721 dev_cap->srq_entry_sz = size;
722 MLX4_GET(size, outbox, QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET);
723 dev_cap->cmpt_entry_sz = size;
724 MLX4_GET(size, outbox, QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET);
725 dev_cap->mtt_entry_sz = size;
726 MLX4_GET(size, outbox, QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET);
727 dev_cap->dmpt_entry_sz = size;
728
729 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET);
730 dev_cap->max_srq_sz = 1 << field;
731 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_SZ_OFFSET);
732 dev_cap->max_qp_sz = 1 << field;
733 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSZ_SRQ_OFFSET);
734 dev_cap->resize_srq = field & 1;
735 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_RQ_OFFSET);
736 dev_cap->max_rq_sg = field;
737 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET);
738 dev_cap->max_rq_desc_sz = size;
739 MLX4_GET(field, outbox, QUERY_DEV_CAP_CQ_EQ_CACHE_LINE_STRIDE);
740 if (field & (1 << 6))
741 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_CQE_STRIDE;
742 if (field & (1 << 7))
743 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_EQE_STRIDE;
744
745 MLX4_GET(dev_cap->bmme_flags, outbox,
746 QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
747 MLX4_GET(dev_cap->reserved_lkey, outbox,
748 QUERY_DEV_CAP_RSVD_LKEY_OFFSET);
749 MLX4_GET(field, outbox, QUERY_DEV_CAP_FW_REASSIGN_MAC);
750 if (field & 1<<6)
751 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN;
752 MLX4_GET(field, outbox, QUERY_DEV_CAP_VXLAN);
753 if (field & 1<<3)
754 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS;
755 MLX4_GET(dev_cap->max_icm_sz, outbox,
756 QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET);
757 if (dev_cap->flags & MLX4_DEV_CAP_FLAG_COUNTERS)
758 MLX4_GET(dev_cap->max_counters, outbox,
759 QUERY_DEV_CAP_MAX_COUNTERS_OFFSET);
760
761 MLX4_GET(field32, outbox,
762 QUERY_DEV_CAP_MAD_DEMUX_OFFSET);
763 if (field32 & (1 << 0))
764 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_MAD_DEMUX;
765
766 MLX4_GET(field32, outbox, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET);
767 if (field32 & (1 << 16))
768 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_UPDATE_QP;
769 if (field32 & (1 << 26))
770 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_VLAN_CONTROL;
771 if (field32 & (1 << 20))
772 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FSM;
773
774 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
775 for (i = 1; i <= dev_cap->num_ports; ++i) {
776 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET);
777 dev_cap->max_vl[i] = field >> 4;
778 MLX4_GET(field, outbox, QUERY_DEV_CAP_MTU_WIDTH_OFFSET);
779 dev_cap->ib_mtu[i] = field >> 4;
780 dev_cap->max_port_width[i] = field & 0xf;
781 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GID_OFFSET);
782 dev_cap->max_gids[i] = 1 << (field & 0xf);
783 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PKEY_OFFSET);
784 dev_cap->max_pkeys[i] = 1 << (field & 0xf);
785 }
786 } else {
787 #define QUERY_PORT_SUPPORTED_TYPE_OFFSET 0x00
788 #define QUERY_PORT_MTU_OFFSET 0x01
789 #define QUERY_PORT_ETH_MTU_OFFSET 0x02
790 #define QUERY_PORT_WIDTH_OFFSET 0x06
791 #define QUERY_PORT_MAX_GID_PKEY_OFFSET 0x07
792 #define QUERY_PORT_MAX_MACVLAN_OFFSET 0x0a
793 #define QUERY_PORT_MAX_VL_OFFSET 0x0b
794 #define QUERY_PORT_MAC_OFFSET 0x10
795 #define QUERY_PORT_TRANS_VENDOR_OFFSET 0x18
796 #define QUERY_PORT_WAVELENGTH_OFFSET 0x1c
797 #define QUERY_PORT_TRANS_CODE_OFFSET 0x20
798
799 for (i = 1; i <= dev_cap->num_ports; ++i) {
800 err = mlx4_cmd_box(dev, 0, mailbox->dma, i, 0, MLX4_CMD_QUERY_PORT,
801 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
802 if (err)
803 goto out;
804
805 MLX4_GET(field, outbox, QUERY_PORT_SUPPORTED_TYPE_OFFSET);
806 dev_cap->supported_port_types[i] = field & 3;
807 dev_cap->suggested_type[i] = (field >> 3) & 1;
808 dev_cap->default_sense[i] = (field >> 4) & 1;
809 MLX4_GET(field, outbox, QUERY_PORT_MTU_OFFSET);
810 dev_cap->ib_mtu[i] = field & 0xf;
811 MLX4_GET(field, outbox, QUERY_PORT_WIDTH_OFFSET);
812 dev_cap->max_port_width[i] = field & 0xf;
813 MLX4_GET(field, outbox, QUERY_PORT_MAX_GID_PKEY_OFFSET);
814 dev_cap->max_gids[i] = 1 << (field >> 4);
815 dev_cap->max_pkeys[i] = 1 << (field & 0xf);
816 MLX4_GET(field, outbox, QUERY_PORT_MAX_VL_OFFSET);
817 dev_cap->max_vl[i] = field & 0xf;
818 MLX4_GET(field, outbox, QUERY_PORT_MAX_MACVLAN_OFFSET);
819 dev_cap->log_max_macs[i] = field & 0xf;
820 dev_cap->log_max_vlans[i] = field >> 4;
821 MLX4_GET(dev_cap->eth_mtu[i], outbox, QUERY_PORT_ETH_MTU_OFFSET);
822 MLX4_GET(dev_cap->def_mac[i], outbox, QUERY_PORT_MAC_OFFSET);
823 MLX4_GET(field32, outbox, QUERY_PORT_TRANS_VENDOR_OFFSET);
824 dev_cap->trans_type[i] = field32 >> 24;
825 dev_cap->vendor_oui[i] = field32 & 0xffffff;
826 MLX4_GET(dev_cap->wavelength[i], outbox, QUERY_PORT_WAVELENGTH_OFFSET);
827 MLX4_GET(dev_cap->trans_code[i], outbox, QUERY_PORT_TRANS_CODE_OFFSET);
828 }
829 }
830
831 mlx4_dbg(dev, "Base MM extensions: flags %08x, rsvd L_Key %08x\n",
832 dev_cap->bmme_flags, dev_cap->reserved_lkey);
833
834 /*
835 * Each UAR has 4 EQ doorbells; so if a UAR is reserved, then
836 * we can't use any EQs whose doorbell falls on that page,
837 * even if the EQ itself isn't reserved.
838 */
839 dev_cap->reserved_eqs = max(dev_cap->reserved_uars * 4,
840 dev_cap->reserved_eqs);
841
842 mlx4_dbg(dev, "Max ICM size %lld MB\n",
843 (unsigned long long) dev_cap->max_icm_sz >> 20);
844 mlx4_dbg(dev, "Max QPs: %d, reserved QPs: %d, entry size: %d\n",
845 dev_cap->max_qps, dev_cap->reserved_qps, dev_cap->qpc_entry_sz);
846 mlx4_dbg(dev, "Max SRQs: %d, reserved SRQs: %d, entry size: %d\n",
847 dev_cap->max_srqs, dev_cap->reserved_srqs, dev_cap->srq_entry_sz);
848 mlx4_dbg(dev, "Max CQs: %d, reserved CQs: %d, entry size: %d\n",
849 dev_cap->max_cqs, dev_cap->reserved_cqs, dev_cap->cqc_entry_sz);
850 mlx4_dbg(dev, "Max EQs: %d, reserved EQs: %d, entry size: %d\n",
851 dev_cap->max_eqs, dev_cap->reserved_eqs, dev_cap->eqc_entry_sz);
852 mlx4_dbg(dev, "reserved MPTs: %d, reserved MTTs: %d\n",
853 dev_cap->reserved_mrws, dev_cap->reserved_mtts);
854 mlx4_dbg(dev, "Max PDs: %d, reserved PDs: %d, reserved UARs: %d\n",
855 dev_cap->max_pds, dev_cap->reserved_pds, dev_cap->reserved_uars);
856 mlx4_dbg(dev, "Max QP/MCG: %d, reserved MGMs: %d\n",
857 dev_cap->max_pds, dev_cap->reserved_mgms);
858 mlx4_dbg(dev, "Max CQEs: %d, max WQEs: %d, max SRQ WQEs: %d\n",
859 dev_cap->max_cq_sz, dev_cap->max_qp_sz, dev_cap->max_srq_sz);
860 mlx4_dbg(dev, "Local CA ACK delay: %d, max MTU: %d, port width cap: %d\n",
861 dev_cap->local_ca_ack_delay, 128 << dev_cap->ib_mtu[1],
862 dev_cap->max_port_width[1]);
863 mlx4_dbg(dev, "Max SQ desc size: %d, max SQ S/G: %d\n",
864 dev_cap->max_sq_desc_sz, dev_cap->max_sq_sg);
865 mlx4_dbg(dev, "Max RQ desc size: %d, max RQ S/G: %d\n",
866 dev_cap->max_rq_desc_sz, dev_cap->max_rq_sg);
867 mlx4_dbg(dev, "Max GSO size: %d\n", dev_cap->max_gso_sz);
868 mlx4_dbg(dev, "Max counters: %d\n", dev_cap->max_counters);
869 mlx4_dbg(dev, "Max RSS Table size: %d\n", dev_cap->max_rss_tbl_sz);
870
871 dump_dev_cap_flags(dev, dev_cap->flags);
872 dump_dev_cap_flags2(dev, dev_cap->flags2);
873
874 out:
875 mlx4_free_cmd_mailbox(dev, mailbox);
876 return err;
877 }
878
879 int mlx4_QUERY_DEV_CAP_wrapper(struct mlx4_dev *dev, int slave,
880 struct mlx4_vhcr *vhcr,
881 struct mlx4_cmd_mailbox *inbox,
882 struct mlx4_cmd_mailbox *outbox,
883 struct mlx4_cmd_info *cmd)
884 {
885 u64 flags;
886 int err = 0;
887 u8 field;
888 u32 bmme_flags;
889 int real_port;
890 int slave_port;
891 int first_port;
892 struct mlx4_active_ports actv_ports;
893
894 err = mlx4_cmd_box(dev, 0, outbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP,
895 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
896 if (err)
897 return err;
898
899 /* add port mng change event capability and disable mw type 1
900 * unconditionally to slaves
901 */
902 MLX4_GET(flags, outbox->buf, QUERY_DEV_CAP_EXT_FLAGS_OFFSET);
903 flags |= MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV;
904 flags &= ~MLX4_DEV_CAP_FLAG_MEM_WINDOW;
905 actv_ports = mlx4_get_active_ports(dev, slave);
906 first_port = find_first_bit(actv_ports.ports, dev->caps.num_ports);
907 for (slave_port = 0, real_port = first_port;
908 real_port < first_port +
909 bitmap_weight(actv_ports.ports, dev->caps.num_ports);
910 ++real_port, ++slave_port) {
911 if (flags & (MLX4_DEV_CAP_FLAG_WOL_PORT1 << real_port))
912 flags |= MLX4_DEV_CAP_FLAG_WOL_PORT1 << slave_port;
913 else
914 flags &= ~(MLX4_DEV_CAP_FLAG_WOL_PORT1 << slave_port);
915 }
916 for (; slave_port < dev->caps.num_ports; ++slave_port)
917 flags &= ~(MLX4_DEV_CAP_FLAG_WOL_PORT1 << slave_port);
918 MLX4_PUT(outbox->buf, flags, QUERY_DEV_CAP_EXT_FLAGS_OFFSET);
919
920 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_VL_PORT_OFFSET);
921 field &= ~0x0F;
922 field |= bitmap_weight(actv_ports.ports, dev->caps.num_ports) & 0x0F;
923 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_VL_PORT_OFFSET);
924
925 /* For guests, disable timestamp */
926 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET);
927 field &= 0x7f;
928 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET);
929
930 /* For guests, disable vxlan tunneling */
931 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_VXLAN);
932 field &= 0xf7;
933 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_VXLAN);
934
935 /* For guests, report Blueflame disabled */
936 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_BF_OFFSET);
937 field &= 0x7f;
938 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_BF_OFFSET);
939
940 /* For guests, disable mw type 2 */
941 MLX4_GET(bmme_flags, outbox->buf, QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
942 bmme_flags &= ~MLX4_BMME_FLAG_TYPE_2_WIN;
943 MLX4_PUT(outbox->buf, bmme_flags, QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
944
945 /* turn off device-managed steering capability if not enabled */
946 if (dev->caps.steering_mode != MLX4_STEERING_MODE_DEVICE_MANAGED) {
947 MLX4_GET(field, outbox->buf,
948 QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET);
949 field &= 0x7f;
950 MLX4_PUT(outbox->buf, field,
951 QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET);
952 }
953
954 /* turn off ipoib managed steering for guests */
955 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET);
956 field &= ~0x80;
957 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET);
958
959 return 0;
960 }
961
962 int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave,
963 struct mlx4_vhcr *vhcr,
964 struct mlx4_cmd_mailbox *inbox,
965 struct mlx4_cmd_mailbox *outbox,
966 struct mlx4_cmd_info *cmd)
967 {
968 struct mlx4_priv *priv = mlx4_priv(dev);
969 u64 def_mac;
970 u8 port_type;
971 u16 short_field;
972 int err;
973 int admin_link_state;
974 int port = mlx4_slave_convert_port(dev, slave,
975 vhcr->in_modifier & 0xFF);
976
977 #define MLX4_VF_PORT_NO_LINK_SENSE_MASK 0xE0
978 #define MLX4_PORT_LINK_UP_MASK 0x80
979 #define QUERY_PORT_CUR_MAX_PKEY_OFFSET 0x0c
980 #define QUERY_PORT_CUR_MAX_GID_OFFSET 0x0e
981
982 if (port < 0)
983 return -EINVAL;
984
985 /* Protect against untrusted guests: enforce that this is the
986 * QUERY_PORT general query.
987 */
988 if (vhcr->op_modifier || vhcr->in_modifier & ~0xFF)
989 return -EINVAL;
990
991 vhcr->in_modifier = port;
992
993 err = mlx4_cmd_box(dev, 0, outbox->dma, vhcr->in_modifier, 0,
994 MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B,
995 MLX4_CMD_NATIVE);
996
997 if (!err && dev->caps.function != slave) {
998 def_mac = priv->mfunc.master.vf_oper[slave].vport[vhcr->in_modifier].state.mac;
999 MLX4_PUT(outbox->buf, def_mac, QUERY_PORT_MAC_OFFSET);
1000
1001 /* get port type - currently only eth is enabled */
1002 MLX4_GET(port_type, outbox->buf,
1003 QUERY_PORT_SUPPORTED_TYPE_OFFSET);
1004
1005 /* No link sensing allowed */
1006 port_type &= MLX4_VF_PORT_NO_LINK_SENSE_MASK;
1007 /* set port type to currently operating port type */
1008 port_type |= (dev->caps.port_type[vhcr->in_modifier] & 0x3);
1009
1010 admin_link_state = priv->mfunc.master.vf_oper[slave].vport[vhcr->in_modifier].state.link_state;
1011 if (IFLA_VF_LINK_STATE_ENABLE == admin_link_state)
1012 port_type |= MLX4_PORT_LINK_UP_MASK;
1013 else if (IFLA_VF_LINK_STATE_DISABLE == admin_link_state)
1014 port_type &= ~MLX4_PORT_LINK_UP_MASK;
1015
1016 MLX4_PUT(outbox->buf, port_type,
1017 QUERY_PORT_SUPPORTED_TYPE_OFFSET);
1018
1019 if (dev->caps.port_type[vhcr->in_modifier] == MLX4_PORT_TYPE_ETH)
1020 short_field = mlx4_get_slave_num_gids(dev, slave, port);
1021 else
1022 short_field = 1; /* slave max gids */
1023 MLX4_PUT(outbox->buf, short_field,
1024 QUERY_PORT_CUR_MAX_GID_OFFSET);
1025
1026 short_field = dev->caps.pkey_table_len[vhcr->in_modifier];
1027 MLX4_PUT(outbox->buf, short_field,
1028 QUERY_PORT_CUR_MAX_PKEY_OFFSET);
1029 }
1030
1031 return err;
1032 }
1033
1034 int mlx4_get_slave_pkey_gid_tbl_len(struct mlx4_dev *dev, u8 port,
1035 int *gid_tbl_len, int *pkey_tbl_len)
1036 {
1037 struct mlx4_cmd_mailbox *mailbox;
1038 u32 *outbox;
1039 u16 field;
1040 int err;
1041
1042 mailbox = mlx4_alloc_cmd_mailbox(dev);
1043 if (IS_ERR(mailbox))
1044 return PTR_ERR(mailbox);
1045
1046 err = mlx4_cmd_box(dev, 0, mailbox->dma, port, 0,
1047 MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B,
1048 MLX4_CMD_WRAPPED);
1049 if (err)
1050 goto out;
1051
1052 outbox = mailbox->buf;
1053
1054 MLX4_GET(field, outbox, QUERY_PORT_CUR_MAX_GID_OFFSET);
1055 *gid_tbl_len = field;
1056
1057 MLX4_GET(field, outbox, QUERY_PORT_CUR_MAX_PKEY_OFFSET);
1058 *pkey_tbl_len = field;
1059
1060 out:
1061 mlx4_free_cmd_mailbox(dev, mailbox);
1062 return err;
1063 }
1064 EXPORT_SYMBOL(mlx4_get_slave_pkey_gid_tbl_len);
1065
1066 int mlx4_map_cmd(struct mlx4_dev *dev, u16 op, struct mlx4_icm *icm, u64 virt)
1067 {
1068 struct mlx4_cmd_mailbox *mailbox;
1069 struct mlx4_icm_iter iter;
1070 __be64 *pages;
1071 int lg;
1072 int nent = 0;
1073 int i;
1074 int err = 0;
1075 int ts = 0, tc = 0;
1076
1077 mailbox = mlx4_alloc_cmd_mailbox(dev);
1078 if (IS_ERR(mailbox))
1079 return PTR_ERR(mailbox);
1080 pages = mailbox->buf;
1081
1082 for (mlx4_icm_first(icm, &iter);
1083 !mlx4_icm_last(&iter);
1084 mlx4_icm_next(&iter)) {
1085 /*
1086 * We have to pass pages that are aligned to their
1087 * size, so find the least significant 1 in the
1088 * address or size and use that as our log2 size.
1089 */
1090 lg = ffs(mlx4_icm_addr(&iter) | mlx4_icm_size(&iter)) - 1;
1091 if (lg < MLX4_ICM_PAGE_SHIFT) {
1092 mlx4_warn(dev, "Got FW area not aligned to %d (%llx/%lx)\n",
1093 MLX4_ICM_PAGE_SIZE,
1094 (unsigned long long) mlx4_icm_addr(&iter),
1095 mlx4_icm_size(&iter));
1096 err = -EINVAL;
1097 goto out;
1098 }
1099
1100 for (i = 0; i < mlx4_icm_size(&iter) >> lg; ++i) {
1101 if (virt != -1) {
1102 pages[nent * 2] = cpu_to_be64(virt);
1103 virt += 1 << lg;
1104 }
1105
1106 pages[nent * 2 + 1] =
1107 cpu_to_be64((mlx4_icm_addr(&iter) + (i << lg)) |
1108 (lg - MLX4_ICM_PAGE_SHIFT));
1109 ts += 1 << (lg - 10);
1110 ++tc;
1111
1112 if (++nent == MLX4_MAILBOX_SIZE / 16) {
1113 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op,
1114 MLX4_CMD_TIME_CLASS_B,
1115 MLX4_CMD_NATIVE);
1116 if (err)
1117 goto out;
1118 nent = 0;
1119 }
1120 }
1121 }
1122
1123 if (nent)
1124 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op,
1125 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
1126 if (err)
1127 goto out;
1128
1129 switch (op) {
1130 case MLX4_CMD_MAP_FA:
1131 mlx4_dbg(dev, "Mapped %d chunks/%d KB for FW\n", tc, ts);
1132 break;
1133 case MLX4_CMD_MAP_ICM_AUX:
1134 mlx4_dbg(dev, "Mapped %d chunks/%d KB for ICM aux\n", tc, ts);
1135 break;
1136 case MLX4_CMD_MAP_ICM:
1137 mlx4_dbg(dev, "Mapped %d chunks/%d KB at %llx for ICM\n",
1138 tc, ts, (unsigned long long) virt - (ts << 10));
1139 break;
1140 }
1141
1142 out:
1143 mlx4_free_cmd_mailbox(dev, mailbox);
1144 return err;
1145 }
1146
1147 int mlx4_MAP_FA(struct mlx4_dev *dev, struct mlx4_icm *icm)
1148 {
1149 return mlx4_map_cmd(dev, MLX4_CMD_MAP_FA, icm, -1);
1150 }
1151
1152 int mlx4_UNMAP_FA(struct mlx4_dev *dev)
1153 {
1154 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_UNMAP_FA,
1155 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
1156 }
1157
1158
1159 int mlx4_RUN_FW(struct mlx4_dev *dev)
1160 {
1161 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_RUN_FW,
1162 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1163 }
1164
1165 int mlx4_QUERY_FW(struct mlx4_dev *dev)
1166 {
1167 struct mlx4_fw *fw = &mlx4_priv(dev)->fw;
1168 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
1169 struct mlx4_cmd_mailbox *mailbox;
1170 u32 *outbox;
1171 int err = 0;
1172 u64 fw_ver;
1173 u16 cmd_if_rev;
1174 u8 lg;
1175
1176 #define QUERY_FW_OUT_SIZE 0x100
1177 #define QUERY_FW_VER_OFFSET 0x00
1178 #define QUERY_FW_PPF_ID 0x09
1179 #define QUERY_FW_CMD_IF_REV_OFFSET 0x0a
1180 #define QUERY_FW_MAX_CMD_OFFSET 0x0f
1181 #define QUERY_FW_ERR_START_OFFSET 0x30
1182 #define QUERY_FW_ERR_SIZE_OFFSET 0x38
1183 #define QUERY_FW_ERR_BAR_OFFSET 0x3c
1184
1185 #define QUERY_FW_SIZE_OFFSET 0x00
1186 #define QUERY_FW_CLR_INT_BASE_OFFSET 0x20
1187 #define QUERY_FW_CLR_INT_BAR_OFFSET 0x28
1188
1189 #define QUERY_FW_COMM_BASE_OFFSET 0x40
1190 #define QUERY_FW_COMM_BAR_OFFSET 0x48
1191
1192 #define QUERY_FW_CLOCK_OFFSET 0x50
1193 #define QUERY_FW_CLOCK_BAR 0x58
1194
1195 mailbox = mlx4_alloc_cmd_mailbox(dev);
1196 if (IS_ERR(mailbox))
1197 return PTR_ERR(mailbox);
1198 outbox = mailbox->buf;
1199
1200 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_FW,
1201 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1202 if (err)
1203 goto out;
1204
1205 MLX4_GET(fw_ver, outbox, QUERY_FW_VER_OFFSET);
1206 /*
1207 * FW subminor version is at more significant bits than minor
1208 * version, so swap here.
1209 */
1210 dev->caps.fw_ver = (fw_ver & 0xffff00000000ull) |
1211 ((fw_ver & 0xffff0000ull) >> 16) |
1212 ((fw_ver & 0x0000ffffull) << 16);
1213
1214 MLX4_GET(lg, outbox, QUERY_FW_PPF_ID);
1215 dev->caps.function = lg;
1216
1217 if (mlx4_is_slave(dev))
1218 goto out;
1219
1220
1221 MLX4_GET(cmd_if_rev, outbox, QUERY_FW_CMD_IF_REV_OFFSET);
1222 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_MIN_REV ||
1223 cmd_if_rev > MLX4_COMMAND_INTERFACE_MAX_REV) {
1224 mlx4_err(dev, "Installed FW has unsupported command interface revision %d\n",
1225 cmd_if_rev);
1226 mlx4_err(dev, "(Installed FW version is %d.%d.%03d)\n",
1227 (int) (dev->caps.fw_ver >> 32),
1228 (int) (dev->caps.fw_ver >> 16) & 0xffff,
1229 (int) dev->caps.fw_ver & 0xffff);
1230 mlx4_err(dev, "This driver version supports only revisions %d to %d\n",
1231 MLX4_COMMAND_INTERFACE_MIN_REV, MLX4_COMMAND_INTERFACE_MAX_REV);
1232 err = -ENODEV;
1233 goto out;
1234 }
1235
1236 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS)
1237 dev->flags |= MLX4_FLAG_OLD_PORT_CMDS;
1238
1239 MLX4_GET(lg, outbox, QUERY_FW_MAX_CMD_OFFSET);
1240 cmd->max_cmds = 1 << lg;
1241
1242 mlx4_dbg(dev, "FW version %d.%d.%03d (cmd intf rev %d), max commands %d\n",
1243 (int) (dev->caps.fw_ver >> 32),
1244 (int) (dev->caps.fw_ver >> 16) & 0xffff,
1245 (int) dev->caps.fw_ver & 0xffff,
1246 cmd_if_rev, cmd->max_cmds);
1247
1248 MLX4_GET(fw->catas_offset, outbox, QUERY_FW_ERR_START_OFFSET);
1249 MLX4_GET(fw->catas_size, outbox, QUERY_FW_ERR_SIZE_OFFSET);
1250 MLX4_GET(fw->catas_bar, outbox, QUERY_FW_ERR_BAR_OFFSET);
1251 fw->catas_bar = (fw->catas_bar >> 6) * 2;
1252
1253 mlx4_dbg(dev, "Catastrophic error buffer at 0x%llx, size 0x%x, BAR %d\n",
1254 (unsigned long long) fw->catas_offset, fw->catas_size, fw->catas_bar);
1255
1256 MLX4_GET(fw->fw_pages, outbox, QUERY_FW_SIZE_OFFSET);
1257 MLX4_GET(fw->clr_int_base, outbox, QUERY_FW_CLR_INT_BASE_OFFSET);
1258 MLX4_GET(fw->clr_int_bar, outbox, QUERY_FW_CLR_INT_BAR_OFFSET);
1259 fw->clr_int_bar = (fw->clr_int_bar >> 6) * 2;
1260
1261 MLX4_GET(fw->comm_base, outbox, QUERY_FW_COMM_BASE_OFFSET);
1262 MLX4_GET(fw->comm_bar, outbox, QUERY_FW_COMM_BAR_OFFSET);
1263 fw->comm_bar = (fw->comm_bar >> 6) * 2;
1264 mlx4_dbg(dev, "Communication vector bar:%d offset:0x%llx\n",
1265 fw->comm_bar, fw->comm_base);
1266 mlx4_dbg(dev, "FW size %d KB\n", fw->fw_pages >> 2);
1267
1268 MLX4_GET(fw->clock_offset, outbox, QUERY_FW_CLOCK_OFFSET);
1269 MLX4_GET(fw->clock_bar, outbox, QUERY_FW_CLOCK_BAR);
1270 fw->clock_bar = (fw->clock_bar >> 6) * 2;
1271 mlx4_dbg(dev, "Internal clock bar:%d offset:0x%llx\n",
1272 fw->clock_bar, fw->clock_offset);
1273
1274 /*
1275 * Round up number of system pages needed in case
1276 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE.
1277 */
1278 fw->fw_pages =
1279 ALIGN(fw->fw_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >>
1280 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT);
1281
1282 mlx4_dbg(dev, "Clear int @ %llx, BAR %d\n",
1283 (unsigned long long) fw->clr_int_base, fw->clr_int_bar);
1284
1285 out:
1286 mlx4_free_cmd_mailbox(dev, mailbox);
1287 return err;
1288 }
1289
1290 int mlx4_QUERY_FW_wrapper(struct mlx4_dev *dev, int slave,
1291 struct mlx4_vhcr *vhcr,
1292 struct mlx4_cmd_mailbox *inbox,
1293 struct mlx4_cmd_mailbox *outbox,
1294 struct mlx4_cmd_info *cmd)
1295 {
1296 u8 *outbuf;
1297 int err;
1298
1299 outbuf = outbox->buf;
1300 err = mlx4_cmd_box(dev, 0, outbox->dma, 0, 0, MLX4_CMD_QUERY_FW,
1301 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1302 if (err)
1303 return err;
1304
1305 /* for slaves, set pci PPF ID to invalid and zero out everything
1306 * else except FW version */
1307 outbuf[0] = outbuf[1] = 0;
1308 memset(&outbuf[8], 0, QUERY_FW_OUT_SIZE - 8);
1309 outbuf[QUERY_FW_PPF_ID] = MLX4_INVALID_SLAVE_ID;
1310
1311 return 0;
1312 }
1313
1314 static void get_board_id(void *vsd, char *board_id)
1315 {
1316 int i;
1317
1318 #define VSD_OFFSET_SIG1 0x00
1319 #define VSD_OFFSET_SIG2 0xde
1320 #define VSD_OFFSET_MLX_BOARD_ID 0xd0
1321 #define VSD_OFFSET_TS_BOARD_ID 0x20
1322
1323 #define VSD_SIGNATURE_TOPSPIN 0x5ad
1324
1325 memset(board_id, 0, MLX4_BOARD_ID_LEN);
1326
1327 if (be16_to_cpup(vsd + VSD_OFFSET_SIG1) == VSD_SIGNATURE_TOPSPIN &&
1328 be16_to_cpup(vsd + VSD_OFFSET_SIG2) == VSD_SIGNATURE_TOPSPIN) {
1329 strlcpy(board_id, vsd + VSD_OFFSET_TS_BOARD_ID, MLX4_BOARD_ID_LEN);
1330 } else {
1331 /*
1332 * The board ID is a string but the firmware byte
1333 * swaps each 4-byte word before passing it back to
1334 * us. Therefore we need to swab it before printing.
1335 */
1336 for (i = 0; i < 4; ++i)
1337 ((u32 *) board_id)[i] =
1338 swab32(*(u32 *) (vsd + VSD_OFFSET_MLX_BOARD_ID + i * 4));
1339 }
1340 }
1341
1342 int mlx4_QUERY_ADAPTER(struct mlx4_dev *dev, struct mlx4_adapter *adapter)
1343 {
1344 struct mlx4_cmd_mailbox *mailbox;
1345 u32 *outbox;
1346 int err;
1347
1348 #define QUERY_ADAPTER_OUT_SIZE 0x100
1349 #define QUERY_ADAPTER_INTA_PIN_OFFSET 0x10
1350 #define QUERY_ADAPTER_VSD_OFFSET 0x20
1351
1352 mailbox = mlx4_alloc_cmd_mailbox(dev);
1353 if (IS_ERR(mailbox))
1354 return PTR_ERR(mailbox);
1355 outbox = mailbox->buf;
1356
1357 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_ADAPTER,
1358 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1359 if (err)
1360 goto out;
1361
1362 MLX4_GET(adapter->inta_pin, outbox, QUERY_ADAPTER_INTA_PIN_OFFSET);
1363
1364 get_board_id(outbox + QUERY_ADAPTER_VSD_OFFSET / 4,
1365 adapter->board_id);
1366
1367 out:
1368 mlx4_free_cmd_mailbox(dev, mailbox);
1369 return err;
1370 }
1371
1372 int mlx4_INIT_HCA(struct mlx4_dev *dev, struct mlx4_init_hca_param *param)
1373 {
1374 struct mlx4_cmd_mailbox *mailbox;
1375 __be32 *inbox;
1376 int err;
1377
1378 #define INIT_HCA_IN_SIZE 0x200
1379 #define INIT_HCA_VERSION_OFFSET 0x000
1380 #define INIT_HCA_VERSION 2
1381 #define INIT_HCA_VXLAN_OFFSET 0x0c
1382 #define INIT_HCA_CACHELINE_SZ_OFFSET 0x0e
1383 #define INIT_HCA_FLAGS_OFFSET 0x014
1384 #define INIT_HCA_QPC_OFFSET 0x020
1385 #define INIT_HCA_QPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x10)
1386 #define INIT_HCA_LOG_QP_OFFSET (INIT_HCA_QPC_OFFSET + 0x17)
1387 #define INIT_HCA_SRQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x28)
1388 #define INIT_HCA_LOG_SRQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x2f)
1389 #define INIT_HCA_CQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x30)
1390 #define INIT_HCA_LOG_CQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x37)
1391 #define INIT_HCA_EQE_CQE_OFFSETS (INIT_HCA_QPC_OFFSET + 0x38)
1392 #define INIT_HCA_EQE_CQE_STRIDE_OFFSET (INIT_HCA_QPC_OFFSET + 0x3b)
1393 #define INIT_HCA_ALTC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x40)
1394 #define INIT_HCA_AUXC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x50)
1395 #define INIT_HCA_EQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x60)
1396 #define INIT_HCA_LOG_EQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x67)
1397 #define INIT_HCA_RDMARC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x70)
1398 #define INIT_HCA_LOG_RD_OFFSET (INIT_HCA_QPC_OFFSET + 0x77)
1399 #define INIT_HCA_MCAST_OFFSET 0x0c0
1400 #define INIT_HCA_MC_BASE_OFFSET (INIT_HCA_MCAST_OFFSET + 0x00)
1401 #define INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x12)
1402 #define INIT_HCA_LOG_MC_HASH_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x16)
1403 #define INIT_HCA_UC_STEERING_OFFSET (INIT_HCA_MCAST_OFFSET + 0x18)
1404 #define INIT_HCA_LOG_MC_TABLE_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x1b)
1405 #define INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN 0x6
1406 #define INIT_HCA_FS_PARAM_OFFSET 0x1d0
1407 #define INIT_HCA_FS_BASE_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x00)
1408 #define INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x12)
1409 #define INIT_HCA_FS_LOG_TABLE_SZ_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x1b)
1410 #define INIT_HCA_FS_ETH_BITS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x21)
1411 #define INIT_HCA_FS_ETH_NUM_ADDRS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x22)
1412 #define INIT_HCA_FS_IB_BITS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x25)
1413 #define INIT_HCA_FS_IB_NUM_ADDRS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x26)
1414 #define INIT_HCA_TPT_OFFSET 0x0f0
1415 #define INIT_HCA_DMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x00)
1416 #define INIT_HCA_TPT_MW_OFFSET (INIT_HCA_TPT_OFFSET + 0x08)
1417 #define INIT_HCA_LOG_MPT_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x0b)
1418 #define INIT_HCA_MTT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x10)
1419 #define INIT_HCA_CMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x18)
1420 #define INIT_HCA_UAR_OFFSET 0x120
1421 #define INIT_HCA_LOG_UAR_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0a)
1422 #define INIT_HCA_UAR_PAGE_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0b)
1423
1424 mailbox = mlx4_alloc_cmd_mailbox(dev);
1425 if (IS_ERR(mailbox))
1426 return PTR_ERR(mailbox);
1427 inbox = mailbox->buf;
1428
1429 *((u8 *) mailbox->buf + INIT_HCA_VERSION_OFFSET) = INIT_HCA_VERSION;
1430
1431 *((u8 *) mailbox->buf + INIT_HCA_CACHELINE_SZ_OFFSET) =
1432 (ilog2(cache_line_size()) - 4) << 5;
1433
1434 #if defined(__LITTLE_ENDIAN)
1435 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) &= ~cpu_to_be32(1 << 1);
1436 #elif defined(__BIG_ENDIAN)
1437 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 1);
1438 #else
1439 #error Host endianness not defined
1440 #endif
1441 /* Check port for UD address vector: */
1442 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1);
1443
1444 /* Enable IPoIB checksumming if we can: */
1445 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_IPOIB_CSUM)
1446 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 3);
1447
1448 /* Enable QoS support if module parameter set */
1449 if (enable_qos)
1450 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 2);
1451
1452 /* enable counters */
1453 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS)
1454 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 4);
1455
1456 /* CX3 is capable of extending CQEs/EQEs from 32 to 64 bytes */
1457 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_64B_EQE) {
1458 *(inbox + INIT_HCA_EQE_CQE_OFFSETS / 4) |= cpu_to_be32(1 << 29);
1459 dev->caps.eqe_size = 64;
1460 dev->caps.eqe_factor = 1;
1461 } else {
1462 dev->caps.eqe_size = 32;
1463 dev->caps.eqe_factor = 0;
1464 }
1465
1466 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_64B_CQE) {
1467 *(inbox + INIT_HCA_EQE_CQE_OFFSETS / 4) |= cpu_to_be32(1 << 30);
1468 dev->caps.cqe_size = 64;
1469 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE;
1470 } else {
1471 dev->caps.cqe_size = 32;
1472 }
1473
1474 /* CX3 is capable of extending CQEs\EQEs to strides larger than 64B */
1475 if ((dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_EQE_STRIDE) &&
1476 (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_CQE_STRIDE)) {
1477 dev->caps.eqe_size = cache_line_size();
1478 dev->caps.cqe_size = cache_line_size();
1479 dev->caps.eqe_factor = 0;
1480 MLX4_PUT(inbox, (u8)((ilog2(dev->caps.eqe_size) - 5) << 4 |
1481 (ilog2(dev->caps.eqe_size) - 5)),
1482 INIT_HCA_EQE_CQE_STRIDE_OFFSET);
1483
1484 /* User still need to know to support CQE > 32B */
1485 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE;
1486 }
1487
1488 /* QPC/EEC/CQC/EQC/RDMARC attributes */
1489
1490 MLX4_PUT(inbox, param->qpc_base, INIT_HCA_QPC_BASE_OFFSET);
1491 MLX4_PUT(inbox, param->log_num_qps, INIT_HCA_LOG_QP_OFFSET);
1492 MLX4_PUT(inbox, param->srqc_base, INIT_HCA_SRQC_BASE_OFFSET);
1493 MLX4_PUT(inbox, param->log_num_srqs, INIT_HCA_LOG_SRQ_OFFSET);
1494 MLX4_PUT(inbox, param->cqc_base, INIT_HCA_CQC_BASE_OFFSET);
1495 MLX4_PUT(inbox, param->log_num_cqs, INIT_HCA_LOG_CQ_OFFSET);
1496 MLX4_PUT(inbox, param->altc_base, INIT_HCA_ALTC_BASE_OFFSET);
1497 MLX4_PUT(inbox, param->auxc_base, INIT_HCA_AUXC_BASE_OFFSET);
1498 MLX4_PUT(inbox, param->eqc_base, INIT_HCA_EQC_BASE_OFFSET);
1499 MLX4_PUT(inbox, param->log_num_eqs, INIT_HCA_LOG_EQ_OFFSET);
1500 MLX4_PUT(inbox, param->rdmarc_base, INIT_HCA_RDMARC_BASE_OFFSET);
1501 MLX4_PUT(inbox, param->log_rd_per_qp, INIT_HCA_LOG_RD_OFFSET);
1502
1503 /* steering attributes */
1504 if (dev->caps.steering_mode ==
1505 MLX4_STEERING_MODE_DEVICE_MANAGED) {
1506 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |=
1507 cpu_to_be32(1 <<
1508 INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN);
1509
1510 MLX4_PUT(inbox, param->mc_base, INIT_HCA_FS_BASE_OFFSET);
1511 MLX4_PUT(inbox, param->log_mc_entry_sz,
1512 INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET);
1513 MLX4_PUT(inbox, param->log_mc_table_sz,
1514 INIT_HCA_FS_LOG_TABLE_SZ_OFFSET);
1515 /* Enable Ethernet flow steering
1516 * with udp unicast and tcp unicast
1517 */
1518 MLX4_PUT(inbox, (u8) (MLX4_FS_UDP_UC_EN | MLX4_FS_TCP_UC_EN),
1519 INIT_HCA_FS_ETH_BITS_OFFSET);
1520 MLX4_PUT(inbox, (u16) MLX4_FS_NUM_OF_L2_ADDR,
1521 INIT_HCA_FS_ETH_NUM_ADDRS_OFFSET);
1522 /* Enable IPoIB flow steering
1523 * with udp unicast and tcp unicast
1524 */
1525 MLX4_PUT(inbox, (u8) (MLX4_FS_UDP_UC_EN | MLX4_FS_TCP_UC_EN),
1526 INIT_HCA_FS_IB_BITS_OFFSET);
1527 MLX4_PUT(inbox, (u16) MLX4_FS_NUM_OF_L2_ADDR,
1528 INIT_HCA_FS_IB_NUM_ADDRS_OFFSET);
1529 } else {
1530 MLX4_PUT(inbox, param->mc_base, INIT_HCA_MC_BASE_OFFSET);
1531 MLX4_PUT(inbox, param->log_mc_entry_sz,
1532 INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET);
1533 MLX4_PUT(inbox, param->log_mc_hash_sz,
1534 INIT_HCA_LOG_MC_HASH_SZ_OFFSET);
1535 MLX4_PUT(inbox, param->log_mc_table_sz,
1536 INIT_HCA_LOG_MC_TABLE_SZ_OFFSET);
1537 if (dev->caps.steering_mode == MLX4_STEERING_MODE_B0)
1538 MLX4_PUT(inbox, (u8) (1 << 3),
1539 INIT_HCA_UC_STEERING_OFFSET);
1540 }
1541
1542 /* TPT attributes */
1543
1544 MLX4_PUT(inbox, param->dmpt_base, INIT_HCA_DMPT_BASE_OFFSET);
1545 MLX4_PUT(inbox, param->mw_enabled, INIT_HCA_TPT_MW_OFFSET);
1546 MLX4_PUT(inbox, param->log_mpt_sz, INIT_HCA_LOG_MPT_SZ_OFFSET);
1547 MLX4_PUT(inbox, param->mtt_base, INIT_HCA_MTT_BASE_OFFSET);
1548 MLX4_PUT(inbox, param->cmpt_base, INIT_HCA_CMPT_BASE_OFFSET);
1549
1550 /* UAR attributes */
1551
1552 MLX4_PUT(inbox, param->uar_page_sz, INIT_HCA_UAR_PAGE_SZ_OFFSET);
1553 MLX4_PUT(inbox, param->log_uar_sz, INIT_HCA_LOG_UAR_SZ_OFFSET);
1554
1555 /* set parser VXLAN attributes */
1556 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS) {
1557 u8 parser_params = 0;
1558 MLX4_PUT(inbox, parser_params, INIT_HCA_VXLAN_OFFSET);
1559 }
1560
1561 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_INIT_HCA, 10000,
1562 MLX4_CMD_NATIVE);
1563
1564 if (err)
1565 mlx4_err(dev, "INIT_HCA returns %d\n", err);
1566
1567 mlx4_free_cmd_mailbox(dev, mailbox);
1568 return err;
1569 }
1570
1571 int mlx4_QUERY_HCA(struct mlx4_dev *dev,
1572 struct mlx4_init_hca_param *param)
1573 {
1574 struct mlx4_cmd_mailbox *mailbox;
1575 __be32 *outbox;
1576 u32 dword_field;
1577 int err;
1578 u8 byte_field;
1579
1580 #define QUERY_HCA_GLOBAL_CAPS_OFFSET 0x04
1581 #define QUERY_HCA_CORE_CLOCK_OFFSET 0x0c
1582
1583 mailbox = mlx4_alloc_cmd_mailbox(dev);
1584 if (IS_ERR(mailbox))
1585 return PTR_ERR(mailbox);
1586 outbox = mailbox->buf;
1587
1588 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0,
1589 MLX4_CMD_QUERY_HCA,
1590 MLX4_CMD_TIME_CLASS_B,
1591 !mlx4_is_slave(dev));
1592 if (err)
1593 goto out;
1594
1595 MLX4_GET(param->global_caps, outbox, QUERY_HCA_GLOBAL_CAPS_OFFSET);
1596 MLX4_GET(param->hca_core_clock, outbox, QUERY_HCA_CORE_CLOCK_OFFSET);
1597
1598 /* QPC/EEC/CQC/EQC/RDMARC attributes */
1599
1600 MLX4_GET(param->qpc_base, outbox, INIT_HCA_QPC_BASE_OFFSET);
1601 MLX4_GET(param->log_num_qps, outbox, INIT_HCA_LOG_QP_OFFSET);
1602 MLX4_GET(param->srqc_base, outbox, INIT_HCA_SRQC_BASE_OFFSET);
1603 MLX4_GET(param->log_num_srqs, outbox, INIT_HCA_LOG_SRQ_OFFSET);
1604 MLX4_GET(param->cqc_base, outbox, INIT_HCA_CQC_BASE_OFFSET);
1605 MLX4_GET(param->log_num_cqs, outbox, INIT_HCA_LOG_CQ_OFFSET);
1606 MLX4_GET(param->altc_base, outbox, INIT_HCA_ALTC_BASE_OFFSET);
1607 MLX4_GET(param->auxc_base, outbox, INIT_HCA_AUXC_BASE_OFFSET);
1608 MLX4_GET(param->eqc_base, outbox, INIT_HCA_EQC_BASE_OFFSET);
1609 MLX4_GET(param->log_num_eqs, outbox, INIT_HCA_LOG_EQ_OFFSET);
1610 MLX4_GET(param->rdmarc_base, outbox, INIT_HCA_RDMARC_BASE_OFFSET);
1611 MLX4_GET(param->log_rd_per_qp, outbox, INIT_HCA_LOG_RD_OFFSET);
1612
1613 MLX4_GET(dword_field, outbox, INIT_HCA_FLAGS_OFFSET);
1614 if (dword_field & (1 << INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN)) {
1615 param->steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED;
1616 } else {
1617 MLX4_GET(byte_field, outbox, INIT_HCA_UC_STEERING_OFFSET);
1618 if (byte_field & 0x8)
1619 param->steering_mode = MLX4_STEERING_MODE_B0;
1620 else
1621 param->steering_mode = MLX4_STEERING_MODE_A0;
1622 }
1623 /* steering attributes */
1624 if (param->steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) {
1625 MLX4_GET(param->mc_base, outbox, INIT_HCA_FS_BASE_OFFSET);
1626 MLX4_GET(param->log_mc_entry_sz, outbox,
1627 INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET);
1628 MLX4_GET(param->log_mc_table_sz, outbox,
1629 INIT_HCA_FS_LOG_TABLE_SZ_OFFSET);
1630 } else {
1631 MLX4_GET(param->mc_base, outbox, INIT_HCA_MC_BASE_OFFSET);
1632 MLX4_GET(param->log_mc_entry_sz, outbox,
1633 INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET);
1634 MLX4_GET(param->log_mc_hash_sz, outbox,
1635 INIT_HCA_LOG_MC_HASH_SZ_OFFSET);
1636 MLX4_GET(param->log_mc_table_sz, outbox,
1637 INIT_HCA_LOG_MC_TABLE_SZ_OFFSET);
1638 }
1639
1640 /* CX3 is capable of extending CQEs/EQEs from 32 to 64 bytes */
1641 MLX4_GET(byte_field, outbox, INIT_HCA_EQE_CQE_OFFSETS);
1642 if (byte_field & 0x20) /* 64-bytes eqe enabled */
1643 param->dev_cap_enabled |= MLX4_DEV_CAP_64B_EQE_ENABLED;
1644 if (byte_field & 0x40) /* 64-bytes cqe enabled */
1645 param->dev_cap_enabled |= MLX4_DEV_CAP_64B_CQE_ENABLED;
1646
1647 /* CX3 is capable of extending CQEs\EQEs to strides larger than 64B */
1648 MLX4_GET(byte_field, outbox, INIT_HCA_EQE_CQE_STRIDE_OFFSET);
1649 if (byte_field) {
1650 param->dev_cap_enabled |= MLX4_DEV_CAP_64B_EQE_ENABLED;
1651 param->dev_cap_enabled |= MLX4_DEV_CAP_64B_CQE_ENABLED;
1652 param->cqe_size = 1 << ((byte_field &
1653 MLX4_CQE_SIZE_MASK_STRIDE) + 5);
1654 param->eqe_size = 1 << (((byte_field &
1655 MLX4_EQE_SIZE_MASK_STRIDE) >> 4) + 5);
1656 }
1657
1658 /* TPT attributes */
1659
1660 MLX4_GET(param->dmpt_base, outbox, INIT_HCA_DMPT_BASE_OFFSET);
1661 MLX4_GET(param->mw_enabled, outbox, INIT_HCA_TPT_MW_OFFSET);
1662 MLX4_GET(param->log_mpt_sz, outbox, INIT_HCA_LOG_MPT_SZ_OFFSET);
1663 MLX4_GET(param->mtt_base, outbox, INIT_HCA_MTT_BASE_OFFSET);
1664 MLX4_GET(param->cmpt_base, outbox, INIT_HCA_CMPT_BASE_OFFSET);
1665
1666 /* UAR attributes */
1667
1668 MLX4_GET(param->uar_page_sz, outbox, INIT_HCA_UAR_PAGE_SZ_OFFSET);
1669 MLX4_GET(param->log_uar_sz, outbox, INIT_HCA_LOG_UAR_SZ_OFFSET);
1670
1671 out:
1672 mlx4_free_cmd_mailbox(dev, mailbox);
1673
1674 return err;
1675 }
1676
1677 /* for IB-type ports only in SRIOV mode. Checks that both proxy QP0
1678 * and real QP0 are active, so that the paravirtualized QP0 is ready
1679 * to operate */
1680 static int check_qp0_state(struct mlx4_dev *dev, int function, int port)
1681 {
1682 struct mlx4_priv *priv = mlx4_priv(dev);
1683 /* irrelevant if not infiniband */
1684 if (priv->mfunc.master.qp0_state[port].proxy_qp0_active &&
1685 priv->mfunc.master.qp0_state[port].qp0_active)
1686 return 1;
1687 return 0;
1688 }
1689
1690 int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave,
1691 struct mlx4_vhcr *vhcr,
1692 struct mlx4_cmd_mailbox *inbox,
1693 struct mlx4_cmd_mailbox *outbox,
1694 struct mlx4_cmd_info *cmd)
1695 {
1696 struct mlx4_priv *priv = mlx4_priv(dev);
1697 int port = mlx4_slave_convert_port(dev, slave, vhcr->in_modifier);
1698 int err;
1699
1700 if (port < 0)
1701 return -EINVAL;
1702
1703 if (priv->mfunc.master.slave_state[slave].init_port_mask & (1 << port))
1704 return 0;
1705
1706 if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB) {
1707 /* Enable port only if it was previously disabled */
1708 if (!priv->mfunc.master.init_port_ref[port]) {
1709 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
1710 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1711 if (err)
1712 return err;
1713 }
1714 priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port);
1715 } else {
1716 if (slave == mlx4_master_func_num(dev)) {
1717 if (check_qp0_state(dev, slave, port) &&
1718 !priv->mfunc.master.qp0_state[port].port_active) {
1719 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
1720 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1721 if (err)
1722 return err;
1723 priv->mfunc.master.qp0_state[port].port_active = 1;
1724 priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port);
1725 }
1726 } else
1727 priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port);
1728 }
1729 ++priv->mfunc.master.init_port_ref[port];
1730 return 0;
1731 }
1732
1733 int mlx4_INIT_PORT(struct mlx4_dev *dev, int port)
1734 {
1735 struct mlx4_cmd_mailbox *mailbox;
1736 u32 *inbox;
1737 int err;
1738 u32 flags;
1739 u16 field;
1740
1741 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
1742 #define INIT_PORT_IN_SIZE 256
1743 #define INIT_PORT_FLAGS_OFFSET 0x00
1744 #define INIT_PORT_FLAG_SIG (1 << 18)
1745 #define INIT_PORT_FLAG_NG (1 << 17)
1746 #define INIT_PORT_FLAG_G0 (1 << 16)
1747 #define INIT_PORT_VL_SHIFT 4
1748 #define INIT_PORT_PORT_WIDTH_SHIFT 8
1749 #define INIT_PORT_MTU_OFFSET 0x04
1750 #define INIT_PORT_MAX_GID_OFFSET 0x06
1751 #define INIT_PORT_MAX_PKEY_OFFSET 0x0a
1752 #define INIT_PORT_GUID0_OFFSET 0x10
1753 #define INIT_PORT_NODE_GUID_OFFSET 0x18
1754 #define INIT_PORT_SI_GUID_OFFSET 0x20
1755
1756 mailbox = mlx4_alloc_cmd_mailbox(dev);
1757 if (IS_ERR(mailbox))
1758 return PTR_ERR(mailbox);
1759 inbox = mailbox->buf;
1760
1761 flags = 0;
1762 flags |= (dev->caps.vl_cap[port] & 0xf) << INIT_PORT_VL_SHIFT;
1763 flags |= (dev->caps.port_width_cap[port] & 0xf) << INIT_PORT_PORT_WIDTH_SHIFT;
1764 MLX4_PUT(inbox, flags, INIT_PORT_FLAGS_OFFSET);
1765
1766 field = 128 << dev->caps.ib_mtu_cap[port];
1767 MLX4_PUT(inbox, field, INIT_PORT_MTU_OFFSET);
1768 field = dev->caps.gid_table_len[port];
1769 MLX4_PUT(inbox, field, INIT_PORT_MAX_GID_OFFSET);
1770 field = dev->caps.pkey_table_len[port];
1771 MLX4_PUT(inbox, field, INIT_PORT_MAX_PKEY_OFFSET);
1772
1773 err = mlx4_cmd(dev, mailbox->dma, port, 0, MLX4_CMD_INIT_PORT,
1774 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1775
1776 mlx4_free_cmd_mailbox(dev, mailbox);
1777 } else
1778 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
1779 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
1780
1781 return err;
1782 }
1783 EXPORT_SYMBOL_GPL(mlx4_INIT_PORT);
1784
1785 int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave,
1786 struct mlx4_vhcr *vhcr,
1787 struct mlx4_cmd_mailbox *inbox,
1788 struct mlx4_cmd_mailbox *outbox,
1789 struct mlx4_cmd_info *cmd)
1790 {
1791 struct mlx4_priv *priv = mlx4_priv(dev);
1792 int port = mlx4_slave_convert_port(dev, slave, vhcr->in_modifier);
1793 int err;
1794
1795 if (port < 0)
1796 return -EINVAL;
1797
1798 if (!(priv->mfunc.master.slave_state[slave].init_port_mask &
1799 (1 << port)))
1800 return 0;
1801
1802 if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB) {
1803 if (priv->mfunc.master.init_port_ref[port] == 1) {
1804 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT,
1805 1000, MLX4_CMD_NATIVE);
1806 if (err)
1807 return err;
1808 }
1809 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port);
1810 } else {
1811 /* infiniband port */
1812 if (slave == mlx4_master_func_num(dev)) {
1813 if (!priv->mfunc.master.qp0_state[port].qp0_active &&
1814 priv->mfunc.master.qp0_state[port].port_active) {
1815 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT,
1816 1000, MLX4_CMD_NATIVE);
1817 if (err)
1818 return err;
1819 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port);
1820 priv->mfunc.master.qp0_state[port].port_active = 0;
1821 }
1822 } else
1823 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port);
1824 }
1825 --priv->mfunc.master.init_port_ref[port];
1826 return 0;
1827 }
1828
1829 int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port)
1830 {
1831 return mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, 1000,
1832 MLX4_CMD_WRAPPED);
1833 }
1834 EXPORT_SYMBOL_GPL(mlx4_CLOSE_PORT);
1835
1836 int mlx4_CLOSE_HCA(struct mlx4_dev *dev, int panic)
1837 {
1838 return mlx4_cmd(dev, 0, 0, panic, MLX4_CMD_CLOSE_HCA, 1000,
1839 MLX4_CMD_NATIVE);
1840 }
1841
1842 struct mlx4_config_dev {
1843 __be32 update_flags;
1844 __be32 rsdv1[3];
1845 __be16 vxlan_udp_dport;
1846 __be16 rsvd2;
1847 };
1848
1849 #define MLX4_VXLAN_UDP_DPORT (1 << 0)
1850
1851 static int mlx4_CONFIG_DEV(struct mlx4_dev *dev, struct mlx4_config_dev *config_dev)
1852 {
1853 int err;
1854 struct mlx4_cmd_mailbox *mailbox;
1855
1856 mailbox = mlx4_alloc_cmd_mailbox(dev);
1857 if (IS_ERR(mailbox))
1858 return PTR_ERR(mailbox);
1859
1860 memcpy(mailbox->buf, config_dev, sizeof(*config_dev));
1861
1862 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_CONFIG_DEV,
1863 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
1864
1865 mlx4_free_cmd_mailbox(dev, mailbox);
1866 return err;
1867 }
1868
1869 int mlx4_config_vxlan_port(struct mlx4_dev *dev, __be16 udp_port)
1870 {
1871 struct mlx4_config_dev config_dev;
1872
1873 memset(&config_dev, 0, sizeof(config_dev));
1874 config_dev.update_flags = cpu_to_be32(MLX4_VXLAN_UDP_DPORT);
1875 config_dev.vxlan_udp_dport = udp_port;
1876
1877 return mlx4_CONFIG_DEV(dev, &config_dev);
1878 }
1879 EXPORT_SYMBOL_GPL(mlx4_config_vxlan_port);
1880
1881
1882 int mlx4_SET_ICM_SIZE(struct mlx4_dev *dev, u64 icm_size, u64 *aux_pages)
1883 {
1884 int ret = mlx4_cmd_imm(dev, icm_size, aux_pages, 0, 0,
1885 MLX4_CMD_SET_ICM_SIZE,
1886 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1887 if (ret)
1888 return ret;
1889
1890 /*
1891 * Round up number of system pages needed in case
1892 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE.
1893 */
1894 *aux_pages = ALIGN(*aux_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >>
1895 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT);
1896
1897 return 0;
1898 }
1899
1900 int mlx4_NOP(struct mlx4_dev *dev)
1901 {
1902 /* Input modifier of 0x1f means "finish as soon as possible." */
1903 return mlx4_cmd(dev, 0, 0x1f, 0, MLX4_CMD_NOP, 100, MLX4_CMD_NATIVE);
1904 }
1905
1906 int mlx4_get_phys_port_id(struct mlx4_dev *dev)
1907 {
1908 u8 port;
1909 u32 *outbox;
1910 struct mlx4_cmd_mailbox *mailbox;
1911 u32 in_mod;
1912 u32 guid_hi, guid_lo;
1913 int err, ret = 0;
1914 #define MOD_STAT_CFG_PORT_OFFSET 8
1915 #define MOD_STAT_CFG_GUID_H 0X14
1916 #define MOD_STAT_CFG_GUID_L 0X1c
1917
1918 mailbox = mlx4_alloc_cmd_mailbox(dev);
1919 if (IS_ERR(mailbox))
1920 return PTR_ERR(mailbox);
1921 outbox = mailbox->buf;
1922
1923 for (port = 1; port <= dev->caps.num_ports; port++) {
1924 in_mod = port << MOD_STAT_CFG_PORT_OFFSET;
1925 err = mlx4_cmd_box(dev, 0, mailbox->dma, in_mod, 0x2,
1926 MLX4_CMD_MOD_STAT_CFG, MLX4_CMD_TIME_CLASS_A,
1927 MLX4_CMD_NATIVE);
1928 if (err) {
1929 mlx4_err(dev, "Fail to get port %d uplink guid\n",
1930 port);
1931 ret = err;
1932 } else {
1933 MLX4_GET(guid_hi, outbox, MOD_STAT_CFG_GUID_H);
1934 MLX4_GET(guid_lo, outbox, MOD_STAT_CFG_GUID_L);
1935 dev->caps.phys_port_id[port] = (u64)guid_lo |
1936 (u64)guid_hi << 32;
1937 }
1938 }
1939 mlx4_free_cmd_mailbox(dev, mailbox);
1940 return ret;
1941 }
1942
1943 #define MLX4_WOL_SETUP_MODE (5 << 28)
1944 int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port)
1945 {
1946 u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8;
1947
1948 return mlx4_cmd_imm(dev, 0, config, in_mod, 0x3,
1949 MLX4_CMD_MOD_STAT_CFG, MLX4_CMD_TIME_CLASS_A,
1950 MLX4_CMD_NATIVE);
1951 }
1952 EXPORT_SYMBOL_GPL(mlx4_wol_read);
1953
1954 int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port)
1955 {
1956 u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8;
1957
1958 return mlx4_cmd(dev, config, in_mod, 0x1, MLX4_CMD_MOD_STAT_CFG,
1959 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1960 }
1961 EXPORT_SYMBOL_GPL(mlx4_wol_write);
1962
1963 enum {
1964 ADD_TO_MCG = 0x26,
1965 };
1966
1967
1968 void mlx4_opreq_action(struct work_struct *work)
1969 {
1970 struct mlx4_priv *priv = container_of(work, struct mlx4_priv,
1971 opreq_task);
1972 struct mlx4_dev *dev = &priv->dev;
1973 int num_tasks = atomic_read(&priv->opreq_count);
1974 struct mlx4_cmd_mailbox *mailbox;
1975 struct mlx4_mgm *mgm;
1976 u32 *outbox;
1977 u32 modifier;
1978 u16 token;
1979 u16 type;
1980 int err;
1981 u32 num_qps;
1982 struct mlx4_qp qp;
1983 int i;
1984 u8 rem_mcg;
1985 u8 prot;
1986
1987 #define GET_OP_REQ_MODIFIER_OFFSET 0x08
1988 #define GET_OP_REQ_TOKEN_OFFSET 0x14
1989 #define GET_OP_REQ_TYPE_OFFSET 0x1a
1990 #define GET_OP_REQ_DATA_OFFSET 0x20
1991
1992 mailbox = mlx4_alloc_cmd_mailbox(dev);
1993 if (IS_ERR(mailbox)) {
1994 mlx4_err(dev, "Failed to allocate mailbox for GET_OP_REQ\n");
1995 return;
1996 }
1997 outbox = mailbox->buf;
1998
1999 while (num_tasks) {
2000 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0,
2001 MLX4_CMD_GET_OP_REQ, MLX4_CMD_TIME_CLASS_A,
2002 MLX4_CMD_NATIVE);
2003 if (err) {
2004 mlx4_err(dev, "Failed to retrieve required operation: %d\n",
2005 err);
2006 return;
2007 }
2008 MLX4_GET(modifier, outbox, GET_OP_REQ_MODIFIER_OFFSET);
2009 MLX4_GET(token, outbox, GET_OP_REQ_TOKEN_OFFSET);
2010 MLX4_GET(type, outbox, GET_OP_REQ_TYPE_OFFSET);
2011 type &= 0xfff;
2012
2013 switch (type) {
2014 case ADD_TO_MCG:
2015 if (dev->caps.steering_mode ==
2016 MLX4_STEERING_MODE_DEVICE_MANAGED) {
2017 mlx4_warn(dev, "ADD MCG operation is not supported in DEVICE_MANAGED steering mode\n");
2018 err = EPERM;
2019 break;
2020 }
2021 mgm = (struct mlx4_mgm *)((u8 *)(outbox) +
2022 GET_OP_REQ_DATA_OFFSET);
2023 num_qps = be32_to_cpu(mgm->members_count) &
2024 MGM_QPN_MASK;
2025 rem_mcg = ((u8 *)(&mgm->members_count))[0] & 1;
2026 prot = ((u8 *)(&mgm->members_count))[0] >> 6;
2027
2028 for (i = 0; i < num_qps; i++) {
2029 qp.qpn = be32_to_cpu(mgm->qp[i]);
2030 if (rem_mcg)
2031 err = mlx4_multicast_detach(dev, &qp,
2032 mgm->gid,
2033 prot, 0);
2034 else
2035 err = mlx4_multicast_attach(dev, &qp,
2036 mgm->gid,
2037 mgm->gid[5]
2038 , 0, prot,
2039 NULL);
2040 if (err)
2041 break;
2042 }
2043 break;
2044 default:
2045 mlx4_warn(dev, "Bad type for required operation\n");
2046 err = EINVAL;
2047 break;
2048 }
2049 err = mlx4_cmd(dev, 0, ((u32) err |
2050 (__force u32)cpu_to_be32(token) << 16),
2051 1, MLX4_CMD_GET_OP_REQ, MLX4_CMD_TIME_CLASS_A,
2052 MLX4_CMD_NATIVE);
2053 if (err) {
2054 mlx4_err(dev, "Failed to acknowledge required request: %d\n",
2055 err);
2056 goto out;
2057 }
2058 memset(outbox, 0, 0xffc);
2059 num_tasks = atomic_dec_return(&priv->opreq_count);
2060 }
2061
2062 out:
2063 mlx4_free_cmd_mailbox(dev, mailbox);
2064 }
2065
2066 static int mlx4_check_smp_firewall_active(struct mlx4_dev *dev,
2067 struct mlx4_cmd_mailbox *mailbox)
2068 {
2069 #define MLX4_CMD_MAD_DEMUX_SET_ATTR_OFFSET 0x10
2070 #define MLX4_CMD_MAD_DEMUX_GETRESP_ATTR_OFFSET 0x20
2071 #define MLX4_CMD_MAD_DEMUX_TRAP_ATTR_OFFSET 0x40
2072 #define MLX4_CMD_MAD_DEMUX_TRAP_REPRESS_ATTR_OFFSET 0x70
2073
2074 u32 set_attr_mask, getresp_attr_mask;
2075 u32 trap_attr_mask, traprepress_attr_mask;
2076
2077 MLX4_GET(set_attr_mask, mailbox->buf,
2078 MLX4_CMD_MAD_DEMUX_SET_ATTR_OFFSET);
2079 mlx4_dbg(dev, "SMP firewall set_attribute_mask = 0x%x\n",
2080 set_attr_mask);
2081
2082 MLX4_GET(getresp_attr_mask, mailbox->buf,
2083 MLX4_CMD_MAD_DEMUX_GETRESP_ATTR_OFFSET);
2084 mlx4_dbg(dev, "SMP firewall getresp_attribute_mask = 0x%x\n",
2085 getresp_attr_mask);
2086
2087 MLX4_GET(trap_attr_mask, mailbox->buf,
2088 MLX4_CMD_MAD_DEMUX_TRAP_ATTR_OFFSET);
2089 mlx4_dbg(dev, "SMP firewall trap_attribute_mask = 0x%x\n",
2090 trap_attr_mask);
2091
2092 MLX4_GET(traprepress_attr_mask, mailbox->buf,
2093 MLX4_CMD_MAD_DEMUX_TRAP_REPRESS_ATTR_OFFSET);
2094 mlx4_dbg(dev, "SMP firewall traprepress_attribute_mask = 0x%x\n",
2095 traprepress_attr_mask);
2096
2097 if (set_attr_mask && getresp_attr_mask && trap_attr_mask &&
2098 traprepress_attr_mask)
2099 return 1;
2100
2101 return 0;
2102 }
2103
2104 int mlx4_config_mad_demux(struct mlx4_dev *dev)
2105 {
2106 struct mlx4_cmd_mailbox *mailbox;
2107 int secure_host_active;
2108 int err;
2109
2110 /* Check if mad_demux is supported */
2111 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_MAD_DEMUX))
2112 return 0;
2113
2114 mailbox = mlx4_alloc_cmd_mailbox(dev);
2115 if (IS_ERR(mailbox)) {
2116 mlx4_warn(dev, "Failed to allocate mailbox for cmd MAD_DEMUX");
2117 return -ENOMEM;
2118 }
2119
2120 /* Query mad_demux to find out which MADs are handled by internal sma */
2121 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0x01 /* subn mgmt class */,
2122 MLX4_CMD_MAD_DEMUX_QUERY_RESTR, MLX4_CMD_MAD_DEMUX,
2123 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
2124 if (err) {
2125 mlx4_warn(dev, "MLX4_CMD_MAD_DEMUX: query restrictions failed (%d)\n",
2126 err);
2127 goto out;
2128 }
2129
2130 secure_host_active = mlx4_check_smp_firewall_active(dev, mailbox);
2131
2132 /* Config mad_demux to handle all MADs returned by the query above */
2133 err = mlx4_cmd(dev, mailbox->dma, 0x01 /* subn mgmt class */,
2134 MLX4_CMD_MAD_DEMUX_CONFIG, MLX4_CMD_MAD_DEMUX,
2135 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
2136 if (err) {
2137 mlx4_warn(dev, "MLX4_CMD_MAD_DEMUX: configure failed (%d)\n", err);
2138 goto out;
2139 }
2140
2141 if (secure_host_active)
2142 mlx4_warn(dev, "HCA operating in secure-host mode. SMP firewall activated.\n");
2143 out:
2144 mlx4_free_cmd_mailbox(dev, mailbox);
2145 return err;
2146 }
Linux kernel - Deliverables
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