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mlx4: Put physical GID and P_Key table sizes in mlx4_phys_caps struct and paravirtual...
[deliverable/linux.git] / drivers / net / ethernet / mellanox / mlx4 / fw.c
1 /*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35 #include <linux/etherdevice.h>
36 #include <linux/mlx4/cmd.h>
37 #include <linux/module.h>
38 #include <linux/cache.h>
39
40 #include "fw.h"
41 #include "icm.h"
42
43 enum {
44 MLX4_COMMAND_INTERFACE_MIN_REV = 2,
45 MLX4_COMMAND_INTERFACE_MAX_REV = 3,
46 MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS = 3,
47 };
48
49 extern void __buggy_use_of_MLX4_GET(void);
50 extern void __buggy_use_of_MLX4_PUT(void);
51
52 static bool enable_qos;
53 module_param(enable_qos, bool, 0444);
54 MODULE_PARM_DESC(enable_qos, "Enable Quality of Service support in the HCA (default: off)");
55
56 #define MLX4_GET(dest, source, offset) \
57 do { \
58 void *__p = (char *) (source) + (offset); \
59 switch (sizeof (dest)) { \
60 case 1: (dest) = *(u8 *) __p; break; \
61 case 2: (dest) = be16_to_cpup(__p); break; \
62 case 4: (dest) = be32_to_cpup(__p); break; \
63 case 8: (dest) = be64_to_cpup(__p); break; \
64 default: __buggy_use_of_MLX4_GET(); \
65 } \
66 } while (0)
67
68 #define MLX4_PUT(dest, source, offset) \
69 do { \
70 void *__d = ((char *) (dest) + (offset)); \
71 switch (sizeof(source)) { \
72 case 1: *(u8 *) __d = (source); break; \
73 case 2: *(__be16 *) __d = cpu_to_be16(source); break; \
74 case 4: *(__be32 *) __d = cpu_to_be32(source); break; \
75 case 8: *(__be64 *) __d = cpu_to_be64(source); break; \
76 default: __buggy_use_of_MLX4_PUT(); \
77 } \
78 } while (0)
79
80 static void dump_dev_cap_flags(struct mlx4_dev *dev, u64 flags)
81 {
82 static const char *fname[] = {
83 [ 0] = "RC transport",
84 [ 1] = "UC transport",
85 [ 2] = "UD transport",
86 [ 3] = "XRC transport",
87 [ 4] = "reliable multicast",
88 [ 5] = "FCoIB support",
89 [ 6] = "SRQ support",
90 [ 7] = "IPoIB checksum offload",
91 [ 8] = "P_Key violation counter",
92 [ 9] = "Q_Key violation counter",
93 [10] = "VMM",
94 [12] = "DPDP",
95 [15] = "Big LSO headers",
96 [16] = "MW support",
97 [17] = "APM support",
98 [18] = "Atomic ops support",
99 [19] = "Raw multicast support",
100 [20] = "Address vector port checking support",
101 [21] = "UD multicast support",
102 [24] = "Demand paging support",
103 [25] = "Router support",
104 [30] = "IBoE support",
105 [32] = "Unicast loopback support",
106 [34] = "FCS header control",
107 [38] = "Wake On LAN support",
108 [40] = "UDP RSS support",
109 [41] = "Unicast VEP steering support",
110 [42] = "Multicast VEP steering support",
111 [48] = "Counters support",
112 [59] = "Port management change event support",
113 };
114 int i;
115
116 mlx4_dbg(dev, "DEV_CAP flags:\n");
117 for (i = 0; i < ARRAY_SIZE(fname); ++i)
118 if (fname[i] && (flags & (1LL << i)))
119 mlx4_dbg(dev, " %s\n", fname[i]);
120 }
121
122 static void dump_dev_cap_flags2(struct mlx4_dev *dev, u64 flags)
123 {
124 static const char * const fname[] = {
125 [0] = "RSS support",
126 [1] = "RSS Toeplitz Hash Function support",
127 [2] = "RSS XOR Hash Function support"
128 };
129 int i;
130
131 for (i = 0; i < ARRAY_SIZE(fname); ++i)
132 if (fname[i] && (flags & (1LL << i)))
133 mlx4_dbg(dev, " %s\n", fname[i]);
134 }
135
136 int mlx4_MOD_STAT_CFG(struct mlx4_dev *dev, struct mlx4_mod_stat_cfg *cfg)
137 {
138 struct mlx4_cmd_mailbox *mailbox;
139 u32 *inbox;
140 int err = 0;
141
142 #define MOD_STAT_CFG_IN_SIZE 0x100
143
144 #define MOD_STAT_CFG_PG_SZ_M_OFFSET 0x002
145 #define MOD_STAT_CFG_PG_SZ_OFFSET 0x003
146
147 mailbox = mlx4_alloc_cmd_mailbox(dev);
148 if (IS_ERR(mailbox))
149 return PTR_ERR(mailbox);
150 inbox = mailbox->buf;
151
152 memset(inbox, 0, MOD_STAT_CFG_IN_SIZE);
153
154 MLX4_PUT(inbox, cfg->log_pg_sz, MOD_STAT_CFG_PG_SZ_OFFSET);
155 MLX4_PUT(inbox, cfg->log_pg_sz_m, MOD_STAT_CFG_PG_SZ_M_OFFSET);
156
157 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_MOD_STAT_CFG,
158 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
159
160 mlx4_free_cmd_mailbox(dev, mailbox);
161 return err;
162 }
163
164 int mlx4_QUERY_FUNC_CAP_wrapper(struct mlx4_dev *dev, int slave,
165 struct mlx4_vhcr *vhcr,
166 struct mlx4_cmd_mailbox *inbox,
167 struct mlx4_cmd_mailbox *outbox,
168 struct mlx4_cmd_info *cmd)
169 {
170 u8 field;
171 u32 size;
172 int err = 0;
173
174 #define QUERY_FUNC_CAP_FLAGS_OFFSET 0x0
175 #define QUERY_FUNC_CAP_NUM_PORTS_OFFSET 0x1
176 #define QUERY_FUNC_CAP_PF_BHVR_OFFSET 0x4
177 #define QUERY_FUNC_CAP_FMR_OFFSET 0x8
178 #define QUERY_FUNC_CAP_QP_QUOTA_OFFSET 0x10
179 #define QUERY_FUNC_CAP_CQ_QUOTA_OFFSET 0x14
180 #define QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET 0x18
181 #define QUERY_FUNC_CAP_MPT_QUOTA_OFFSET 0x20
182 #define QUERY_FUNC_CAP_MTT_QUOTA_OFFSET 0x24
183 #define QUERY_FUNC_CAP_MCG_QUOTA_OFFSET 0x28
184 #define QUERY_FUNC_CAP_MAX_EQ_OFFSET 0x2c
185 #define QUERY_FUNC_CAP_RESERVED_EQ_OFFSET 0X30
186
187 #define QUERY_FUNC_CAP_FMR_FLAG 0x80
188 #define QUERY_FUNC_CAP_FLAG_RDMA 0x40
189 #define QUERY_FUNC_CAP_FLAG_ETH 0x80
190
191 /* when opcode modifier = 1 */
192 #define QUERY_FUNC_CAP_PHYS_PORT_OFFSET 0x3
193 #define QUERY_FUNC_CAP_RDMA_PROPS_OFFSET 0x8
194 #define QUERY_FUNC_CAP_ETH_PROPS_OFFSET 0xc
195
196 #define QUERY_FUNC_CAP_ETH_PROPS_FORCE_MAC 0x40
197 #define QUERY_FUNC_CAP_ETH_PROPS_FORCE_VLAN 0x80
198
199 #define QUERY_FUNC_CAP_RDMA_PROPS_FORCE_PHY_WQE_GID 0x80
200
201 if (vhcr->op_modifier == 1) {
202 field = vhcr->in_modifier;
203 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_PHYS_PORT_OFFSET);
204
205 field = 0;
206 /* ensure force vlan and force mac bits are not set */
207 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_ETH_PROPS_OFFSET);
208 /* ensure that phy_wqe_gid bit is not set */
209 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_RDMA_PROPS_OFFSET);
210
211 } else if (vhcr->op_modifier == 0) {
212 /* enable rdma and ethernet interfaces */
213 field = (QUERY_FUNC_CAP_FLAG_ETH | QUERY_FUNC_CAP_FLAG_RDMA);
214 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FLAGS_OFFSET);
215
216 field = dev->caps.num_ports;
217 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_NUM_PORTS_OFFSET);
218
219 size = 0; /* no PF behaviour is set for now */
220 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_PF_BHVR_OFFSET);
221
222 field = 0; /* protected FMR support not available as yet */
223 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FMR_OFFSET);
224
225 size = dev->caps.num_qps;
226 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP_QUOTA_OFFSET);
227
228 size = dev->caps.num_srqs;
229 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET);
230
231 size = dev->caps.num_cqs;
232 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET);
233
234 size = dev->caps.num_eqs;
235 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MAX_EQ_OFFSET);
236
237 size = dev->caps.reserved_eqs;
238 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET);
239
240 size = dev->caps.num_mpts;
241 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET);
242
243 size = dev->caps.num_mtts;
244 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET);
245
246 size = dev->caps.num_mgms + dev->caps.num_amgms;
247 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET);
248
249 } else
250 err = -EINVAL;
251
252 return err;
253 }
254
255 int mlx4_QUERY_FUNC_CAP(struct mlx4_dev *dev, struct mlx4_func_cap *func_cap)
256 {
257 struct mlx4_cmd_mailbox *mailbox;
258 u32 *outbox;
259 u8 field;
260 u32 size;
261 int i;
262 int err = 0;
263
264
265 mailbox = mlx4_alloc_cmd_mailbox(dev);
266 if (IS_ERR(mailbox))
267 return PTR_ERR(mailbox);
268
269 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_FUNC_CAP,
270 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
271 if (err)
272 goto out;
273
274 outbox = mailbox->buf;
275
276 MLX4_GET(field, outbox, QUERY_FUNC_CAP_FLAGS_OFFSET);
277 if (!(field & (QUERY_FUNC_CAP_FLAG_ETH | QUERY_FUNC_CAP_FLAG_RDMA))) {
278 mlx4_err(dev, "The host supports neither eth nor rdma interfaces\n");
279 err = -EPROTONOSUPPORT;
280 goto out;
281 }
282 func_cap->flags = field;
283
284 MLX4_GET(field, outbox, QUERY_FUNC_CAP_NUM_PORTS_OFFSET);
285 func_cap->num_ports = field;
286
287 MLX4_GET(size, outbox, QUERY_FUNC_CAP_PF_BHVR_OFFSET);
288 func_cap->pf_context_behaviour = size;
289
290 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP_QUOTA_OFFSET);
291 func_cap->qp_quota = size & 0xFFFFFF;
292
293 MLX4_GET(size, outbox, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET);
294 func_cap->srq_quota = size & 0xFFFFFF;
295
296 MLX4_GET(size, outbox, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET);
297 func_cap->cq_quota = size & 0xFFFFFF;
298
299 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MAX_EQ_OFFSET);
300 func_cap->max_eq = size & 0xFFFFFF;
301
302 MLX4_GET(size, outbox, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET);
303 func_cap->reserved_eq = size & 0xFFFFFF;
304
305 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET);
306 func_cap->mpt_quota = size & 0xFFFFFF;
307
308 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET);
309 func_cap->mtt_quota = size & 0xFFFFFF;
310
311 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET);
312 func_cap->mcg_quota = size & 0xFFFFFF;
313
314 for (i = 1; i <= func_cap->num_ports; ++i) {
315 err = mlx4_cmd_box(dev, 0, mailbox->dma, i, 1,
316 MLX4_CMD_QUERY_FUNC_CAP,
317 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
318 if (err)
319 goto out;
320
321 if (dev->caps.port_type[i] == MLX4_PORT_TYPE_ETH) {
322 MLX4_GET(field, outbox, QUERY_FUNC_CAP_ETH_PROPS_OFFSET);
323 if (field & QUERY_FUNC_CAP_ETH_PROPS_FORCE_VLAN) {
324 mlx4_err(dev, "VLAN is enforced on this port\n");
325 err = -EPROTONOSUPPORT;
326 goto out;
327 }
328
329 if (field & QUERY_FUNC_CAP_ETH_PROPS_FORCE_MAC) {
330 mlx4_err(dev, "Force mac is enabled on this port\n");
331 err = -EPROTONOSUPPORT;
332 goto out;
333 }
334 } else if (dev->caps.port_type[i] == MLX4_PORT_TYPE_IB) {
335 MLX4_GET(field, outbox, QUERY_FUNC_CAP_RDMA_PROPS_OFFSET);
336 if (field & QUERY_FUNC_CAP_RDMA_PROPS_FORCE_PHY_WQE_GID) {
337 mlx4_err(dev, "phy_wqe_gid is "
338 "enforced on this ib port\n");
339 err = -EPROTONOSUPPORT;
340 goto out;
341 }
342 }
343
344 MLX4_GET(field, outbox, QUERY_FUNC_CAP_PHYS_PORT_OFFSET);
345 func_cap->physical_port[i] = field;
346 }
347
348 /* All other resources are allocated by the master, but we still report
349 * 'num' and 'reserved' capabilities as follows:
350 * - num remains the maximum resource index
351 * - 'num - reserved' is the total available objects of a resource, but
352 * resource indices may be less than 'reserved'
353 * TODO: set per-resource quotas */
354
355 out:
356 mlx4_free_cmd_mailbox(dev, mailbox);
357
358 return err;
359 }
360
361 int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
362 {
363 struct mlx4_cmd_mailbox *mailbox;
364 u32 *outbox;
365 u8 field;
366 u32 field32, flags, ext_flags;
367 u16 size;
368 u16 stat_rate;
369 int err;
370 int i;
371
372 #define QUERY_DEV_CAP_OUT_SIZE 0x100
373 #define QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET 0x10
374 #define QUERY_DEV_CAP_MAX_QP_SZ_OFFSET 0x11
375 #define QUERY_DEV_CAP_RSVD_QP_OFFSET 0x12
376 #define QUERY_DEV_CAP_MAX_QP_OFFSET 0x13
377 #define QUERY_DEV_CAP_RSVD_SRQ_OFFSET 0x14
378 #define QUERY_DEV_CAP_MAX_SRQ_OFFSET 0x15
379 #define QUERY_DEV_CAP_RSVD_EEC_OFFSET 0x16
380 #define QUERY_DEV_CAP_MAX_EEC_OFFSET 0x17
381 #define QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET 0x19
382 #define QUERY_DEV_CAP_RSVD_CQ_OFFSET 0x1a
383 #define QUERY_DEV_CAP_MAX_CQ_OFFSET 0x1b
384 #define QUERY_DEV_CAP_MAX_MPT_OFFSET 0x1d
385 #define QUERY_DEV_CAP_RSVD_EQ_OFFSET 0x1e
386 #define QUERY_DEV_CAP_MAX_EQ_OFFSET 0x1f
387 #define QUERY_DEV_CAP_RSVD_MTT_OFFSET 0x20
388 #define QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET 0x21
389 #define QUERY_DEV_CAP_RSVD_MRW_OFFSET 0x22
390 #define QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET 0x23
391 #define QUERY_DEV_CAP_MAX_AV_OFFSET 0x27
392 #define QUERY_DEV_CAP_MAX_REQ_QP_OFFSET 0x29
393 #define QUERY_DEV_CAP_MAX_RES_QP_OFFSET 0x2b
394 #define QUERY_DEV_CAP_MAX_GSO_OFFSET 0x2d
395 #define QUERY_DEV_CAP_RSS_OFFSET 0x2e
396 #define QUERY_DEV_CAP_MAX_RDMA_OFFSET 0x2f
397 #define QUERY_DEV_CAP_RSZ_SRQ_OFFSET 0x33
398 #define QUERY_DEV_CAP_ACK_DELAY_OFFSET 0x35
399 #define QUERY_DEV_CAP_MTU_WIDTH_OFFSET 0x36
400 #define QUERY_DEV_CAP_VL_PORT_OFFSET 0x37
401 #define QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET 0x38
402 #define QUERY_DEV_CAP_MAX_GID_OFFSET 0x3b
403 #define QUERY_DEV_CAP_RATE_SUPPORT_OFFSET 0x3c
404 #define QUERY_DEV_CAP_MAX_PKEY_OFFSET 0x3f
405 #define QUERY_DEV_CAP_EXT_FLAGS_OFFSET 0x40
406 #define QUERY_DEV_CAP_FLAGS_OFFSET 0x44
407 #define QUERY_DEV_CAP_RSVD_UAR_OFFSET 0x48
408 #define QUERY_DEV_CAP_UAR_SZ_OFFSET 0x49
409 #define QUERY_DEV_CAP_PAGE_SZ_OFFSET 0x4b
410 #define QUERY_DEV_CAP_BF_OFFSET 0x4c
411 #define QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET 0x4d
412 #define QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET 0x4e
413 #define QUERY_DEV_CAP_LOG_MAX_BF_PAGES_OFFSET 0x4f
414 #define QUERY_DEV_CAP_MAX_SG_SQ_OFFSET 0x51
415 #define QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET 0x52
416 #define QUERY_DEV_CAP_MAX_SG_RQ_OFFSET 0x55
417 #define QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET 0x56
418 #define QUERY_DEV_CAP_MAX_QP_MCG_OFFSET 0x61
419 #define QUERY_DEV_CAP_RSVD_MCG_OFFSET 0x62
420 #define QUERY_DEV_CAP_MAX_MCG_OFFSET 0x63
421 #define QUERY_DEV_CAP_RSVD_PD_OFFSET 0x64
422 #define QUERY_DEV_CAP_MAX_PD_OFFSET 0x65
423 #define QUERY_DEV_CAP_RSVD_XRC_OFFSET 0x66
424 #define QUERY_DEV_CAP_MAX_XRC_OFFSET 0x67
425 #define QUERY_DEV_CAP_MAX_COUNTERS_OFFSET 0x68
426 #define QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET 0x80
427 #define QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET 0x82
428 #define QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET 0x84
429 #define QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET 0x86
430 #define QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET 0x88
431 #define QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET 0x8a
432 #define QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET 0x8c
433 #define QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET 0x8e
434 #define QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET 0x90
435 #define QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET 0x92
436 #define QUERY_DEV_CAP_BMME_FLAGS_OFFSET 0x94
437 #define QUERY_DEV_CAP_RSVD_LKEY_OFFSET 0x98
438 #define QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET 0xa0
439
440 dev_cap->flags2 = 0;
441 mailbox = mlx4_alloc_cmd_mailbox(dev);
442 if (IS_ERR(mailbox))
443 return PTR_ERR(mailbox);
444 outbox = mailbox->buf;
445
446 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP,
447 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
448 if (err)
449 goto out;
450
451 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_QP_OFFSET);
452 dev_cap->reserved_qps = 1 << (field & 0xf);
453 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_OFFSET);
454 dev_cap->max_qps = 1 << (field & 0x1f);
455 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_SRQ_OFFSET);
456 dev_cap->reserved_srqs = 1 << (field >> 4);
457 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_OFFSET);
458 dev_cap->max_srqs = 1 << (field & 0x1f);
459 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET);
460 dev_cap->max_cq_sz = 1 << field;
461 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_CQ_OFFSET);
462 dev_cap->reserved_cqs = 1 << (field & 0xf);
463 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_OFFSET);
464 dev_cap->max_cqs = 1 << (field & 0x1f);
465 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MPT_OFFSET);
466 dev_cap->max_mpts = 1 << (field & 0x3f);
467 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_EQ_OFFSET);
468 dev_cap->reserved_eqs = field & 0xf;
469 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_EQ_OFFSET);
470 dev_cap->max_eqs = 1 << (field & 0xf);
471 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MTT_OFFSET);
472 dev_cap->reserved_mtts = 1 << (field >> 4);
473 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET);
474 dev_cap->max_mrw_sz = 1 << field;
475 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MRW_OFFSET);
476 dev_cap->reserved_mrws = 1 << (field & 0xf);
477 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET);
478 dev_cap->max_mtt_seg = 1 << (field & 0x3f);
479 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_REQ_QP_OFFSET);
480 dev_cap->max_requester_per_qp = 1 << (field & 0x3f);
481 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RES_QP_OFFSET);
482 dev_cap->max_responder_per_qp = 1 << (field & 0x3f);
483 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GSO_OFFSET);
484 field &= 0x1f;
485 if (!field)
486 dev_cap->max_gso_sz = 0;
487 else
488 dev_cap->max_gso_sz = 1 << field;
489
490 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSS_OFFSET);
491 if (field & 0x20)
492 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_XOR;
493 if (field & 0x10)
494 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_TOP;
495 field &= 0xf;
496 if (field) {
497 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS;
498 dev_cap->max_rss_tbl_sz = 1 << field;
499 } else
500 dev_cap->max_rss_tbl_sz = 0;
501 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RDMA_OFFSET);
502 dev_cap->max_rdma_global = 1 << (field & 0x3f);
503 MLX4_GET(field, outbox, QUERY_DEV_CAP_ACK_DELAY_OFFSET);
504 dev_cap->local_ca_ack_delay = field & 0x1f;
505 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET);
506 dev_cap->num_ports = field & 0xf;
507 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET);
508 dev_cap->max_msg_sz = 1 << (field & 0x1f);
509 MLX4_GET(stat_rate, outbox, QUERY_DEV_CAP_RATE_SUPPORT_OFFSET);
510 dev_cap->stat_rate_support = stat_rate;
511 MLX4_GET(ext_flags, outbox, QUERY_DEV_CAP_EXT_FLAGS_OFFSET);
512 MLX4_GET(flags, outbox, QUERY_DEV_CAP_FLAGS_OFFSET);
513 dev_cap->flags = flags | (u64)ext_flags << 32;
514 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_UAR_OFFSET);
515 dev_cap->reserved_uars = field >> 4;
516 MLX4_GET(field, outbox, QUERY_DEV_CAP_UAR_SZ_OFFSET);
517 dev_cap->uar_size = 1 << ((field & 0x3f) + 20);
518 MLX4_GET(field, outbox, QUERY_DEV_CAP_PAGE_SZ_OFFSET);
519 dev_cap->min_page_sz = 1 << field;
520
521 MLX4_GET(field, outbox, QUERY_DEV_CAP_BF_OFFSET);
522 if (field & 0x80) {
523 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET);
524 dev_cap->bf_reg_size = 1 << (field & 0x1f);
525 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET);
526 if ((1 << (field & 0x3f)) > (PAGE_SIZE / dev_cap->bf_reg_size))
527 field = 3;
528 dev_cap->bf_regs_per_page = 1 << (field & 0x3f);
529 mlx4_dbg(dev, "BlueFlame available (reg size %d, regs/page %d)\n",
530 dev_cap->bf_reg_size, dev_cap->bf_regs_per_page);
531 } else {
532 dev_cap->bf_reg_size = 0;
533 mlx4_dbg(dev, "BlueFlame not available\n");
534 }
535
536 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_SQ_OFFSET);
537 dev_cap->max_sq_sg = field;
538 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET);
539 dev_cap->max_sq_desc_sz = size;
540
541 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_MCG_OFFSET);
542 dev_cap->max_qp_per_mcg = 1 << field;
543 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MCG_OFFSET);
544 dev_cap->reserved_mgms = field & 0xf;
545 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MCG_OFFSET);
546 dev_cap->max_mcgs = 1 << field;
547 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_PD_OFFSET);
548 dev_cap->reserved_pds = field >> 4;
549 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PD_OFFSET);
550 dev_cap->max_pds = 1 << (field & 0x3f);
551 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_XRC_OFFSET);
552 dev_cap->reserved_xrcds = field >> 4;
553 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PD_OFFSET);
554 dev_cap->max_xrcds = 1 << (field & 0x1f);
555
556 MLX4_GET(size, outbox, QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET);
557 dev_cap->rdmarc_entry_sz = size;
558 MLX4_GET(size, outbox, QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET);
559 dev_cap->qpc_entry_sz = size;
560 MLX4_GET(size, outbox, QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET);
561 dev_cap->aux_entry_sz = size;
562 MLX4_GET(size, outbox, QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET);
563 dev_cap->altc_entry_sz = size;
564 MLX4_GET(size, outbox, QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET);
565 dev_cap->eqc_entry_sz = size;
566 MLX4_GET(size, outbox, QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET);
567 dev_cap->cqc_entry_sz = size;
568 MLX4_GET(size, outbox, QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET);
569 dev_cap->srq_entry_sz = size;
570 MLX4_GET(size, outbox, QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET);
571 dev_cap->cmpt_entry_sz = size;
572 MLX4_GET(size, outbox, QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET);
573 dev_cap->mtt_entry_sz = size;
574 MLX4_GET(size, outbox, QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET);
575 dev_cap->dmpt_entry_sz = size;
576
577 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET);
578 dev_cap->max_srq_sz = 1 << field;
579 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_SZ_OFFSET);
580 dev_cap->max_qp_sz = 1 << field;
581 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSZ_SRQ_OFFSET);
582 dev_cap->resize_srq = field & 1;
583 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_RQ_OFFSET);
584 dev_cap->max_rq_sg = field;
585 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET);
586 dev_cap->max_rq_desc_sz = size;
587
588 MLX4_GET(dev_cap->bmme_flags, outbox,
589 QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
590 MLX4_GET(dev_cap->reserved_lkey, outbox,
591 QUERY_DEV_CAP_RSVD_LKEY_OFFSET);
592 MLX4_GET(dev_cap->max_icm_sz, outbox,
593 QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET);
594 if (dev_cap->flags & MLX4_DEV_CAP_FLAG_COUNTERS)
595 MLX4_GET(dev_cap->max_counters, outbox,
596 QUERY_DEV_CAP_MAX_COUNTERS_OFFSET);
597
598 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
599 for (i = 1; i <= dev_cap->num_ports; ++i) {
600 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET);
601 dev_cap->max_vl[i] = field >> 4;
602 MLX4_GET(field, outbox, QUERY_DEV_CAP_MTU_WIDTH_OFFSET);
603 dev_cap->ib_mtu[i] = field >> 4;
604 dev_cap->max_port_width[i] = field & 0xf;
605 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GID_OFFSET);
606 dev_cap->max_gids[i] = 1 << (field & 0xf);
607 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PKEY_OFFSET);
608 dev_cap->max_pkeys[i] = 1 << (field & 0xf);
609 }
610 } else {
611 #define QUERY_PORT_SUPPORTED_TYPE_OFFSET 0x00
612 #define QUERY_PORT_MTU_OFFSET 0x01
613 #define QUERY_PORT_ETH_MTU_OFFSET 0x02
614 #define QUERY_PORT_WIDTH_OFFSET 0x06
615 #define QUERY_PORT_MAX_GID_PKEY_OFFSET 0x07
616 #define QUERY_PORT_MAX_MACVLAN_OFFSET 0x0a
617 #define QUERY_PORT_MAX_VL_OFFSET 0x0b
618 #define QUERY_PORT_MAC_OFFSET 0x10
619 #define QUERY_PORT_TRANS_VENDOR_OFFSET 0x18
620 #define QUERY_PORT_WAVELENGTH_OFFSET 0x1c
621 #define QUERY_PORT_TRANS_CODE_OFFSET 0x20
622
623 for (i = 1; i <= dev_cap->num_ports; ++i) {
624 err = mlx4_cmd_box(dev, 0, mailbox->dma, i, 0, MLX4_CMD_QUERY_PORT,
625 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
626 if (err)
627 goto out;
628
629 MLX4_GET(field, outbox, QUERY_PORT_SUPPORTED_TYPE_OFFSET);
630 dev_cap->supported_port_types[i] = field & 3;
631 dev_cap->suggested_type[i] = (field >> 3) & 1;
632 dev_cap->default_sense[i] = (field >> 4) & 1;
633 MLX4_GET(field, outbox, QUERY_PORT_MTU_OFFSET);
634 dev_cap->ib_mtu[i] = field & 0xf;
635 MLX4_GET(field, outbox, QUERY_PORT_WIDTH_OFFSET);
636 dev_cap->max_port_width[i] = field & 0xf;
637 MLX4_GET(field, outbox, QUERY_PORT_MAX_GID_PKEY_OFFSET);
638 dev_cap->max_gids[i] = 1 << (field >> 4);
639 dev_cap->max_pkeys[i] = 1 << (field & 0xf);
640 MLX4_GET(field, outbox, QUERY_PORT_MAX_VL_OFFSET);
641 dev_cap->max_vl[i] = field & 0xf;
642 MLX4_GET(field, outbox, QUERY_PORT_MAX_MACVLAN_OFFSET);
643 dev_cap->log_max_macs[i] = field & 0xf;
644 dev_cap->log_max_vlans[i] = field >> 4;
645 MLX4_GET(dev_cap->eth_mtu[i], outbox, QUERY_PORT_ETH_MTU_OFFSET);
646 MLX4_GET(dev_cap->def_mac[i], outbox, QUERY_PORT_MAC_OFFSET);
647 MLX4_GET(field32, outbox, QUERY_PORT_TRANS_VENDOR_OFFSET);
648 dev_cap->trans_type[i] = field32 >> 24;
649 dev_cap->vendor_oui[i] = field32 & 0xffffff;
650 MLX4_GET(dev_cap->wavelength[i], outbox, QUERY_PORT_WAVELENGTH_OFFSET);
651 MLX4_GET(dev_cap->trans_code[i], outbox, QUERY_PORT_TRANS_CODE_OFFSET);
652 }
653 }
654
655 mlx4_dbg(dev, "Base MM extensions: flags %08x, rsvd L_Key %08x\n",
656 dev_cap->bmme_flags, dev_cap->reserved_lkey);
657
658 /*
659 * Each UAR has 4 EQ doorbells; so if a UAR is reserved, then
660 * we can't use any EQs whose doorbell falls on that page,
661 * even if the EQ itself isn't reserved.
662 */
663 dev_cap->reserved_eqs = max(dev_cap->reserved_uars * 4,
664 dev_cap->reserved_eqs);
665
666 mlx4_dbg(dev, "Max ICM size %lld MB\n",
667 (unsigned long long) dev_cap->max_icm_sz >> 20);
668 mlx4_dbg(dev, "Max QPs: %d, reserved QPs: %d, entry size: %d\n",
669 dev_cap->max_qps, dev_cap->reserved_qps, dev_cap->qpc_entry_sz);
670 mlx4_dbg(dev, "Max SRQs: %d, reserved SRQs: %d, entry size: %d\n",
671 dev_cap->max_srqs, dev_cap->reserved_srqs, dev_cap->srq_entry_sz);
672 mlx4_dbg(dev, "Max CQs: %d, reserved CQs: %d, entry size: %d\n",
673 dev_cap->max_cqs, dev_cap->reserved_cqs, dev_cap->cqc_entry_sz);
674 mlx4_dbg(dev, "Max EQs: %d, reserved EQs: %d, entry size: %d\n",
675 dev_cap->max_eqs, dev_cap->reserved_eqs, dev_cap->eqc_entry_sz);
676 mlx4_dbg(dev, "reserved MPTs: %d, reserved MTTs: %d\n",
677 dev_cap->reserved_mrws, dev_cap->reserved_mtts);
678 mlx4_dbg(dev, "Max PDs: %d, reserved PDs: %d, reserved UARs: %d\n",
679 dev_cap->max_pds, dev_cap->reserved_pds, dev_cap->reserved_uars);
680 mlx4_dbg(dev, "Max QP/MCG: %d, reserved MGMs: %d\n",
681 dev_cap->max_pds, dev_cap->reserved_mgms);
682 mlx4_dbg(dev, "Max CQEs: %d, max WQEs: %d, max SRQ WQEs: %d\n",
683 dev_cap->max_cq_sz, dev_cap->max_qp_sz, dev_cap->max_srq_sz);
684 mlx4_dbg(dev, "Local CA ACK delay: %d, max MTU: %d, port width cap: %d\n",
685 dev_cap->local_ca_ack_delay, 128 << dev_cap->ib_mtu[1],
686 dev_cap->max_port_width[1]);
687 mlx4_dbg(dev, "Max SQ desc size: %d, max SQ S/G: %d\n",
688 dev_cap->max_sq_desc_sz, dev_cap->max_sq_sg);
689 mlx4_dbg(dev, "Max RQ desc size: %d, max RQ S/G: %d\n",
690 dev_cap->max_rq_desc_sz, dev_cap->max_rq_sg);
691 mlx4_dbg(dev, "Max GSO size: %d\n", dev_cap->max_gso_sz);
692 mlx4_dbg(dev, "Max counters: %d\n", dev_cap->max_counters);
693 mlx4_dbg(dev, "Max RSS Table size: %d\n", dev_cap->max_rss_tbl_sz);
694
695 dump_dev_cap_flags(dev, dev_cap->flags);
696 dump_dev_cap_flags2(dev, dev_cap->flags2);
697
698 out:
699 mlx4_free_cmd_mailbox(dev, mailbox);
700 return err;
701 }
702
703 int mlx4_QUERY_DEV_CAP_wrapper(struct mlx4_dev *dev, int slave,
704 struct mlx4_vhcr *vhcr,
705 struct mlx4_cmd_mailbox *inbox,
706 struct mlx4_cmd_mailbox *outbox,
707 struct mlx4_cmd_info *cmd)
708 {
709 int err = 0;
710 u8 field;
711
712 err = mlx4_cmd_box(dev, 0, outbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP,
713 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
714 if (err)
715 return err;
716
717 /* For guests, report Blueflame disabled */
718 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_BF_OFFSET);
719 field &= 0x7f;
720 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_BF_OFFSET);
721
722 return 0;
723 }
724
725 int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave,
726 struct mlx4_vhcr *vhcr,
727 struct mlx4_cmd_mailbox *inbox,
728 struct mlx4_cmd_mailbox *outbox,
729 struct mlx4_cmd_info *cmd)
730 {
731 u64 def_mac;
732 u8 port_type;
733 u16 short_field;
734 int err;
735
736 #define MLX4_VF_PORT_NO_LINK_SENSE_MASK 0xE0
737 #define QUERY_PORT_CUR_MAX_PKEY_OFFSET 0x0c
738 #define QUERY_PORT_CUR_MAX_GID_OFFSET 0x0e
739
740 err = mlx4_cmd_box(dev, 0, outbox->dma, vhcr->in_modifier, 0,
741 MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B,
742 MLX4_CMD_NATIVE);
743
744 if (!err && dev->caps.function != slave) {
745 /* set slave default_mac address */
746 MLX4_GET(def_mac, outbox->buf, QUERY_PORT_MAC_OFFSET);
747 def_mac += slave << 8;
748 MLX4_PUT(outbox->buf, def_mac, QUERY_PORT_MAC_OFFSET);
749
750 /* get port type - currently only eth is enabled */
751 MLX4_GET(port_type, outbox->buf,
752 QUERY_PORT_SUPPORTED_TYPE_OFFSET);
753
754 /* No link sensing allowed */
755 port_type &= MLX4_VF_PORT_NO_LINK_SENSE_MASK;
756 /* set port type to currently operating port type */
757 port_type |= (dev->caps.port_type[vhcr->in_modifier] & 0x3);
758
759 MLX4_PUT(outbox->buf, port_type,
760 QUERY_PORT_SUPPORTED_TYPE_OFFSET);
761
762 short_field = 1; /* slave max gids */
763 MLX4_PUT(outbox->buf, short_field,
764 QUERY_PORT_CUR_MAX_GID_OFFSET);
765
766 short_field = dev->caps.pkey_table_len[vhcr->in_modifier];
767 MLX4_PUT(outbox->buf, short_field,
768 QUERY_PORT_CUR_MAX_PKEY_OFFSET);
769 }
770
771 return err;
772 }
773
774 int mlx4_get_slave_pkey_gid_tbl_len(struct mlx4_dev *dev, u8 port,
775 int *gid_tbl_len, int *pkey_tbl_len)
776 {
777 struct mlx4_cmd_mailbox *mailbox;
778 u32 *outbox;
779 u16 field;
780 int err;
781
782 mailbox = mlx4_alloc_cmd_mailbox(dev);
783 if (IS_ERR(mailbox))
784 return PTR_ERR(mailbox);
785
786 err = mlx4_cmd_box(dev, 0, mailbox->dma, port, 0,
787 MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B,
788 MLX4_CMD_WRAPPED);
789 if (err)
790 goto out;
791
792 outbox = mailbox->buf;
793
794 MLX4_GET(field, outbox, QUERY_PORT_CUR_MAX_GID_OFFSET);
795 *gid_tbl_len = field;
796
797 MLX4_GET(field, outbox, QUERY_PORT_CUR_MAX_PKEY_OFFSET);
798 *pkey_tbl_len = field;
799
800 out:
801 mlx4_free_cmd_mailbox(dev, mailbox);
802 return err;
803 }
804 EXPORT_SYMBOL(mlx4_get_slave_pkey_gid_tbl_len);
805
806 int mlx4_map_cmd(struct mlx4_dev *dev, u16 op, struct mlx4_icm *icm, u64 virt)
807 {
808 struct mlx4_cmd_mailbox *mailbox;
809 struct mlx4_icm_iter iter;
810 __be64 *pages;
811 int lg;
812 int nent = 0;
813 int i;
814 int err = 0;
815 int ts = 0, tc = 0;
816
817 mailbox = mlx4_alloc_cmd_mailbox(dev);
818 if (IS_ERR(mailbox))
819 return PTR_ERR(mailbox);
820 memset(mailbox->buf, 0, MLX4_MAILBOX_SIZE);
821 pages = mailbox->buf;
822
823 for (mlx4_icm_first(icm, &iter);
824 !mlx4_icm_last(&iter);
825 mlx4_icm_next(&iter)) {
826 /*
827 * We have to pass pages that are aligned to their
828 * size, so find the least significant 1 in the
829 * address or size and use that as our log2 size.
830 */
831 lg = ffs(mlx4_icm_addr(&iter) | mlx4_icm_size(&iter)) - 1;
832 if (lg < MLX4_ICM_PAGE_SHIFT) {
833 mlx4_warn(dev, "Got FW area not aligned to %d (%llx/%lx).\n",
834 MLX4_ICM_PAGE_SIZE,
835 (unsigned long long) mlx4_icm_addr(&iter),
836 mlx4_icm_size(&iter));
837 err = -EINVAL;
838 goto out;
839 }
840
841 for (i = 0; i < mlx4_icm_size(&iter) >> lg; ++i) {
842 if (virt != -1) {
843 pages[nent * 2] = cpu_to_be64(virt);
844 virt += 1 << lg;
845 }
846
847 pages[nent * 2 + 1] =
848 cpu_to_be64((mlx4_icm_addr(&iter) + (i << lg)) |
849 (lg - MLX4_ICM_PAGE_SHIFT));
850 ts += 1 << (lg - 10);
851 ++tc;
852
853 if (++nent == MLX4_MAILBOX_SIZE / 16) {
854 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op,
855 MLX4_CMD_TIME_CLASS_B,
856 MLX4_CMD_NATIVE);
857 if (err)
858 goto out;
859 nent = 0;
860 }
861 }
862 }
863
864 if (nent)
865 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op,
866 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
867 if (err)
868 goto out;
869
870 switch (op) {
871 case MLX4_CMD_MAP_FA:
872 mlx4_dbg(dev, "Mapped %d chunks/%d KB for FW.\n", tc, ts);
873 break;
874 case MLX4_CMD_MAP_ICM_AUX:
875 mlx4_dbg(dev, "Mapped %d chunks/%d KB for ICM aux.\n", tc, ts);
876 break;
877 case MLX4_CMD_MAP_ICM:
878 mlx4_dbg(dev, "Mapped %d chunks/%d KB at %llx for ICM.\n",
879 tc, ts, (unsigned long long) virt - (ts << 10));
880 break;
881 }
882
883 out:
884 mlx4_free_cmd_mailbox(dev, mailbox);
885 return err;
886 }
887
888 int mlx4_MAP_FA(struct mlx4_dev *dev, struct mlx4_icm *icm)
889 {
890 return mlx4_map_cmd(dev, MLX4_CMD_MAP_FA, icm, -1);
891 }
892
893 int mlx4_UNMAP_FA(struct mlx4_dev *dev)
894 {
895 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_UNMAP_FA,
896 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
897 }
898
899
900 int mlx4_RUN_FW(struct mlx4_dev *dev)
901 {
902 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_RUN_FW,
903 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
904 }
905
906 int mlx4_QUERY_FW(struct mlx4_dev *dev)
907 {
908 struct mlx4_fw *fw = &mlx4_priv(dev)->fw;
909 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
910 struct mlx4_cmd_mailbox *mailbox;
911 u32 *outbox;
912 int err = 0;
913 u64 fw_ver;
914 u16 cmd_if_rev;
915 u8 lg;
916
917 #define QUERY_FW_OUT_SIZE 0x100
918 #define QUERY_FW_VER_OFFSET 0x00
919 #define QUERY_FW_PPF_ID 0x09
920 #define QUERY_FW_CMD_IF_REV_OFFSET 0x0a
921 #define QUERY_FW_MAX_CMD_OFFSET 0x0f
922 #define QUERY_FW_ERR_START_OFFSET 0x30
923 #define QUERY_FW_ERR_SIZE_OFFSET 0x38
924 #define QUERY_FW_ERR_BAR_OFFSET 0x3c
925
926 #define QUERY_FW_SIZE_OFFSET 0x00
927 #define QUERY_FW_CLR_INT_BASE_OFFSET 0x20
928 #define QUERY_FW_CLR_INT_BAR_OFFSET 0x28
929
930 #define QUERY_FW_COMM_BASE_OFFSET 0x40
931 #define QUERY_FW_COMM_BAR_OFFSET 0x48
932
933 mailbox = mlx4_alloc_cmd_mailbox(dev);
934 if (IS_ERR(mailbox))
935 return PTR_ERR(mailbox);
936 outbox = mailbox->buf;
937
938 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_FW,
939 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
940 if (err)
941 goto out;
942
943 MLX4_GET(fw_ver, outbox, QUERY_FW_VER_OFFSET);
944 /*
945 * FW subminor version is at more significant bits than minor
946 * version, so swap here.
947 */
948 dev->caps.fw_ver = (fw_ver & 0xffff00000000ull) |
949 ((fw_ver & 0xffff0000ull) >> 16) |
950 ((fw_ver & 0x0000ffffull) << 16);
951
952 MLX4_GET(lg, outbox, QUERY_FW_PPF_ID);
953 dev->caps.function = lg;
954
955 if (mlx4_is_slave(dev))
956 goto out;
957
958
959 MLX4_GET(cmd_if_rev, outbox, QUERY_FW_CMD_IF_REV_OFFSET);
960 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_MIN_REV ||
961 cmd_if_rev > MLX4_COMMAND_INTERFACE_MAX_REV) {
962 mlx4_err(dev, "Installed FW has unsupported "
963 "command interface revision %d.\n",
964 cmd_if_rev);
965 mlx4_err(dev, "(Installed FW version is %d.%d.%03d)\n",
966 (int) (dev->caps.fw_ver >> 32),
967 (int) (dev->caps.fw_ver >> 16) & 0xffff,
968 (int) dev->caps.fw_ver & 0xffff);
969 mlx4_err(dev, "This driver version supports only revisions %d to %d.\n",
970 MLX4_COMMAND_INTERFACE_MIN_REV, MLX4_COMMAND_INTERFACE_MAX_REV);
971 err = -ENODEV;
972 goto out;
973 }
974
975 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS)
976 dev->flags |= MLX4_FLAG_OLD_PORT_CMDS;
977
978 MLX4_GET(lg, outbox, QUERY_FW_MAX_CMD_OFFSET);
979 cmd->max_cmds = 1 << lg;
980
981 mlx4_dbg(dev, "FW version %d.%d.%03d (cmd intf rev %d), max commands %d\n",
982 (int) (dev->caps.fw_ver >> 32),
983 (int) (dev->caps.fw_ver >> 16) & 0xffff,
984 (int) dev->caps.fw_ver & 0xffff,
985 cmd_if_rev, cmd->max_cmds);
986
987 MLX4_GET(fw->catas_offset, outbox, QUERY_FW_ERR_START_OFFSET);
988 MLX4_GET(fw->catas_size, outbox, QUERY_FW_ERR_SIZE_OFFSET);
989 MLX4_GET(fw->catas_bar, outbox, QUERY_FW_ERR_BAR_OFFSET);
990 fw->catas_bar = (fw->catas_bar >> 6) * 2;
991
992 mlx4_dbg(dev, "Catastrophic error buffer at 0x%llx, size 0x%x, BAR %d\n",
993 (unsigned long long) fw->catas_offset, fw->catas_size, fw->catas_bar);
994
995 MLX4_GET(fw->fw_pages, outbox, QUERY_FW_SIZE_OFFSET);
996 MLX4_GET(fw->clr_int_base, outbox, QUERY_FW_CLR_INT_BASE_OFFSET);
997 MLX4_GET(fw->clr_int_bar, outbox, QUERY_FW_CLR_INT_BAR_OFFSET);
998 fw->clr_int_bar = (fw->clr_int_bar >> 6) * 2;
999
1000 MLX4_GET(fw->comm_base, outbox, QUERY_FW_COMM_BASE_OFFSET);
1001 MLX4_GET(fw->comm_bar, outbox, QUERY_FW_COMM_BAR_OFFSET);
1002 fw->comm_bar = (fw->comm_bar >> 6) * 2;
1003 mlx4_dbg(dev, "Communication vector bar:%d offset:0x%llx\n",
1004 fw->comm_bar, fw->comm_base);
1005 mlx4_dbg(dev, "FW size %d KB\n", fw->fw_pages >> 2);
1006
1007 /*
1008 * Round up number of system pages needed in case
1009 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE.
1010 */
1011 fw->fw_pages =
1012 ALIGN(fw->fw_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >>
1013 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT);
1014
1015 mlx4_dbg(dev, "Clear int @ %llx, BAR %d\n",
1016 (unsigned long long) fw->clr_int_base, fw->clr_int_bar);
1017
1018 out:
1019 mlx4_free_cmd_mailbox(dev, mailbox);
1020 return err;
1021 }
1022
1023 int mlx4_QUERY_FW_wrapper(struct mlx4_dev *dev, int slave,
1024 struct mlx4_vhcr *vhcr,
1025 struct mlx4_cmd_mailbox *inbox,
1026 struct mlx4_cmd_mailbox *outbox,
1027 struct mlx4_cmd_info *cmd)
1028 {
1029 u8 *outbuf;
1030 int err;
1031
1032 outbuf = outbox->buf;
1033 err = mlx4_cmd_box(dev, 0, outbox->dma, 0, 0, MLX4_CMD_QUERY_FW,
1034 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1035 if (err)
1036 return err;
1037
1038 /* for slaves, set pci PPF ID to invalid and zero out everything
1039 * else except FW version */
1040 outbuf[0] = outbuf[1] = 0;
1041 memset(&outbuf[8], 0, QUERY_FW_OUT_SIZE - 8);
1042 outbuf[QUERY_FW_PPF_ID] = MLX4_INVALID_SLAVE_ID;
1043
1044 return 0;
1045 }
1046
1047 static void get_board_id(void *vsd, char *board_id)
1048 {
1049 int i;
1050
1051 #define VSD_OFFSET_SIG1 0x00
1052 #define VSD_OFFSET_SIG2 0xde
1053 #define VSD_OFFSET_MLX_BOARD_ID 0xd0
1054 #define VSD_OFFSET_TS_BOARD_ID 0x20
1055
1056 #define VSD_SIGNATURE_TOPSPIN 0x5ad
1057
1058 memset(board_id, 0, MLX4_BOARD_ID_LEN);
1059
1060 if (be16_to_cpup(vsd + VSD_OFFSET_SIG1) == VSD_SIGNATURE_TOPSPIN &&
1061 be16_to_cpup(vsd + VSD_OFFSET_SIG2) == VSD_SIGNATURE_TOPSPIN) {
1062 strlcpy(board_id, vsd + VSD_OFFSET_TS_BOARD_ID, MLX4_BOARD_ID_LEN);
1063 } else {
1064 /*
1065 * The board ID is a string but the firmware byte
1066 * swaps each 4-byte word before passing it back to
1067 * us. Therefore we need to swab it before printing.
1068 */
1069 for (i = 0; i < 4; ++i)
1070 ((u32 *) board_id)[i] =
1071 swab32(*(u32 *) (vsd + VSD_OFFSET_MLX_BOARD_ID + i * 4));
1072 }
1073 }
1074
1075 int mlx4_QUERY_ADAPTER(struct mlx4_dev *dev, struct mlx4_adapter *adapter)
1076 {
1077 struct mlx4_cmd_mailbox *mailbox;
1078 u32 *outbox;
1079 int err;
1080
1081 #define QUERY_ADAPTER_OUT_SIZE 0x100
1082 #define QUERY_ADAPTER_INTA_PIN_OFFSET 0x10
1083 #define QUERY_ADAPTER_VSD_OFFSET 0x20
1084
1085 mailbox = mlx4_alloc_cmd_mailbox(dev);
1086 if (IS_ERR(mailbox))
1087 return PTR_ERR(mailbox);
1088 outbox = mailbox->buf;
1089
1090 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_ADAPTER,
1091 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1092 if (err)
1093 goto out;
1094
1095 MLX4_GET(adapter->inta_pin, outbox, QUERY_ADAPTER_INTA_PIN_OFFSET);
1096
1097 get_board_id(outbox + QUERY_ADAPTER_VSD_OFFSET / 4,
1098 adapter->board_id);
1099
1100 out:
1101 mlx4_free_cmd_mailbox(dev, mailbox);
1102 return err;
1103 }
1104
1105 int mlx4_INIT_HCA(struct mlx4_dev *dev, struct mlx4_init_hca_param *param)
1106 {
1107 struct mlx4_cmd_mailbox *mailbox;
1108 __be32 *inbox;
1109 int err;
1110
1111 #define INIT_HCA_IN_SIZE 0x200
1112 #define INIT_HCA_VERSION_OFFSET 0x000
1113 #define INIT_HCA_VERSION 2
1114 #define INIT_HCA_CACHELINE_SZ_OFFSET 0x0e
1115 #define INIT_HCA_FLAGS_OFFSET 0x014
1116 #define INIT_HCA_QPC_OFFSET 0x020
1117 #define INIT_HCA_QPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x10)
1118 #define INIT_HCA_LOG_QP_OFFSET (INIT_HCA_QPC_OFFSET + 0x17)
1119 #define INIT_HCA_SRQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x28)
1120 #define INIT_HCA_LOG_SRQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x2f)
1121 #define INIT_HCA_CQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x30)
1122 #define INIT_HCA_LOG_CQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x37)
1123 #define INIT_HCA_EQE_CQE_OFFSETS (INIT_HCA_QPC_OFFSET + 0x38)
1124 #define INIT_HCA_ALTC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x40)
1125 #define INIT_HCA_AUXC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x50)
1126 #define INIT_HCA_EQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x60)
1127 #define INIT_HCA_LOG_EQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x67)
1128 #define INIT_HCA_RDMARC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x70)
1129 #define INIT_HCA_LOG_RD_OFFSET (INIT_HCA_QPC_OFFSET + 0x77)
1130 #define INIT_HCA_MCAST_OFFSET 0x0c0
1131 #define INIT_HCA_MC_BASE_OFFSET (INIT_HCA_MCAST_OFFSET + 0x00)
1132 #define INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x12)
1133 #define INIT_HCA_LOG_MC_HASH_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x16)
1134 #define INIT_HCA_UC_STEERING_OFFSET (INIT_HCA_MCAST_OFFSET + 0x18)
1135 #define INIT_HCA_LOG_MC_TABLE_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x1b)
1136 #define INIT_HCA_TPT_OFFSET 0x0f0
1137 #define INIT_HCA_DMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x00)
1138 #define INIT_HCA_LOG_MPT_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x0b)
1139 #define INIT_HCA_MTT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x10)
1140 #define INIT_HCA_CMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x18)
1141 #define INIT_HCA_UAR_OFFSET 0x120
1142 #define INIT_HCA_LOG_UAR_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0a)
1143 #define INIT_HCA_UAR_PAGE_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0b)
1144
1145 mailbox = mlx4_alloc_cmd_mailbox(dev);
1146 if (IS_ERR(mailbox))
1147 return PTR_ERR(mailbox);
1148 inbox = mailbox->buf;
1149
1150 memset(inbox, 0, INIT_HCA_IN_SIZE);
1151
1152 *((u8 *) mailbox->buf + INIT_HCA_VERSION_OFFSET) = INIT_HCA_VERSION;
1153
1154 *((u8 *) mailbox->buf + INIT_HCA_CACHELINE_SZ_OFFSET) =
1155 (ilog2(cache_line_size()) - 4) << 5;
1156
1157 #if defined(__LITTLE_ENDIAN)
1158 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) &= ~cpu_to_be32(1 << 1);
1159 #elif defined(__BIG_ENDIAN)
1160 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 1);
1161 #else
1162 #error Host endianness not defined
1163 #endif
1164 /* Check port for UD address vector: */
1165 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1);
1166
1167 /* Enable IPoIB checksumming if we can: */
1168 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_IPOIB_CSUM)
1169 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 3);
1170
1171 /* Enable QoS support if module parameter set */
1172 if (enable_qos)
1173 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 2);
1174
1175 /* enable counters */
1176 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS)
1177 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 4);
1178
1179 /* QPC/EEC/CQC/EQC/RDMARC attributes */
1180
1181 MLX4_PUT(inbox, param->qpc_base, INIT_HCA_QPC_BASE_OFFSET);
1182 MLX4_PUT(inbox, param->log_num_qps, INIT_HCA_LOG_QP_OFFSET);
1183 MLX4_PUT(inbox, param->srqc_base, INIT_HCA_SRQC_BASE_OFFSET);
1184 MLX4_PUT(inbox, param->log_num_srqs, INIT_HCA_LOG_SRQ_OFFSET);
1185 MLX4_PUT(inbox, param->cqc_base, INIT_HCA_CQC_BASE_OFFSET);
1186 MLX4_PUT(inbox, param->log_num_cqs, INIT_HCA_LOG_CQ_OFFSET);
1187 MLX4_PUT(inbox, param->altc_base, INIT_HCA_ALTC_BASE_OFFSET);
1188 MLX4_PUT(inbox, param->auxc_base, INIT_HCA_AUXC_BASE_OFFSET);
1189 MLX4_PUT(inbox, param->eqc_base, INIT_HCA_EQC_BASE_OFFSET);
1190 MLX4_PUT(inbox, param->log_num_eqs, INIT_HCA_LOG_EQ_OFFSET);
1191 MLX4_PUT(inbox, param->rdmarc_base, INIT_HCA_RDMARC_BASE_OFFSET);
1192 MLX4_PUT(inbox, param->log_rd_per_qp, INIT_HCA_LOG_RD_OFFSET);
1193
1194 /* multicast attributes */
1195
1196 MLX4_PUT(inbox, param->mc_base, INIT_HCA_MC_BASE_OFFSET);
1197 MLX4_PUT(inbox, param->log_mc_entry_sz, INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET);
1198 MLX4_PUT(inbox, param->log_mc_hash_sz, INIT_HCA_LOG_MC_HASH_SZ_OFFSET);
1199 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER)
1200 MLX4_PUT(inbox, (u8) (1 << 3), INIT_HCA_UC_STEERING_OFFSET);
1201 MLX4_PUT(inbox, param->log_mc_table_sz, INIT_HCA_LOG_MC_TABLE_SZ_OFFSET);
1202
1203 /* TPT attributes */
1204
1205 MLX4_PUT(inbox, param->dmpt_base, INIT_HCA_DMPT_BASE_OFFSET);
1206 MLX4_PUT(inbox, param->log_mpt_sz, INIT_HCA_LOG_MPT_SZ_OFFSET);
1207 MLX4_PUT(inbox, param->mtt_base, INIT_HCA_MTT_BASE_OFFSET);
1208 MLX4_PUT(inbox, param->cmpt_base, INIT_HCA_CMPT_BASE_OFFSET);
1209
1210 /* UAR attributes */
1211
1212 MLX4_PUT(inbox, param->uar_page_sz, INIT_HCA_UAR_PAGE_SZ_OFFSET);
1213 MLX4_PUT(inbox, param->log_uar_sz, INIT_HCA_LOG_UAR_SZ_OFFSET);
1214
1215 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_INIT_HCA, 10000,
1216 MLX4_CMD_NATIVE);
1217
1218 if (err)
1219 mlx4_err(dev, "INIT_HCA returns %d\n", err);
1220
1221 mlx4_free_cmd_mailbox(dev, mailbox);
1222 return err;
1223 }
1224
1225 int mlx4_QUERY_HCA(struct mlx4_dev *dev,
1226 struct mlx4_init_hca_param *param)
1227 {
1228 struct mlx4_cmd_mailbox *mailbox;
1229 __be32 *outbox;
1230 int err;
1231
1232 #define QUERY_HCA_GLOBAL_CAPS_OFFSET 0x04
1233
1234 mailbox = mlx4_alloc_cmd_mailbox(dev);
1235 if (IS_ERR(mailbox))
1236 return PTR_ERR(mailbox);
1237 outbox = mailbox->buf;
1238
1239 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0,
1240 MLX4_CMD_QUERY_HCA,
1241 MLX4_CMD_TIME_CLASS_B,
1242 !mlx4_is_slave(dev));
1243 if (err)
1244 goto out;
1245
1246 MLX4_GET(param->global_caps, outbox, QUERY_HCA_GLOBAL_CAPS_OFFSET);
1247
1248 /* QPC/EEC/CQC/EQC/RDMARC attributes */
1249
1250 MLX4_GET(param->qpc_base, outbox, INIT_HCA_QPC_BASE_OFFSET);
1251 MLX4_GET(param->log_num_qps, outbox, INIT_HCA_LOG_QP_OFFSET);
1252 MLX4_GET(param->srqc_base, outbox, INIT_HCA_SRQC_BASE_OFFSET);
1253 MLX4_GET(param->log_num_srqs, outbox, INIT_HCA_LOG_SRQ_OFFSET);
1254 MLX4_GET(param->cqc_base, outbox, INIT_HCA_CQC_BASE_OFFSET);
1255 MLX4_GET(param->log_num_cqs, outbox, INIT_HCA_LOG_CQ_OFFSET);
1256 MLX4_GET(param->altc_base, outbox, INIT_HCA_ALTC_BASE_OFFSET);
1257 MLX4_GET(param->auxc_base, outbox, INIT_HCA_AUXC_BASE_OFFSET);
1258 MLX4_GET(param->eqc_base, outbox, INIT_HCA_EQC_BASE_OFFSET);
1259 MLX4_GET(param->log_num_eqs, outbox, INIT_HCA_LOG_EQ_OFFSET);
1260 MLX4_GET(param->rdmarc_base, outbox, INIT_HCA_RDMARC_BASE_OFFSET);
1261 MLX4_GET(param->log_rd_per_qp, outbox, INIT_HCA_LOG_RD_OFFSET);
1262
1263 /* multicast attributes */
1264
1265 MLX4_GET(param->mc_base, outbox, INIT_HCA_MC_BASE_OFFSET);
1266 MLX4_GET(param->log_mc_entry_sz, outbox,
1267 INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET);
1268 MLX4_GET(param->log_mc_hash_sz, outbox,
1269 INIT_HCA_LOG_MC_HASH_SZ_OFFSET);
1270 MLX4_GET(param->log_mc_table_sz, outbox,
1271 INIT_HCA_LOG_MC_TABLE_SZ_OFFSET);
1272
1273 /* TPT attributes */
1274
1275 MLX4_GET(param->dmpt_base, outbox, INIT_HCA_DMPT_BASE_OFFSET);
1276 MLX4_GET(param->log_mpt_sz, outbox, INIT_HCA_LOG_MPT_SZ_OFFSET);
1277 MLX4_GET(param->mtt_base, outbox, INIT_HCA_MTT_BASE_OFFSET);
1278 MLX4_GET(param->cmpt_base, outbox, INIT_HCA_CMPT_BASE_OFFSET);
1279
1280 /* UAR attributes */
1281
1282 MLX4_GET(param->uar_page_sz, outbox, INIT_HCA_UAR_PAGE_SZ_OFFSET);
1283 MLX4_GET(param->log_uar_sz, outbox, INIT_HCA_LOG_UAR_SZ_OFFSET);
1284
1285 out:
1286 mlx4_free_cmd_mailbox(dev, mailbox);
1287
1288 return err;
1289 }
1290
1291 int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave,
1292 struct mlx4_vhcr *vhcr,
1293 struct mlx4_cmd_mailbox *inbox,
1294 struct mlx4_cmd_mailbox *outbox,
1295 struct mlx4_cmd_info *cmd)
1296 {
1297 struct mlx4_priv *priv = mlx4_priv(dev);
1298 int port = vhcr->in_modifier;
1299 int err;
1300
1301 if (priv->mfunc.master.slave_state[slave].init_port_mask & (1 << port))
1302 return 0;
1303
1304 if (dev->caps.port_mask[port] == MLX4_PORT_TYPE_IB)
1305 return -ENODEV;
1306
1307 /* Enable port only if it was previously disabled */
1308 if (!priv->mfunc.master.init_port_ref[port]) {
1309 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
1310 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1311 if (err)
1312 return err;
1313 }
1314 priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port);
1315 ++priv->mfunc.master.init_port_ref[port];
1316 return 0;
1317 }
1318
1319 int mlx4_INIT_PORT(struct mlx4_dev *dev, int port)
1320 {
1321 struct mlx4_cmd_mailbox *mailbox;
1322 u32 *inbox;
1323 int err;
1324 u32 flags;
1325 u16 field;
1326
1327 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
1328 #define INIT_PORT_IN_SIZE 256
1329 #define INIT_PORT_FLAGS_OFFSET 0x00
1330 #define INIT_PORT_FLAG_SIG (1 << 18)
1331 #define INIT_PORT_FLAG_NG (1 << 17)
1332 #define INIT_PORT_FLAG_G0 (1 << 16)
1333 #define INIT_PORT_VL_SHIFT 4
1334 #define INIT_PORT_PORT_WIDTH_SHIFT 8
1335 #define INIT_PORT_MTU_OFFSET 0x04
1336 #define INIT_PORT_MAX_GID_OFFSET 0x06
1337 #define INIT_PORT_MAX_PKEY_OFFSET 0x0a
1338 #define INIT_PORT_GUID0_OFFSET 0x10
1339 #define INIT_PORT_NODE_GUID_OFFSET 0x18
1340 #define INIT_PORT_SI_GUID_OFFSET 0x20
1341
1342 mailbox = mlx4_alloc_cmd_mailbox(dev);
1343 if (IS_ERR(mailbox))
1344 return PTR_ERR(mailbox);
1345 inbox = mailbox->buf;
1346
1347 memset(inbox, 0, INIT_PORT_IN_SIZE);
1348
1349 flags = 0;
1350 flags |= (dev->caps.vl_cap[port] & 0xf) << INIT_PORT_VL_SHIFT;
1351 flags |= (dev->caps.port_width_cap[port] & 0xf) << INIT_PORT_PORT_WIDTH_SHIFT;
1352 MLX4_PUT(inbox, flags, INIT_PORT_FLAGS_OFFSET);
1353
1354 field = 128 << dev->caps.ib_mtu_cap[port];
1355 MLX4_PUT(inbox, field, INIT_PORT_MTU_OFFSET);
1356 field = dev->caps.gid_table_len[port];
1357 MLX4_PUT(inbox, field, INIT_PORT_MAX_GID_OFFSET);
1358 field = dev->caps.pkey_table_len[port];
1359 MLX4_PUT(inbox, field, INIT_PORT_MAX_PKEY_OFFSET);
1360
1361 err = mlx4_cmd(dev, mailbox->dma, port, 0, MLX4_CMD_INIT_PORT,
1362 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1363
1364 mlx4_free_cmd_mailbox(dev, mailbox);
1365 } else
1366 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
1367 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
1368
1369 return err;
1370 }
1371 EXPORT_SYMBOL_GPL(mlx4_INIT_PORT);
1372
1373 int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave,
1374 struct mlx4_vhcr *vhcr,
1375 struct mlx4_cmd_mailbox *inbox,
1376 struct mlx4_cmd_mailbox *outbox,
1377 struct mlx4_cmd_info *cmd)
1378 {
1379 struct mlx4_priv *priv = mlx4_priv(dev);
1380 int port = vhcr->in_modifier;
1381 int err;
1382
1383 if (!(priv->mfunc.master.slave_state[slave].init_port_mask &
1384 (1 << port)))
1385 return 0;
1386
1387 if (dev->caps.port_mask[port] == MLX4_PORT_TYPE_IB)
1388 return -ENODEV;
1389 if (priv->mfunc.master.init_port_ref[port] == 1) {
1390 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, 1000,
1391 MLX4_CMD_NATIVE);
1392 if (err)
1393 return err;
1394 }
1395 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port);
1396 --priv->mfunc.master.init_port_ref[port];
1397 return 0;
1398 }
1399
1400 int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port)
1401 {
1402 return mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, 1000,
1403 MLX4_CMD_WRAPPED);
1404 }
1405 EXPORT_SYMBOL_GPL(mlx4_CLOSE_PORT);
1406
1407 int mlx4_CLOSE_HCA(struct mlx4_dev *dev, int panic)
1408 {
1409 return mlx4_cmd(dev, 0, 0, panic, MLX4_CMD_CLOSE_HCA, 1000,
1410 MLX4_CMD_NATIVE);
1411 }
1412
1413 int mlx4_SET_ICM_SIZE(struct mlx4_dev *dev, u64 icm_size, u64 *aux_pages)
1414 {
1415 int ret = mlx4_cmd_imm(dev, icm_size, aux_pages, 0, 0,
1416 MLX4_CMD_SET_ICM_SIZE,
1417 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1418 if (ret)
1419 return ret;
1420
1421 /*
1422 * Round up number of system pages needed in case
1423 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE.
1424 */
1425 *aux_pages = ALIGN(*aux_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >>
1426 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT);
1427
1428 return 0;
1429 }
1430
1431 int mlx4_NOP(struct mlx4_dev *dev)
1432 {
1433 /* Input modifier of 0x1f means "finish as soon as possible." */
1434 return mlx4_cmd(dev, 0, 0x1f, 0, MLX4_CMD_NOP, 100, MLX4_CMD_NATIVE);
1435 }
1436
1437 #define MLX4_WOL_SETUP_MODE (5 << 28)
1438 int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port)
1439 {
1440 u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8;
1441
1442 return mlx4_cmd_imm(dev, 0, config, in_mod, 0x3,
1443 MLX4_CMD_MOD_STAT_CFG, MLX4_CMD_TIME_CLASS_A,
1444 MLX4_CMD_NATIVE);
1445 }
1446 EXPORT_SYMBOL_GPL(mlx4_wol_read);
1447
1448 int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port)
1449 {
1450 u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8;
1451
1452 return mlx4_cmd(dev, config, in_mod, 0x1, MLX4_CMD_MOD_STAT_CFG,
1453 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1454 }
1455 EXPORT_SYMBOL_GPL(mlx4_wol_write);
Linux kernel - Deliverables
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