2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <linux/etherdevice.h>
36 #include <linux/mlx4/cmd.h>
37 #include <linux/module.h>
38 #include <linux/cache.h>
44 MLX4_COMMAND_INTERFACE_MIN_REV
= 2,
45 MLX4_COMMAND_INTERFACE_MAX_REV
= 3,
46 MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS
= 3,
49 extern void __buggy_use_of_MLX4_GET(void);
50 extern void __buggy_use_of_MLX4_PUT(void);
52 static bool enable_qos
;
53 module_param(enable_qos
, bool, 0444);
54 MODULE_PARM_DESC(enable_qos
, "Enable Quality of Service support in the HCA (default: off)");
56 #define MLX4_GET(dest, source, offset) \
58 void *__p = (char *) (source) + (offset); \
59 switch (sizeof (dest)) { \
60 case 1: (dest) = *(u8 *) __p; break; \
61 case 2: (dest) = be16_to_cpup(__p); break; \
62 case 4: (dest) = be32_to_cpup(__p); break; \
63 case 8: (dest) = be64_to_cpup(__p); break; \
64 default: __buggy_use_of_MLX4_GET(); \
68 #define MLX4_PUT(dest, source, offset) \
70 void *__d = ((char *) (dest) + (offset)); \
71 switch (sizeof(source)) { \
72 case 1: *(u8 *) __d = (source); break; \
73 case 2: *(__be16 *) __d = cpu_to_be16(source); break; \
74 case 4: *(__be32 *) __d = cpu_to_be32(source); break; \
75 case 8: *(__be64 *) __d = cpu_to_be64(source); break; \
76 default: __buggy_use_of_MLX4_PUT(); \
80 static void dump_dev_cap_flags(struct mlx4_dev
*dev
, u64 flags
)
82 static const char *fname
[] = {
83 [ 0] = "RC transport",
84 [ 1] = "UC transport",
85 [ 2] = "UD transport",
86 [ 3] = "XRC transport",
88 [ 7] = "IPoIB checksum offload",
89 [ 8] = "P_Key violation counter",
90 [ 9] = "Q_Key violation counter",
91 [12] = "Dual Port Different Protocol (DPDP) support",
92 [15] = "Big LSO headers",
95 [18] = "Atomic ops support",
96 [19] = "Raw multicast support",
97 [20] = "Address vector port checking support",
98 [21] = "UD multicast support",
99 [30] = "IBoE support",
100 [32] = "Unicast loopback support",
101 [34] = "FCS header control",
102 [37] = "Wake On LAN (port1) support",
103 [38] = "Wake On LAN (port2) support",
104 [40] = "UDP RSS support",
105 [41] = "Unicast VEP steering support",
106 [42] = "Multicast VEP steering support",
107 [48] = "Counters support",
108 [53] = "Port ETS Scheduler support",
109 [55] = "Port link type sensing support",
110 [59] = "Port management change event support",
111 [61] = "64 byte EQE support",
112 [62] = "64 byte CQE support",
116 mlx4_dbg(dev
, "DEV_CAP flags:\n");
117 for (i
= 0; i
< ARRAY_SIZE(fname
); ++i
)
118 if (fname
[i
] && (flags
& (1LL << i
)))
119 mlx4_dbg(dev
, " %s\n", fname
[i
]);
122 static void dump_dev_cap_flags2(struct mlx4_dev
*dev
, u64 flags
)
124 static const char * const fname
[] = {
126 [1] = "RSS Toeplitz Hash Function support",
127 [2] = "RSS XOR Hash Function support",
128 [3] = "Device managed flow steering support",
129 [4] = "Automatic MAC reassignment support",
130 [5] = "Time stamping support",
131 [6] = "VST (control vlan insertion/stripping) support",
132 [7] = "FSM (MAC anti-spoofing) support",
133 [8] = "Dynamic QP updates support",
134 [9] = "Device managed flow steering IPoIB support",
135 [10] = "TCP/IP offloads/flow-steering for VXLAN support",
136 [11] = "MAD DEMUX (Secure-Host) support",
137 [12] = "Large cache line (>64B) CQE stride support",
138 [13] = "Large cache line (>64B) EQE stride support",
139 [14] = "Ethernet protocol control support",
140 [15] = "Ethernet Backplane autoneg support",
141 [16] = "CONFIG DEV support",
142 [17] = "Asymmetric EQs support",
143 [18] = "More than 80 VFs support",
144 [19] = "Performance optimized for limited rule configuration flow steering support",
145 [20] = "Recoverable error events support",
146 [21] = "Port Remap support"
150 for (i
= 0; i
< ARRAY_SIZE(fname
); ++i
)
151 if (fname
[i
] && (flags
& (1LL << i
)))
152 mlx4_dbg(dev
, " %s\n", fname
[i
]);
155 int mlx4_MOD_STAT_CFG(struct mlx4_dev
*dev
, struct mlx4_mod_stat_cfg
*cfg
)
157 struct mlx4_cmd_mailbox
*mailbox
;
161 #define MOD_STAT_CFG_IN_SIZE 0x100
163 #define MOD_STAT_CFG_PG_SZ_M_OFFSET 0x002
164 #define MOD_STAT_CFG_PG_SZ_OFFSET 0x003
166 mailbox
= mlx4_alloc_cmd_mailbox(dev
);
168 return PTR_ERR(mailbox
);
169 inbox
= mailbox
->buf
;
171 MLX4_PUT(inbox
, cfg
->log_pg_sz
, MOD_STAT_CFG_PG_SZ_OFFSET
);
172 MLX4_PUT(inbox
, cfg
->log_pg_sz_m
, MOD_STAT_CFG_PG_SZ_M_OFFSET
);
174 err
= mlx4_cmd(dev
, mailbox
->dma
, 0, 0, MLX4_CMD_MOD_STAT_CFG
,
175 MLX4_CMD_TIME_CLASS_A
, MLX4_CMD_NATIVE
);
177 mlx4_free_cmd_mailbox(dev
, mailbox
);
181 int mlx4_QUERY_FUNC(struct mlx4_dev
*dev
, struct mlx4_func
*func
, int slave
)
183 struct mlx4_cmd_mailbox
*mailbox
;
190 #define QUERY_FUNC_BUS_OFFSET 0x00
191 #define QUERY_FUNC_DEVICE_OFFSET 0x01
192 #define QUERY_FUNC_FUNCTION_OFFSET 0x01
193 #define QUERY_FUNC_PHYSICAL_FUNCTION_OFFSET 0x03
194 #define QUERY_FUNC_RSVD_EQS_OFFSET 0x04
195 #define QUERY_FUNC_MAX_EQ_OFFSET 0x06
196 #define QUERY_FUNC_RSVD_UARS_OFFSET 0x0b
198 mailbox
= mlx4_alloc_cmd_mailbox(dev
);
200 return PTR_ERR(mailbox
);
201 outbox
= mailbox
->buf
;
205 err
= mlx4_cmd_box(dev
, 0, mailbox
->dma
, in_modifier
, 0,
207 MLX4_CMD_TIME_CLASS_A
,
212 MLX4_GET(field
, outbox
, QUERY_FUNC_BUS_OFFSET
);
213 func
->bus
= field
& 0xf;
214 MLX4_GET(field
, outbox
, QUERY_FUNC_DEVICE_OFFSET
);
215 func
->device
= field
& 0xf1;
216 MLX4_GET(field
, outbox
, QUERY_FUNC_FUNCTION_OFFSET
);
217 func
->function
= field
& 0x7;
218 MLX4_GET(field
, outbox
, QUERY_FUNC_PHYSICAL_FUNCTION_OFFSET
);
219 func
->physical_function
= field
& 0xf;
220 MLX4_GET(field16
, outbox
, QUERY_FUNC_RSVD_EQS_OFFSET
);
221 func
->rsvd_eqs
= field16
& 0xffff;
222 MLX4_GET(field16
, outbox
, QUERY_FUNC_MAX_EQ_OFFSET
);
223 func
->max_eq
= field16
& 0xffff;
224 MLX4_GET(field
, outbox
, QUERY_FUNC_RSVD_UARS_OFFSET
);
225 func
->rsvd_uars
= field
& 0x0f;
227 mlx4_dbg(dev
, "Bus: %d, Device: %d, Function: %d, Physical function: %d, Max EQs: %d, Reserved EQs: %d, Reserved UARs: %d\n",
228 func
->bus
, func
->device
, func
->function
, func
->physical_function
,
229 func
->max_eq
, func
->rsvd_eqs
, func
->rsvd_uars
);
232 mlx4_free_cmd_mailbox(dev
, mailbox
);
236 int mlx4_QUERY_FUNC_CAP_wrapper(struct mlx4_dev
*dev
, int slave
,
237 struct mlx4_vhcr
*vhcr
,
238 struct mlx4_cmd_mailbox
*inbox
,
239 struct mlx4_cmd_mailbox
*outbox
,
240 struct mlx4_cmd_info
*cmd
)
242 struct mlx4_priv
*priv
= mlx4_priv(dev
);
244 u32 size
, proxy_qp
, qkey
;
246 struct mlx4_func func
;
248 #define QUERY_FUNC_CAP_FLAGS_OFFSET 0x0
249 #define QUERY_FUNC_CAP_NUM_PORTS_OFFSET 0x1
250 #define QUERY_FUNC_CAP_PF_BHVR_OFFSET 0x4
251 #define QUERY_FUNC_CAP_FMR_OFFSET 0x8
252 #define QUERY_FUNC_CAP_QP_QUOTA_OFFSET_DEP 0x10
253 #define QUERY_FUNC_CAP_CQ_QUOTA_OFFSET_DEP 0x14
254 #define QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET_DEP 0x18
255 #define QUERY_FUNC_CAP_MPT_QUOTA_OFFSET_DEP 0x20
256 #define QUERY_FUNC_CAP_MTT_QUOTA_OFFSET_DEP 0x24
257 #define QUERY_FUNC_CAP_MCG_QUOTA_OFFSET_DEP 0x28
258 #define QUERY_FUNC_CAP_MAX_EQ_OFFSET 0x2c
259 #define QUERY_FUNC_CAP_RESERVED_EQ_OFFSET 0x30
260 #define QUERY_FUNC_CAP_QP_RESD_LKEY_OFFSET 0x48
262 #define QUERY_FUNC_CAP_QP_QUOTA_OFFSET 0x50
263 #define QUERY_FUNC_CAP_CQ_QUOTA_OFFSET 0x54
264 #define QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET 0x58
265 #define QUERY_FUNC_CAP_MPT_QUOTA_OFFSET 0x60
266 #define QUERY_FUNC_CAP_MTT_QUOTA_OFFSET 0x64
267 #define QUERY_FUNC_CAP_MCG_QUOTA_OFFSET 0x68
269 #define QUERY_FUNC_CAP_EXTRA_FLAGS_OFFSET 0x6c
271 #define QUERY_FUNC_CAP_FMR_FLAG 0x80
272 #define QUERY_FUNC_CAP_FLAG_RDMA 0x40
273 #define QUERY_FUNC_CAP_FLAG_ETH 0x80
274 #define QUERY_FUNC_CAP_FLAG_QUOTAS 0x10
275 #define QUERY_FUNC_CAP_FLAG_RESD_LKEY 0x08
276 #define QUERY_FUNC_CAP_FLAG_VALID_MAILBOX 0x04
278 #define QUERY_FUNC_CAP_EXTRA_FLAGS_BF_QP_ALLOC_FLAG (1UL << 31)
279 #define QUERY_FUNC_CAP_EXTRA_FLAGS_A0_QP_ALLOC_FLAG (1UL << 30)
281 /* when opcode modifier = 1 */
282 #define QUERY_FUNC_CAP_PHYS_PORT_OFFSET 0x3
283 #define QUERY_FUNC_CAP_PRIV_VF_QKEY_OFFSET 0x4
284 #define QUERY_FUNC_CAP_FLAGS0_OFFSET 0x8
285 #define QUERY_FUNC_CAP_FLAGS1_OFFSET 0xc
287 #define QUERY_FUNC_CAP_QP0_TUNNEL 0x10
288 #define QUERY_FUNC_CAP_QP0_PROXY 0x14
289 #define QUERY_FUNC_CAP_QP1_TUNNEL 0x18
290 #define QUERY_FUNC_CAP_QP1_PROXY 0x1c
291 #define QUERY_FUNC_CAP_PHYS_PORT_ID 0x28
293 #define QUERY_FUNC_CAP_FLAGS1_FORCE_MAC 0x40
294 #define QUERY_FUNC_CAP_FLAGS1_FORCE_VLAN 0x80
295 #define QUERY_FUNC_CAP_FLAGS1_NIC_INFO 0x10
296 #define QUERY_FUNC_CAP_VF_ENABLE_QP0 0x08
298 #define QUERY_FUNC_CAP_FLAGS0_FORCE_PHY_WQE_GID 0x80
299 #define QUERY_FUNC_CAP_SUPPORTS_NON_POWER_OF_2_NUM_EQS (1 << 31)
301 if (vhcr
->op_modifier
== 1) {
302 struct mlx4_active_ports actv_ports
=
303 mlx4_get_active_ports(dev
, slave
);
304 int converted_port
= mlx4_slave_convert_port(
305 dev
, slave
, vhcr
->in_modifier
);
307 if (converted_port
< 0)
310 vhcr
->in_modifier
= converted_port
;
311 /* phys-port = logical-port */
312 field
= vhcr
->in_modifier
-
313 find_first_bit(actv_ports
.ports
, dev
->caps
.num_ports
);
314 MLX4_PUT(outbox
->buf
, field
, QUERY_FUNC_CAP_PHYS_PORT_OFFSET
);
316 port
= vhcr
->in_modifier
;
317 proxy_qp
= dev
->phys_caps
.base_proxy_sqpn
+ 8 * slave
+ port
- 1;
319 /* Set nic_info bit to mark new fields support */
320 field
= QUERY_FUNC_CAP_FLAGS1_NIC_INFO
;
322 if (mlx4_vf_smi_enabled(dev
, slave
, port
) &&
323 !mlx4_get_parav_qkey(dev
, proxy_qp
, &qkey
)) {
324 field
|= QUERY_FUNC_CAP_VF_ENABLE_QP0
;
325 MLX4_PUT(outbox
->buf
, qkey
,
326 QUERY_FUNC_CAP_PRIV_VF_QKEY_OFFSET
);
328 MLX4_PUT(outbox
->buf
, field
, QUERY_FUNC_CAP_FLAGS1_OFFSET
);
330 /* size is now the QP number */
331 size
= dev
->phys_caps
.base_tunnel_sqpn
+ 8 * slave
+ port
- 1;
332 MLX4_PUT(outbox
->buf
, size
, QUERY_FUNC_CAP_QP0_TUNNEL
);
335 MLX4_PUT(outbox
->buf
, size
, QUERY_FUNC_CAP_QP1_TUNNEL
);
337 MLX4_PUT(outbox
->buf
, proxy_qp
, QUERY_FUNC_CAP_QP0_PROXY
);
339 MLX4_PUT(outbox
->buf
, proxy_qp
, QUERY_FUNC_CAP_QP1_PROXY
);
341 MLX4_PUT(outbox
->buf
, dev
->caps
.phys_port_id
[vhcr
->in_modifier
],
342 QUERY_FUNC_CAP_PHYS_PORT_ID
);
344 } else if (vhcr
->op_modifier
== 0) {
345 struct mlx4_active_ports actv_ports
=
346 mlx4_get_active_ports(dev
, slave
);
347 /* enable rdma and ethernet interfaces, new quota locations,
350 field
= (QUERY_FUNC_CAP_FLAG_ETH
| QUERY_FUNC_CAP_FLAG_RDMA
|
351 QUERY_FUNC_CAP_FLAG_QUOTAS
| QUERY_FUNC_CAP_FLAG_VALID_MAILBOX
|
352 QUERY_FUNC_CAP_FLAG_RESD_LKEY
);
353 MLX4_PUT(outbox
->buf
, field
, QUERY_FUNC_CAP_FLAGS_OFFSET
);
356 bitmap_weight(actv_ports
.ports
, dev
->caps
.num_ports
),
357 dev
->caps
.num_ports
);
358 MLX4_PUT(outbox
->buf
, field
, QUERY_FUNC_CAP_NUM_PORTS_OFFSET
);
360 size
= dev
->caps
.function_caps
; /* set PF behaviours */
361 MLX4_PUT(outbox
->buf
, size
, QUERY_FUNC_CAP_PF_BHVR_OFFSET
);
363 field
= 0; /* protected FMR support not available as yet */
364 MLX4_PUT(outbox
->buf
, field
, QUERY_FUNC_CAP_FMR_OFFSET
);
366 size
= priv
->mfunc
.master
.res_tracker
.res_alloc
[RES_QP
].quota
[slave
];
367 MLX4_PUT(outbox
->buf
, size
, QUERY_FUNC_CAP_QP_QUOTA_OFFSET
);
368 size
= dev
->caps
.num_qps
;
369 MLX4_PUT(outbox
->buf
, size
, QUERY_FUNC_CAP_QP_QUOTA_OFFSET_DEP
);
371 size
= priv
->mfunc
.master
.res_tracker
.res_alloc
[RES_SRQ
].quota
[slave
];
372 MLX4_PUT(outbox
->buf
, size
, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET
);
373 size
= dev
->caps
.num_srqs
;
374 MLX4_PUT(outbox
->buf
, size
, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET_DEP
);
376 size
= priv
->mfunc
.master
.res_tracker
.res_alloc
[RES_CQ
].quota
[slave
];
377 MLX4_PUT(outbox
->buf
, size
, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET
);
378 size
= dev
->caps
.num_cqs
;
379 MLX4_PUT(outbox
->buf
, size
, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET_DEP
);
381 if (!(dev
->caps
.flags2
& MLX4_DEV_CAP_FLAG2_SYS_EQS
) ||
382 mlx4_QUERY_FUNC(dev
, &func
, slave
)) {
383 size
= vhcr
->in_modifier
&
384 QUERY_FUNC_CAP_SUPPORTS_NON_POWER_OF_2_NUM_EQS
?
386 rounddown_pow_of_two(dev
->caps
.num_eqs
);
387 MLX4_PUT(outbox
->buf
, size
, QUERY_FUNC_CAP_MAX_EQ_OFFSET
);
388 size
= dev
->caps
.reserved_eqs
;
389 MLX4_PUT(outbox
->buf
, size
, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET
);
391 size
= vhcr
->in_modifier
&
392 QUERY_FUNC_CAP_SUPPORTS_NON_POWER_OF_2_NUM_EQS
?
394 rounddown_pow_of_two(func
.max_eq
);
395 MLX4_PUT(outbox
->buf
, size
, QUERY_FUNC_CAP_MAX_EQ_OFFSET
);
396 size
= func
.rsvd_eqs
;
397 MLX4_PUT(outbox
->buf
, size
, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET
);
400 size
= priv
->mfunc
.master
.res_tracker
.res_alloc
[RES_MPT
].quota
[slave
];
401 MLX4_PUT(outbox
->buf
, size
, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET
);
402 size
= dev
->caps
.num_mpts
;
403 MLX4_PUT(outbox
->buf
, size
, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET_DEP
);
405 size
= priv
->mfunc
.master
.res_tracker
.res_alloc
[RES_MTT
].quota
[slave
];
406 MLX4_PUT(outbox
->buf
, size
, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET
);
407 size
= dev
->caps
.num_mtts
;
408 MLX4_PUT(outbox
->buf
, size
, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET_DEP
);
410 size
= dev
->caps
.num_mgms
+ dev
->caps
.num_amgms
;
411 MLX4_PUT(outbox
->buf
, size
, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET
);
412 MLX4_PUT(outbox
->buf
, size
, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET_DEP
);
414 size
= QUERY_FUNC_CAP_EXTRA_FLAGS_BF_QP_ALLOC_FLAG
|
415 QUERY_FUNC_CAP_EXTRA_FLAGS_A0_QP_ALLOC_FLAG
;
416 MLX4_PUT(outbox
->buf
, size
, QUERY_FUNC_CAP_EXTRA_FLAGS_OFFSET
);
418 size
= dev
->caps
.reserved_lkey
+ ((slave
<< 8) & 0xFF00);
419 MLX4_PUT(outbox
->buf
, size
, QUERY_FUNC_CAP_QP_RESD_LKEY_OFFSET
);
426 int mlx4_QUERY_FUNC_CAP(struct mlx4_dev
*dev
, u8 gen_or_port
,
427 struct mlx4_func_cap
*func_cap
)
429 struct mlx4_cmd_mailbox
*mailbox
;
431 u8 field
, op_modifier
;
433 int err
= 0, quotas
= 0;
436 op_modifier
= !!gen_or_port
; /* 0 = general, 1 = logical port */
437 in_modifier
= op_modifier
? gen_or_port
:
438 QUERY_FUNC_CAP_SUPPORTS_NON_POWER_OF_2_NUM_EQS
;
440 mailbox
= mlx4_alloc_cmd_mailbox(dev
);
442 return PTR_ERR(mailbox
);
444 err
= mlx4_cmd_box(dev
, 0, mailbox
->dma
, in_modifier
, op_modifier
,
445 MLX4_CMD_QUERY_FUNC_CAP
,
446 MLX4_CMD_TIME_CLASS_A
, MLX4_CMD_WRAPPED
);
450 outbox
= mailbox
->buf
;
453 MLX4_GET(field
, outbox
, QUERY_FUNC_CAP_FLAGS_OFFSET
);
454 if (!(field
& (QUERY_FUNC_CAP_FLAG_ETH
| QUERY_FUNC_CAP_FLAG_RDMA
))) {
455 mlx4_err(dev
, "The host supports neither eth nor rdma interfaces\n");
456 err
= -EPROTONOSUPPORT
;
459 func_cap
->flags
= field
;
460 quotas
= !!(func_cap
->flags
& QUERY_FUNC_CAP_FLAG_QUOTAS
);
462 MLX4_GET(field
, outbox
, QUERY_FUNC_CAP_NUM_PORTS_OFFSET
);
463 func_cap
->num_ports
= field
;
465 MLX4_GET(size
, outbox
, QUERY_FUNC_CAP_PF_BHVR_OFFSET
);
466 func_cap
->pf_context_behaviour
= size
;
469 MLX4_GET(size
, outbox
, QUERY_FUNC_CAP_QP_QUOTA_OFFSET
);
470 func_cap
->qp_quota
= size
& 0xFFFFFF;
472 MLX4_GET(size
, outbox
, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET
);
473 func_cap
->srq_quota
= size
& 0xFFFFFF;
475 MLX4_GET(size
, outbox
, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET
);
476 func_cap
->cq_quota
= size
& 0xFFFFFF;
478 MLX4_GET(size
, outbox
, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET
);
479 func_cap
->mpt_quota
= size
& 0xFFFFFF;
481 MLX4_GET(size
, outbox
, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET
);
482 func_cap
->mtt_quota
= size
& 0xFFFFFF;
484 MLX4_GET(size
, outbox
, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET
);
485 func_cap
->mcg_quota
= size
& 0xFFFFFF;
488 MLX4_GET(size
, outbox
, QUERY_FUNC_CAP_QP_QUOTA_OFFSET_DEP
);
489 func_cap
->qp_quota
= size
& 0xFFFFFF;
491 MLX4_GET(size
, outbox
, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET_DEP
);
492 func_cap
->srq_quota
= size
& 0xFFFFFF;
494 MLX4_GET(size
, outbox
, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET_DEP
);
495 func_cap
->cq_quota
= size
& 0xFFFFFF;
497 MLX4_GET(size
, outbox
, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET_DEP
);
498 func_cap
->mpt_quota
= size
& 0xFFFFFF;
500 MLX4_GET(size
, outbox
, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET_DEP
);
501 func_cap
->mtt_quota
= size
& 0xFFFFFF;
503 MLX4_GET(size
, outbox
, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET_DEP
);
504 func_cap
->mcg_quota
= size
& 0xFFFFFF;
506 MLX4_GET(size
, outbox
, QUERY_FUNC_CAP_MAX_EQ_OFFSET
);
507 func_cap
->max_eq
= size
& 0xFFFFFF;
509 MLX4_GET(size
, outbox
, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET
);
510 func_cap
->reserved_eq
= size
& 0xFFFFFF;
512 if (func_cap
->flags
& QUERY_FUNC_CAP_FLAG_RESD_LKEY
) {
513 MLX4_GET(size
, outbox
, QUERY_FUNC_CAP_QP_RESD_LKEY_OFFSET
);
514 func_cap
->reserved_lkey
= size
;
516 func_cap
->reserved_lkey
= 0;
519 func_cap
->extra_flags
= 0;
521 /* Mailbox data from 0x6c and onward should only be treated if
522 * QUERY_FUNC_CAP_FLAG_VALID_MAILBOX is set in func_cap->flags
524 if (func_cap
->flags
& QUERY_FUNC_CAP_FLAG_VALID_MAILBOX
) {
525 MLX4_GET(size
, outbox
, QUERY_FUNC_CAP_EXTRA_FLAGS_OFFSET
);
526 if (size
& QUERY_FUNC_CAP_EXTRA_FLAGS_BF_QP_ALLOC_FLAG
)
527 func_cap
->extra_flags
|= MLX4_QUERY_FUNC_FLAGS_BF_RES_QP
;
528 if (size
& QUERY_FUNC_CAP_EXTRA_FLAGS_A0_QP_ALLOC_FLAG
)
529 func_cap
->extra_flags
|= MLX4_QUERY_FUNC_FLAGS_A0_RES_QP
;
535 /* logical port query */
536 if (gen_or_port
> dev
->caps
.num_ports
) {
541 MLX4_GET(func_cap
->flags1
, outbox
, QUERY_FUNC_CAP_FLAGS1_OFFSET
);
542 if (dev
->caps
.port_type
[gen_or_port
] == MLX4_PORT_TYPE_ETH
) {
543 if (func_cap
->flags1
& QUERY_FUNC_CAP_FLAGS1_FORCE_VLAN
) {
544 mlx4_err(dev
, "VLAN is enforced on this port\n");
545 err
= -EPROTONOSUPPORT
;
549 if (func_cap
->flags1
& QUERY_FUNC_CAP_FLAGS1_FORCE_MAC
) {
550 mlx4_err(dev
, "Force mac is enabled on this port\n");
551 err
= -EPROTONOSUPPORT
;
554 } else if (dev
->caps
.port_type
[gen_or_port
] == MLX4_PORT_TYPE_IB
) {
555 MLX4_GET(field
, outbox
, QUERY_FUNC_CAP_FLAGS0_OFFSET
);
556 if (field
& QUERY_FUNC_CAP_FLAGS0_FORCE_PHY_WQE_GID
) {
557 mlx4_err(dev
, "phy_wqe_gid is enforced on this ib port\n");
558 err
= -EPROTONOSUPPORT
;
563 MLX4_GET(field
, outbox
, QUERY_FUNC_CAP_PHYS_PORT_OFFSET
);
564 func_cap
->physical_port
= field
;
565 if (func_cap
->physical_port
!= gen_or_port
) {
570 if (func_cap
->flags1
& QUERY_FUNC_CAP_VF_ENABLE_QP0
) {
571 MLX4_GET(qkey
, outbox
, QUERY_FUNC_CAP_PRIV_VF_QKEY_OFFSET
);
572 func_cap
->qp0_qkey
= qkey
;
574 func_cap
->qp0_qkey
= 0;
577 MLX4_GET(size
, outbox
, QUERY_FUNC_CAP_QP0_TUNNEL
);
578 func_cap
->qp0_tunnel_qpn
= size
& 0xFFFFFF;
580 MLX4_GET(size
, outbox
, QUERY_FUNC_CAP_QP0_PROXY
);
581 func_cap
->qp0_proxy_qpn
= size
& 0xFFFFFF;
583 MLX4_GET(size
, outbox
, QUERY_FUNC_CAP_QP1_TUNNEL
);
584 func_cap
->qp1_tunnel_qpn
= size
& 0xFFFFFF;
586 MLX4_GET(size
, outbox
, QUERY_FUNC_CAP_QP1_PROXY
);
587 func_cap
->qp1_proxy_qpn
= size
& 0xFFFFFF;
589 if (func_cap
->flags1
& QUERY_FUNC_CAP_FLAGS1_NIC_INFO
)
590 MLX4_GET(func_cap
->phys_port_id
, outbox
,
591 QUERY_FUNC_CAP_PHYS_PORT_ID
);
593 /* All other resources are allocated by the master, but we still report
594 * 'num' and 'reserved' capabilities as follows:
595 * - num remains the maximum resource index
596 * - 'num - reserved' is the total available objects of a resource, but
597 * resource indices may be less than 'reserved'
598 * TODO: set per-resource quotas */
601 mlx4_free_cmd_mailbox(dev
, mailbox
);
606 int mlx4_QUERY_DEV_CAP(struct mlx4_dev
*dev
, struct mlx4_dev_cap
*dev_cap
)
608 struct mlx4_cmd_mailbox
*mailbox
;
611 u32 field32
, flags
, ext_flags
;
617 #define QUERY_DEV_CAP_OUT_SIZE 0x100
618 #define QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET 0x10
619 #define QUERY_DEV_CAP_MAX_QP_SZ_OFFSET 0x11
620 #define QUERY_DEV_CAP_RSVD_QP_OFFSET 0x12
621 #define QUERY_DEV_CAP_MAX_QP_OFFSET 0x13
622 #define QUERY_DEV_CAP_RSVD_SRQ_OFFSET 0x14
623 #define QUERY_DEV_CAP_MAX_SRQ_OFFSET 0x15
624 #define QUERY_DEV_CAP_RSVD_EEC_OFFSET 0x16
625 #define QUERY_DEV_CAP_MAX_EEC_OFFSET 0x17
626 #define QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET 0x19
627 #define QUERY_DEV_CAP_RSVD_CQ_OFFSET 0x1a
628 #define QUERY_DEV_CAP_MAX_CQ_OFFSET 0x1b
629 #define QUERY_DEV_CAP_MAX_MPT_OFFSET 0x1d
630 #define QUERY_DEV_CAP_RSVD_EQ_OFFSET 0x1e
631 #define QUERY_DEV_CAP_MAX_EQ_OFFSET 0x1f
632 #define QUERY_DEV_CAP_RSVD_MTT_OFFSET 0x20
633 #define QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET 0x21
634 #define QUERY_DEV_CAP_RSVD_MRW_OFFSET 0x22
635 #define QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET 0x23
636 #define QUERY_DEV_CAP_NUM_SYS_EQ_OFFSET 0x26
637 #define QUERY_DEV_CAP_MAX_AV_OFFSET 0x27
638 #define QUERY_DEV_CAP_MAX_REQ_QP_OFFSET 0x29
639 #define QUERY_DEV_CAP_MAX_RES_QP_OFFSET 0x2b
640 #define QUERY_DEV_CAP_MAX_GSO_OFFSET 0x2d
641 #define QUERY_DEV_CAP_RSS_OFFSET 0x2e
642 #define QUERY_DEV_CAP_MAX_RDMA_OFFSET 0x2f
643 #define QUERY_DEV_CAP_RSZ_SRQ_OFFSET 0x33
644 #define QUERY_DEV_CAP_ACK_DELAY_OFFSET 0x35
645 #define QUERY_DEV_CAP_MTU_WIDTH_OFFSET 0x36
646 #define QUERY_DEV_CAP_VL_PORT_OFFSET 0x37
647 #define QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET 0x38
648 #define QUERY_DEV_CAP_MAX_GID_OFFSET 0x3b
649 #define QUERY_DEV_CAP_RATE_SUPPORT_OFFSET 0x3c
650 #define QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET 0x3e
651 #define QUERY_DEV_CAP_MAX_PKEY_OFFSET 0x3f
652 #define QUERY_DEV_CAP_EXT_FLAGS_OFFSET 0x40
653 #define QUERY_DEV_CAP_FLAGS_OFFSET 0x44
654 #define QUERY_DEV_CAP_RSVD_UAR_OFFSET 0x48
655 #define QUERY_DEV_CAP_UAR_SZ_OFFSET 0x49
656 #define QUERY_DEV_CAP_PAGE_SZ_OFFSET 0x4b
657 #define QUERY_DEV_CAP_BF_OFFSET 0x4c
658 #define QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET 0x4d
659 #define QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET 0x4e
660 #define QUERY_DEV_CAP_LOG_MAX_BF_PAGES_OFFSET 0x4f
661 #define QUERY_DEV_CAP_MAX_SG_SQ_OFFSET 0x51
662 #define QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET 0x52
663 #define QUERY_DEV_CAP_MAX_SG_RQ_OFFSET 0x55
664 #define QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET 0x56
665 #define QUERY_DEV_CAP_MAX_QP_MCG_OFFSET 0x61
666 #define QUERY_DEV_CAP_RSVD_MCG_OFFSET 0x62
667 #define QUERY_DEV_CAP_MAX_MCG_OFFSET 0x63
668 #define QUERY_DEV_CAP_RSVD_PD_OFFSET 0x64
669 #define QUERY_DEV_CAP_MAX_PD_OFFSET 0x65
670 #define QUERY_DEV_CAP_RSVD_XRC_OFFSET 0x66
671 #define QUERY_DEV_CAP_MAX_XRC_OFFSET 0x67
672 #define QUERY_DEV_CAP_MAX_COUNTERS_OFFSET 0x68
673 #define QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET 0x70
674 #define QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET 0x74
675 #define QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET 0x76
676 #define QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET 0x77
677 #define QUERY_DEV_CAP_CQ_EQ_CACHE_LINE_STRIDE 0x7a
678 #define QUERY_DEV_CAP_ETH_PROT_CTRL_OFFSET 0x7a
679 #define QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET 0x80
680 #define QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET 0x82
681 #define QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET 0x84
682 #define QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET 0x86
683 #define QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET 0x88
684 #define QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET 0x8a
685 #define QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET 0x8c
686 #define QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET 0x8e
687 #define QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET 0x90
688 #define QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET 0x92
689 #define QUERY_DEV_CAP_BMME_FLAGS_OFFSET 0x94
690 #define QUERY_DEV_CAP_CONFIG_DEV_OFFSET 0x94
691 #define QUERY_DEV_CAP_RSVD_LKEY_OFFSET 0x98
692 #define QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET 0xa0
693 #define QUERY_DEV_CAP_ETH_BACKPL_OFFSET 0x9c
694 #define QUERY_DEV_CAP_FW_REASSIGN_MAC 0x9d
695 #define QUERY_DEV_CAP_VXLAN 0x9e
696 #define QUERY_DEV_CAP_MAD_DEMUX_OFFSET 0xb0
697 #define QUERY_DEV_CAP_DMFS_HIGH_RATE_QPN_BASE_OFFSET 0xa8
698 #define QUERY_DEV_CAP_DMFS_HIGH_RATE_QPN_RANGE_OFFSET 0xac
701 mailbox
= mlx4_alloc_cmd_mailbox(dev
);
703 return PTR_ERR(mailbox
);
704 outbox
= mailbox
->buf
;
706 err
= mlx4_cmd_box(dev
, 0, mailbox
->dma
, 0, 0, MLX4_CMD_QUERY_DEV_CAP
,
707 MLX4_CMD_TIME_CLASS_A
, MLX4_CMD_NATIVE
);
711 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_RSVD_QP_OFFSET
);
712 dev_cap
->reserved_qps
= 1 << (field
& 0xf);
713 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_MAX_QP_OFFSET
);
714 dev_cap
->max_qps
= 1 << (field
& 0x1f);
715 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_RSVD_SRQ_OFFSET
);
716 dev_cap
->reserved_srqs
= 1 << (field
>> 4);
717 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_MAX_SRQ_OFFSET
);
718 dev_cap
->max_srqs
= 1 << (field
& 0x1f);
719 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET
);
720 dev_cap
->max_cq_sz
= 1 << field
;
721 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_RSVD_CQ_OFFSET
);
722 dev_cap
->reserved_cqs
= 1 << (field
& 0xf);
723 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_MAX_CQ_OFFSET
);
724 dev_cap
->max_cqs
= 1 << (field
& 0x1f);
725 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_MAX_MPT_OFFSET
);
726 dev_cap
->max_mpts
= 1 << (field
& 0x3f);
727 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_RSVD_EQ_OFFSET
);
728 dev_cap
->reserved_eqs
= 1 << (field
& 0xf);
729 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_MAX_EQ_OFFSET
);
730 dev_cap
->max_eqs
= 1 << (field
& 0xf);
731 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_RSVD_MTT_OFFSET
);
732 dev_cap
->reserved_mtts
= 1 << (field
>> 4);
733 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET
);
734 dev_cap
->max_mrw_sz
= 1 << field
;
735 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_RSVD_MRW_OFFSET
);
736 dev_cap
->reserved_mrws
= 1 << (field
& 0xf);
737 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET
);
738 dev_cap
->max_mtt_seg
= 1 << (field
& 0x3f);
739 MLX4_GET(size
, outbox
, QUERY_DEV_CAP_NUM_SYS_EQ_OFFSET
);
740 dev_cap
->num_sys_eqs
= size
& 0xfff;
741 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_MAX_REQ_QP_OFFSET
);
742 dev_cap
->max_requester_per_qp
= 1 << (field
& 0x3f);
743 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_MAX_RES_QP_OFFSET
);
744 dev_cap
->max_responder_per_qp
= 1 << (field
& 0x3f);
745 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_MAX_GSO_OFFSET
);
748 dev_cap
->max_gso_sz
= 0;
750 dev_cap
->max_gso_sz
= 1 << field
;
752 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_RSS_OFFSET
);
754 dev_cap
->flags2
|= MLX4_DEV_CAP_FLAG2_RSS_XOR
;
756 dev_cap
->flags2
|= MLX4_DEV_CAP_FLAG2_RSS_TOP
;
759 dev_cap
->flags2
|= MLX4_DEV_CAP_FLAG2_RSS
;
760 dev_cap
->max_rss_tbl_sz
= 1 << field
;
762 dev_cap
->max_rss_tbl_sz
= 0;
763 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_MAX_RDMA_OFFSET
);
764 dev_cap
->max_rdma_global
= 1 << (field
& 0x3f);
765 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_ACK_DELAY_OFFSET
);
766 dev_cap
->local_ca_ack_delay
= field
& 0x1f;
767 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_VL_PORT_OFFSET
);
768 dev_cap
->num_ports
= field
& 0xf;
769 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET
);
770 dev_cap
->max_msg_sz
= 1 << (field
& 0x1f);
771 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET
);
773 dev_cap
->flags2
|= MLX4_DEV_CAP_FLAG2_FS_EN
;
774 dev_cap
->fs_log_max_ucast_qp_range_size
= field
& 0x1f;
775 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET
);
777 dev_cap
->flags2
|= MLX4_DEV_CAP_FLAG2_DMFS_IPOIB
;
778 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET
);
779 dev_cap
->fs_max_num_qp_per_entry
= field
;
780 MLX4_GET(stat_rate
, outbox
, QUERY_DEV_CAP_RATE_SUPPORT_OFFSET
);
781 dev_cap
->stat_rate_support
= stat_rate
;
782 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET
);
784 dev_cap
->flags2
|= MLX4_DEV_CAP_FLAG2_TS
;
785 MLX4_GET(ext_flags
, outbox
, QUERY_DEV_CAP_EXT_FLAGS_OFFSET
);
786 MLX4_GET(flags
, outbox
, QUERY_DEV_CAP_FLAGS_OFFSET
);
787 dev_cap
->flags
= flags
| (u64
)ext_flags
<< 32;
788 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_RSVD_UAR_OFFSET
);
789 dev_cap
->reserved_uars
= field
>> 4;
790 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_UAR_SZ_OFFSET
);
791 dev_cap
->uar_size
= 1 << ((field
& 0x3f) + 20);
792 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_PAGE_SZ_OFFSET
);
793 dev_cap
->min_page_sz
= 1 << field
;
795 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_BF_OFFSET
);
797 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET
);
798 dev_cap
->bf_reg_size
= 1 << (field
& 0x1f);
799 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET
);
800 if ((1 << (field
& 0x3f)) > (PAGE_SIZE
/ dev_cap
->bf_reg_size
))
802 dev_cap
->bf_regs_per_page
= 1 << (field
& 0x3f);
804 dev_cap
->bf_reg_size
= 0;
807 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_MAX_SG_SQ_OFFSET
);
808 dev_cap
->max_sq_sg
= field
;
809 MLX4_GET(size
, outbox
, QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET
);
810 dev_cap
->max_sq_desc_sz
= size
;
812 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_MAX_QP_MCG_OFFSET
);
813 dev_cap
->max_qp_per_mcg
= 1 << field
;
814 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_RSVD_MCG_OFFSET
);
815 dev_cap
->reserved_mgms
= field
& 0xf;
816 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_MAX_MCG_OFFSET
);
817 dev_cap
->max_mcgs
= 1 << field
;
818 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_RSVD_PD_OFFSET
);
819 dev_cap
->reserved_pds
= field
>> 4;
820 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_MAX_PD_OFFSET
);
821 dev_cap
->max_pds
= 1 << (field
& 0x3f);
822 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_RSVD_XRC_OFFSET
);
823 dev_cap
->reserved_xrcds
= field
>> 4;
824 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_MAX_XRC_OFFSET
);
825 dev_cap
->max_xrcds
= 1 << (field
& 0x1f);
827 MLX4_GET(size
, outbox
, QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET
);
828 dev_cap
->rdmarc_entry_sz
= size
;
829 MLX4_GET(size
, outbox
, QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET
);
830 dev_cap
->qpc_entry_sz
= size
;
831 MLX4_GET(size
, outbox
, QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET
);
832 dev_cap
->aux_entry_sz
= size
;
833 MLX4_GET(size
, outbox
, QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET
);
834 dev_cap
->altc_entry_sz
= size
;
835 MLX4_GET(size
, outbox
, QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET
);
836 dev_cap
->eqc_entry_sz
= size
;
837 MLX4_GET(size
, outbox
, QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET
);
838 dev_cap
->cqc_entry_sz
= size
;
839 MLX4_GET(size
, outbox
, QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET
);
840 dev_cap
->srq_entry_sz
= size
;
841 MLX4_GET(size
, outbox
, QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET
);
842 dev_cap
->cmpt_entry_sz
= size
;
843 MLX4_GET(size
, outbox
, QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET
);
844 dev_cap
->mtt_entry_sz
= size
;
845 MLX4_GET(size
, outbox
, QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET
);
846 dev_cap
->dmpt_entry_sz
= size
;
848 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET
);
849 dev_cap
->max_srq_sz
= 1 << field
;
850 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_MAX_QP_SZ_OFFSET
);
851 dev_cap
->max_qp_sz
= 1 << field
;
852 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_RSZ_SRQ_OFFSET
);
853 dev_cap
->resize_srq
= field
& 1;
854 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_MAX_SG_RQ_OFFSET
);
855 dev_cap
->max_rq_sg
= field
;
856 MLX4_GET(size
, outbox
, QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET
);
857 dev_cap
->max_rq_desc_sz
= size
;
858 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_CQ_EQ_CACHE_LINE_STRIDE
);
859 if (field
& (1 << 5))
860 dev_cap
->flags2
|= MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL
;
861 if (field
& (1 << 6))
862 dev_cap
->flags2
|= MLX4_DEV_CAP_FLAG2_CQE_STRIDE
;
863 if (field
& (1 << 7))
864 dev_cap
->flags2
|= MLX4_DEV_CAP_FLAG2_EQE_STRIDE
;
865 MLX4_GET(dev_cap
->bmme_flags
, outbox
,
866 QUERY_DEV_CAP_BMME_FLAGS_OFFSET
);
867 if (dev_cap
->bmme_flags
& MLX4_FLAG_PORT_REMAP
)
868 dev_cap
->flags2
|= MLX4_DEV_CAP_FLAG2_PORT_REMAP
;
869 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_CONFIG_DEV_OFFSET
);
871 dev_cap
->flags2
|= MLX4_DEV_CAP_FLAG2_CONFIG_DEV
;
872 MLX4_GET(dev_cap
->reserved_lkey
, outbox
,
873 QUERY_DEV_CAP_RSVD_LKEY_OFFSET
);
874 MLX4_GET(field32
, outbox
, QUERY_DEV_CAP_ETH_BACKPL_OFFSET
);
875 if (field32
& (1 << 0))
876 dev_cap
->flags2
|= MLX4_DEV_CAP_FLAG2_ETH_BACKPL_AN_REP
;
877 if (field32
& (1 << 7))
878 dev_cap
->flags2
|= MLX4_DEV_CAP_FLAG2_RECOVERABLE_ERROR_EVENT
;
879 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_FW_REASSIGN_MAC
);
881 dev_cap
->flags2
|= MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN
;
882 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_VXLAN
);
884 dev_cap
->flags2
|= MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS
;
885 MLX4_GET(dev_cap
->max_icm_sz
, outbox
,
886 QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET
);
887 if (dev_cap
->flags
& MLX4_DEV_CAP_FLAG_COUNTERS
)
888 MLX4_GET(dev_cap
->max_counters
, outbox
,
889 QUERY_DEV_CAP_MAX_COUNTERS_OFFSET
);
891 MLX4_GET(field32
, outbox
,
892 QUERY_DEV_CAP_MAD_DEMUX_OFFSET
);
893 if (field32
& (1 << 0))
894 dev_cap
->flags2
|= MLX4_DEV_CAP_FLAG2_MAD_DEMUX
;
896 MLX4_GET(dev_cap
->dmfs_high_rate_qpn_base
, outbox
,
897 QUERY_DEV_CAP_DMFS_HIGH_RATE_QPN_BASE_OFFSET
);
898 dev_cap
->dmfs_high_rate_qpn_base
&= MGM_QPN_MASK
;
899 MLX4_GET(dev_cap
->dmfs_high_rate_qpn_range
, outbox
,
900 QUERY_DEV_CAP_DMFS_HIGH_RATE_QPN_RANGE_OFFSET
);
901 dev_cap
->dmfs_high_rate_qpn_range
&= MGM_QPN_MASK
;
903 MLX4_GET(field32
, outbox
, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET
);
904 if (field32
& (1 << 16))
905 dev_cap
->flags2
|= MLX4_DEV_CAP_FLAG2_UPDATE_QP
;
906 if (field32
& (1 << 26))
907 dev_cap
->flags2
|= MLX4_DEV_CAP_FLAG2_VLAN_CONTROL
;
908 if (field32
& (1 << 20))
909 dev_cap
->flags2
|= MLX4_DEV_CAP_FLAG2_FSM
;
910 if (field32
& (1 << 21))
911 dev_cap
->flags2
|= MLX4_DEV_CAP_FLAG2_80_VFS
;
913 for (i
= 1; i
<= dev_cap
->num_ports
; i
++) {
914 err
= mlx4_QUERY_PORT(dev
, i
, dev_cap
->port_cap
+ i
);
920 * Each UAR has 4 EQ doorbells; so if a UAR is reserved, then
921 * we can't use any EQs whose doorbell falls on that page,
922 * even if the EQ itself isn't reserved.
924 if (dev_cap
->num_sys_eqs
== 0)
925 dev_cap
->reserved_eqs
= max(dev_cap
->reserved_uars
* 4,
926 dev_cap
->reserved_eqs
);
928 dev_cap
->flags2
|= MLX4_DEV_CAP_FLAG2_SYS_EQS
;
931 mlx4_free_cmd_mailbox(dev
, mailbox
);
935 void mlx4_dev_cap_dump(struct mlx4_dev
*dev
, struct mlx4_dev_cap
*dev_cap
)
937 if (dev_cap
->bf_reg_size
> 0)
938 mlx4_dbg(dev
, "BlueFlame available (reg size %d, regs/page %d)\n",
939 dev_cap
->bf_reg_size
, dev_cap
->bf_regs_per_page
);
941 mlx4_dbg(dev
, "BlueFlame not available\n");
943 mlx4_dbg(dev
, "Base MM extensions: flags %08x, rsvd L_Key %08x\n",
944 dev_cap
->bmme_flags
, dev_cap
->reserved_lkey
);
945 mlx4_dbg(dev
, "Max ICM size %lld MB\n",
946 (unsigned long long) dev_cap
->max_icm_sz
>> 20);
947 mlx4_dbg(dev
, "Max QPs: %d, reserved QPs: %d, entry size: %d\n",
948 dev_cap
->max_qps
, dev_cap
->reserved_qps
, dev_cap
->qpc_entry_sz
);
949 mlx4_dbg(dev
, "Max SRQs: %d, reserved SRQs: %d, entry size: %d\n",
950 dev_cap
->max_srqs
, dev_cap
->reserved_srqs
, dev_cap
->srq_entry_sz
);
951 mlx4_dbg(dev
, "Max CQs: %d, reserved CQs: %d, entry size: %d\n",
952 dev_cap
->max_cqs
, dev_cap
->reserved_cqs
, dev_cap
->cqc_entry_sz
);
953 mlx4_dbg(dev
, "Num sys EQs: %d, max EQs: %d, reserved EQs: %d, entry size: %d\n",
954 dev_cap
->num_sys_eqs
, dev_cap
->max_eqs
, dev_cap
->reserved_eqs
,
955 dev_cap
->eqc_entry_sz
);
956 mlx4_dbg(dev
, "reserved MPTs: %d, reserved MTTs: %d\n",
957 dev_cap
->reserved_mrws
, dev_cap
->reserved_mtts
);
958 mlx4_dbg(dev
, "Max PDs: %d, reserved PDs: %d, reserved UARs: %d\n",
959 dev_cap
->max_pds
, dev_cap
->reserved_pds
, dev_cap
->reserved_uars
);
960 mlx4_dbg(dev
, "Max QP/MCG: %d, reserved MGMs: %d\n",
961 dev_cap
->max_pds
, dev_cap
->reserved_mgms
);
962 mlx4_dbg(dev
, "Max CQEs: %d, max WQEs: %d, max SRQ WQEs: %d\n",
963 dev_cap
->max_cq_sz
, dev_cap
->max_qp_sz
, dev_cap
->max_srq_sz
);
964 mlx4_dbg(dev
, "Local CA ACK delay: %d, max MTU: %d, port width cap: %d\n",
965 dev_cap
->local_ca_ack_delay
, 128 << dev_cap
->port_cap
[1].ib_mtu
,
966 dev_cap
->port_cap
[1].max_port_width
);
967 mlx4_dbg(dev
, "Max SQ desc size: %d, max SQ S/G: %d\n",
968 dev_cap
->max_sq_desc_sz
, dev_cap
->max_sq_sg
);
969 mlx4_dbg(dev
, "Max RQ desc size: %d, max RQ S/G: %d\n",
970 dev_cap
->max_rq_desc_sz
, dev_cap
->max_rq_sg
);
971 mlx4_dbg(dev
, "Max GSO size: %d\n", dev_cap
->max_gso_sz
);
972 mlx4_dbg(dev
, "Max counters: %d\n", dev_cap
->max_counters
);
973 mlx4_dbg(dev
, "Max RSS Table size: %d\n", dev_cap
->max_rss_tbl_sz
);
974 mlx4_dbg(dev
, "DMFS high rate steer QPn base: %d\n",
975 dev_cap
->dmfs_high_rate_qpn_base
);
976 mlx4_dbg(dev
, "DMFS high rate steer QPn range: %d\n",
977 dev_cap
->dmfs_high_rate_qpn_range
);
978 dump_dev_cap_flags(dev
, dev_cap
->flags
);
979 dump_dev_cap_flags2(dev
, dev_cap
->flags2
);
982 int mlx4_QUERY_PORT(struct mlx4_dev
*dev
, int port
, struct mlx4_port_cap
*port_cap
)
984 struct mlx4_cmd_mailbox
*mailbox
;
990 mailbox
= mlx4_alloc_cmd_mailbox(dev
);
992 return PTR_ERR(mailbox
);
993 outbox
= mailbox
->buf
;
995 if (dev
->flags
& MLX4_FLAG_OLD_PORT_CMDS
) {
996 err
= mlx4_cmd_box(dev
, 0, mailbox
->dma
, 0, 0, MLX4_CMD_QUERY_DEV_CAP
,
997 MLX4_CMD_TIME_CLASS_A
,
1003 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_VL_PORT_OFFSET
);
1004 port_cap
->max_vl
= field
>> 4;
1005 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_MTU_WIDTH_OFFSET
);
1006 port_cap
->ib_mtu
= field
>> 4;
1007 port_cap
->max_port_width
= field
& 0xf;
1008 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_MAX_GID_OFFSET
);
1009 port_cap
->max_gids
= 1 << (field
& 0xf);
1010 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_MAX_PKEY_OFFSET
);
1011 port_cap
->max_pkeys
= 1 << (field
& 0xf);
1013 #define QUERY_PORT_SUPPORTED_TYPE_OFFSET 0x00
1014 #define QUERY_PORT_MTU_OFFSET 0x01
1015 #define QUERY_PORT_ETH_MTU_OFFSET 0x02
1016 #define QUERY_PORT_WIDTH_OFFSET 0x06
1017 #define QUERY_PORT_MAX_GID_PKEY_OFFSET 0x07
1018 #define QUERY_PORT_MAX_MACVLAN_OFFSET 0x0a
1019 #define QUERY_PORT_MAX_VL_OFFSET 0x0b
1020 #define QUERY_PORT_MAC_OFFSET 0x10
1021 #define QUERY_PORT_TRANS_VENDOR_OFFSET 0x18
1022 #define QUERY_PORT_WAVELENGTH_OFFSET 0x1c
1023 #define QUERY_PORT_TRANS_CODE_OFFSET 0x20
1025 err
= mlx4_cmd_box(dev
, 0, mailbox
->dma
, port
, 0, MLX4_CMD_QUERY_PORT
,
1026 MLX4_CMD_TIME_CLASS_B
, MLX4_CMD_NATIVE
);
1030 MLX4_GET(field
, outbox
, QUERY_PORT_SUPPORTED_TYPE_OFFSET
);
1031 port_cap
->supported_port_types
= field
& 3;
1032 port_cap
->suggested_type
= (field
>> 3) & 1;
1033 port_cap
->default_sense
= (field
>> 4) & 1;
1034 port_cap
->dmfs_optimized_state
= (field
>> 5) & 1;
1035 MLX4_GET(field
, outbox
, QUERY_PORT_MTU_OFFSET
);
1036 port_cap
->ib_mtu
= field
& 0xf;
1037 MLX4_GET(field
, outbox
, QUERY_PORT_WIDTH_OFFSET
);
1038 port_cap
->max_port_width
= field
& 0xf;
1039 MLX4_GET(field
, outbox
, QUERY_PORT_MAX_GID_PKEY_OFFSET
);
1040 port_cap
->max_gids
= 1 << (field
>> 4);
1041 port_cap
->max_pkeys
= 1 << (field
& 0xf);
1042 MLX4_GET(field
, outbox
, QUERY_PORT_MAX_VL_OFFSET
);
1043 port_cap
->max_vl
= field
& 0xf;
1044 MLX4_GET(field
, outbox
, QUERY_PORT_MAX_MACVLAN_OFFSET
);
1045 port_cap
->log_max_macs
= field
& 0xf;
1046 port_cap
->log_max_vlans
= field
>> 4;
1047 MLX4_GET(port_cap
->eth_mtu
, outbox
, QUERY_PORT_ETH_MTU_OFFSET
);
1048 MLX4_GET(port_cap
->def_mac
, outbox
, QUERY_PORT_MAC_OFFSET
);
1049 MLX4_GET(field32
, outbox
, QUERY_PORT_TRANS_VENDOR_OFFSET
);
1050 port_cap
->trans_type
= field32
>> 24;
1051 port_cap
->vendor_oui
= field32
& 0xffffff;
1052 MLX4_GET(port_cap
->wavelength
, outbox
, QUERY_PORT_WAVELENGTH_OFFSET
);
1053 MLX4_GET(port_cap
->trans_code
, outbox
, QUERY_PORT_TRANS_CODE_OFFSET
);
1057 mlx4_free_cmd_mailbox(dev
, mailbox
);
1061 #define DEV_CAP_EXT_2_FLAG_VLAN_CONTROL (1 << 26)
1062 #define DEV_CAP_EXT_2_FLAG_80_VFS (1 << 21)
1063 #define DEV_CAP_EXT_2_FLAG_FSM (1 << 20)
1065 int mlx4_QUERY_DEV_CAP_wrapper(struct mlx4_dev
*dev
, int slave
,
1066 struct mlx4_vhcr
*vhcr
,
1067 struct mlx4_cmd_mailbox
*inbox
,
1068 struct mlx4_cmd_mailbox
*outbox
,
1069 struct mlx4_cmd_info
*cmd
)
1074 u32 bmme_flags
, field32
;
1078 struct mlx4_active_ports actv_ports
;
1080 err
= mlx4_cmd_box(dev
, 0, outbox
->dma
, 0, 0, MLX4_CMD_QUERY_DEV_CAP
,
1081 MLX4_CMD_TIME_CLASS_A
, MLX4_CMD_NATIVE
);
1085 /* add port mng change event capability and disable mw type 1
1086 * unconditionally to slaves
1088 MLX4_GET(flags
, outbox
->buf
, QUERY_DEV_CAP_EXT_FLAGS_OFFSET
);
1089 flags
|= MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV
;
1090 flags
&= ~MLX4_DEV_CAP_FLAG_MEM_WINDOW
;
1091 actv_ports
= mlx4_get_active_ports(dev
, slave
);
1092 first_port
= find_first_bit(actv_ports
.ports
, dev
->caps
.num_ports
);
1093 for (slave_port
= 0, real_port
= first_port
;
1094 real_port
< first_port
+
1095 bitmap_weight(actv_ports
.ports
, dev
->caps
.num_ports
);
1096 ++real_port
, ++slave_port
) {
1097 if (flags
& (MLX4_DEV_CAP_FLAG_WOL_PORT1
<< real_port
))
1098 flags
|= MLX4_DEV_CAP_FLAG_WOL_PORT1
<< slave_port
;
1100 flags
&= ~(MLX4_DEV_CAP_FLAG_WOL_PORT1
<< slave_port
);
1102 for (; slave_port
< dev
->caps
.num_ports
; ++slave_port
)
1103 flags
&= ~(MLX4_DEV_CAP_FLAG_WOL_PORT1
<< slave_port
);
1104 MLX4_PUT(outbox
->buf
, flags
, QUERY_DEV_CAP_EXT_FLAGS_OFFSET
);
1106 MLX4_GET(field
, outbox
->buf
, QUERY_DEV_CAP_VL_PORT_OFFSET
);
1108 field
|= bitmap_weight(actv_ports
.ports
, dev
->caps
.num_ports
) & 0x0F;
1109 MLX4_PUT(outbox
->buf
, field
, QUERY_DEV_CAP_VL_PORT_OFFSET
);
1111 /* For guests, disable timestamp */
1112 MLX4_GET(field
, outbox
->buf
, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET
);
1114 MLX4_PUT(outbox
->buf
, field
, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET
);
1116 /* For guests, disable vxlan tunneling */
1117 MLX4_GET(field
, outbox
->buf
, QUERY_DEV_CAP_VXLAN
);
1119 MLX4_PUT(outbox
->buf
, field
, QUERY_DEV_CAP_VXLAN
);
1121 /* For guests, report Blueflame disabled */
1122 MLX4_GET(field
, outbox
->buf
, QUERY_DEV_CAP_BF_OFFSET
);
1124 MLX4_PUT(outbox
->buf
, field
, QUERY_DEV_CAP_BF_OFFSET
);
1126 /* For guests, disable mw type 2 and port remap*/
1127 MLX4_GET(bmme_flags
, outbox
->buf
, QUERY_DEV_CAP_BMME_FLAGS_OFFSET
);
1128 bmme_flags
&= ~MLX4_BMME_FLAG_TYPE_2_WIN
;
1129 bmme_flags
&= ~MLX4_FLAG_PORT_REMAP
;
1130 MLX4_PUT(outbox
->buf
, bmme_flags
, QUERY_DEV_CAP_BMME_FLAGS_OFFSET
);
1132 /* turn off device-managed steering capability if not enabled */
1133 if (dev
->caps
.steering_mode
!= MLX4_STEERING_MODE_DEVICE_MANAGED
) {
1134 MLX4_GET(field
, outbox
->buf
,
1135 QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET
);
1137 MLX4_PUT(outbox
->buf
, field
,
1138 QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET
);
1141 /* turn off ipoib managed steering for guests */
1142 MLX4_GET(field
, outbox
->buf
, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET
);
1144 MLX4_PUT(outbox
->buf
, field
, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET
);
1146 /* turn off host side virt features (VST, FSM, etc) for guests */
1147 MLX4_GET(field32
, outbox
->buf
, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET
);
1148 field32
&= ~(DEV_CAP_EXT_2_FLAG_VLAN_CONTROL
| DEV_CAP_EXT_2_FLAG_80_VFS
|
1149 DEV_CAP_EXT_2_FLAG_FSM
);
1150 MLX4_PUT(outbox
->buf
, field32
, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET
);
1155 int mlx4_QUERY_PORT_wrapper(struct mlx4_dev
*dev
, int slave
,
1156 struct mlx4_vhcr
*vhcr
,
1157 struct mlx4_cmd_mailbox
*inbox
,
1158 struct mlx4_cmd_mailbox
*outbox
,
1159 struct mlx4_cmd_info
*cmd
)
1161 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1166 int admin_link_state
;
1167 int port
= mlx4_slave_convert_port(dev
, slave
,
1168 vhcr
->in_modifier
& 0xFF);
1170 #define MLX4_VF_PORT_NO_LINK_SENSE_MASK 0xE0
1171 #define MLX4_PORT_LINK_UP_MASK 0x80
1172 #define QUERY_PORT_CUR_MAX_PKEY_OFFSET 0x0c
1173 #define QUERY_PORT_CUR_MAX_GID_OFFSET 0x0e
1178 /* Protect against untrusted guests: enforce that this is the
1179 * QUERY_PORT general query.
1181 if (vhcr
->op_modifier
|| vhcr
->in_modifier
& ~0xFF)
1184 vhcr
->in_modifier
= port
;
1186 err
= mlx4_cmd_box(dev
, 0, outbox
->dma
, vhcr
->in_modifier
, 0,
1187 MLX4_CMD_QUERY_PORT
, MLX4_CMD_TIME_CLASS_B
,
1190 if (!err
&& dev
->caps
.function
!= slave
) {
1191 def_mac
= priv
->mfunc
.master
.vf_oper
[slave
].vport
[vhcr
->in_modifier
].state
.mac
;
1192 MLX4_PUT(outbox
->buf
, def_mac
, QUERY_PORT_MAC_OFFSET
);
1194 /* get port type - currently only eth is enabled */
1195 MLX4_GET(port_type
, outbox
->buf
,
1196 QUERY_PORT_SUPPORTED_TYPE_OFFSET
);
1198 /* No link sensing allowed */
1199 port_type
&= MLX4_VF_PORT_NO_LINK_SENSE_MASK
;
1200 /* set port type to currently operating port type */
1201 port_type
|= (dev
->caps
.port_type
[vhcr
->in_modifier
] & 0x3);
1203 admin_link_state
= priv
->mfunc
.master
.vf_oper
[slave
].vport
[vhcr
->in_modifier
].state
.link_state
;
1204 if (IFLA_VF_LINK_STATE_ENABLE
== admin_link_state
)
1205 port_type
|= MLX4_PORT_LINK_UP_MASK
;
1206 else if (IFLA_VF_LINK_STATE_DISABLE
== admin_link_state
)
1207 port_type
&= ~MLX4_PORT_LINK_UP_MASK
;
1209 MLX4_PUT(outbox
->buf
, port_type
,
1210 QUERY_PORT_SUPPORTED_TYPE_OFFSET
);
1212 if (dev
->caps
.port_type
[vhcr
->in_modifier
] == MLX4_PORT_TYPE_ETH
)
1213 short_field
= mlx4_get_slave_num_gids(dev
, slave
, port
);
1215 short_field
= 1; /* slave max gids */
1216 MLX4_PUT(outbox
->buf
, short_field
,
1217 QUERY_PORT_CUR_MAX_GID_OFFSET
);
1219 short_field
= dev
->caps
.pkey_table_len
[vhcr
->in_modifier
];
1220 MLX4_PUT(outbox
->buf
, short_field
,
1221 QUERY_PORT_CUR_MAX_PKEY_OFFSET
);
1227 int mlx4_get_slave_pkey_gid_tbl_len(struct mlx4_dev
*dev
, u8 port
,
1228 int *gid_tbl_len
, int *pkey_tbl_len
)
1230 struct mlx4_cmd_mailbox
*mailbox
;
1235 mailbox
= mlx4_alloc_cmd_mailbox(dev
);
1236 if (IS_ERR(mailbox
))
1237 return PTR_ERR(mailbox
);
1239 err
= mlx4_cmd_box(dev
, 0, mailbox
->dma
, port
, 0,
1240 MLX4_CMD_QUERY_PORT
, MLX4_CMD_TIME_CLASS_B
,
1245 outbox
= mailbox
->buf
;
1247 MLX4_GET(field
, outbox
, QUERY_PORT_CUR_MAX_GID_OFFSET
);
1248 *gid_tbl_len
= field
;
1250 MLX4_GET(field
, outbox
, QUERY_PORT_CUR_MAX_PKEY_OFFSET
);
1251 *pkey_tbl_len
= field
;
1254 mlx4_free_cmd_mailbox(dev
, mailbox
);
1257 EXPORT_SYMBOL(mlx4_get_slave_pkey_gid_tbl_len
);
1259 int mlx4_map_cmd(struct mlx4_dev
*dev
, u16 op
, struct mlx4_icm
*icm
, u64 virt
)
1261 struct mlx4_cmd_mailbox
*mailbox
;
1262 struct mlx4_icm_iter iter
;
1270 mailbox
= mlx4_alloc_cmd_mailbox(dev
);
1271 if (IS_ERR(mailbox
))
1272 return PTR_ERR(mailbox
);
1273 pages
= mailbox
->buf
;
1275 for (mlx4_icm_first(icm
, &iter
);
1276 !mlx4_icm_last(&iter
);
1277 mlx4_icm_next(&iter
)) {
1279 * We have to pass pages that are aligned to their
1280 * size, so find the least significant 1 in the
1281 * address or size and use that as our log2 size.
1283 lg
= ffs(mlx4_icm_addr(&iter
) | mlx4_icm_size(&iter
)) - 1;
1284 if (lg
< MLX4_ICM_PAGE_SHIFT
) {
1285 mlx4_warn(dev
, "Got FW area not aligned to %d (%llx/%lx)\n",
1287 (unsigned long long) mlx4_icm_addr(&iter
),
1288 mlx4_icm_size(&iter
));
1293 for (i
= 0; i
< mlx4_icm_size(&iter
) >> lg
; ++i
) {
1295 pages
[nent
* 2] = cpu_to_be64(virt
);
1299 pages
[nent
* 2 + 1] =
1300 cpu_to_be64((mlx4_icm_addr(&iter
) + (i
<< lg
)) |
1301 (lg
- MLX4_ICM_PAGE_SHIFT
));
1302 ts
+= 1 << (lg
- 10);
1305 if (++nent
== MLX4_MAILBOX_SIZE
/ 16) {
1306 err
= mlx4_cmd(dev
, mailbox
->dma
, nent
, 0, op
,
1307 MLX4_CMD_TIME_CLASS_B
,
1317 err
= mlx4_cmd(dev
, mailbox
->dma
, nent
, 0, op
,
1318 MLX4_CMD_TIME_CLASS_B
, MLX4_CMD_NATIVE
);
1323 case MLX4_CMD_MAP_FA
:
1324 mlx4_dbg(dev
, "Mapped %d chunks/%d KB for FW\n", tc
, ts
);
1326 case MLX4_CMD_MAP_ICM_AUX
:
1327 mlx4_dbg(dev
, "Mapped %d chunks/%d KB for ICM aux\n", tc
, ts
);
1329 case MLX4_CMD_MAP_ICM
:
1330 mlx4_dbg(dev
, "Mapped %d chunks/%d KB at %llx for ICM\n",
1331 tc
, ts
, (unsigned long long) virt
- (ts
<< 10));
1336 mlx4_free_cmd_mailbox(dev
, mailbox
);
1340 int mlx4_MAP_FA(struct mlx4_dev
*dev
, struct mlx4_icm
*icm
)
1342 return mlx4_map_cmd(dev
, MLX4_CMD_MAP_FA
, icm
, -1);
1345 int mlx4_UNMAP_FA(struct mlx4_dev
*dev
)
1347 return mlx4_cmd(dev
, 0, 0, 0, MLX4_CMD_UNMAP_FA
,
1348 MLX4_CMD_TIME_CLASS_B
, MLX4_CMD_NATIVE
);
1352 int mlx4_RUN_FW(struct mlx4_dev
*dev
)
1354 return mlx4_cmd(dev
, 0, 0, 0, MLX4_CMD_RUN_FW
,
1355 MLX4_CMD_TIME_CLASS_A
, MLX4_CMD_NATIVE
);
1358 int mlx4_QUERY_FW(struct mlx4_dev
*dev
)
1360 struct mlx4_fw
*fw
= &mlx4_priv(dev
)->fw
;
1361 struct mlx4_cmd
*cmd
= &mlx4_priv(dev
)->cmd
;
1362 struct mlx4_cmd_mailbox
*mailbox
;
1369 #define QUERY_FW_OUT_SIZE 0x100
1370 #define QUERY_FW_VER_OFFSET 0x00
1371 #define QUERY_FW_PPF_ID 0x09
1372 #define QUERY_FW_CMD_IF_REV_OFFSET 0x0a
1373 #define QUERY_FW_MAX_CMD_OFFSET 0x0f
1374 #define QUERY_FW_ERR_START_OFFSET 0x30
1375 #define QUERY_FW_ERR_SIZE_OFFSET 0x38
1376 #define QUERY_FW_ERR_BAR_OFFSET 0x3c
1378 #define QUERY_FW_SIZE_OFFSET 0x00
1379 #define QUERY_FW_CLR_INT_BASE_OFFSET 0x20
1380 #define QUERY_FW_CLR_INT_BAR_OFFSET 0x28
1382 #define QUERY_FW_COMM_BASE_OFFSET 0x40
1383 #define QUERY_FW_COMM_BAR_OFFSET 0x48
1385 #define QUERY_FW_CLOCK_OFFSET 0x50
1386 #define QUERY_FW_CLOCK_BAR 0x58
1388 mailbox
= mlx4_alloc_cmd_mailbox(dev
);
1389 if (IS_ERR(mailbox
))
1390 return PTR_ERR(mailbox
);
1391 outbox
= mailbox
->buf
;
1393 err
= mlx4_cmd_box(dev
, 0, mailbox
->dma
, 0, 0, MLX4_CMD_QUERY_FW
,
1394 MLX4_CMD_TIME_CLASS_A
, MLX4_CMD_NATIVE
);
1398 MLX4_GET(fw_ver
, outbox
, QUERY_FW_VER_OFFSET
);
1400 * FW subminor version is at more significant bits than minor
1401 * version, so swap here.
1403 dev
->caps
.fw_ver
= (fw_ver
& 0xffff00000000ull
) |
1404 ((fw_ver
& 0xffff0000ull
) >> 16) |
1405 ((fw_ver
& 0x0000ffffull
) << 16);
1407 MLX4_GET(lg
, outbox
, QUERY_FW_PPF_ID
);
1408 dev
->caps
.function
= lg
;
1410 if (mlx4_is_slave(dev
))
1414 MLX4_GET(cmd_if_rev
, outbox
, QUERY_FW_CMD_IF_REV_OFFSET
);
1415 if (cmd_if_rev
< MLX4_COMMAND_INTERFACE_MIN_REV
||
1416 cmd_if_rev
> MLX4_COMMAND_INTERFACE_MAX_REV
) {
1417 mlx4_err(dev
, "Installed FW has unsupported command interface revision %d\n",
1419 mlx4_err(dev
, "(Installed FW version is %d.%d.%03d)\n",
1420 (int) (dev
->caps
.fw_ver
>> 32),
1421 (int) (dev
->caps
.fw_ver
>> 16) & 0xffff,
1422 (int) dev
->caps
.fw_ver
& 0xffff);
1423 mlx4_err(dev
, "This driver version supports only revisions %d to %d\n",
1424 MLX4_COMMAND_INTERFACE_MIN_REV
, MLX4_COMMAND_INTERFACE_MAX_REV
);
1429 if (cmd_if_rev
< MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS
)
1430 dev
->flags
|= MLX4_FLAG_OLD_PORT_CMDS
;
1432 MLX4_GET(lg
, outbox
, QUERY_FW_MAX_CMD_OFFSET
);
1433 cmd
->max_cmds
= 1 << lg
;
1435 mlx4_dbg(dev
, "FW version %d.%d.%03d (cmd intf rev %d), max commands %d\n",
1436 (int) (dev
->caps
.fw_ver
>> 32),
1437 (int) (dev
->caps
.fw_ver
>> 16) & 0xffff,
1438 (int) dev
->caps
.fw_ver
& 0xffff,
1439 cmd_if_rev
, cmd
->max_cmds
);
1441 MLX4_GET(fw
->catas_offset
, outbox
, QUERY_FW_ERR_START_OFFSET
);
1442 MLX4_GET(fw
->catas_size
, outbox
, QUERY_FW_ERR_SIZE_OFFSET
);
1443 MLX4_GET(fw
->catas_bar
, outbox
, QUERY_FW_ERR_BAR_OFFSET
);
1444 fw
->catas_bar
= (fw
->catas_bar
>> 6) * 2;
1446 mlx4_dbg(dev
, "Catastrophic error buffer at 0x%llx, size 0x%x, BAR %d\n",
1447 (unsigned long long) fw
->catas_offset
, fw
->catas_size
, fw
->catas_bar
);
1449 MLX4_GET(fw
->fw_pages
, outbox
, QUERY_FW_SIZE_OFFSET
);
1450 MLX4_GET(fw
->clr_int_base
, outbox
, QUERY_FW_CLR_INT_BASE_OFFSET
);
1451 MLX4_GET(fw
->clr_int_bar
, outbox
, QUERY_FW_CLR_INT_BAR_OFFSET
);
1452 fw
->clr_int_bar
= (fw
->clr_int_bar
>> 6) * 2;
1454 MLX4_GET(fw
->comm_base
, outbox
, QUERY_FW_COMM_BASE_OFFSET
);
1455 MLX4_GET(fw
->comm_bar
, outbox
, QUERY_FW_COMM_BAR_OFFSET
);
1456 fw
->comm_bar
= (fw
->comm_bar
>> 6) * 2;
1457 mlx4_dbg(dev
, "Communication vector bar:%d offset:0x%llx\n",
1458 fw
->comm_bar
, fw
->comm_base
);
1459 mlx4_dbg(dev
, "FW size %d KB\n", fw
->fw_pages
>> 2);
1461 MLX4_GET(fw
->clock_offset
, outbox
, QUERY_FW_CLOCK_OFFSET
);
1462 MLX4_GET(fw
->clock_bar
, outbox
, QUERY_FW_CLOCK_BAR
);
1463 fw
->clock_bar
= (fw
->clock_bar
>> 6) * 2;
1464 mlx4_dbg(dev
, "Internal clock bar:%d offset:0x%llx\n",
1465 fw
->clock_bar
, fw
->clock_offset
);
1468 * Round up number of system pages needed in case
1469 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE.
1472 ALIGN(fw
->fw_pages
, PAGE_SIZE
/ MLX4_ICM_PAGE_SIZE
) >>
1473 (PAGE_SHIFT
- MLX4_ICM_PAGE_SHIFT
);
1475 mlx4_dbg(dev
, "Clear int @ %llx, BAR %d\n",
1476 (unsigned long long) fw
->clr_int_base
, fw
->clr_int_bar
);
1479 mlx4_free_cmd_mailbox(dev
, mailbox
);
1483 int mlx4_QUERY_FW_wrapper(struct mlx4_dev
*dev
, int slave
,
1484 struct mlx4_vhcr
*vhcr
,
1485 struct mlx4_cmd_mailbox
*inbox
,
1486 struct mlx4_cmd_mailbox
*outbox
,
1487 struct mlx4_cmd_info
*cmd
)
1492 outbuf
= outbox
->buf
;
1493 err
= mlx4_cmd_box(dev
, 0, outbox
->dma
, 0, 0, MLX4_CMD_QUERY_FW
,
1494 MLX4_CMD_TIME_CLASS_A
, MLX4_CMD_NATIVE
);
1498 /* for slaves, set pci PPF ID to invalid and zero out everything
1499 * else except FW version */
1500 outbuf
[0] = outbuf
[1] = 0;
1501 memset(&outbuf
[8], 0, QUERY_FW_OUT_SIZE
- 8);
1502 outbuf
[QUERY_FW_PPF_ID
] = MLX4_INVALID_SLAVE_ID
;
1507 static void get_board_id(void *vsd
, char *board_id
)
1511 #define VSD_OFFSET_SIG1 0x00
1512 #define VSD_OFFSET_SIG2 0xde
1513 #define VSD_OFFSET_MLX_BOARD_ID 0xd0
1514 #define VSD_OFFSET_TS_BOARD_ID 0x20
1516 #define VSD_SIGNATURE_TOPSPIN 0x5ad
1518 memset(board_id
, 0, MLX4_BOARD_ID_LEN
);
1520 if (be16_to_cpup(vsd
+ VSD_OFFSET_SIG1
) == VSD_SIGNATURE_TOPSPIN
&&
1521 be16_to_cpup(vsd
+ VSD_OFFSET_SIG2
) == VSD_SIGNATURE_TOPSPIN
) {
1522 strlcpy(board_id
, vsd
+ VSD_OFFSET_TS_BOARD_ID
, MLX4_BOARD_ID_LEN
);
1525 * The board ID is a string but the firmware byte
1526 * swaps each 4-byte word before passing it back to
1527 * us. Therefore we need to swab it before printing.
1529 for (i
= 0; i
< 4; ++i
)
1530 ((u32
*) board_id
)[i
] =
1531 swab32(*(u32
*) (vsd
+ VSD_OFFSET_MLX_BOARD_ID
+ i
* 4));
1535 int mlx4_QUERY_ADAPTER(struct mlx4_dev
*dev
, struct mlx4_adapter
*adapter
)
1537 struct mlx4_cmd_mailbox
*mailbox
;
1541 #define QUERY_ADAPTER_OUT_SIZE 0x100
1542 #define QUERY_ADAPTER_INTA_PIN_OFFSET 0x10
1543 #define QUERY_ADAPTER_VSD_OFFSET 0x20
1545 mailbox
= mlx4_alloc_cmd_mailbox(dev
);
1546 if (IS_ERR(mailbox
))
1547 return PTR_ERR(mailbox
);
1548 outbox
= mailbox
->buf
;
1550 err
= mlx4_cmd_box(dev
, 0, mailbox
->dma
, 0, 0, MLX4_CMD_QUERY_ADAPTER
,
1551 MLX4_CMD_TIME_CLASS_A
, MLX4_CMD_NATIVE
);
1555 MLX4_GET(adapter
->inta_pin
, outbox
, QUERY_ADAPTER_INTA_PIN_OFFSET
);
1557 get_board_id(outbox
+ QUERY_ADAPTER_VSD_OFFSET
/ 4,
1561 mlx4_free_cmd_mailbox(dev
, mailbox
);
1565 int mlx4_INIT_HCA(struct mlx4_dev
*dev
, struct mlx4_init_hca_param
*param
)
1567 struct mlx4_cmd_mailbox
*mailbox
;
1570 static const u8 a0_dmfs_hw_steering
[] = {
1571 [MLX4_STEERING_DMFS_A0_DEFAULT
] = 0,
1572 [MLX4_STEERING_DMFS_A0_DYNAMIC
] = 1,
1573 [MLX4_STEERING_DMFS_A0_STATIC
] = 2,
1574 [MLX4_STEERING_DMFS_A0_DISABLE
] = 3
1577 #define INIT_HCA_IN_SIZE 0x200
1578 #define INIT_HCA_VERSION_OFFSET 0x000
1579 #define INIT_HCA_VERSION 2
1580 #define INIT_HCA_VXLAN_OFFSET 0x0c
1581 #define INIT_HCA_CACHELINE_SZ_OFFSET 0x0e
1582 #define INIT_HCA_FLAGS_OFFSET 0x014
1583 #define INIT_HCA_RECOVERABLE_ERROR_EVENT_OFFSET 0x018
1584 #define INIT_HCA_QPC_OFFSET 0x020
1585 #define INIT_HCA_QPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x10)
1586 #define INIT_HCA_LOG_QP_OFFSET (INIT_HCA_QPC_OFFSET + 0x17)
1587 #define INIT_HCA_SRQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x28)
1588 #define INIT_HCA_LOG_SRQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x2f)
1589 #define INIT_HCA_CQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x30)
1590 #define INIT_HCA_LOG_CQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x37)
1591 #define INIT_HCA_EQE_CQE_OFFSETS (INIT_HCA_QPC_OFFSET + 0x38)
1592 #define INIT_HCA_EQE_CQE_STRIDE_OFFSET (INIT_HCA_QPC_OFFSET + 0x3b)
1593 #define INIT_HCA_ALTC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x40)
1594 #define INIT_HCA_AUXC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x50)
1595 #define INIT_HCA_EQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x60)
1596 #define INIT_HCA_LOG_EQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x67)
1597 #define INIT_HCA_NUM_SYS_EQS_OFFSET (INIT_HCA_QPC_OFFSET + 0x6a)
1598 #define INIT_HCA_RDMARC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x70)
1599 #define INIT_HCA_LOG_RD_OFFSET (INIT_HCA_QPC_OFFSET + 0x77)
1600 #define INIT_HCA_MCAST_OFFSET 0x0c0
1601 #define INIT_HCA_MC_BASE_OFFSET (INIT_HCA_MCAST_OFFSET + 0x00)
1602 #define INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x12)
1603 #define INIT_HCA_LOG_MC_HASH_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x16)
1604 #define INIT_HCA_UC_STEERING_OFFSET (INIT_HCA_MCAST_OFFSET + 0x18)
1605 #define INIT_HCA_LOG_MC_TABLE_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x1b)
1606 #define INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN 0x6
1607 #define INIT_HCA_FS_PARAM_OFFSET 0x1d0
1608 #define INIT_HCA_FS_BASE_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x00)
1609 #define INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x12)
1610 #define INIT_HCA_FS_A0_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x18)
1611 #define INIT_HCA_FS_LOG_TABLE_SZ_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x1b)
1612 #define INIT_HCA_FS_ETH_BITS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x21)
1613 #define INIT_HCA_FS_ETH_NUM_ADDRS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x22)
1614 #define INIT_HCA_FS_IB_BITS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x25)
1615 #define INIT_HCA_FS_IB_NUM_ADDRS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x26)
1616 #define INIT_HCA_TPT_OFFSET 0x0f0
1617 #define INIT_HCA_DMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x00)
1618 #define INIT_HCA_TPT_MW_OFFSET (INIT_HCA_TPT_OFFSET + 0x08)
1619 #define INIT_HCA_LOG_MPT_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x0b)
1620 #define INIT_HCA_MTT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x10)
1621 #define INIT_HCA_CMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x18)
1622 #define INIT_HCA_UAR_OFFSET 0x120
1623 #define INIT_HCA_LOG_UAR_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0a)
1624 #define INIT_HCA_UAR_PAGE_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0b)
1626 mailbox
= mlx4_alloc_cmd_mailbox(dev
);
1627 if (IS_ERR(mailbox
))
1628 return PTR_ERR(mailbox
);
1629 inbox
= mailbox
->buf
;
1631 *((u8
*) mailbox
->buf
+ INIT_HCA_VERSION_OFFSET
) = INIT_HCA_VERSION
;
1633 *((u8
*) mailbox
->buf
+ INIT_HCA_CACHELINE_SZ_OFFSET
) =
1634 (ilog2(cache_line_size()) - 4) << 5;
1636 #if defined(__LITTLE_ENDIAN)
1637 *(inbox
+ INIT_HCA_FLAGS_OFFSET
/ 4) &= ~cpu_to_be32(1 << 1);
1638 #elif defined(__BIG_ENDIAN)
1639 *(inbox
+ INIT_HCA_FLAGS_OFFSET
/ 4) |= cpu_to_be32(1 << 1);
1641 #error Host endianness not defined
1643 /* Check port for UD address vector: */
1644 *(inbox
+ INIT_HCA_FLAGS_OFFSET
/ 4) |= cpu_to_be32(1);
1646 /* Enable IPoIB checksumming if we can: */
1647 if (dev
->caps
.flags
& MLX4_DEV_CAP_FLAG_IPOIB_CSUM
)
1648 *(inbox
+ INIT_HCA_FLAGS_OFFSET
/ 4) |= cpu_to_be32(1 << 3);
1650 /* Enable QoS support if module parameter set */
1652 *(inbox
+ INIT_HCA_FLAGS_OFFSET
/ 4) |= cpu_to_be32(1 << 2);
1654 /* enable counters */
1655 if (dev
->caps
.flags
& MLX4_DEV_CAP_FLAG_COUNTERS
)
1656 *(inbox
+ INIT_HCA_FLAGS_OFFSET
/ 4) |= cpu_to_be32(1 << 4);
1658 /* CX3 is capable of extending CQEs/EQEs from 32 to 64 bytes */
1659 if (dev
->caps
.flags
& MLX4_DEV_CAP_FLAG_64B_EQE
) {
1660 *(inbox
+ INIT_HCA_EQE_CQE_OFFSETS
/ 4) |= cpu_to_be32(1 << 29);
1661 dev
->caps
.eqe_size
= 64;
1662 dev
->caps
.eqe_factor
= 1;
1664 dev
->caps
.eqe_size
= 32;
1665 dev
->caps
.eqe_factor
= 0;
1668 if (dev
->caps
.flags
& MLX4_DEV_CAP_FLAG_64B_CQE
) {
1669 *(inbox
+ INIT_HCA_EQE_CQE_OFFSETS
/ 4) |= cpu_to_be32(1 << 30);
1670 dev
->caps
.cqe_size
= 64;
1671 dev
->caps
.userspace_caps
|= MLX4_USER_DEV_CAP_LARGE_CQE
;
1673 dev
->caps
.cqe_size
= 32;
1676 /* CX3 is capable of extending CQEs\EQEs to strides larger than 64B */
1677 if ((dev
->caps
.flags2
& MLX4_DEV_CAP_FLAG2_EQE_STRIDE
) &&
1678 (dev
->caps
.flags2
& MLX4_DEV_CAP_FLAG2_CQE_STRIDE
)) {
1679 dev
->caps
.eqe_size
= cache_line_size();
1680 dev
->caps
.cqe_size
= cache_line_size();
1681 dev
->caps
.eqe_factor
= 0;
1682 MLX4_PUT(inbox
, (u8
)((ilog2(dev
->caps
.eqe_size
) - 5) << 4 |
1683 (ilog2(dev
->caps
.eqe_size
) - 5)),
1684 INIT_HCA_EQE_CQE_STRIDE_OFFSET
);
1686 /* User still need to know to support CQE > 32B */
1687 dev
->caps
.userspace_caps
|= MLX4_USER_DEV_CAP_LARGE_CQE
;
1690 if (dev
->caps
.flags2
& MLX4_DEV_CAP_FLAG2_RECOVERABLE_ERROR_EVENT
)
1691 *(inbox
+ INIT_HCA_RECOVERABLE_ERROR_EVENT_OFFSET
/ 4) |= cpu_to_be32(1 << 31);
1693 /* QPC/EEC/CQC/EQC/RDMARC attributes */
1695 MLX4_PUT(inbox
, param
->qpc_base
, INIT_HCA_QPC_BASE_OFFSET
);
1696 MLX4_PUT(inbox
, param
->log_num_qps
, INIT_HCA_LOG_QP_OFFSET
);
1697 MLX4_PUT(inbox
, param
->srqc_base
, INIT_HCA_SRQC_BASE_OFFSET
);
1698 MLX4_PUT(inbox
, param
->log_num_srqs
, INIT_HCA_LOG_SRQ_OFFSET
);
1699 MLX4_PUT(inbox
, param
->cqc_base
, INIT_HCA_CQC_BASE_OFFSET
);
1700 MLX4_PUT(inbox
, param
->log_num_cqs
, INIT_HCA_LOG_CQ_OFFSET
);
1701 MLX4_PUT(inbox
, param
->altc_base
, INIT_HCA_ALTC_BASE_OFFSET
);
1702 MLX4_PUT(inbox
, param
->auxc_base
, INIT_HCA_AUXC_BASE_OFFSET
);
1703 MLX4_PUT(inbox
, param
->eqc_base
, INIT_HCA_EQC_BASE_OFFSET
);
1704 MLX4_PUT(inbox
, param
->log_num_eqs
, INIT_HCA_LOG_EQ_OFFSET
);
1705 MLX4_PUT(inbox
, param
->num_sys_eqs
, INIT_HCA_NUM_SYS_EQS_OFFSET
);
1706 MLX4_PUT(inbox
, param
->rdmarc_base
, INIT_HCA_RDMARC_BASE_OFFSET
);
1707 MLX4_PUT(inbox
, param
->log_rd_per_qp
, INIT_HCA_LOG_RD_OFFSET
);
1709 /* steering attributes */
1710 if (dev
->caps
.steering_mode
==
1711 MLX4_STEERING_MODE_DEVICE_MANAGED
) {
1712 *(inbox
+ INIT_HCA_FLAGS_OFFSET
/ 4) |=
1714 INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN
);
1716 MLX4_PUT(inbox
, param
->mc_base
, INIT_HCA_FS_BASE_OFFSET
);
1717 MLX4_PUT(inbox
, param
->log_mc_entry_sz
,
1718 INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET
);
1719 MLX4_PUT(inbox
, param
->log_mc_table_sz
,
1720 INIT_HCA_FS_LOG_TABLE_SZ_OFFSET
);
1721 /* Enable Ethernet flow steering
1722 * with udp unicast and tcp unicast
1724 if (dev
->caps
.dmfs_high_steer_mode
!=
1725 MLX4_STEERING_DMFS_A0_STATIC
)
1727 (u8
)(MLX4_FS_UDP_UC_EN
| MLX4_FS_TCP_UC_EN
),
1728 INIT_HCA_FS_ETH_BITS_OFFSET
);
1729 MLX4_PUT(inbox
, (u16
) MLX4_FS_NUM_OF_L2_ADDR
,
1730 INIT_HCA_FS_ETH_NUM_ADDRS_OFFSET
);
1731 /* Enable IPoIB flow steering
1732 * with udp unicast and tcp unicast
1734 MLX4_PUT(inbox
, (u8
) (MLX4_FS_UDP_UC_EN
| MLX4_FS_TCP_UC_EN
),
1735 INIT_HCA_FS_IB_BITS_OFFSET
);
1736 MLX4_PUT(inbox
, (u16
) MLX4_FS_NUM_OF_L2_ADDR
,
1737 INIT_HCA_FS_IB_NUM_ADDRS_OFFSET
);
1739 if (dev
->caps
.dmfs_high_steer_mode
!=
1740 MLX4_STEERING_DMFS_A0_NOT_SUPPORTED
)
1742 ((u8
)(a0_dmfs_hw_steering
[dev
->caps
.dmfs_high_steer_mode
]
1744 INIT_HCA_FS_A0_OFFSET
);
1746 MLX4_PUT(inbox
, param
->mc_base
, INIT_HCA_MC_BASE_OFFSET
);
1747 MLX4_PUT(inbox
, param
->log_mc_entry_sz
,
1748 INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET
);
1749 MLX4_PUT(inbox
, param
->log_mc_hash_sz
,
1750 INIT_HCA_LOG_MC_HASH_SZ_OFFSET
);
1751 MLX4_PUT(inbox
, param
->log_mc_table_sz
,
1752 INIT_HCA_LOG_MC_TABLE_SZ_OFFSET
);
1753 if (dev
->caps
.steering_mode
== MLX4_STEERING_MODE_B0
)
1754 MLX4_PUT(inbox
, (u8
) (1 << 3),
1755 INIT_HCA_UC_STEERING_OFFSET
);
1758 /* TPT attributes */
1760 MLX4_PUT(inbox
, param
->dmpt_base
, INIT_HCA_DMPT_BASE_OFFSET
);
1761 MLX4_PUT(inbox
, param
->mw_enabled
, INIT_HCA_TPT_MW_OFFSET
);
1762 MLX4_PUT(inbox
, param
->log_mpt_sz
, INIT_HCA_LOG_MPT_SZ_OFFSET
);
1763 MLX4_PUT(inbox
, param
->mtt_base
, INIT_HCA_MTT_BASE_OFFSET
);
1764 MLX4_PUT(inbox
, param
->cmpt_base
, INIT_HCA_CMPT_BASE_OFFSET
);
1766 /* UAR attributes */
1768 MLX4_PUT(inbox
, param
->uar_page_sz
, INIT_HCA_UAR_PAGE_SZ_OFFSET
);
1769 MLX4_PUT(inbox
, param
->log_uar_sz
, INIT_HCA_LOG_UAR_SZ_OFFSET
);
1771 /* set parser VXLAN attributes */
1772 if (dev
->caps
.flags2
& MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS
) {
1773 u8 parser_params
= 0;
1774 MLX4_PUT(inbox
, parser_params
, INIT_HCA_VXLAN_OFFSET
);
1777 err
= mlx4_cmd(dev
, mailbox
->dma
, 0, 0, MLX4_CMD_INIT_HCA
,
1778 MLX4_CMD_TIME_CLASS_C
, MLX4_CMD_NATIVE
);
1781 mlx4_err(dev
, "INIT_HCA returns %d\n", err
);
1783 mlx4_free_cmd_mailbox(dev
, mailbox
);
1787 int mlx4_QUERY_HCA(struct mlx4_dev
*dev
,
1788 struct mlx4_init_hca_param
*param
)
1790 struct mlx4_cmd_mailbox
*mailbox
;
1795 static const u8 a0_dmfs_query_hw_steering
[] = {
1796 [0] = MLX4_STEERING_DMFS_A0_DEFAULT
,
1797 [1] = MLX4_STEERING_DMFS_A0_DYNAMIC
,
1798 [2] = MLX4_STEERING_DMFS_A0_STATIC
,
1799 [3] = MLX4_STEERING_DMFS_A0_DISABLE
1802 #define QUERY_HCA_GLOBAL_CAPS_OFFSET 0x04
1803 #define QUERY_HCA_CORE_CLOCK_OFFSET 0x0c
1805 mailbox
= mlx4_alloc_cmd_mailbox(dev
);
1806 if (IS_ERR(mailbox
))
1807 return PTR_ERR(mailbox
);
1808 outbox
= mailbox
->buf
;
1810 err
= mlx4_cmd_box(dev
, 0, mailbox
->dma
, 0, 0,
1812 MLX4_CMD_TIME_CLASS_B
,
1813 !mlx4_is_slave(dev
));
1817 MLX4_GET(param
->global_caps
, outbox
, QUERY_HCA_GLOBAL_CAPS_OFFSET
);
1818 MLX4_GET(param
->hca_core_clock
, outbox
, QUERY_HCA_CORE_CLOCK_OFFSET
);
1820 /* QPC/EEC/CQC/EQC/RDMARC attributes */
1822 MLX4_GET(param
->qpc_base
, outbox
, INIT_HCA_QPC_BASE_OFFSET
);
1823 MLX4_GET(param
->log_num_qps
, outbox
, INIT_HCA_LOG_QP_OFFSET
);
1824 MLX4_GET(param
->srqc_base
, outbox
, INIT_HCA_SRQC_BASE_OFFSET
);
1825 MLX4_GET(param
->log_num_srqs
, outbox
, INIT_HCA_LOG_SRQ_OFFSET
);
1826 MLX4_GET(param
->cqc_base
, outbox
, INIT_HCA_CQC_BASE_OFFSET
);
1827 MLX4_GET(param
->log_num_cqs
, outbox
, INIT_HCA_LOG_CQ_OFFSET
);
1828 MLX4_GET(param
->altc_base
, outbox
, INIT_HCA_ALTC_BASE_OFFSET
);
1829 MLX4_GET(param
->auxc_base
, outbox
, INIT_HCA_AUXC_BASE_OFFSET
);
1830 MLX4_GET(param
->eqc_base
, outbox
, INIT_HCA_EQC_BASE_OFFSET
);
1831 MLX4_GET(param
->log_num_eqs
, outbox
, INIT_HCA_LOG_EQ_OFFSET
);
1832 MLX4_GET(param
->num_sys_eqs
, outbox
, INIT_HCA_NUM_SYS_EQS_OFFSET
);
1833 MLX4_GET(param
->rdmarc_base
, outbox
, INIT_HCA_RDMARC_BASE_OFFSET
);
1834 MLX4_GET(param
->log_rd_per_qp
, outbox
, INIT_HCA_LOG_RD_OFFSET
);
1836 MLX4_GET(dword_field
, outbox
, INIT_HCA_FLAGS_OFFSET
);
1837 if (dword_field
& (1 << INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN
)) {
1838 param
->steering_mode
= MLX4_STEERING_MODE_DEVICE_MANAGED
;
1840 MLX4_GET(byte_field
, outbox
, INIT_HCA_UC_STEERING_OFFSET
);
1841 if (byte_field
& 0x8)
1842 param
->steering_mode
= MLX4_STEERING_MODE_B0
;
1844 param
->steering_mode
= MLX4_STEERING_MODE_A0
;
1846 /* steering attributes */
1847 if (param
->steering_mode
== MLX4_STEERING_MODE_DEVICE_MANAGED
) {
1848 MLX4_GET(param
->mc_base
, outbox
, INIT_HCA_FS_BASE_OFFSET
);
1849 MLX4_GET(param
->log_mc_entry_sz
, outbox
,
1850 INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET
);
1851 MLX4_GET(param
->log_mc_table_sz
, outbox
,
1852 INIT_HCA_FS_LOG_TABLE_SZ_OFFSET
);
1853 MLX4_GET(byte_field
, outbox
,
1854 INIT_HCA_FS_A0_OFFSET
);
1855 param
->dmfs_high_steer_mode
=
1856 a0_dmfs_query_hw_steering
[(byte_field
>> 6) & 3];
1858 MLX4_GET(param
->mc_base
, outbox
, INIT_HCA_MC_BASE_OFFSET
);
1859 MLX4_GET(param
->log_mc_entry_sz
, outbox
,
1860 INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET
);
1861 MLX4_GET(param
->log_mc_hash_sz
, outbox
,
1862 INIT_HCA_LOG_MC_HASH_SZ_OFFSET
);
1863 MLX4_GET(param
->log_mc_table_sz
, outbox
,
1864 INIT_HCA_LOG_MC_TABLE_SZ_OFFSET
);
1867 /* CX3 is capable of extending CQEs/EQEs from 32 to 64 bytes */
1868 MLX4_GET(byte_field
, outbox
, INIT_HCA_EQE_CQE_OFFSETS
);
1869 if (byte_field
& 0x20) /* 64-bytes eqe enabled */
1870 param
->dev_cap_enabled
|= MLX4_DEV_CAP_64B_EQE_ENABLED
;
1871 if (byte_field
& 0x40) /* 64-bytes cqe enabled */
1872 param
->dev_cap_enabled
|= MLX4_DEV_CAP_64B_CQE_ENABLED
;
1874 /* CX3 is capable of extending CQEs\EQEs to strides larger than 64B */
1875 MLX4_GET(byte_field
, outbox
, INIT_HCA_EQE_CQE_STRIDE_OFFSET
);
1877 param
->dev_cap_enabled
|= MLX4_DEV_CAP_EQE_STRIDE_ENABLED
;
1878 param
->dev_cap_enabled
|= MLX4_DEV_CAP_CQE_STRIDE_ENABLED
;
1879 param
->cqe_size
= 1 << ((byte_field
&
1880 MLX4_CQE_SIZE_MASK_STRIDE
) + 5);
1881 param
->eqe_size
= 1 << (((byte_field
&
1882 MLX4_EQE_SIZE_MASK_STRIDE
) >> 4) + 5);
1885 /* TPT attributes */
1887 MLX4_GET(param
->dmpt_base
, outbox
, INIT_HCA_DMPT_BASE_OFFSET
);
1888 MLX4_GET(param
->mw_enabled
, outbox
, INIT_HCA_TPT_MW_OFFSET
);
1889 MLX4_GET(param
->log_mpt_sz
, outbox
, INIT_HCA_LOG_MPT_SZ_OFFSET
);
1890 MLX4_GET(param
->mtt_base
, outbox
, INIT_HCA_MTT_BASE_OFFSET
);
1891 MLX4_GET(param
->cmpt_base
, outbox
, INIT_HCA_CMPT_BASE_OFFSET
);
1893 /* UAR attributes */
1895 MLX4_GET(param
->uar_page_sz
, outbox
, INIT_HCA_UAR_PAGE_SZ_OFFSET
);
1896 MLX4_GET(param
->log_uar_sz
, outbox
, INIT_HCA_LOG_UAR_SZ_OFFSET
);
1899 mlx4_free_cmd_mailbox(dev
, mailbox
);
1904 static int mlx4_hca_core_clock_update(struct mlx4_dev
*dev
)
1906 struct mlx4_cmd_mailbox
*mailbox
;
1910 mailbox
= mlx4_alloc_cmd_mailbox(dev
);
1911 if (IS_ERR(mailbox
)) {
1912 mlx4_warn(dev
, "hca_core_clock mailbox allocation failed\n");
1913 return PTR_ERR(mailbox
);
1915 outbox
= mailbox
->buf
;
1917 err
= mlx4_cmd_box(dev
, 0, mailbox
->dma
, 0, 0,
1919 MLX4_CMD_TIME_CLASS_B
,
1920 !mlx4_is_slave(dev
));
1922 mlx4_warn(dev
, "hca_core_clock update failed\n");
1926 MLX4_GET(dev
->caps
.hca_core_clock
, outbox
, QUERY_HCA_CORE_CLOCK_OFFSET
);
1929 mlx4_free_cmd_mailbox(dev
, mailbox
);
1934 /* for IB-type ports only in SRIOV mode. Checks that both proxy QP0
1935 * and real QP0 are active, so that the paravirtualized QP0 is ready
1937 static int check_qp0_state(struct mlx4_dev
*dev
, int function
, int port
)
1939 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1940 /* irrelevant if not infiniband */
1941 if (priv
->mfunc
.master
.qp0_state
[port
].proxy_qp0_active
&&
1942 priv
->mfunc
.master
.qp0_state
[port
].qp0_active
)
1947 int mlx4_INIT_PORT_wrapper(struct mlx4_dev
*dev
, int slave
,
1948 struct mlx4_vhcr
*vhcr
,
1949 struct mlx4_cmd_mailbox
*inbox
,
1950 struct mlx4_cmd_mailbox
*outbox
,
1951 struct mlx4_cmd_info
*cmd
)
1953 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1954 int port
= mlx4_slave_convert_port(dev
, slave
, vhcr
->in_modifier
);
1960 if (priv
->mfunc
.master
.slave_state
[slave
].init_port_mask
& (1 << port
))
1963 if (dev
->caps
.port_mask
[port
] != MLX4_PORT_TYPE_IB
) {
1964 /* Enable port only if it was previously disabled */
1965 if (!priv
->mfunc
.master
.init_port_ref
[port
]) {
1966 err
= mlx4_cmd(dev
, 0, port
, 0, MLX4_CMD_INIT_PORT
,
1967 MLX4_CMD_TIME_CLASS_A
, MLX4_CMD_NATIVE
);
1971 priv
->mfunc
.master
.slave_state
[slave
].init_port_mask
|= (1 << port
);
1973 if (slave
== mlx4_master_func_num(dev
)) {
1974 if (check_qp0_state(dev
, slave
, port
) &&
1975 !priv
->mfunc
.master
.qp0_state
[port
].port_active
) {
1976 err
= mlx4_cmd(dev
, 0, port
, 0, MLX4_CMD_INIT_PORT
,
1977 MLX4_CMD_TIME_CLASS_A
, MLX4_CMD_NATIVE
);
1980 priv
->mfunc
.master
.qp0_state
[port
].port_active
= 1;
1981 priv
->mfunc
.master
.slave_state
[slave
].init_port_mask
|= (1 << port
);
1984 priv
->mfunc
.master
.slave_state
[slave
].init_port_mask
|= (1 << port
);
1986 ++priv
->mfunc
.master
.init_port_ref
[port
];
1990 int mlx4_INIT_PORT(struct mlx4_dev
*dev
, int port
)
1992 struct mlx4_cmd_mailbox
*mailbox
;
1998 if (dev
->flags
& MLX4_FLAG_OLD_PORT_CMDS
) {
1999 #define INIT_PORT_IN_SIZE 256
2000 #define INIT_PORT_FLAGS_OFFSET 0x00
2001 #define INIT_PORT_FLAG_SIG (1 << 18)
2002 #define INIT_PORT_FLAG_NG (1 << 17)
2003 #define INIT_PORT_FLAG_G0 (1 << 16)
2004 #define INIT_PORT_VL_SHIFT 4
2005 #define INIT_PORT_PORT_WIDTH_SHIFT 8
2006 #define INIT_PORT_MTU_OFFSET 0x04
2007 #define INIT_PORT_MAX_GID_OFFSET 0x06
2008 #define INIT_PORT_MAX_PKEY_OFFSET 0x0a
2009 #define INIT_PORT_GUID0_OFFSET 0x10
2010 #define INIT_PORT_NODE_GUID_OFFSET 0x18
2011 #define INIT_PORT_SI_GUID_OFFSET 0x20
2013 mailbox
= mlx4_alloc_cmd_mailbox(dev
);
2014 if (IS_ERR(mailbox
))
2015 return PTR_ERR(mailbox
);
2016 inbox
= mailbox
->buf
;
2019 flags
|= (dev
->caps
.vl_cap
[port
] & 0xf) << INIT_PORT_VL_SHIFT
;
2020 flags
|= (dev
->caps
.port_width_cap
[port
] & 0xf) << INIT_PORT_PORT_WIDTH_SHIFT
;
2021 MLX4_PUT(inbox
, flags
, INIT_PORT_FLAGS_OFFSET
);
2023 field
= 128 << dev
->caps
.ib_mtu_cap
[port
];
2024 MLX4_PUT(inbox
, field
, INIT_PORT_MTU_OFFSET
);
2025 field
= dev
->caps
.gid_table_len
[port
];
2026 MLX4_PUT(inbox
, field
, INIT_PORT_MAX_GID_OFFSET
);
2027 field
= dev
->caps
.pkey_table_len
[port
];
2028 MLX4_PUT(inbox
, field
, INIT_PORT_MAX_PKEY_OFFSET
);
2030 err
= mlx4_cmd(dev
, mailbox
->dma
, port
, 0, MLX4_CMD_INIT_PORT
,
2031 MLX4_CMD_TIME_CLASS_A
, MLX4_CMD_NATIVE
);
2033 mlx4_free_cmd_mailbox(dev
, mailbox
);
2035 err
= mlx4_cmd(dev
, 0, port
, 0, MLX4_CMD_INIT_PORT
,
2036 MLX4_CMD_TIME_CLASS_A
, MLX4_CMD_WRAPPED
);
2039 mlx4_hca_core_clock_update(dev
);
2043 EXPORT_SYMBOL_GPL(mlx4_INIT_PORT
);
2045 int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev
*dev
, int slave
,
2046 struct mlx4_vhcr
*vhcr
,
2047 struct mlx4_cmd_mailbox
*inbox
,
2048 struct mlx4_cmd_mailbox
*outbox
,
2049 struct mlx4_cmd_info
*cmd
)
2051 struct mlx4_priv
*priv
= mlx4_priv(dev
);
2052 int port
= mlx4_slave_convert_port(dev
, slave
, vhcr
->in_modifier
);
2058 if (!(priv
->mfunc
.master
.slave_state
[slave
].init_port_mask
&
2062 if (dev
->caps
.port_mask
[port
] != MLX4_PORT_TYPE_IB
) {
2063 if (priv
->mfunc
.master
.init_port_ref
[port
] == 1) {
2064 err
= mlx4_cmd(dev
, 0, port
, 0, MLX4_CMD_CLOSE_PORT
,
2065 MLX4_CMD_TIME_CLASS_A
, MLX4_CMD_NATIVE
);
2069 priv
->mfunc
.master
.slave_state
[slave
].init_port_mask
&= ~(1 << port
);
2071 /* infiniband port */
2072 if (slave
== mlx4_master_func_num(dev
)) {
2073 if (!priv
->mfunc
.master
.qp0_state
[port
].qp0_active
&&
2074 priv
->mfunc
.master
.qp0_state
[port
].port_active
) {
2075 err
= mlx4_cmd(dev
, 0, port
, 0, MLX4_CMD_CLOSE_PORT
,
2076 MLX4_CMD_TIME_CLASS_A
, MLX4_CMD_NATIVE
);
2079 priv
->mfunc
.master
.slave_state
[slave
].init_port_mask
&= ~(1 << port
);
2080 priv
->mfunc
.master
.qp0_state
[port
].port_active
= 0;
2083 priv
->mfunc
.master
.slave_state
[slave
].init_port_mask
&= ~(1 << port
);
2085 --priv
->mfunc
.master
.init_port_ref
[port
];
2089 int mlx4_CLOSE_PORT(struct mlx4_dev
*dev
, int port
)
2091 return mlx4_cmd(dev
, 0, port
, 0, MLX4_CMD_CLOSE_PORT
,
2092 MLX4_CMD_TIME_CLASS_A
, MLX4_CMD_WRAPPED
);
2094 EXPORT_SYMBOL_GPL(mlx4_CLOSE_PORT
);
2096 int mlx4_CLOSE_HCA(struct mlx4_dev
*dev
, int panic
)
2098 return mlx4_cmd(dev
, 0, 0, panic
, MLX4_CMD_CLOSE_HCA
,
2099 MLX4_CMD_TIME_CLASS_C
, MLX4_CMD_NATIVE
);
2102 struct mlx4_config_dev
{
2103 __be32 update_flags
;
2105 __be16 vxlan_udp_dport
;
2115 #define MLX4_VXLAN_UDP_DPORT (1 << 0)
2116 #define MLX4_DISABLE_RX_PORT BIT(18)
2118 static int mlx4_CONFIG_DEV_set(struct mlx4_dev
*dev
, struct mlx4_config_dev
*config_dev
)
2121 struct mlx4_cmd_mailbox
*mailbox
;
2123 mailbox
= mlx4_alloc_cmd_mailbox(dev
);
2124 if (IS_ERR(mailbox
))
2125 return PTR_ERR(mailbox
);
2127 memcpy(mailbox
->buf
, config_dev
, sizeof(*config_dev
));
2129 err
= mlx4_cmd(dev
, mailbox
->dma
, 0, 0, MLX4_CMD_CONFIG_DEV
,
2130 MLX4_CMD_TIME_CLASS_B
, MLX4_CMD_NATIVE
);
2132 mlx4_free_cmd_mailbox(dev
, mailbox
);
2136 static int mlx4_CONFIG_DEV_get(struct mlx4_dev
*dev
, struct mlx4_config_dev
*config_dev
)
2139 struct mlx4_cmd_mailbox
*mailbox
;
2141 mailbox
= mlx4_alloc_cmd_mailbox(dev
);
2142 if (IS_ERR(mailbox
))
2143 return PTR_ERR(mailbox
);
2145 err
= mlx4_cmd_box(dev
, 0, mailbox
->dma
, 0, 1, MLX4_CMD_CONFIG_DEV
,
2146 MLX4_CMD_TIME_CLASS_A
, MLX4_CMD_NATIVE
);
2149 memcpy(config_dev
, mailbox
->buf
, sizeof(*config_dev
));
2151 mlx4_free_cmd_mailbox(dev
, mailbox
);
2155 /* Conversion between the HW values and the actual functionality.
2156 * The value represented by the array index,
2157 * and the functionality determined by the flags.
2159 static const u8 config_dev_csum_flags
[] = {
2161 [1] = MLX4_RX_CSUM_MODE_VAL_NON_TCP_UDP
,
2162 [2] = MLX4_RX_CSUM_MODE_VAL_NON_TCP_UDP
|
2163 MLX4_RX_CSUM_MODE_L4
,
2164 [3] = MLX4_RX_CSUM_MODE_L4
|
2165 MLX4_RX_CSUM_MODE_IP_OK_IP_NON_TCP_UDP
|
2166 MLX4_RX_CSUM_MODE_MULTI_VLAN
2169 int mlx4_config_dev_retrieval(struct mlx4_dev
*dev
,
2170 struct mlx4_config_dev_params
*params
)
2172 struct mlx4_config_dev config_dev
= {0};
2176 #define CONFIG_DEV_RX_CSUM_MODE_MASK 0x7
2177 #define CONFIG_DEV_RX_CSUM_MODE_PORT1_BIT_OFFSET 0
2178 #define CONFIG_DEV_RX_CSUM_MODE_PORT2_BIT_OFFSET 4
2180 if (!(dev
->caps
.flags2
& MLX4_DEV_CAP_FLAG2_CONFIG_DEV
))
2183 err
= mlx4_CONFIG_DEV_get(dev
, &config_dev
);
2187 csum_mask
= (config_dev
.rx_checksum_val
>> CONFIG_DEV_RX_CSUM_MODE_PORT1_BIT_OFFSET
) &
2188 CONFIG_DEV_RX_CSUM_MODE_MASK
;
2190 if (csum_mask
>= sizeof(config_dev_csum_flags
)/sizeof(config_dev_csum_flags
[0]))
2192 params
->rx_csum_flags_port_1
= config_dev_csum_flags
[csum_mask
];
2194 csum_mask
= (config_dev
.rx_checksum_val
>> CONFIG_DEV_RX_CSUM_MODE_PORT2_BIT_OFFSET
) &
2195 CONFIG_DEV_RX_CSUM_MODE_MASK
;
2197 if (csum_mask
>= sizeof(config_dev_csum_flags
)/sizeof(config_dev_csum_flags
[0]))
2199 params
->rx_csum_flags_port_2
= config_dev_csum_flags
[csum_mask
];
2201 params
->vxlan_udp_dport
= be16_to_cpu(config_dev
.vxlan_udp_dport
);
2205 EXPORT_SYMBOL_GPL(mlx4_config_dev_retrieval
);
2207 int mlx4_config_vxlan_port(struct mlx4_dev
*dev
, __be16 udp_port
)
2209 struct mlx4_config_dev config_dev
;
2211 memset(&config_dev
, 0, sizeof(config_dev
));
2212 config_dev
.update_flags
= cpu_to_be32(MLX4_VXLAN_UDP_DPORT
);
2213 config_dev
.vxlan_udp_dport
= udp_port
;
2215 return mlx4_CONFIG_DEV_set(dev
, &config_dev
);
2217 EXPORT_SYMBOL_GPL(mlx4_config_vxlan_port
);
2219 #define CONFIG_DISABLE_RX_PORT BIT(15)
2220 int mlx4_disable_rx_port_check(struct mlx4_dev
*dev
, bool dis
)
2222 struct mlx4_config_dev config_dev
;
2224 memset(&config_dev
, 0, sizeof(config_dev
));
2225 config_dev
.update_flags
= cpu_to_be32(MLX4_DISABLE_RX_PORT
);
2227 config_dev
.roce_flags
=
2228 cpu_to_be32(CONFIG_DISABLE_RX_PORT
);
2230 return mlx4_CONFIG_DEV_set(dev
, &config_dev
);
2233 int mlx4_virt2phy_port_map(struct mlx4_dev
*dev
, u32 port1
, u32 port2
)
2235 struct mlx4_cmd_mailbox
*mailbox
;
2242 mailbox
= mlx4_alloc_cmd_mailbox(dev
);
2243 if (IS_ERR(mailbox
))
2247 v2p
->v_port1
= cpu_to_be32(port1
);
2248 v2p
->v_port2
= cpu_to_be32(port2
);
2250 err
= mlx4_cmd(dev
, mailbox
->dma
, 0,
2251 MLX4_SET_PORT_VIRT2PHY
, MLX4_CMD_VIRT_PORT_MAP
,
2252 MLX4_CMD_TIME_CLASS_B
, MLX4_CMD_NATIVE
);
2254 mlx4_free_cmd_mailbox(dev
, mailbox
);
2259 int mlx4_SET_ICM_SIZE(struct mlx4_dev
*dev
, u64 icm_size
, u64
*aux_pages
)
2261 int ret
= mlx4_cmd_imm(dev
, icm_size
, aux_pages
, 0, 0,
2262 MLX4_CMD_SET_ICM_SIZE
,
2263 MLX4_CMD_TIME_CLASS_A
, MLX4_CMD_NATIVE
);
2268 * Round up number of system pages needed in case
2269 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE.
2271 *aux_pages
= ALIGN(*aux_pages
, PAGE_SIZE
/ MLX4_ICM_PAGE_SIZE
) >>
2272 (PAGE_SHIFT
- MLX4_ICM_PAGE_SHIFT
);
2277 int mlx4_NOP(struct mlx4_dev
*dev
)
2279 /* Input modifier of 0x1f means "finish as soon as possible." */
2280 return mlx4_cmd(dev
, 0, 0x1f, 0, MLX4_CMD_NOP
, MLX4_CMD_TIME_CLASS_A
,
2284 int mlx4_get_phys_port_id(struct mlx4_dev
*dev
)
2288 struct mlx4_cmd_mailbox
*mailbox
;
2290 u32 guid_hi
, guid_lo
;
2292 #define MOD_STAT_CFG_PORT_OFFSET 8
2293 #define MOD_STAT_CFG_GUID_H 0X14
2294 #define MOD_STAT_CFG_GUID_L 0X1c
2296 mailbox
= mlx4_alloc_cmd_mailbox(dev
);
2297 if (IS_ERR(mailbox
))
2298 return PTR_ERR(mailbox
);
2299 outbox
= mailbox
->buf
;
2301 for (port
= 1; port
<= dev
->caps
.num_ports
; port
++) {
2302 in_mod
= port
<< MOD_STAT_CFG_PORT_OFFSET
;
2303 err
= mlx4_cmd_box(dev
, 0, mailbox
->dma
, in_mod
, 0x2,
2304 MLX4_CMD_MOD_STAT_CFG
, MLX4_CMD_TIME_CLASS_A
,
2307 mlx4_err(dev
, "Fail to get port %d uplink guid\n",
2311 MLX4_GET(guid_hi
, outbox
, MOD_STAT_CFG_GUID_H
);
2312 MLX4_GET(guid_lo
, outbox
, MOD_STAT_CFG_GUID_L
);
2313 dev
->caps
.phys_port_id
[port
] = (u64
)guid_lo
|
2317 mlx4_free_cmd_mailbox(dev
, mailbox
);
2321 #define MLX4_WOL_SETUP_MODE (5 << 28)
2322 int mlx4_wol_read(struct mlx4_dev
*dev
, u64
*config
, int port
)
2324 u32 in_mod
= MLX4_WOL_SETUP_MODE
| port
<< 8;
2326 return mlx4_cmd_imm(dev
, 0, config
, in_mod
, 0x3,
2327 MLX4_CMD_MOD_STAT_CFG
, MLX4_CMD_TIME_CLASS_A
,
2330 EXPORT_SYMBOL_GPL(mlx4_wol_read
);
2332 int mlx4_wol_write(struct mlx4_dev
*dev
, u64 config
, int port
)
2334 u32 in_mod
= MLX4_WOL_SETUP_MODE
| port
<< 8;
2336 return mlx4_cmd(dev
, config
, in_mod
, 0x1, MLX4_CMD_MOD_STAT_CFG
,
2337 MLX4_CMD_TIME_CLASS_A
, MLX4_CMD_NATIVE
);
2339 EXPORT_SYMBOL_GPL(mlx4_wol_write
);
2346 void mlx4_opreq_action(struct work_struct
*work
)
2348 struct mlx4_priv
*priv
= container_of(work
, struct mlx4_priv
,
2350 struct mlx4_dev
*dev
= &priv
->dev
;
2351 int num_tasks
= atomic_read(&priv
->opreq_count
);
2352 struct mlx4_cmd_mailbox
*mailbox
;
2353 struct mlx4_mgm
*mgm
;
2365 #define GET_OP_REQ_MODIFIER_OFFSET 0x08
2366 #define GET_OP_REQ_TOKEN_OFFSET 0x14
2367 #define GET_OP_REQ_TYPE_OFFSET 0x1a
2368 #define GET_OP_REQ_DATA_OFFSET 0x20
2370 mailbox
= mlx4_alloc_cmd_mailbox(dev
);
2371 if (IS_ERR(mailbox
)) {
2372 mlx4_err(dev
, "Failed to allocate mailbox for GET_OP_REQ\n");
2375 outbox
= mailbox
->buf
;
2378 err
= mlx4_cmd_box(dev
, 0, mailbox
->dma
, 0, 0,
2379 MLX4_CMD_GET_OP_REQ
, MLX4_CMD_TIME_CLASS_A
,
2382 mlx4_err(dev
, "Failed to retrieve required operation: %d\n",
2386 MLX4_GET(modifier
, outbox
, GET_OP_REQ_MODIFIER_OFFSET
);
2387 MLX4_GET(token
, outbox
, GET_OP_REQ_TOKEN_OFFSET
);
2388 MLX4_GET(type
, outbox
, GET_OP_REQ_TYPE_OFFSET
);
2393 if (dev
->caps
.steering_mode
==
2394 MLX4_STEERING_MODE_DEVICE_MANAGED
) {
2395 mlx4_warn(dev
, "ADD MCG operation is not supported in DEVICE_MANAGED steering mode\n");
2399 mgm
= (struct mlx4_mgm
*)((u8
*)(outbox
) +
2400 GET_OP_REQ_DATA_OFFSET
);
2401 num_qps
= be32_to_cpu(mgm
->members_count
) &
2403 rem_mcg
= ((u8
*)(&mgm
->members_count
))[0] & 1;
2404 prot
= ((u8
*)(&mgm
->members_count
))[0] >> 6;
2406 for (i
= 0; i
< num_qps
; i
++) {
2407 qp
.qpn
= be32_to_cpu(mgm
->qp
[i
]);
2409 err
= mlx4_multicast_detach(dev
, &qp
,
2413 err
= mlx4_multicast_attach(dev
, &qp
,
2423 mlx4_warn(dev
, "Bad type for required operation\n");
2427 err
= mlx4_cmd(dev
, 0, ((u32
) err
|
2428 (__force u32
)cpu_to_be32(token
) << 16),
2429 1, MLX4_CMD_GET_OP_REQ
, MLX4_CMD_TIME_CLASS_A
,
2432 mlx4_err(dev
, "Failed to acknowledge required request: %d\n",
2436 memset(outbox
, 0, 0xffc);
2437 num_tasks
= atomic_dec_return(&priv
->opreq_count
);
2441 mlx4_free_cmd_mailbox(dev
, mailbox
);
2444 static int mlx4_check_smp_firewall_active(struct mlx4_dev
*dev
,
2445 struct mlx4_cmd_mailbox
*mailbox
)
2447 #define MLX4_CMD_MAD_DEMUX_SET_ATTR_OFFSET 0x10
2448 #define MLX4_CMD_MAD_DEMUX_GETRESP_ATTR_OFFSET 0x20
2449 #define MLX4_CMD_MAD_DEMUX_TRAP_ATTR_OFFSET 0x40
2450 #define MLX4_CMD_MAD_DEMUX_TRAP_REPRESS_ATTR_OFFSET 0x70
2452 u32 set_attr_mask
, getresp_attr_mask
;
2453 u32 trap_attr_mask
, traprepress_attr_mask
;
2455 MLX4_GET(set_attr_mask
, mailbox
->buf
,
2456 MLX4_CMD_MAD_DEMUX_SET_ATTR_OFFSET
);
2457 mlx4_dbg(dev
, "SMP firewall set_attribute_mask = 0x%x\n",
2460 MLX4_GET(getresp_attr_mask
, mailbox
->buf
,
2461 MLX4_CMD_MAD_DEMUX_GETRESP_ATTR_OFFSET
);
2462 mlx4_dbg(dev
, "SMP firewall getresp_attribute_mask = 0x%x\n",
2465 MLX4_GET(trap_attr_mask
, mailbox
->buf
,
2466 MLX4_CMD_MAD_DEMUX_TRAP_ATTR_OFFSET
);
2467 mlx4_dbg(dev
, "SMP firewall trap_attribute_mask = 0x%x\n",
2470 MLX4_GET(traprepress_attr_mask
, mailbox
->buf
,
2471 MLX4_CMD_MAD_DEMUX_TRAP_REPRESS_ATTR_OFFSET
);
2472 mlx4_dbg(dev
, "SMP firewall traprepress_attribute_mask = 0x%x\n",
2473 traprepress_attr_mask
);
2475 if (set_attr_mask
&& getresp_attr_mask
&& trap_attr_mask
&&
2476 traprepress_attr_mask
)
2482 int mlx4_config_mad_demux(struct mlx4_dev
*dev
)
2484 struct mlx4_cmd_mailbox
*mailbox
;
2485 int secure_host_active
;
2488 /* Check if mad_demux is supported */
2489 if (!(dev
->caps
.flags2
& MLX4_DEV_CAP_FLAG2_MAD_DEMUX
))
2492 mailbox
= mlx4_alloc_cmd_mailbox(dev
);
2493 if (IS_ERR(mailbox
)) {
2494 mlx4_warn(dev
, "Failed to allocate mailbox for cmd MAD_DEMUX");
2498 /* Query mad_demux to find out which MADs are handled by internal sma */
2499 err
= mlx4_cmd_box(dev
, 0, mailbox
->dma
, 0x01 /* subn mgmt class */,
2500 MLX4_CMD_MAD_DEMUX_QUERY_RESTR
, MLX4_CMD_MAD_DEMUX
,
2501 MLX4_CMD_TIME_CLASS_B
, MLX4_CMD_NATIVE
);
2503 mlx4_warn(dev
, "MLX4_CMD_MAD_DEMUX: query restrictions failed (%d)\n",
2508 secure_host_active
= mlx4_check_smp_firewall_active(dev
, mailbox
);
2510 /* Config mad_demux to handle all MADs returned by the query above */
2511 err
= mlx4_cmd(dev
, mailbox
->dma
, 0x01 /* subn mgmt class */,
2512 MLX4_CMD_MAD_DEMUX_CONFIG
, MLX4_CMD_MAD_DEMUX
,
2513 MLX4_CMD_TIME_CLASS_B
, MLX4_CMD_NATIVE
);
2515 mlx4_warn(dev
, "MLX4_CMD_MAD_DEMUX: configure failed (%d)\n", err
);
2519 if (secure_host_active
)
2520 mlx4_warn(dev
, "HCA operating in secure-host mode. SMP firewall activated.\n");
2522 mlx4_free_cmd_mailbox(dev
, mailbox
);
2526 /* Access Reg commands */
2527 enum mlx4_access_reg_masks
{
2528 MLX4_ACCESS_REG_STATUS_MASK
= 0x7f,
2529 MLX4_ACCESS_REG_METHOD_MASK
= 0x7f,
2530 MLX4_ACCESS_REG_LEN_MASK
= 0x7ff
2533 struct mlx4_access_reg
{
2543 #define MLX4_ACCESS_REG_HEADER_SIZE (20)
2544 u8 reg_data
[MLX4_MAILBOX_SIZE
-MLX4_ACCESS_REG_HEADER_SIZE
];
2545 } __attribute__((__packed__
));
2548 * mlx4_ACCESS_REG - Generic access reg command.
2550 * @reg_id: register ID to access.
2551 * @method: Access method Read/Write.
2552 * @reg_len: register length to Read/Write in bytes.
2553 * @reg_data: reg_data pointer to Read/Write From/To.
2555 * Access ConnectX registers FW command.
2556 * Returns 0 on success and copies outbox mlx4_access_reg data
2557 * field into reg_data or a negative error code.
2559 static int mlx4_ACCESS_REG(struct mlx4_dev
*dev
, u16 reg_id
,
2560 enum mlx4_access_reg_method method
,
2561 u16 reg_len
, void *reg_data
)
2563 struct mlx4_cmd_mailbox
*inbox
, *outbox
;
2564 struct mlx4_access_reg
*inbuf
, *outbuf
;
2567 inbox
= mlx4_alloc_cmd_mailbox(dev
);
2569 return PTR_ERR(inbox
);
2571 outbox
= mlx4_alloc_cmd_mailbox(dev
);
2572 if (IS_ERR(outbox
)) {
2573 mlx4_free_cmd_mailbox(dev
, inbox
);
2574 return PTR_ERR(outbox
);
2578 outbuf
= outbox
->buf
;
2580 inbuf
->constant1
= cpu_to_be16(0x1<<11 | 0x4);
2581 inbuf
->constant2
= 0x1;
2582 inbuf
->reg_id
= cpu_to_be16(reg_id
);
2583 inbuf
->method
= method
& MLX4_ACCESS_REG_METHOD_MASK
;
2585 reg_len
= min(reg_len
, (u16
)(sizeof(inbuf
->reg_data
)));
2587 cpu_to_be16(((reg_len
/4 + 1) & MLX4_ACCESS_REG_LEN_MASK
) |
2590 memcpy(inbuf
->reg_data
, reg_data
, reg_len
);
2591 err
= mlx4_cmd_box(dev
, inbox
->dma
, outbox
->dma
, 0, 0,
2592 MLX4_CMD_ACCESS_REG
, MLX4_CMD_TIME_CLASS_C
,
2597 if (outbuf
->status
& MLX4_ACCESS_REG_STATUS_MASK
) {
2598 err
= outbuf
->status
& MLX4_ACCESS_REG_STATUS_MASK
;
2600 "MLX4_CMD_ACCESS_REG(%x) returned REG status (%x)\n",
2605 memcpy(reg_data
, outbuf
->reg_data
, reg_len
);
2607 mlx4_free_cmd_mailbox(dev
, inbox
);
2608 mlx4_free_cmd_mailbox(dev
, outbox
);
2612 /* ConnectX registers IDs */
2614 MLX4_REG_ID_PTYS
= 0x5004,
2618 * mlx4_ACCESS_PTYS_REG - Access PTYs (Port Type and Speed)
2621 * @method: Access method Read/Write.
2622 * @ptys_reg: PTYS register data pointer.
2624 * Access ConnectX PTYS register, to Read/Write Port Type/Speed
2626 * Returns 0 on success or a negative error code.
2628 int mlx4_ACCESS_PTYS_REG(struct mlx4_dev
*dev
,
2629 enum mlx4_access_reg_method method
,
2630 struct mlx4_ptys_reg
*ptys_reg
)
2632 return mlx4_ACCESS_REG(dev
, MLX4_REG_ID_PTYS
,
2633 method
, sizeof(*ptys_reg
), ptys_reg
);
2635 EXPORT_SYMBOL_GPL(mlx4_ACCESS_PTYS_REG
);
2637 int mlx4_ACCESS_REG_wrapper(struct mlx4_dev
*dev
, int slave
,
2638 struct mlx4_vhcr
*vhcr
,
2639 struct mlx4_cmd_mailbox
*inbox
,
2640 struct mlx4_cmd_mailbox
*outbox
,
2641 struct mlx4_cmd_info
*cmd
)
2643 struct mlx4_access_reg
*inbuf
= inbox
->buf
;
2644 u8 method
= inbuf
->method
& MLX4_ACCESS_REG_METHOD_MASK
;
2645 u16 reg_id
= be16_to_cpu(inbuf
->reg_id
);
2647 if (slave
!= mlx4_master_func_num(dev
) &&
2648 method
== MLX4_ACCESS_REG_WRITE
)
2651 if (reg_id
== MLX4_REG_ID_PTYS
) {
2652 struct mlx4_ptys_reg
*ptys_reg
=
2653 (struct mlx4_ptys_reg
*)inbuf
->reg_data
;
2655 ptys_reg
->local_port
=
2656 mlx4_slave_convert_port(dev
, slave
,
2657 ptys_reg
->local_port
);
2660 return mlx4_cmd_box(dev
, inbox
->dma
, outbox
->dma
, vhcr
->in_modifier
,
2661 0, MLX4_CMD_ACCESS_REG
, MLX4_CMD_TIME_CLASS_C
,