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mlx4: In RoCE allow guests to have multiple GIDS
[deliverable/linux.git] / drivers / net / ethernet / mellanox / mlx4 / fw.c
1 /*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35 #include <linux/etherdevice.h>
36 #include <linux/mlx4/cmd.h>
37 #include <linux/module.h>
38 #include <linux/cache.h>
39
40 #include "fw.h"
41 #include "icm.h"
42
43 enum {
44 MLX4_COMMAND_INTERFACE_MIN_REV = 2,
45 MLX4_COMMAND_INTERFACE_MAX_REV = 3,
46 MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS = 3,
47 };
48
49 extern void __buggy_use_of_MLX4_GET(void);
50 extern void __buggy_use_of_MLX4_PUT(void);
51
52 static bool enable_qos;
53 module_param(enable_qos, bool, 0444);
54 MODULE_PARM_DESC(enable_qos, "Enable Quality of Service support in the HCA (default: off)");
55
56 #define MLX4_GET(dest, source, offset) \
57 do { \
58 void *__p = (char *) (source) + (offset); \
59 switch (sizeof (dest)) { \
60 case 1: (dest) = *(u8 *) __p; break; \
61 case 2: (dest) = be16_to_cpup(__p); break; \
62 case 4: (dest) = be32_to_cpup(__p); break; \
63 case 8: (dest) = be64_to_cpup(__p); break; \
64 default: __buggy_use_of_MLX4_GET(); \
65 } \
66 } while (0)
67
68 #define MLX4_PUT(dest, source, offset) \
69 do { \
70 void *__d = ((char *) (dest) + (offset)); \
71 switch (sizeof(source)) { \
72 case 1: *(u8 *) __d = (source); break; \
73 case 2: *(__be16 *) __d = cpu_to_be16(source); break; \
74 case 4: *(__be32 *) __d = cpu_to_be32(source); break; \
75 case 8: *(__be64 *) __d = cpu_to_be64(source); break; \
76 default: __buggy_use_of_MLX4_PUT(); \
77 } \
78 } while (0)
79
80 static void dump_dev_cap_flags(struct mlx4_dev *dev, u64 flags)
81 {
82 static const char *fname[] = {
83 [ 0] = "RC transport",
84 [ 1] = "UC transport",
85 [ 2] = "UD transport",
86 [ 3] = "XRC transport",
87 [ 4] = "reliable multicast",
88 [ 5] = "FCoIB support",
89 [ 6] = "SRQ support",
90 [ 7] = "IPoIB checksum offload",
91 [ 8] = "P_Key violation counter",
92 [ 9] = "Q_Key violation counter",
93 [10] = "VMM",
94 [12] = "Dual Port Different Protocol (DPDP) support",
95 [15] = "Big LSO headers",
96 [16] = "MW support",
97 [17] = "APM support",
98 [18] = "Atomic ops support",
99 [19] = "Raw multicast support",
100 [20] = "Address vector port checking support",
101 [21] = "UD multicast support",
102 [24] = "Demand paging support",
103 [25] = "Router support",
104 [30] = "IBoE support",
105 [32] = "Unicast loopback support",
106 [34] = "FCS header control",
107 [38] = "Wake On LAN support",
108 [40] = "UDP RSS support",
109 [41] = "Unicast VEP steering support",
110 [42] = "Multicast VEP steering support",
111 [48] = "Counters support",
112 [53] = "Port ETS Scheduler support",
113 [55] = "Port link type sensing support",
114 [59] = "Port management change event support",
115 [61] = "64 byte EQE support",
116 [62] = "64 byte CQE support",
117 };
118 int i;
119
120 mlx4_dbg(dev, "DEV_CAP flags:\n");
121 for (i = 0; i < ARRAY_SIZE(fname); ++i)
122 if (fname[i] && (flags & (1LL << i)))
123 mlx4_dbg(dev, " %s\n", fname[i]);
124 }
125
126 static void dump_dev_cap_flags2(struct mlx4_dev *dev, u64 flags)
127 {
128 static const char * const fname[] = {
129 [0] = "RSS support",
130 [1] = "RSS Toeplitz Hash Function support",
131 [2] = "RSS XOR Hash Function support",
132 [3] = "Device manage flow steering support",
133 [4] = "Automatic MAC reassignment support",
134 [5] = "Time stamping support",
135 [6] = "VST (control vlan insertion/stripping) support",
136 [7] = "FSM (MAC anti-spoofing) support",
137 [8] = "Dynamic QP updates support",
138 [9] = "TCP/IP offloads/flow-steering for VXLAN support"
139 };
140 int i;
141
142 for (i = 0; i < ARRAY_SIZE(fname); ++i)
143 if (fname[i] && (flags & (1LL << i)))
144 mlx4_dbg(dev, " %s\n", fname[i]);
145 }
146
147 int mlx4_MOD_STAT_CFG(struct mlx4_dev *dev, struct mlx4_mod_stat_cfg *cfg)
148 {
149 struct mlx4_cmd_mailbox *mailbox;
150 u32 *inbox;
151 int err = 0;
152
153 #define MOD_STAT_CFG_IN_SIZE 0x100
154
155 #define MOD_STAT_CFG_PG_SZ_M_OFFSET 0x002
156 #define MOD_STAT_CFG_PG_SZ_OFFSET 0x003
157
158 mailbox = mlx4_alloc_cmd_mailbox(dev);
159 if (IS_ERR(mailbox))
160 return PTR_ERR(mailbox);
161 inbox = mailbox->buf;
162
163 MLX4_PUT(inbox, cfg->log_pg_sz, MOD_STAT_CFG_PG_SZ_OFFSET);
164 MLX4_PUT(inbox, cfg->log_pg_sz_m, MOD_STAT_CFG_PG_SZ_M_OFFSET);
165
166 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_MOD_STAT_CFG,
167 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
168
169 mlx4_free_cmd_mailbox(dev, mailbox);
170 return err;
171 }
172
173 int mlx4_QUERY_FUNC_CAP_wrapper(struct mlx4_dev *dev, int slave,
174 struct mlx4_vhcr *vhcr,
175 struct mlx4_cmd_mailbox *inbox,
176 struct mlx4_cmd_mailbox *outbox,
177 struct mlx4_cmd_info *cmd)
178 {
179 struct mlx4_priv *priv = mlx4_priv(dev);
180 u8 field;
181 u32 size;
182 int err = 0;
183
184 #define QUERY_FUNC_CAP_FLAGS_OFFSET 0x0
185 #define QUERY_FUNC_CAP_NUM_PORTS_OFFSET 0x1
186 #define QUERY_FUNC_CAP_PF_BHVR_OFFSET 0x4
187 #define QUERY_FUNC_CAP_FMR_OFFSET 0x8
188 #define QUERY_FUNC_CAP_QP_QUOTA_OFFSET_DEP 0x10
189 #define QUERY_FUNC_CAP_CQ_QUOTA_OFFSET_DEP 0x14
190 #define QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET_DEP 0x18
191 #define QUERY_FUNC_CAP_MPT_QUOTA_OFFSET_DEP 0x20
192 #define QUERY_FUNC_CAP_MTT_QUOTA_OFFSET_DEP 0x24
193 #define QUERY_FUNC_CAP_MCG_QUOTA_OFFSET_DEP 0x28
194 #define QUERY_FUNC_CAP_MAX_EQ_OFFSET 0x2c
195 #define QUERY_FUNC_CAP_RESERVED_EQ_OFFSET 0x30
196
197 #define QUERY_FUNC_CAP_QP_QUOTA_OFFSET 0x50
198 #define QUERY_FUNC_CAP_CQ_QUOTA_OFFSET 0x54
199 #define QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET 0x58
200 #define QUERY_FUNC_CAP_MPT_QUOTA_OFFSET 0x60
201 #define QUERY_FUNC_CAP_MTT_QUOTA_OFFSET 0x64
202 #define QUERY_FUNC_CAP_MCG_QUOTA_OFFSET 0x68
203
204 #define QUERY_FUNC_CAP_FMR_FLAG 0x80
205 #define QUERY_FUNC_CAP_FLAG_RDMA 0x40
206 #define QUERY_FUNC_CAP_FLAG_ETH 0x80
207 #define QUERY_FUNC_CAP_FLAG_QUOTAS 0x10
208
209 /* when opcode modifier = 1 */
210 #define QUERY_FUNC_CAP_PHYS_PORT_OFFSET 0x3
211 #define QUERY_FUNC_CAP_FLAGS0_OFFSET 0x8
212 #define QUERY_FUNC_CAP_FLAGS1_OFFSET 0xc
213
214 #define QUERY_FUNC_CAP_QP0_TUNNEL 0x10
215 #define QUERY_FUNC_CAP_QP0_PROXY 0x14
216 #define QUERY_FUNC_CAP_QP1_TUNNEL 0x18
217 #define QUERY_FUNC_CAP_QP1_PROXY 0x1c
218 #define QUERY_FUNC_CAP_PHYS_PORT_ID 0x28
219
220 #define QUERY_FUNC_CAP_FLAGS1_FORCE_MAC 0x40
221 #define QUERY_FUNC_CAP_FLAGS1_FORCE_VLAN 0x80
222 #define QUERY_FUNC_CAP_FLAGS1_NIC_INFO 0x10
223
224 #define QUERY_FUNC_CAP_FLAGS0_FORCE_PHY_WQE_GID 0x80
225
226 if (vhcr->op_modifier == 1) {
227 /* Set nic_info bit to mark new fields support */
228 field = QUERY_FUNC_CAP_FLAGS1_NIC_INFO;
229 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FLAGS1_OFFSET);
230
231 field = vhcr->in_modifier; /* phys-port = logical-port */
232 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_PHYS_PORT_OFFSET);
233
234 /* size is now the QP number */
235 size = dev->phys_caps.base_tunnel_sqpn + 8 * slave + field - 1;
236 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP0_TUNNEL);
237
238 size += 2;
239 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP1_TUNNEL);
240
241 size = dev->phys_caps.base_proxy_sqpn + 8 * slave + field - 1;
242 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP0_PROXY);
243
244 size += 2;
245 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP1_PROXY);
246
247 MLX4_PUT(outbox->buf, dev->caps.phys_port_id[vhcr->in_modifier],
248 QUERY_FUNC_CAP_PHYS_PORT_ID);
249
250 } else if (vhcr->op_modifier == 0) {
251 /* enable rdma and ethernet interfaces, and new quota locations */
252 field = (QUERY_FUNC_CAP_FLAG_ETH | QUERY_FUNC_CAP_FLAG_RDMA |
253 QUERY_FUNC_CAP_FLAG_QUOTAS);
254 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FLAGS_OFFSET);
255
256 field = dev->caps.num_ports;
257 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_NUM_PORTS_OFFSET);
258
259 size = dev->caps.function_caps; /* set PF behaviours */
260 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_PF_BHVR_OFFSET);
261
262 field = 0; /* protected FMR support not available as yet */
263 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FMR_OFFSET);
264
265 size = priv->mfunc.master.res_tracker.res_alloc[RES_QP].quota[slave];
266 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP_QUOTA_OFFSET);
267 size = dev->caps.num_qps;
268 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP_QUOTA_OFFSET_DEP);
269
270 size = priv->mfunc.master.res_tracker.res_alloc[RES_SRQ].quota[slave];
271 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET);
272 size = dev->caps.num_srqs;
273 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET_DEP);
274
275 size = priv->mfunc.master.res_tracker.res_alloc[RES_CQ].quota[slave];
276 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET);
277 size = dev->caps.num_cqs;
278 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET_DEP);
279
280 size = dev->caps.num_eqs;
281 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MAX_EQ_OFFSET);
282
283 size = dev->caps.reserved_eqs;
284 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET);
285
286 size = priv->mfunc.master.res_tracker.res_alloc[RES_MPT].quota[slave];
287 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET);
288 size = dev->caps.num_mpts;
289 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET_DEP);
290
291 size = priv->mfunc.master.res_tracker.res_alloc[RES_MTT].quota[slave];
292 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET);
293 size = dev->caps.num_mtts;
294 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET_DEP);
295
296 size = dev->caps.num_mgms + dev->caps.num_amgms;
297 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET);
298 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET_DEP);
299
300 } else
301 err = -EINVAL;
302
303 return err;
304 }
305
306 int mlx4_QUERY_FUNC_CAP(struct mlx4_dev *dev, u32 gen_or_port,
307 struct mlx4_func_cap *func_cap)
308 {
309 struct mlx4_cmd_mailbox *mailbox;
310 u32 *outbox;
311 u8 field, op_modifier;
312 u32 size;
313 int err = 0, quotas = 0;
314
315 op_modifier = !!gen_or_port; /* 0 = general, 1 = logical port */
316
317 mailbox = mlx4_alloc_cmd_mailbox(dev);
318 if (IS_ERR(mailbox))
319 return PTR_ERR(mailbox);
320
321 err = mlx4_cmd_box(dev, 0, mailbox->dma, gen_or_port, op_modifier,
322 MLX4_CMD_QUERY_FUNC_CAP,
323 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
324 if (err)
325 goto out;
326
327 outbox = mailbox->buf;
328
329 if (!op_modifier) {
330 MLX4_GET(field, outbox, QUERY_FUNC_CAP_FLAGS_OFFSET);
331 if (!(field & (QUERY_FUNC_CAP_FLAG_ETH | QUERY_FUNC_CAP_FLAG_RDMA))) {
332 mlx4_err(dev, "The host supports neither eth nor rdma interfaces\n");
333 err = -EPROTONOSUPPORT;
334 goto out;
335 }
336 func_cap->flags = field;
337 quotas = !!(func_cap->flags & QUERY_FUNC_CAP_FLAG_QUOTAS);
338
339 MLX4_GET(field, outbox, QUERY_FUNC_CAP_NUM_PORTS_OFFSET);
340 func_cap->num_ports = field;
341
342 MLX4_GET(size, outbox, QUERY_FUNC_CAP_PF_BHVR_OFFSET);
343 func_cap->pf_context_behaviour = size;
344
345 if (quotas) {
346 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP_QUOTA_OFFSET);
347 func_cap->qp_quota = size & 0xFFFFFF;
348
349 MLX4_GET(size, outbox, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET);
350 func_cap->srq_quota = size & 0xFFFFFF;
351
352 MLX4_GET(size, outbox, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET);
353 func_cap->cq_quota = size & 0xFFFFFF;
354
355 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET);
356 func_cap->mpt_quota = size & 0xFFFFFF;
357
358 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET);
359 func_cap->mtt_quota = size & 0xFFFFFF;
360
361 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET);
362 func_cap->mcg_quota = size & 0xFFFFFF;
363
364 } else {
365 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP_QUOTA_OFFSET_DEP);
366 func_cap->qp_quota = size & 0xFFFFFF;
367
368 MLX4_GET(size, outbox, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET_DEP);
369 func_cap->srq_quota = size & 0xFFFFFF;
370
371 MLX4_GET(size, outbox, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET_DEP);
372 func_cap->cq_quota = size & 0xFFFFFF;
373
374 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET_DEP);
375 func_cap->mpt_quota = size & 0xFFFFFF;
376
377 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET_DEP);
378 func_cap->mtt_quota = size & 0xFFFFFF;
379
380 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET_DEP);
381 func_cap->mcg_quota = size & 0xFFFFFF;
382 }
383 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MAX_EQ_OFFSET);
384 func_cap->max_eq = size & 0xFFFFFF;
385
386 MLX4_GET(size, outbox, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET);
387 func_cap->reserved_eq = size & 0xFFFFFF;
388
389 goto out;
390 }
391
392 /* logical port query */
393 if (gen_or_port > dev->caps.num_ports) {
394 err = -EINVAL;
395 goto out;
396 }
397
398 MLX4_GET(func_cap->flags1, outbox, QUERY_FUNC_CAP_FLAGS1_OFFSET);
399 if (dev->caps.port_type[gen_or_port] == MLX4_PORT_TYPE_ETH) {
400 if (func_cap->flags1 & QUERY_FUNC_CAP_FLAGS1_OFFSET) {
401 mlx4_err(dev, "VLAN is enforced on this port\n");
402 err = -EPROTONOSUPPORT;
403 goto out;
404 }
405
406 if (func_cap->flags1 & QUERY_FUNC_CAP_FLAGS1_FORCE_MAC) {
407 mlx4_err(dev, "Force mac is enabled on this port\n");
408 err = -EPROTONOSUPPORT;
409 goto out;
410 }
411 } else if (dev->caps.port_type[gen_or_port] == MLX4_PORT_TYPE_IB) {
412 MLX4_GET(field, outbox, QUERY_FUNC_CAP_FLAGS0_OFFSET);
413 if (field & QUERY_FUNC_CAP_FLAGS0_FORCE_PHY_WQE_GID) {
414 mlx4_err(dev, "phy_wqe_gid is "
415 "enforced on this ib port\n");
416 err = -EPROTONOSUPPORT;
417 goto out;
418 }
419 }
420
421 MLX4_GET(field, outbox, QUERY_FUNC_CAP_PHYS_PORT_OFFSET);
422 func_cap->physical_port = field;
423 if (func_cap->physical_port != gen_or_port) {
424 err = -ENOSYS;
425 goto out;
426 }
427
428 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP0_TUNNEL);
429 func_cap->qp0_tunnel_qpn = size & 0xFFFFFF;
430
431 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP0_PROXY);
432 func_cap->qp0_proxy_qpn = size & 0xFFFFFF;
433
434 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP1_TUNNEL);
435 func_cap->qp1_tunnel_qpn = size & 0xFFFFFF;
436
437 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP1_PROXY);
438 func_cap->qp1_proxy_qpn = size & 0xFFFFFF;
439
440 if (func_cap->flags1 & QUERY_FUNC_CAP_FLAGS1_NIC_INFO)
441 MLX4_GET(func_cap->phys_port_id, outbox,
442 QUERY_FUNC_CAP_PHYS_PORT_ID);
443
444 /* All other resources are allocated by the master, but we still report
445 * 'num' and 'reserved' capabilities as follows:
446 * - num remains the maximum resource index
447 * - 'num - reserved' is the total available objects of a resource, but
448 * resource indices may be less than 'reserved'
449 * TODO: set per-resource quotas */
450
451 out:
452 mlx4_free_cmd_mailbox(dev, mailbox);
453
454 return err;
455 }
456
457 int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
458 {
459 struct mlx4_cmd_mailbox *mailbox;
460 u32 *outbox;
461 u8 field;
462 u32 field32, flags, ext_flags;
463 u16 size;
464 u16 stat_rate;
465 int err;
466 int i;
467
468 #define QUERY_DEV_CAP_OUT_SIZE 0x100
469 #define QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET 0x10
470 #define QUERY_DEV_CAP_MAX_QP_SZ_OFFSET 0x11
471 #define QUERY_DEV_CAP_RSVD_QP_OFFSET 0x12
472 #define QUERY_DEV_CAP_MAX_QP_OFFSET 0x13
473 #define QUERY_DEV_CAP_RSVD_SRQ_OFFSET 0x14
474 #define QUERY_DEV_CAP_MAX_SRQ_OFFSET 0x15
475 #define QUERY_DEV_CAP_RSVD_EEC_OFFSET 0x16
476 #define QUERY_DEV_CAP_MAX_EEC_OFFSET 0x17
477 #define QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET 0x19
478 #define QUERY_DEV_CAP_RSVD_CQ_OFFSET 0x1a
479 #define QUERY_DEV_CAP_MAX_CQ_OFFSET 0x1b
480 #define QUERY_DEV_CAP_MAX_MPT_OFFSET 0x1d
481 #define QUERY_DEV_CAP_RSVD_EQ_OFFSET 0x1e
482 #define QUERY_DEV_CAP_MAX_EQ_OFFSET 0x1f
483 #define QUERY_DEV_CAP_RSVD_MTT_OFFSET 0x20
484 #define QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET 0x21
485 #define QUERY_DEV_CAP_RSVD_MRW_OFFSET 0x22
486 #define QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET 0x23
487 #define QUERY_DEV_CAP_MAX_AV_OFFSET 0x27
488 #define QUERY_DEV_CAP_MAX_REQ_QP_OFFSET 0x29
489 #define QUERY_DEV_CAP_MAX_RES_QP_OFFSET 0x2b
490 #define QUERY_DEV_CAP_MAX_GSO_OFFSET 0x2d
491 #define QUERY_DEV_CAP_RSS_OFFSET 0x2e
492 #define QUERY_DEV_CAP_MAX_RDMA_OFFSET 0x2f
493 #define QUERY_DEV_CAP_RSZ_SRQ_OFFSET 0x33
494 #define QUERY_DEV_CAP_ACK_DELAY_OFFSET 0x35
495 #define QUERY_DEV_CAP_MTU_WIDTH_OFFSET 0x36
496 #define QUERY_DEV_CAP_VL_PORT_OFFSET 0x37
497 #define QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET 0x38
498 #define QUERY_DEV_CAP_MAX_GID_OFFSET 0x3b
499 #define QUERY_DEV_CAP_RATE_SUPPORT_OFFSET 0x3c
500 #define QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET 0x3e
501 #define QUERY_DEV_CAP_MAX_PKEY_OFFSET 0x3f
502 #define QUERY_DEV_CAP_EXT_FLAGS_OFFSET 0x40
503 #define QUERY_DEV_CAP_FLAGS_OFFSET 0x44
504 #define QUERY_DEV_CAP_RSVD_UAR_OFFSET 0x48
505 #define QUERY_DEV_CAP_UAR_SZ_OFFSET 0x49
506 #define QUERY_DEV_CAP_PAGE_SZ_OFFSET 0x4b
507 #define QUERY_DEV_CAP_BF_OFFSET 0x4c
508 #define QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET 0x4d
509 #define QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET 0x4e
510 #define QUERY_DEV_CAP_LOG_MAX_BF_PAGES_OFFSET 0x4f
511 #define QUERY_DEV_CAP_MAX_SG_SQ_OFFSET 0x51
512 #define QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET 0x52
513 #define QUERY_DEV_CAP_MAX_SG_RQ_OFFSET 0x55
514 #define QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET 0x56
515 #define QUERY_DEV_CAP_MAX_QP_MCG_OFFSET 0x61
516 #define QUERY_DEV_CAP_RSVD_MCG_OFFSET 0x62
517 #define QUERY_DEV_CAP_MAX_MCG_OFFSET 0x63
518 #define QUERY_DEV_CAP_RSVD_PD_OFFSET 0x64
519 #define QUERY_DEV_CAP_MAX_PD_OFFSET 0x65
520 #define QUERY_DEV_CAP_RSVD_XRC_OFFSET 0x66
521 #define QUERY_DEV_CAP_MAX_XRC_OFFSET 0x67
522 #define QUERY_DEV_CAP_MAX_COUNTERS_OFFSET 0x68
523 #define QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET 0x70
524 #define QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET 0x74
525 #define QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET 0x76
526 #define QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET 0x77
527 #define QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET 0x80
528 #define QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET 0x82
529 #define QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET 0x84
530 #define QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET 0x86
531 #define QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET 0x88
532 #define QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET 0x8a
533 #define QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET 0x8c
534 #define QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET 0x8e
535 #define QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET 0x90
536 #define QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET 0x92
537 #define QUERY_DEV_CAP_BMME_FLAGS_OFFSET 0x94
538 #define QUERY_DEV_CAP_RSVD_LKEY_OFFSET 0x98
539 #define QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET 0xa0
540 #define QUERY_DEV_CAP_FW_REASSIGN_MAC 0x9d
541 #define QUERY_DEV_CAP_VXLAN 0x9e
542
543 dev_cap->flags2 = 0;
544 mailbox = mlx4_alloc_cmd_mailbox(dev);
545 if (IS_ERR(mailbox))
546 return PTR_ERR(mailbox);
547 outbox = mailbox->buf;
548
549 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP,
550 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
551 if (err)
552 goto out;
553
554 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_QP_OFFSET);
555 dev_cap->reserved_qps = 1 << (field & 0xf);
556 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_OFFSET);
557 dev_cap->max_qps = 1 << (field & 0x1f);
558 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_SRQ_OFFSET);
559 dev_cap->reserved_srqs = 1 << (field >> 4);
560 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_OFFSET);
561 dev_cap->max_srqs = 1 << (field & 0x1f);
562 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET);
563 dev_cap->max_cq_sz = 1 << field;
564 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_CQ_OFFSET);
565 dev_cap->reserved_cqs = 1 << (field & 0xf);
566 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_OFFSET);
567 dev_cap->max_cqs = 1 << (field & 0x1f);
568 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MPT_OFFSET);
569 dev_cap->max_mpts = 1 << (field & 0x3f);
570 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_EQ_OFFSET);
571 dev_cap->reserved_eqs = field & 0xf;
572 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_EQ_OFFSET);
573 dev_cap->max_eqs = 1 << (field & 0xf);
574 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MTT_OFFSET);
575 dev_cap->reserved_mtts = 1 << (field >> 4);
576 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET);
577 dev_cap->max_mrw_sz = 1 << field;
578 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MRW_OFFSET);
579 dev_cap->reserved_mrws = 1 << (field & 0xf);
580 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET);
581 dev_cap->max_mtt_seg = 1 << (field & 0x3f);
582 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_REQ_QP_OFFSET);
583 dev_cap->max_requester_per_qp = 1 << (field & 0x3f);
584 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RES_QP_OFFSET);
585 dev_cap->max_responder_per_qp = 1 << (field & 0x3f);
586 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GSO_OFFSET);
587 field &= 0x1f;
588 if (!field)
589 dev_cap->max_gso_sz = 0;
590 else
591 dev_cap->max_gso_sz = 1 << field;
592
593 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSS_OFFSET);
594 if (field & 0x20)
595 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_XOR;
596 if (field & 0x10)
597 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_TOP;
598 field &= 0xf;
599 if (field) {
600 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS;
601 dev_cap->max_rss_tbl_sz = 1 << field;
602 } else
603 dev_cap->max_rss_tbl_sz = 0;
604 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RDMA_OFFSET);
605 dev_cap->max_rdma_global = 1 << (field & 0x3f);
606 MLX4_GET(field, outbox, QUERY_DEV_CAP_ACK_DELAY_OFFSET);
607 dev_cap->local_ca_ack_delay = field & 0x1f;
608 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET);
609 dev_cap->num_ports = field & 0xf;
610 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET);
611 dev_cap->max_msg_sz = 1 << (field & 0x1f);
612 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET);
613 if (field & 0x80)
614 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FS_EN;
615 dev_cap->fs_log_max_ucast_qp_range_size = field & 0x1f;
616 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET);
617 if (field & 0x80)
618 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_DMFS_IPOIB;
619 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET);
620 dev_cap->fs_max_num_qp_per_entry = field;
621 MLX4_GET(stat_rate, outbox, QUERY_DEV_CAP_RATE_SUPPORT_OFFSET);
622 dev_cap->stat_rate_support = stat_rate;
623 MLX4_GET(field, outbox, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET);
624 if (field & 0x80)
625 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_TS;
626 MLX4_GET(ext_flags, outbox, QUERY_DEV_CAP_EXT_FLAGS_OFFSET);
627 MLX4_GET(flags, outbox, QUERY_DEV_CAP_FLAGS_OFFSET);
628 dev_cap->flags = flags | (u64)ext_flags << 32;
629 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_UAR_OFFSET);
630 dev_cap->reserved_uars = field >> 4;
631 MLX4_GET(field, outbox, QUERY_DEV_CAP_UAR_SZ_OFFSET);
632 dev_cap->uar_size = 1 << ((field & 0x3f) + 20);
633 MLX4_GET(field, outbox, QUERY_DEV_CAP_PAGE_SZ_OFFSET);
634 dev_cap->min_page_sz = 1 << field;
635
636 MLX4_GET(field, outbox, QUERY_DEV_CAP_BF_OFFSET);
637 if (field & 0x80) {
638 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET);
639 dev_cap->bf_reg_size = 1 << (field & 0x1f);
640 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET);
641 if ((1 << (field & 0x3f)) > (PAGE_SIZE / dev_cap->bf_reg_size))
642 field = 3;
643 dev_cap->bf_regs_per_page = 1 << (field & 0x3f);
644 mlx4_dbg(dev, "BlueFlame available (reg size %d, regs/page %d)\n",
645 dev_cap->bf_reg_size, dev_cap->bf_regs_per_page);
646 } else {
647 dev_cap->bf_reg_size = 0;
648 mlx4_dbg(dev, "BlueFlame not available\n");
649 }
650
651 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_SQ_OFFSET);
652 dev_cap->max_sq_sg = field;
653 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET);
654 dev_cap->max_sq_desc_sz = size;
655
656 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_MCG_OFFSET);
657 dev_cap->max_qp_per_mcg = 1 << field;
658 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MCG_OFFSET);
659 dev_cap->reserved_mgms = field & 0xf;
660 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MCG_OFFSET);
661 dev_cap->max_mcgs = 1 << field;
662 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_PD_OFFSET);
663 dev_cap->reserved_pds = field >> 4;
664 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PD_OFFSET);
665 dev_cap->max_pds = 1 << (field & 0x3f);
666 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_XRC_OFFSET);
667 dev_cap->reserved_xrcds = field >> 4;
668 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_XRC_OFFSET);
669 dev_cap->max_xrcds = 1 << (field & 0x1f);
670
671 MLX4_GET(size, outbox, QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET);
672 dev_cap->rdmarc_entry_sz = size;
673 MLX4_GET(size, outbox, QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET);
674 dev_cap->qpc_entry_sz = size;
675 MLX4_GET(size, outbox, QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET);
676 dev_cap->aux_entry_sz = size;
677 MLX4_GET(size, outbox, QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET);
678 dev_cap->altc_entry_sz = size;
679 MLX4_GET(size, outbox, QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET);
680 dev_cap->eqc_entry_sz = size;
681 MLX4_GET(size, outbox, QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET);
682 dev_cap->cqc_entry_sz = size;
683 MLX4_GET(size, outbox, QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET);
684 dev_cap->srq_entry_sz = size;
685 MLX4_GET(size, outbox, QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET);
686 dev_cap->cmpt_entry_sz = size;
687 MLX4_GET(size, outbox, QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET);
688 dev_cap->mtt_entry_sz = size;
689 MLX4_GET(size, outbox, QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET);
690 dev_cap->dmpt_entry_sz = size;
691
692 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET);
693 dev_cap->max_srq_sz = 1 << field;
694 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_SZ_OFFSET);
695 dev_cap->max_qp_sz = 1 << field;
696 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSZ_SRQ_OFFSET);
697 dev_cap->resize_srq = field & 1;
698 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_RQ_OFFSET);
699 dev_cap->max_rq_sg = field;
700 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET);
701 dev_cap->max_rq_desc_sz = size;
702
703 MLX4_GET(dev_cap->bmme_flags, outbox,
704 QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
705 MLX4_GET(dev_cap->reserved_lkey, outbox,
706 QUERY_DEV_CAP_RSVD_LKEY_OFFSET);
707 MLX4_GET(field, outbox, QUERY_DEV_CAP_FW_REASSIGN_MAC);
708 if (field & 1<<6)
709 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN;
710 MLX4_GET(field, outbox, QUERY_DEV_CAP_VXLAN);
711 if (field & 1<<3)
712 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS;
713 MLX4_GET(dev_cap->max_icm_sz, outbox,
714 QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET);
715 if (dev_cap->flags & MLX4_DEV_CAP_FLAG_COUNTERS)
716 MLX4_GET(dev_cap->max_counters, outbox,
717 QUERY_DEV_CAP_MAX_COUNTERS_OFFSET);
718
719 MLX4_GET(field32, outbox, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET);
720 if (field32 & (1 << 16))
721 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_UPDATE_QP;
722 if (field32 & (1 << 26))
723 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_VLAN_CONTROL;
724 if (field32 & (1 << 20))
725 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FSM;
726
727 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
728 for (i = 1; i <= dev_cap->num_ports; ++i) {
729 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET);
730 dev_cap->max_vl[i] = field >> 4;
731 MLX4_GET(field, outbox, QUERY_DEV_CAP_MTU_WIDTH_OFFSET);
732 dev_cap->ib_mtu[i] = field >> 4;
733 dev_cap->max_port_width[i] = field & 0xf;
734 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GID_OFFSET);
735 dev_cap->max_gids[i] = 1 << (field & 0xf);
736 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PKEY_OFFSET);
737 dev_cap->max_pkeys[i] = 1 << (field & 0xf);
738 }
739 } else {
740 #define QUERY_PORT_SUPPORTED_TYPE_OFFSET 0x00
741 #define QUERY_PORT_MTU_OFFSET 0x01
742 #define QUERY_PORT_ETH_MTU_OFFSET 0x02
743 #define QUERY_PORT_WIDTH_OFFSET 0x06
744 #define QUERY_PORT_MAX_GID_PKEY_OFFSET 0x07
745 #define QUERY_PORT_MAX_MACVLAN_OFFSET 0x0a
746 #define QUERY_PORT_MAX_VL_OFFSET 0x0b
747 #define QUERY_PORT_MAC_OFFSET 0x10
748 #define QUERY_PORT_TRANS_VENDOR_OFFSET 0x18
749 #define QUERY_PORT_WAVELENGTH_OFFSET 0x1c
750 #define QUERY_PORT_TRANS_CODE_OFFSET 0x20
751
752 for (i = 1; i <= dev_cap->num_ports; ++i) {
753 err = mlx4_cmd_box(dev, 0, mailbox->dma, i, 0, MLX4_CMD_QUERY_PORT,
754 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
755 if (err)
756 goto out;
757
758 MLX4_GET(field, outbox, QUERY_PORT_SUPPORTED_TYPE_OFFSET);
759 dev_cap->supported_port_types[i] = field & 3;
760 dev_cap->suggested_type[i] = (field >> 3) & 1;
761 dev_cap->default_sense[i] = (field >> 4) & 1;
762 MLX4_GET(field, outbox, QUERY_PORT_MTU_OFFSET);
763 dev_cap->ib_mtu[i] = field & 0xf;
764 MLX4_GET(field, outbox, QUERY_PORT_WIDTH_OFFSET);
765 dev_cap->max_port_width[i] = field & 0xf;
766 MLX4_GET(field, outbox, QUERY_PORT_MAX_GID_PKEY_OFFSET);
767 dev_cap->max_gids[i] = 1 << (field >> 4);
768 dev_cap->max_pkeys[i] = 1 << (field & 0xf);
769 MLX4_GET(field, outbox, QUERY_PORT_MAX_VL_OFFSET);
770 dev_cap->max_vl[i] = field & 0xf;
771 MLX4_GET(field, outbox, QUERY_PORT_MAX_MACVLAN_OFFSET);
772 dev_cap->log_max_macs[i] = field & 0xf;
773 dev_cap->log_max_vlans[i] = field >> 4;
774 MLX4_GET(dev_cap->eth_mtu[i], outbox, QUERY_PORT_ETH_MTU_OFFSET);
775 MLX4_GET(dev_cap->def_mac[i], outbox, QUERY_PORT_MAC_OFFSET);
776 MLX4_GET(field32, outbox, QUERY_PORT_TRANS_VENDOR_OFFSET);
777 dev_cap->trans_type[i] = field32 >> 24;
778 dev_cap->vendor_oui[i] = field32 & 0xffffff;
779 MLX4_GET(dev_cap->wavelength[i], outbox, QUERY_PORT_WAVELENGTH_OFFSET);
780 MLX4_GET(dev_cap->trans_code[i], outbox, QUERY_PORT_TRANS_CODE_OFFSET);
781 }
782 }
783
784 mlx4_dbg(dev, "Base MM extensions: flags %08x, rsvd L_Key %08x\n",
785 dev_cap->bmme_flags, dev_cap->reserved_lkey);
786
787 /*
788 * Each UAR has 4 EQ doorbells; so if a UAR is reserved, then
789 * we can't use any EQs whose doorbell falls on that page,
790 * even if the EQ itself isn't reserved.
791 */
792 dev_cap->reserved_eqs = max(dev_cap->reserved_uars * 4,
793 dev_cap->reserved_eqs);
794
795 mlx4_dbg(dev, "Max ICM size %lld MB\n",
796 (unsigned long long) dev_cap->max_icm_sz >> 20);
797 mlx4_dbg(dev, "Max QPs: %d, reserved QPs: %d, entry size: %d\n",
798 dev_cap->max_qps, dev_cap->reserved_qps, dev_cap->qpc_entry_sz);
799 mlx4_dbg(dev, "Max SRQs: %d, reserved SRQs: %d, entry size: %d\n",
800 dev_cap->max_srqs, dev_cap->reserved_srqs, dev_cap->srq_entry_sz);
801 mlx4_dbg(dev, "Max CQs: %d, reserved CQs: %d, entry size: %d\n",
802 dev_cap->max_cqs, dev_cap->reserved_cqs, dev_cap->cqc_entry_sz);
803 mlx4_dbg(dev, "Max EQs: %d, reserved EQs: %d, entry size: %d\n",
804 dev_cap->max_eqs, dev_cap->reserved_eqs, dev_cap->eqc_entry_sz);
805 mlx4_dbg(dev, "reserved MPTs: %d, reserved MTTs: %d\n",
806 dev_cap->reserved_mrws, dev_cap->reserved_mtts);
807 mlx4_dbg(dev, "Max PDs: %d, reserved PDs: %d, reserved UARs: %d\n",
808 dev_cap->max_pds, dev_cap->reserved_pds, dev_cap->reserved_uars);
809 mlx4_dbg(dev, "Max QP/MCG: %d, reserved MGMs: %d\n",
810 dev_cap->max_pds, dev_cap->reserved_mgms);
811 mlx4_dbg(dev, "Max CQEs: %d, max WQEs: %d, max SRQ WQEs: %d\n",
812 dev_cap->max_cq_sz, dev_cap->max_qp_sz, dev_cap->max_srq_sz);
813 mlx4_dbg(dev, "Local CA ACK delay: %d, max MTU: %d, port width cap: %d\n",
814 dev_cap->local_ca_ack_delay, 128 << dev_cap->ib_mtu[1],
815 dev_cap->max_port_width[1]);
816 mlx4_dbg(dev, "Max SQ desc size: %d, max SQ S/G: %d\n",
817 dev_cap->max_sq_desc_sz, dev_cap->max_sq_sg);
818 mlx4_dbg(dev, "Max RQ desc size: %d, max RQ S/G: %d\n",
819 dev_cap->max_rq_desc_sz, dev_cap->max_rq_sg);
820 mlx4_dbg(dev, "Max GSO size: %d\n", dev_cap->max_gso_sz);
821 mlx4_dbg(dev, "Max counters: %d\n", dev_cap->max_counters);
822 mlx4_dbg(dev, "Max RSS Table size: %d\n", dev_cap->max_rss_tbl_sz);
823
824 dump_dev_cap_flags(dev, dev_cap->flags);
825 dump_dev_cap_flags2(dev, dev_cap->flags2);
826
827 out:
828 mlx4_free_cmd_mailbox(dev, mailbox);
829 return err;
830 }
831
832 int mlx4_QUERY_DEV_CAP_wrapper(struct mlx4_dev *dev, int slave,
833 struct mlx4_vhcr *vhcr,
834 struct mlx4_cmd_mailbox *inbox,
835 struct mlx4_cmd_mailbox *outbox,
836 struct mlx4_cmd_info *cmd)
837 {
838 u64 flags;
839 int err = 0;
840 u8 field;
841 u32 bmme_flags;
842
843 err = mlx4_cmd_box(dev, 0, outbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP,
844 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
845 if (err)
846 return err;
847
848 /* add port mng change event capability and disable mw type 1
849 * unconditionally to slaves
850 */
851 MLX4_GET(flags, outbox->buf, QUERY_DEV_CAP_EXT_FLAGS_OFFSET);
852 flags |= MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV;
853 flags &= ~MLX4_DEV_CAP_FLAG_MEM_WINDOW;
854 MLX4_PUT(outbox->buf, flags, QUERY_DEV_CAP_EXT_FLAGS_OFFSET);
855
856 /* For guests, disable timestamp */
857 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET);
858 field &= 0x7f;
859 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET);
860
861 /* For guests, disable vxlan tunneling */
862 MLX4_GET(field, outbox, QUERY_DEV_CAP_VXLAN);
863 field &= 0xf7;
864 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_VXLAN);
865
866 /* For guests, report Blueflame disabled */
867 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_BF_OFFSET);
868 field &= 0x7f;
869 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_BF_OFFSET);
870
871 /* For guests, disable mw type 2 */
872 MLX4_GET(bmme_flags, outbox, QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
873 bmme_flags &= ~MLX4_BMME_FLAG_TYPE_2_WIN;
874 MLX4_PUT(outbox->buf, bmme_flags, QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
875
876 /* turn off device-managed steering capability if not enabled */
877 if (dev->caps.steering_mode != MLX4_STEERING_MODE_DEVICE_MANAGED) {
878 MLX4_GET(field, outbox->buf,
879 QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET);
880 field &= 0x7f;
881 MLX4_PUT(outbox->buf, field,
882 QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET);
883 }
884
885 /* turn off ipoib managed steering for guests */
886 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET);
887 field &= ~0x80;
888 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET);
889
890 return 0;
891 }
892
893 int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave,
894 struct mlx4_vhcr *vhcr,
895 struct mlx4_cmd_mailbox *inbox,
896 struct mlx4_cmd_mailbox *outbox,
897 struct mlx4_cmd_info *cmd)
898 {
899 struct mlx4_priv *priv = mlx4_priv(dev);
900 u64 def_mac;
901 u8 port_type;
902 u16 short_field;
903 int err;
904 int admin_link_state;
905
906 #define MLX4_VF_PORT_NO_LINK_SENSE_MASK 0xE0
907 #define MLX4_PORT_LINK_UP_MASK 0x80
908 #define QUERY_PORT_CUR_MAX_PKEY_OFFSET 0x0c
909 #define QUERY_PORT_CUR_MAX_GID_OFFSET 0x0e
910
911 err = mlx4_cmd_box(dev, 0, outbox->dma, vhcr->in_modifier, 0,
912 MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B,
913 MLX4_CMD_NATIVE);
914
915 if (!err && dev->caps.function != slave) {
916 def_mac = priv->mfunc.master.vf_oper[slave].vport[vhcr->in_modifier].state.mac;
917 MLX4_PUT(outbox->buf, def_mac, QUERY_PORT_MAC_OFFSET);
918
919 /* get port type - currently only eth is enabled */
920 MLX4_GET(port_type, outbox->buf,
921 QUERY_PORT_SUPPORTED_TYPE_OFFSET);
922
923 /* No link sensing allowed */
924 port_type &= MLX4_VF_PORT_NO_LINK_SENSE_MASK;
925 /* set port type to currently operating port type */
926 port_type |= (dev->caps.port_type[vhcr->in_modifier] & 0x3);
927
928 admin_link_state = priv->mfunc.master.vf_oper[slave].vport[vhcr->in_modifier].state.link_state;
929 if (IFLA_VF_LINK_STATE_ENABLE == admin_link_state)
930 port_type |= MLX4_PORT_LINK_UP_MASK;
931 else if (IFLA_VF_LINK_STATE_DISABLE == admin_link_state)
932 port_type &= ~MLX4_PORT_LINK_UP_MASK;
933
934 MLX4_PUT(outbox->buf, port_type,
935 QUERY_PORT_SUPPORTED_TYPE_OFFSET);
936
937 if (dev->caps.port_type[vhcr->in_modifier] == MLX4_PORT_TYPE_ETH)
938 short_field = mlx4_get_slave_num_gids(dev, slave);
939 else
940 short_field = 1; /* slave max gids */
941 MLX4_PUT(outbox->buf, short_field,
942 QUERY_PORT_CUR_MAX_GID_OFFSET);
943
944 short_field = dev->caps.pkey_table_len[vhcr->in_modifier];
945 MLX4_PUT(outbox->buf, short_field,
946 QUERY_PORT_CUR_MAX_PKEY_OFFSET);
947 }
948
949 return err;
950 }
951
952 int mlx4_get_slave_pkey_gid_tbl_len(struct mlx4_dev *dev, u8 port,
953 int *gid_tbl_len, int *pkey_tbl_len)
954 {
955 struct mlx4_cmd_mailbox *mailbox;
956 u32 *outbox;
957 u16 field;
958 int err;
959
960 mailbox = mlx4_alloc_cmd_mailbox(dev);
961 if (IS_ERR(mailbox))
962 return PTR_ERR(mailbox);
963
964 err = mlx4_cmd_box(dev, 0, mailbox->dma, port, 0,
965 MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B,
966 MLX4_CMD_WRAPPED);
967 if (err)
968 goto out;
969
970 outbox = mailbox->buf;
971
972 MLX4_GET(field, outbox, QUERY_PORT_CUR_MAX_GID_OFFSET);
973 *gid_tbl_len = field;
974
975 MLX4_GET(field, outbox, QUERY_PORT_CUR_MAX_PKEY_OFFSET);
976 *pkey_tbl_len = field;
977
978 out:
979 mlx4_free_cmd_mailbox(dev, mailbox);
980 return err;
981 }
982 EXPORT_SYMBOL(mlx4_get_slave_pkey_gid_tbl_len);
983
984 int mlx4_map_cmd(struct mlx4_dev *dev, u16 op, struct mlx4_icm *icm, u64 virt)
985 {
986 struct mlx4_cmd_mailbox *mailbox;
987 struct mlx4_icm_iter iter;
988 __be64 *pages;
989 int lg;
990 int nent = 0;
991 int i;
992 int err = 0;
993 int ts = 0, tc = 0;
994
995 mailbox = mlx4_alloc_cmd_mailbox(dev);
996 if (IS_ERR(mailbox))
997 return PTR_ERR(mailbox);
998 pages = mailbox->buf;
999
1000 for (mlx4_icm_first(icm, &iter);
1001 !mlx4_icm_last(&iter);
1002 mlx4_icm_next(&iter)) {
1003 /*
1004 * We have to pass pages that are aligned to their
1005 * size, so find the least significant 1 in the
1006 * address or size and use that as our log2 size.
1007 */
1008 lg = ffs(mlx4_icm_addr(&iter) | mlx4_icm_size(&iter)) - 1;
1009 if (lg < MLX4_ICM_PAGE_SHIFT) {
1010 mlx4_warn(dev, "Got FW area not aligned to %d (%llx/%lx).\n",
1011 MLX4_ICM_PAGE_SIZE,
1012 (unsigned long long) mlx4_icm_addr(&iter),
1013 mlx4_icm_size(&iter));
1014 err = -EINVAL;
1015 goto out;
1016 }
1017
1018 for (i = 0; i < mlx4_icm_size(&iter) >> lg; ++i) {
1019 if (virt != -1) {
1020 pages[nent * 2] = cpu_to_be64(virt);
1021 virt += 1 << lg;
1022 }
1023
1024 pages[nent * 2 + 1] =
1025 cpu_to_be64((mlx4_icm_addr(&iter) + (i << lg)) |
1026 (lg - MLX4_ICM_PAGE_SHIFT));
1027 ts += 1 << (lg - 10);
1028 ++tc;
1029
1030 if (++nent == MLX4_MAILBOX_SIZE / 16) {
1031 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op,
1032 MLX4_CMD_TIME_CLASS_B,
1033 MLX4_CMD_NATIVE);
1034 if (err)
1035 goto out;
1036 nent = 0;
1037 }
1038 }
1039 }
1040
1041 if (nent)
1042 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op,
1043 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
1044 if (err)
1045 goto out;
1046
1047 switch (op) {
1048 case MLX4_CMD_MAP_FA:
1049 mlx4_dbg(dev, "Mapped %d chunks/%d KB for FW.\n", tc, ts);
1050 break;
1051 case MLX4_CMD_MAP_ICM_AUX:
1052 mlx4_dbg(dev, "Mapped %d chunks/%d KB for ICM aux.\n", tc, ts);
1053 break;
1054 case MLX4_CMD_MAP_ICM:
1055 mlx4_dbg(dev, "Mapped %d chunks/%d KB at %llx for ICM.\n",
1056 tc, ts, (unsigned long long) virt - (ts << 10));
1057 break;
1058 }
1059
1060 out:
1061 mlx4_free_cmd_mailbox(dev, mailbox);
1062 return err;
1063 }
1064
1065 int mlx4_MAP_FA(struct mlx4_dev *dev, struct mlx4_icm *icm)
1066 {
1067 return mlx4_map_cmd(dev, MLX4_CMD_MAP_FA, icm, -1);
1068 }
1069
1070 int mlx4_UNMAP_FA(struct mlx4_dev *dev)
1071 {
1072 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_UNMAP_FA,
1073 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
1074 }
1075
1076
1077 int mlx4_RUN_FW(struct mlx4_dev *dev)
1078 {
1079 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_RUN_FW,
1080 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1081 }
1082
1083 int mlx4_QUERY_FW(struct mlx4_dev *dev)
1084 {
1085 struct mlx4_fw *fw = &mlx4_priv(dev)->fw;
1086 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
1087 struct mlx4_cmd_mailbox *mailbox;
1088 u32 *outbox;
1089 int err = 0;
1090 u64 fw_ver;
1091 u16 cmd_if_rev;
1092 u8 lg;
1093
1094 #define QUERY_FW_OUT_SIZE 0x100
1095 #define QUERY_FW_VER_OFFSET 0x00
1096 #define QUERY_FW_PPF_ID 0x09
1097 #define QUERY_FW_CMD_IF_REV_OFFSET 0x0a
1098 #define QUERY_FW_MAX_CMD_OFFSET 0x0f
1099 #define QUERY_FW_ERR_START_OFFSET 0x30
1100 #define QUERY_FW_ERR_SIZE_OFFSET 0x38
1101 #define QUERY_FW_ERR_BAR_OFFSET 0x3c
1102
1103 #define QUERY_FW_SIZE_OFFSET 0x00
1104 #define QUERY_FW_CLR_INT_BASE_OFFSET 0x20
1105 #define QUERY_FW_CLR_INT_BAR_OFFSET 0x28
1106
1107 #define QUERY_FW_COMM_BASE_OFFSET 0x40
1108 #define QUERY_FW_COMM_BAR_OFFSET 0x48
1109
1110 #define QUERY_FW_CLOCK_OFFSET 0x50
1111 #define QUERY_FW_CLOCK_BAR 0x58
1112
1113 mailbox = mlx4_alloc_cmd_mailbox(dev);
1114 if (IS_ERR(mailbox))
1115 return PTR_ERR(mailbox);
1116 outbox = mailbox->buf;
1117
1118 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_FW,
1119 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1120 if (err)
1121 goto out;
1122
1123 MLX4_GET(fw_ver, outbox, QUERY_FW_VER_OFFSET);
1124 /*
1125 * FW subminor version is at more significant bits than minor
1126 * version, so swap here.
1127 */
1128 dev->caps.fw_ver = (fw_ver & 0xffff00000000ull) |
1129 ((fw_ver & 0xffff0000ull) >> 16) |
1130 ((fw_ver & 0x0000ffffull) << 16);
1131
1132 MLX4_GET(lg, outbox, QUERY_FW_PPF_ID);
1133 dev->caps.function = lg;
1134
1135 if (mlx4_is_slave(dev))
1136 goto out;
1137
1138
1139 MLX4_GET(cmd_if_rev, outbox, QUERY_FW_CMD_IF_REV_OFFSET);
1140 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_MIN_REV ||
1141 cmd_if_rev > MLX4_COMMAND_INTERFACE_MAX_REV) {
1142 mlx4_err(dev, "Installed FW has unsupported "
1143 "command interface revision %d.\n",
1144 cmd_if_rev);
1145 mlx4_err(dev, "(Installed FW version is %d.%d.%03d)\n",
1146 (int) (dev->caps.fw_ver >> 32),
1147 (int) (dev->caps.fw_ver >> 16) & 0xffff,
1148 (int) dev->caps.fw_ver & 0xffff);
1149 mlx4_err(dev, "This driver version supports only revisions %d to %d.\n",
1150 MLX4_COMMAND_INTERFACE_MIN_REV, MLX4_COMMAND_INTERFACE_MAX_REV);
1151 err = -ENODEV;
1152 goto out;
1153 }
1154
1155 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS)
1156 dev->flags |= MLX4_FLAG_OLD_PORT_CMDS;
1157
1158 MLX4_GET(lg, outbox, QUERY_FW_MAX_CMD_OFFSET);
1159 cmd->max_cmds = 1 << lg;
1160
1161 mlx4_dbg(dev, "FW version %d.%d.%03d (cmd intf rev %d), max commands %d\n",
1162 (int) (dev->caps.fw_ver >> 32),
1163 (int) (dev->caps.fw_ver >> 16) & 0xffff,
1164 (int) dev->caps.fw_ver & 0xffff,
1165 cmd_if_rev, cmd->max_cmds);
1166
1167 MLX4_GET(fw->catas_offset, outbox, QUERY_FW_ERR_START_OFFSET);
1168 MLX4_GET(fw->catas_size, outbox, QUERY_FW_ERR_SIZE_OFFSET);
1169 MLX4_GET(fw->catas_bar, outbox, QUERY_FW_ERR_BAR_OFFSET);
1170 fw->catas_bar = (fw->catas_bar >> 6) * 2;
1171
1172 mlx4_dbg(dev, "Catastrophic error buffer at 0x%llx, size 0x%x, BAR %d\n",
1173 (unsigned long long) fw->catas_offset, fw->catas_size, fw->catas_bar);
1174
1175 MLX4_GET(fw->fw_pages, outbox, QUERY_FW_SIZE_OFFSET);
1176 MLX4_GET(fw->clr_int_base, outbox, QUERY_FW_CLR_INT_BASE_OFFSET);
1177 MLX4_GET(fw->clr_int_bar, outbox, QUERY_FW_CLR_INT_BAR_OFFSET);
1178 fw->clr_int_bar = (fw->clr_int_bar >> 6) * 2;
1179
1180 MLX4_GET(fw->comm_base, outbox, QUERY_FW_COMM_BASE_OFFSET);
1181 MLX4_GET(fw->comm_bar, outbox, QUERY_FW_COMM_BAR_OFFSET);
1182 fw->comm_bar = (fw->comm_bar >> 6) * 2;
1183 mlx4_dbg(dev, "Communication vector bar:%d offset:0x%llx\n",
1184 fw->comm_bar, fw->comm_base);
1185 mlx4_dbg(dev, "FW size %d KB\n", fw->fw_pages >> 2);
1186
1187 MLX4_GET(fw->clock_offset, outbox, QUERY_FW_CLOCK_OFFSET);
1188 MLX4_GET(fw->clock_bar, outbox, QUERY_FW_CLOCK_BAR);
1189 fw->clock_bar = (fw->clock_bar >> 6) * 2;
1190 mlx4_dbg(dev, "Internal clock bar:%d offset:0x%llx\n",
1191 fw->clock_bar, fw->clock_offset);
1192
1193 /*
1194 * Round up number of system pages needed in case
1195 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE.
1196 */
1197 fw->fw_pages =
1198 ALIGN(fw->fw_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >>
1199 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT);
1200
1201 mlx4_dbg(dev, "Clear int @ %llx, BAR %d\n",
1202 (unsigned long long) fw->clr_int_base, fw->clr_int_bar);
1203
1204 out:
1205 mlx4_free_cmd_mailbox(dev, mailbox);
1206 return err;
1207 }
1208
1209 int mlx4_QUERY_FW_wrapper(struct mlx4_dev *dev, int slave,
1210 struct mlx4_vhcr *vhcr,
1211 struct mlx4_cmd_mailbox *inbox,
1212 struct mlx4_cmd_mailbox *outbox,
1213 struct mlx4_cmd_info *cmd)
1214 {
1215 u8 *outbuf;
1216 int err;
1217
1218 outbuf = outbox->buf;
1219 err = mlx4_cmd_box(dev, 0, outbox->dma, 0, 0, MLX4_CMD_QUERY_FW,
1220 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1221 if (err)
1222 return err;
1223
1224 /* for slaves, set pci PPF ID to invalid and zero out everything
1225 * else except FW version */
1226 outbuf[0] = outbuf[1] = 0;
1227 memset(&outbuf[8], 0, QUERY_FW_OUT_SIZE - 8);
1228 outbuf[QUERY_FW_PPF_ID] = MLX4_INVALID_SLAVE_ID;
1229
1230 return 0;
1231 }
1232
1233 static void get_board_id(void *vsd, char *board_id)
1234 {
1235 int i;
1236
1237 #define VSD_OFFSET_SIG1 0x00
1238 #define VSD_OFFSET_SIG2 0xde
1239 #define VSD_OFFSET_MLX_BOARD_ID 0xd0
1240 #define VSD_OFFSET_TS_BOARD_ID 0x20
1241
1242 #define VSD_SIGNATURE_TOPSPIN 0x5ad
1243
1244 memset(board_id, 0, MLX4_BOARD_ID_LEN);
1245
1246 if (be16_to_cpup(vsd + VSD_OFFSET_SIG1) == VSD_SIGNATURE_TOPSPIN &&
1247 be16_to_cpup(vsd + VSD_OFFSET_SIG2) == VSD_SIGNATURE_TOPSPIN) {
1248 strlcpy(board_id, vsd + VSD_OFFSET_TS_BOARD_ID, MLX4_BOARD_ID_LEN);
1249 } else {
1250 /*
1251 * The board ID is a string but the firmware byte
1252 * swaps each 4-byte word before passing it back to
1253 * us. Therefore we need to swab it before printing.
1254 */
1255 for (i = 0; i < 4; ++i)
1256 ((u32 *) board_id)[i] =
1257 swab32(*(u32 *) (vsd + VSD_OFFSET_MLX_BOARD_ID + i * 4));
1258 }
1259 }
1260
1261 int mlx4_QUERY_ADAPTER(struct mlx4_dev *dev, struct mlx4_adapter *adapter)
1262 {
1263 struct mlx4_cmd_mailbox *mailbox;
1264 u32 *outbox;
1265 int err;
1266
1267 #define QUERY_ADAPTER_OUT_SIZE 0x100
1268 #define QUERY_ADAPTER_INTA_PIN_OFFSET 0x10
1269 #define QUERY_ADAPTER_VSD_OFFSET 0x20
1270
1271 mailbox = mlx4_alloc_cmd_mailbox(dev);
1272 if (IS_ERR(mailbox))
1273 return PTR_ERR(mailbox);
1274 outbox = mailbox->buf;
1275
1276 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_ADAPTER,
1277 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1278 if (err)
1279 goto out;
1280
1281 MLX4_GET(adapter->inta_pin, outbox, QUERY_ADAPTER_INTA_PIN_OFFSET);
1282
1283 get_board_id(outbox + QUERY_ADAPTER_VSD_OFFSET / 4,
1284 adapter->board_id);
1285
1286 out:
1287 mlx4_free_cmd_mailbox(dev, mailbox);
1288 return err;
1289 }
1290
1291 int mlx4_INIT_HCA(struct mlx4_dev *dev, struct mlx4_init_hca_param *param)
1292 {
1293 struct mlx4_cmd_mailbox *mailbox;
1294 __be32 *inbox;
1295 int err;
1296
1297 #define INIT_HCA_IN_SIZE 0x200
1298 #define INIT_HCA_VERSION_OFFSET 0x000
1299 #define INIT_HCA_VERSION 2
1300 #define INIT_HCA_VXLAN_OFFSET 0x0c
1301 #define INIT_HCA_CACHELINE_SZ_OFFSET 0x0e
1302 #define INIT_HCA_FLAGS_OFFSET 0x014
1303 #define INIT_HCA_QPC_OFFSET 0x020
1304 #define INIT_HCA_QPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x10)
1305 #define INIT_HCA_LOG_QP_OFFSET (INIT_HCA_QPC_OFFSET + 0x17)
1306 #define INIT_HCA_SRQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x28)
1307 #define INIT_HCA_LOG_SRQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x2f)
1308 #define INIT_HCA_CQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x30)
1309 #define INIT_HCA_LOG_CQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x37)
1310 #define INIT_HCA_EQE_CQE_OFFSETS (INIT_HCA_QPC_OFFSET + 0x38)
1311 #define INIT_HCA_ALTC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x40)
1312 #define INIT_HCA_AUXC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x50)
1313 #define INIT_HCA_EQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x60)
1314 #define INIT_HCA_LOG_EQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x67)
1315 #define INIT_HCA_RDMARC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x70)
1316 #define INIT_HCA_LOG_RD_OFFSET (INIT_HCA_QPC_OFFSET + 0x77)
1317 #define INIT_HCA_MCAST_OFFSET 0x0c0
1318 #define INIT_HCA_MC_BASE_OFFSET (INIT_HCA_MCAST_OFFSET + 0x00)
1319 #define INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x12)
1320 #define INIT_HCA_LOG_MC_HASH_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x16)
1321 #define INIT_HCA_UC_STEERING_OFFSET (INIT_HCA_MCAST_OFFSET + 0x18)
1322 #define INIT_HCA_LOG_MC_TABLE_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x1b)
1323 #define INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN 0x6
1324 #define INIT_HCA_FS_PARAM_OFFSET 0x1d0
1325 #define INIT_HCA_FS_BASE_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x00)
1326 #define INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x12)
1327 #define INIT_HCA_FS_LOG_TABLE_SZ_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x1b)
1328 #define INIT_HCA_FS_ETH_BITS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x21)
1329 #define INIT_HCA_FS_ETH_NUM_ADDRS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x22)
1330 #define INIT_HCA_FS_IB_BITS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x25)
1331 #define INIT_HCA_FS_IB_NUM_ADDRS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x26)
1332 #define INIT_HCA_TPT_OFFSET 0x0f0
1333 #define INIT_HCA_DMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x00)
1334 #define INIT_HCA_TPT_MW_OFFSET (INIT_HCA_TPT_OFFSET + 0x08)
1335 #define INIT_HCA_LOG_MPT_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x0b)
1336 #define INIT_HCA_MTT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x10)
1337 #define INIT_HCA_CMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x18)
1338 #define INIT_HCA_UAR_OFFSET 0x120
1339 #define INIT_HCA_LOG_UAR_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0a)
1340 #define INIT_HCA_UAR_PAGE_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0b)
1341
1342 mailbox = mlx4_alloc_cmd_mailbox(dev);
1343 if (IS_ERR(mailbox))
1344 return PTR_ERR(mailbox);
1345 inbox = mailbox->buf;
1346
1347 *((u8 *) mailbox->buf + INIT_HCA_VERSION_OFFSET) = INIT_HCA_VERSION;
1348
1349 *((u8 *) mailbox->buf + INIT_HCA_CACHELINE_SZ_OFFSET) =
1350 (ilog2(cache_line_size()) - 4) << 5;
1351
1352 #if defined(__LITTLE_ENDIAN)
1353 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) &= ~cpu_to_be32(1 << 1);
1354 #elif defined(__BIG_ENDIAN)
1355 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 1);
1356 #else
1357 #error Host endianness not defined
1358 #endif
1359 /* Check port for UD address vector: */
1360 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1);
1361
1362 /* Enable IPoIB checksumming if we can: */
1363 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_IPOIB_CSUM)
1364 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 3);
1365
1366 /* Enable QoS support if module parameter set */
1367 if (enable_qos)
1368 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 2);
1369
1370 /* enable counters */
1371 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS)
1372 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 4);
1373
1374 /* CX3 is capable of extending CQEs/EQEs from 32 to 64 bytes */
1375 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_64B_EQE) {
1376 *(inbox + INIT_HCA_EQE_CQE_OFFSETS / 4) |= cpu_to_be32(1 << 29);
1377 dev->caps.eqe_size = 64;
1378 dev->caps.eqe_factor = 1;
1379 } else {
1380 dev->caps.eqe_size = 32;
1381 dev->caps.eqe_factor = 0;
1382 }
1383
1384 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_64B_CQE) {
1385 *(inbox + INIT_HCA_EQE_CQE_OFFSETS / 4) |= cpu_to_be32(1 << 30);
1386 dev->caps.cqe_size = 64;
1387 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_64B_CQE;
1388 } else {
1389 dev->caps.cqe_size = 32;
1390 }
1391
1392 /* QPC/EEC/CQC/EQC/RDMARC attributes */
1393
1394 MLX4_PUT(inbox, param->qpc_base, INIT_HCA_QPC_BASE_OFFSET);
1395 MLX4_PUT(inbox, param->log_num_qps, INIT_HCA_LOG_QP_OFFSET);
1396 MLX4_PUT(inbox, param->srqc_base, INIT_HCA_SRQC_BASE_OFFSET);
1397 MLX4_PUT(inbox, param->log_num_srqs, INIT_HCA_LOG_SRQ_OFFSET);
1398 MLX4_PUT(inbox, param->cqc_base, INIT_HCA_CQC_BASE_OFFSET);
1399 MLX4_PUT(inbox, param->log_num_cqs, INIT_HCA_LOG_CQ_OFFSET);
1400 MLX4_PUT(inbox, param->altc_base, INIT_HCA_ALTC_BASE_OFFSET);
1401 MLX4_PUT(inbox, param->auxc_base, INIT_HCA_AUXC_BASE_OFFSET);
1402 MLX4_PUT(inbox, param->eqc_base, INIT_HCA_EQC_BASE_OFFSET);
1403 MLX4_PUT(inbox, param->log_num_eqs, INIT_HCA_LOG_EQ_OFFSET);
1404 MLX4_PUT(inbox, param->rdmarc_base, INIT_HCA_RDMARC_BASE_OFFSET);
1405 MLX4_PUT(inbox, param->log_rd_per_qp, INIT_HCA_LOG_RD_OFFSET);
1406
1407 /* steering attributes */
1408 if (dev->caps.steering_mode ==
1409 MLX4_STEERING_MODE_DEVICE_MANAGED) {
1410 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |=
1411 cpu_to_be32(1 <<
1412 INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN);
1413
1414 MLX4_PUT(inbox, param->mc_base, INIT_HCA_FS_BASE_OFFSET);
1415 MLX4_PUT(inbox, param->log_mc_entry_sz,
1416 INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET);
1417 MLX4_PUT(inbox, param->log_mc_table_sz,
1418 INIT_HCA_FS_LOG_TABLE_SZ_OFFSET);
1419 /* Enable Ethernet flow steering
1420 * with udp unicast and tcp unicast
1421 */
1422 MLX4_PUT(inbox, (u8) (MLX4_FS_UDP_UC_EN | MLX4_FS_TCP_UC_EN),
1423 INIT_HCA_FS_ETH_BITS_OFFSET);
1424 MLX4_PUT(inbox, (u16) MLX4_FS_NUM_OF_L2_ADDR,
1425 INIT_HCA_FS_ETH_NUM_ADDRS_OFFSET);
1426 /* Enable IPoIB flow steering
1427 * with udp unicast and tcp unicast
1428 */
1429 MLX4_PUT(inbox, (u8) (MLX4_FS_UDP_UC_EN | MLX4_FS_TCP_UC_EN),
1430 INIT_HCA_FS_IB_BITS_OFFSET);
1431 MLX4_PUT(inbox, (u16) MLX4_FS_NUM_OF_L2_ADDR,
1432 INIT_HCA_FS_IB_NUM_ADDRS_OFFSET);
1433 } else {
1434 MLX4_PUT(inbox, param->mc_base, INIT_HCA_MC_BASE_OFFSET);
1435 MLX4_PUT(inbox, param->log_mc_entry_sz,
1436 INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET);
1437 MLX4_PUT(inbox, param->log_mc_hash_sz,
1438 INIT_HCA_LOG_MC_HASH_SZ_OFFSET);
1439 MLX4_PUT(inbox, param->log_mc_table_sz,
1440 INIT_HCA_LOG_MC_TABLE_SZ_OFFSET);
1441 if (dev->caps.steering_mode == MLX4_STEERING_MODE_B0)
1442 MLX4_PUT(inbox, (u8) (1 << 3),
1443 INIT_HCA_UC_STEERING_OFFSET);
1444 }
1445
1446 /* TPT attributes */
1447
1448 MLX4_PUT(inbox, param->dmpt_base, INIT_HCA_DMPT_BASE_OFFSET);
1449 MLX4_PUT(inbox, param->mw_enabled, INIT_HCA_TPT_MW_OFFSET);
1450 MLX4_PUT(inbox, param->log_mpt_sz, INIT_HCA_LOG_MPT_SZ_OFFSET);
1451 MLX4_PUT(inbox, param->mtt_base, INIT_HCA_MTT_BASE_OFFSET);
1452 MLX4_PUT(inbox, param->cmpt_base, INIT_HCA_CMPT_BASE_OFFSET);
1453
1454 /* UAR attributes */
1455
1456 MLX4_PUT(inbox, param->uar_page_sz, INIT_HCA_UAR_PAGE_SZ_OFFSET);
1457 MLX4_PUT(inbox, param->log_uar_sz, INIT_HCA_LOG_UAR_SZ_OFFSET);
1458
1459 /* set parser VXLAN attributes */
1460 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS) {
1461 u8 parser_params = 0;
1462 MLX4_PUT(inbox, parser_params, INIT_HCA_VXLAN_OFFSET);
1463 }
1464
1465 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_INIT_HCA, 10000,
1466 MLX4_CMD_NATIVE);
1467
1468 if (err)
1469 mlx4_err(dev, "INIT_HCA returns %d\n", err);
1470
1471 mlx4_free_cmd_mailbox(dev, mailbox);
1472 return err;
1473 }
1474
1475 int mlx4_QUERY_HCA(struct mlx4_dev *dev,
1476 struct mlx4_init_hca_param *param)
1477 {
1478 struct mlx4_cmd_mailbox *mailbox;
1479 __be32 *outbox;
1480 u32 dword_field;
1481 int err;
1482 u8 byte_field;
1483
1484 #define QUERY_HCA_GLOBAL_CAPS_OFFSET 0x04
1485 #define QUERY_HCA_CORE_CLOCK_OFFSET 0x0c
1486
1487 mailbox = mlx4_alloc_cmd_mailbox(dev);
1488 if (IS_ERR(mailbox))
1489 return PTR_ERR(mailbox);
1490 outbox = mailbox->buf;
1491
1492 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0,
1493 MLX4_CMD_QUERY_HCA,
1494 MLX4_CMD_TIME_CLASS_B,
1495 !mlx4_is_slave(dev));
1496 if (err)
1497 goto out;
1498
1499 MLX4_GET(param->global_caps, outbox, QUERY_HCA_GLOBAL_CAPS_OFFSET);
1500 MLX4_GET(param->hca_core_clock, outbox, QUERY_HCA_CORE_CLOCK_OFFSET);
1501
1502 /* QPC/EEC/CQC/EQC/RDMARC attributes */
1503
1504 MLX4_GET(param->qpc_base, outbox, INIT_HCA_QPC_BASE_OFFSET);
1505 MLX4_GET(param->log_num_qps, outbox, INIT_HCA_LOG_QP_OFFSET);
1506 MLX4_GET(param->srqc_base, outbox, INIT_HCA_SRQC_BASE_OFFSET);
1507 MLX4_GET(param->log_num_srqs, outbox, INIT_HCA_LOG_SRQ_OFFSET);
1508 MLX4_GET(param->cqc_base, outbox, INIT_HCA_CQC_BASE_OFFSET);
1509 MLX4_GET(param->log_num_cqs, outbox, INIT_HCA_LOG_CQ_OFFSET);
1510 MLX4_GET(param->altc_base, outbox, INIT_HCA_ALTC_BASE_OFFSET);
1511 MLX4_GET(param->auxc_base, outbox, INIT_HCA_AUXC_BASE_OFFSET);
1512 MLX4_GET(param->eqc_base, outbox, INIT_HCA_EQC_BASE_OFFSET);
1513 MLX4_GET(param->log_num_eqs, outbox, INIT_HCA_LOG_EQ_OFFSET);
1514 MLX4_GET(param->rdmarc_base, outbox, INIT_HCA_RDMARC_BASE_OFFSET);
1515 MLX4_GET(param->log_rd_per_qp, outbox, INIT_HCA_LOG_RD_OFFSET);
1516
1517 MLX4_GET(dword_field, outbox, INIT_HCA_FLAGS_OFFSET);
1518 if (dword_field & (1 << INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN)) {
1519 param->steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED;
1520 } else {
1521 MLX4_GET(byte_field, outbox, INIT_HCA_UC_STEERING_OFFSET);
1522 if (byte_field & 0x8)
1523 param->steering_mode = MLX4_STEERING_MODE_B0;
1524 else
1525 param->steering_mode = MLX4_STEERING_MODE_A0;
1526 }
1527 /* steering attributes */
1528 if (param->steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) {
1529 MLX4_GET(param->mc_base, outbox, INIT_HCA_FS_BASE_OFFSET);
1530 MLX4_GET(param->log_mc_entry_sz, outbox,
1531 INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET);
1532 MLX4_GET(param->log_mc_table_sz, outbox,
1533 INIT_HCA_FS_LOG_TABLE_SZ_OFFSET);
1534 } else {
1535 MLX4_GET(param->mc_base, outbox, INIT_HCA_MC_BASE_OFFSET);
1536 MLX4_GET(param->log_mc_entry_sz, outbox,
1537 INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET);
1538 MLX4_GET(param->log_mc_hash_sz, outbox,
1539 INIT_HCA_LOG_MC_HASH_SZ_OFFSET);
1540 MLX4_GET(param->log_mc_table_sz, outbox,
1541 INIT_HCA_LOG_MC_TABLE_SZ_OFFSET);
1542 }
1543
1544 /* CX3 is capable of extending CQEs/EQEs from 32 to 64 bytes */
1545 MLX4_GET(byte_field, outbox, INIT_HCA_EQE_CQE_OFFSETS);
1546 if (byte_field & 0x20) /* 64-bytes eqe enabled */
1547 param->dev_cap_enabled |= MLX4_DEV_CAP_64B_EQE_ENABLED;
1548 if (byte_field & 0x40) /* 64-bytes cqe enabled */
1549 param->dev_cap_enabled |= MLX4_DEV_CAP_64B_CQE_ENABLED;
1550
1551 /* TPT attributes */
1552
1553 MLX4_GET(param->dmpt_base, outbox, INIT_HCA_DMPT_BASE_OFFSET);
1554 MLX4_GET(param->mw_enabled, outbox, INIT_HCA_TPT_MW_OFFSET);
1555 MLX4_GET(param->log_mpt_sz, outbox, INIT_HCA_LOG_MPT_SZ_OFFSET);
1556 MLX4_GET(param->mtt_base, outbox, INIT_HCA_MTT_BASE_OFFSET);
1557 MLX4_GET(param->cmpt_base, outbox, INIT_HCA_CMPT_BASE_OFFSET);
1558
1559 /* UAR attributes */
1560
1561 MLX4_GET(param->uar_page_sz, outbox, INIT_HCA_UAR_PAGE_SZ_OFFSET);
1562 MLX4_GET(param->log_uar_sz, outbox, INIT_HCA_LOG_UAR_SZ_OFFSET);
1563
1564 out:
1565 mlx4_free_cmd_mailbox(dev, mailbox);
1566
1567 return err;
1568 }
1569
1570 /* for IB-type ports only in SRIOV mode. Checks that both proxy QP0
1571 * and real QP0 are active, so that the paravirtualized QP0 is ready
1572 * to operate */
1573 static int check_qp0_state(struct mlx4_dev *dev, int function, int port)
1574 {
1575 struct mlx4_priv *priv = mlx4_priv(dev);
1576 /* irrelevant if not infiniband */
1577 if (priv->mfunc.master.qp0_state[port].proxy_qp0_active &&
1578 priv->mfunc.master.qp0_state[port].qp0_active)
1579 return 1;
1580 return 0;
1581 }
1582
1583 int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave,
1584 struct mlx4_vhcr *vhcr,
1585 struct mlx4_cmd_mailbox *inbox,
1586 struct mlx4_cmd_mailbox *outbox,
1587 struct mlx4_cmd_info *cmd)
1588 {
1589 struct mlx4_priv *priv = mlx4_priv(dev);
1590 int port = vhcr->in_modifier;
1591 int err;
1592
1593 if (priv->mfunc.master.slave_state[slave].init_port_mask & (1 << port))
1594 return 0;
1595
1596 if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB) {
1597 /* Enable port only if it was previously disabled */
1598 if (!priv->mfunc.master.init_port_ref[port]) {
1599 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
1600 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1601 if (err)
1602 return err;
1603 }
1604 priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port);
1605 } else {
1606 if (slave == mlx4_master_func_num(dev)) {
1607 if (check_qp0_state(dev, slave, port) &&
1608 !priv->mfunc.master.qp0_state[port].port_active) {
1609 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
1610 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1611 if (err)
1612 return err;
1613 priv->mfunc.master.qp0_state[port].port_active = 1;
1614 priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port);
1615 }
1616 } else
1617 priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port);
1618 }
1619 ++priv->mfunc.master.init_port_ref[port];
1620 return 0;
1621 }
1622
1623 int mlx4_INIT_PORT(struct mlx4_dev *dev, int port)
1624 {
1625 struct mlx4_cmd_mailbox *mailbox;
1626 u32 *inbox;
1627 int err;
1628 u32 flags;
1629 u16 field;
1630
1631 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
1632 #define INIT_PORT_IN_SIZE 256
1633 #define INIT_PORT_FLAGS_OFFSET 0x00
1634 #define INIT_PORT_FLAG_SIG (1 << 18)
1635 #define INIT_PORT_FLAG_NG (1 << 17)
1636 #define INIT_PORT_FLAG_G0 (1 << 16)
1637 #define INIT_PORT_VL_SHIFT 4
1638 #define INIT_PORT_PORT_WIDTH_SHIFT 8
1639 #define INIT_PORT_MTU_OFFSET 0x04
1640 #define INIT_PORT_MAX_GID_OFFSET 0x06
1641 #define INIT_PORT_MAX_PKEY_OFFSET 0x0a
1642 #define INIT_PORT_GUID0_OFFSET 0x10
1643 #define INIT_PORT_NODE_GUID_OFFSET 0x18
1644 #define INIT_PORT_SI_GUID_OFFSET 0x20
1645
1646 mailbox = mlx4_alloc_cmd_mailbox(dev);
1647 if (IS_ERR(mailbox))
1648 return PTR_ERR(mailbox);
1649 inbox = mailbox->buf;
1650
1651 flags = 0;
1652 flags |= (dev->caps.vl_cap[port] & 0xf) << INIT_PORT_VL_SHIFT;
1653 flags |= (dev->caps.port_width_cap[port] & 0xf) << INIT_PORT_PORT_WIDTH_SHIFT;
1654 MLX4_PUT(inbox, flags, INIT_PORT_FLAGS_OFFSET);
1655
1656 field = 128 << dev->caps.ib_mtu_cap[port];
1657 MLX4_PUT(inbox, field, INIT_PORT_MTU_OFFSET);
1658 field = dev->caps.gid_table_len[port];
1659 MLX4_PUT(inbox, field, INIT_PORT_MAX_GID_OFFSET);
1660 field = dev->caps.pkey_table_len[port];
1661 MLX4_PUT(inbox, field, INIT_PORT_MAX_PKEY_OFFSET);
1662
1663 err = mlx4_cmd(dev, mailbox->dma, port, 0, MLX4_CMD_INIT_PORT,
1664 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1665
1666 mlx4_free_cmd_mailbox(dev, mailbox);
1667 } else
1668 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
1669 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
1670
1671 return err;
1672 }
1673 EXPORT_SYMBOL_GPL(mlx4_INIT_PORT);
1674
1675 int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave,
1676 struct mlx4_vhcr *vhcr,
1677 struct mlx4_cmd_mailbox *inbox,
1678 struct mlx4_cmd_mailbox *outbox,
1679 struct mlx4_cmd_info *cmd)
1680 {
1681 struct mlx4_priv *priv = mlx4_priv(dev);
1682 int port = vhcr->in_modifier;
1683 int err;
1684
1685 if (!(priv->mfunc.master.slave_state[slave].init_port_mask &
1686 (1 << port)))
1687 return 0;
1688
1689 if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB) {
1690 if (priv->mfunc.master.init_port_ref[port] == 1) {
1691 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT,
1692 1000, MLX4_CMD_NATIVE);
1693 if (err)
1694 return err;
1695 }
1696 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port);
1697 } else {
1698 /* infiniband port */
1699 if (slave == mlx4_master_func_num(dev)) {
1700 if (!priv->mfunc.master.qp0_state[port].qp0_active &&
1701 priv->mfunc.master.qp0_state[port].port_active) {
1702 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT,
1703 1000, MLX4_CMD_NATIVE);
1704 if (err)
1705 return err;
1706 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port);
1707 priv->mfunc.master.qp0_state[port].port_active = 0;
1708 }
1709 } else
1710 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port);
1711 }
1712 --priv->mfunc.master.init_port_ref[port];
1713 return 0;
1714 }
1715
1716 int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port)
1717 {
1718 return mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, 1000,
1719 MLX4_CMD_WRAPPED);
1720 }
1721 EXPORT_SYMBOL_GPL(mlx4_CLOSE_PORT);
1722
1723 int mlx4_CLOSE_HCA(struct mlx4_dev *dev, int panic)
1724 {
1725 return mlx4_cmd(dev, 0, 0, panic, MLX4_CMD_CLOSE_HCA, 1000,
1726 MLX4_CMD_NATIVE);
1727 }
1728
1729 int mlx4_SET_ICM_SIZE(struct mlx4_dev *dev, u64 icm_size, u64 *aux_pages)
1730 {
1731 int ret = mlx4_cmd_imm(dev, icm_size, aux_pages, 0, 0,
1732 MLX4_CMD_SET_ICM_SIZE,
1733 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1734 if (ret)
1735 return ret;
1736
1737 /*
1738 * Round up number of system pages needed in case
1739 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE.
1740 */
1741 *aux_pages = ALIGN(*aux_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >>
1742 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT);
1743
1744 return 0;
1745 }
1746
1747 int mlx4_NOP(struct mlx4_dev *dev)
1748 {
1749 /* Input modifier of 0x1f means "finish as soon as possible." */
1750 return mlx4_cmd(dev, 0, 0x1f, 0, MLX4_CMD_NOP, 100, MLX4_CMD_NATIVE);
1751 }
1752
1753 int mlx4_get_phys_port_id(struct mlx4_dev *dev)
1754 {
1755 u8 port;
1756 u32 *outbox;
1757 struct mlx4_cmd_mailbox *mailbox;
1758 u32 in_mod;
1759 u32 guid_hi, guid_lo;
1760 int err, ret = 0;
1761 #define MOD_STAT_CFG_PORT_OFFSET 8
1762 #define MOD_STAT_CFG_GUID_H 0X14
1763 #define MOD_STAT_CFG_GUID_L 0X1c
1764
1765 mailbox = mlx4_alloc_cmd_mailbox(dev);
1766 if (IS_ERR(mailbox))
1767 return PTR_ERR(mailbox);
1768 outbox = mailbox->buf;
1769
1770 for (port = 1; port <= dev->caps.num_ports; port++) {
1771 in_mod = port << MOD_STAT_CFG_PORT_OFFSET;
1772 err = mlx4_cmd_box(dev, 0, mailbox->dma, in_mod, 0x2,
1773 MLX4_CMD_MOD_STAT_CFG, MLX4_CMD_TIME_CLASS_A,
1774 MLX4_CMD_NATIVE);
1775 if (err) {
1776 mlx4_err(dev, "Fail to get port %d uplink guid\n",
1777 port);
1778 ret = err;
1779 } else {
1780 MLX4_GET(guid_hi, outbox, MOD_STAT_CFG_GUID_H);
1781 MLX4_GET(guid_lo, outbox, MOD_STAT_CFG_GUID_L);
1782 dev->caps.phys_port_id[port] = (u64)guid_lo |
1783 (u64)guid_hi << 32;
1784 }
1785 }
1786 mlx4_free_cmd_mailbox(dev, mailbox);
1787 return ret;
1788 }
1789
1790 #define MLX4_WOL_SETUP_MODE (5 << 28)
1791 int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port)
1792 {
1793 u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8;
1794
1795 return mlx4_cmd_imm(dev, 0, config, in_mod, 0x3,
1796 MLX4_CMD_MOD_STAT_CFG, MLX4_CMD_TIME_CLASS_A,
1797 MLX4_CMD_NATIVE);
1798 }
1799 EXPORT_SYMBOL_GPL(mlx4_wol_read);
1800
1801 int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port)
1802 {
1803 u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8;
1804
1805 return mlx4_cmd(dev, config, in_mod, 0x1, MLX4_CMD_MOD_STAT_CFG,
1806 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1807 }
1808 EXPORT_SYMBOL_GPL(mlx4_wol_write);
1809
1810 enum {
1811 ADD_TO_MCG = 0x26,
1812 };
1813
1814
1815 void mlx4_opreq_action(struct work_struct *work)
1816 {
1817 struct mlx4_priv *priv = container_of(work, struct mlx4_priv,
1818 opreq_task);
1819 struct mlx4_dev *dev = &priv->dev;
1820 int num_tasks = atomic_read(&priv->opreq_count);
1821 struct mlx4_cmd_mailbox *mailbox;
1822 struct mlx4_mgm *mgm;
1823 u32 *outbox;
1824 u32 modifier;
1825 u16 token;
1826 u16 type;
1827 int err;
1828 u32 num_qps;
1829 struct mlx4_qp qp;
1830 int i;
1831 u8 rem_mcg;
1832 u8 prot;
1833
1834 #define GET_OP_REQ_MODIFIER_OFFSET 0x08
1835 #define GET_OP_REQ_TOKEN_OFFSET 0x14
1836 #define GET_OP_REQ_TYPE_OFFSET 0x1a
1837 #define GET_OP_REQ_DATA_OFFSET 0x20
1838
1839 mailbox = mlx4_alloc_cmd_mailbox(dev);
1840 if (IS_ERR(mailbox)) {
1841 mlx4_err(dev, "Failed to allocate mailbox for GET_OP_REQ\n");
1842 return;
1843 }
1844 outbox = mailbox->buf;
1845
1846 while (num_tasks) {
1847 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0,
1848 MLX4_CMD_GET_OP_REQ, MLX4_CMD_TIME_CLASS_A,
1849 MLX4_CMD_NATIVE);
1850 if (err) {
1851 mlx4_err(dev, "Failed to retrieve required operation: %d\n",
1852 err);
1853 return;
1854 }
1855 MLX4_GET(modifier, outbox, GET_OP_REQ_MODIFIER_OFFSET);
1856 MLX4_GET(token, outbox, GET_OP_REQ_TOKEN_OFFSET);
1857 MLX4_GET(type, outbox, GET_OP_REQ_TYPE_OFFSET);
1858 type &= 0xfff;
1859
1860 switch (type) {
1861 case ADD_TO_MCG:
1862 if (dev->caps.steering_mode ==
1863 MLX4_STEERING_MODE_DEVICE_MANAGED) {
1864 mlx4_warn(dev, "ADD MCG operation is not supported in DEVICE_MANAGED steering mode\n");
1865 err = EPERM;
1866 break;
1867 }
1868 mgm = (struct mlx4_mgm *)((u8 *)(outbox) +
1869 GET_OP_REQ_DATA_OFFSET);
1870 num_qps = be32_to_cpu(mgm->members_count) &
1871 MGM_QPN_MASK;
1872 rem_mcg = ((u8 *)(&mgm->members_count))[0] & 1;
1873 prot = ((u8 *)(&mgm->members_count))[0] >> 6;
1874
1875 for (i = 0; i < num_qps; i++) {
1876 qp.qpn = be32_to_cpu(mgm->qp[i]);
1877 if (rem_mcg)
1878 err = mlx4_multicast_detach(dev, &qp,
1879 mgm->gid,
1880 prot, 0);
1881 else
1882 err = mlx4_multicast_attach(dev, &qp,
1883 mgm->gid,
1884 mgm->gid[5]
1885 , 0, prot,
1886 NULL);
1887 if (err)
1888 break;
1889 }
1890 break;
1891 default:
1892 mlx4_warn(dev, "Bad type for required operation\n");
1893 err = EINVAL;
1894 break;
1895 }
1896 err = mlx4_cmd(dev, 0, ((u32) err |
1897 (__force u32)cpu_to_be32(token) << 16),
1898 1, MLX4_CMD_GET_OP_REQ, MLX4_CMD_TIME_CLASS_A,
1899 MLX4_CMD_NATIVE);
1900 if (err) {
1901 mlx4_err(dev, "Failed to acknowledge required request: %d\n",
1902 err);
1903 goto out;
1904 }
1905 memset(outbox, 0, 0xffc);
1906 num_tasks = atomic_dec_return(&priv->opreq_count);
1907 }
1908
1909 out:
1910 mlx4_free_cmd_mailbox(dev, mailbox);
1911 }
Linux kernel - Deliverables
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