2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <linux/etherdevice.h>
36 #include <linux/mlx4/cmd.h>
37 #include <linux/module.h>
38 #include <linux/cache.h>
44 MLX4_COMMAND_INTERFACE_MIN_REV
= 2,
45 MLX4_COMMAND_INTERFACE_MAX_REV
= 3,
46 MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS
= 3,
49 extern void __buggy_use_of_MLX4_GET(void);
50 extern void __buggy_use_of_MLX4_PUT(void);
52 static bool enable_qos
;
53 module_param(enable_qos
, bool, 0444);
54 MODULE_PARM_DESC(enable_qos
, "Enable Quality of Service support in the HCA (default: off)");
56 #define MLX4_GET(dest, source, offset) \
58 void *__p = (char *) (source) + (offset); \
59 switch (sizeof (dest)) { \
60 case 1: (dest) = *(u8 *) __p; break; \
61 case 2: (dest) = be16_to_cpup(__p); break; \
62 case 4: (dest) = be32_to_cpup(__p); break; \
63 case 8: (dest) = be64_to_cpup(__p); break; \
64 default: __buggy_use_of_MLX4_GET(); \
68 #define MLX4_PUT(dest, source, offset) \
70 void *__d = ((char *) (dest) + (offset)); \
71 switch (sizeof(source)) { \
72 case 1: *(u8 *) __d = (source); break; \
73 case 2: *(__be16 *) __d = cpu_to_be16(source); break; \
74 case 4: *(__be32 *) __d = cpu_to_be32(source); break; \
75 case 8: *(__be64 *) __d = cpu_to_be64(source); break; \
76 default: __buggy_use_of_MLX4_PUT(); \
80 static void dump_dev_cap_flags(struct mlx4_dev
*dev
, u64 flags
)
82 static const char *fname
[] = {
83 [ 0] = "RC transport",
84 [ 1] = "UC transport",
85 [ 2] = "UD transport",
86 [ 3] = "XRC transport",
87 [ 4] = "reliable multicast",
88 [ 5] = "FCoIB support",
90 [ 7] = "IPoIB checksum offload",
91 [ 8] = "P_Key violation counter",
92 [ 9] = "Q_Key violation counter",
94 [12] = "Dual Port Different Protocol (DPDP) support",
95 [15] = "Big LSO headers",
98 [18] = "Atomic ops support",
99 [19] = "Raw multicast support",
100 [20] = "Address vector port checking support",
101 [21] = "UD multicast support",
102 [24] = "Demand paging support",
103 [25] = "Router support",
104 [30] = "IBoE support",
105 [32] = "Unicast loopback support",
106 [34] = "FCS header control",
107 [38] = "Wake On LAN support",
108 [40] = "UDP RSS support",
109 [41] = "Unicast VEP steering support",
110 [42] = "Multicast VEP steering support",
111 [48] = "Counters support",
112 [53] = "Port ETS Scheduler support",
113 [55] = "Port link type sensing support",
114 [59] = "Port management change event support",
115 [61] = "64 byte EQE support",
116 [62] = "64 byte CQE support",
120 mlx4_dbg(dev
, "DEV_CAP flags:\n");
121 for (i
= 0; i
< ARRAY_SIZE(fname
); ++i
)
122 if (fname
[i
] && (flags
& (1LL << i
)))
123 mlx4_dbg(dev
, " %s\n", fname
[i
]);
126 static void dump_dev_cap_flags2(struct mlx4_dev
*dev
, u64 flags
)
128 static const char * const fname
[] = {
130 [1] = "RSS Toeplitz Hash Function support",
131 [2] = "RSS XOR Hash Function support",
132 [3] = "Device manage flow steering support",
133 [4] = "Automatic MAC reassignment support",
134 [5] = "Time stamping support",
135 [6] = "VST (control vlan insertion/stripping) support",
136 [7] = "FSM (MAC anti-spoofing) support",
137 [8] = "Dynamic QP updates support"
141 for (i
= 0; i
< ARRAY_SIZE(fname
); ++i
)
142 if (fname
[i
] && (flags
& (1LL << i
)))
143 mlx4_dbg(dev
, " %s\n", fname
[i
]);
146 int mlx4_MOD_STAT_CFG(struct mlx4_dev
*dev
, struct mlx4_mod_stat_cfg
*cfg
)
148 struct mlx4_cmd_mailbox
*mailbox
;
152 #define MOD_STAT_CFG_IN_SIZE 0x100
154 #define MOD_STAT_CFG_PG_SZ_M_OFFSET 0x002
155 #define MOD_STAT_CFG_PG_SZ_OFFSET 0x003
157 mailbox
= mlx4_alloc_cmd_mailbox(dev
);
159 return PTR_ERR(mailbox
);
160 inbox
= mailbox
->buf
;
162 memset(inbox
, 0, MOD_STAT_CFG_IN_SIZE
);
164 MLX4_PUT(inbox
, cfg
->log_pg_sz
, MOD_STAT_CFG_PG_SZ_OFFSET
);
165 MLX4_PUT(inbox
, cfg
->log_pg_sz_m
, MOD_STAT_CFG_PG_SZ_M_OFFSET
);
167 err
= mlx4_cmd(dev
, mailbox
->dma
, 0, 0, MLX4_CMD_MOD_STAT_CFG
,
168 MLX4_CMD_TIME_CLASS_A
, MLX4_CMD_NATIVE
);
170 mlx4_free_cmd_mailbox(dev
, mailbox
);
174 int mlx4_QUERY_FUNC_CAP_wrapper(struct mlx4_dev
*dev
, int slave
,
175 struct mlx4_vhcr
*vhcr
,
176 struct mlx4_cmd_mailbox
*inbox
,
177 struct mlx4_cmd_mailbox
*outbox
,
178 struct mlx4_cmd_info
*cmd
)
184 #define QUERY_FUNC_CAP_FLAGS_OFFSET 0x0
185 #define QUERY_FUNC_CAP_NUM_PORTS_OFFSET 0x1
186 #define QUERY_FUNC_CAP_PF_BHVR_OFFSET 0x4
187 #define QUERY_FUNC_CAP_FMR_OFFSET 0x8
188 #define QUERY_FUNC_CAP_QP_QUOTA_OFFSET 0x10
189 #define QUERY_FUNC_CAP_CQ_QUOTA_OFFSET 0x14
190 #define QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET 0x18
191 #define QUERY_FUNC_CAP_MPT_QUOTA_OFFSET 0x20
192 #define QUERY_FUNC_CAP_MTT_QUOTA_OFFSET 0x24
193 #define QUERY_FUNC_CAP_MCG_QUOTA_OFFSET 0x28
194 #define QUERY_FUNC_CAP_MAX_EQ_OFFSET 0x2c
195 #define QUERY_FUNC_CAP_RESERVED_EQ_OFFSET 0x30
197 #define QUERY_FUNC_CAP_FMR_FLAG 0x80
198 #define QUERY_FUNC_CAP_FLAG_RDMA 0x40
199 #define QUERY_FUNC_CAP_FLAG_ETH 0x80
201 /* when opcode modifier = 1 */
202 #define QUERY_FUNC_CAP_PHYS_PORT_OFFSET 0x3
203 #define QUERY_FUNC_CAP_RDMA_PROPS_OFFSET 0x8
204 #define QUERY_FUNC_CAP_ETH_PROPS_OFFSET 0xc
206 #define QUERY_FUNC_CAP_QP0_TUNNEL 0x10
207 #define QUERY_FUNC_CAP_QP0_PROXY 0x14
208 #define QUERY_FUNC_CAP_QP1_TUNNEL 0x18
209 #define QUERY_FUNC_CAP_QP1_PROXY 0x1c
211 #define QUERY_FUNC_CAP_ETH_PROPS_FORCE_MAC 0x40
212 #define QUERY_FUNC_CAP_ETH_PROPS_FORCE_VLAN 0x80
214 #define QUERY_FUNC_CAP_RDMA_PROPS_FORCE_PHY_WQE_GID 0x80
216 if (vhcr
->op_modifier
== 1) {
218 /* ensure force vlan and force mac bits are not set */
219 MLX4_PUT(outbox
->buf
, field
, QUERY_FUNC_CAP_ETH_PROPS_OFFSET
);
220 /* ensure that phy_wqe_gid bit is not set */
221 MLX4_PUT(outbox
->buf
, field
, QUERY_FUNC_CAP_RDMA_PROPS_OFFSET
);
223 field
= vhcr
->in_modifier
; /* phys-port = logical-port */
224 MLX4_PUT(outbox
->buf
, field
, QUERY_FUNC_CAP_PHYS_PORT_OFFSET
);
226 /* size is now the QP number */
227 size
= dev
->phys_caps
.base_tunnel_sqpn
+ 8 * slave
+ field
- 1;
228 MLX4_PUT(outbox
->buf
, size
, QUERY_FUNC_CAP_QP0_TUNNEL
);
231 MLX4_PUT(outbox
->buf
, size
, QUERY_FUNC_CAP_QP1_TUNNEL
);
233 size
= dev
->phys_caps
.base_proxy_sqpn
+ 8 * slave
+ field
- 1;
234 MLX4_PUT(outbox
->buf
, size
, QUERY_FUNC_CAP_QP0_PROXY
);
237 MLX4_PUT(outbox
->buf
, size
, QUERY_FUNC_CAP_QP1_PROXY
);
239 } else if (vhcr
->op_modifier
== 0) {
240 /* enable rdma and ethernet interfaces */
241 field
= (QUERY_FUNC_CAP_FLAG_ETH
| QUERY_FUNC_CAP_FLAG_RDMA
);
242 MLX4_PUT(outbox
->buf
, field
, QUERY_FUNC_CAP_FLAGS_OFFSET
);
244 field
= dev
->caps
.num_ports
;
245 MLX4_PUT(outbox
->buf
, field
, QUERY_FUNC_CAP_NUM_PORTS_OFFSET
);
247 size
= dev
->caps
.function_caps
; /* set PF behaviours */
248 MLX4_PUT(outbox
->buf
, size
, QUERY_FUNC_CAP_PF_BHVR_OFFSET
);
250 field
= 0; /* protected FMR support not available as yet */
251 MLX4_PUT(outbox
->buf
, field
, QUERY_FUNC_CAP_FMR_OFFSET
);
253 size
= dev
->caps
.num_qps
;
254 MLX4_PUT(outbox
->buf
, size
, QUERY_FUNC_CAP_QP_QUOTA_OFFSET
);
256 size
= dev
->caps
.num_srqs
;
257 MLX4_PUT(outbox
->buf
, size
, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET
);
259 size
= dev
->caps
.num_cqs
;
260 MLX4_PUT(outbox
->buf
, size
, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET
);
262 size
= dev
->caps
.num_eqs
;
263 MLX4_PUT(outbox
->buf
, size
, QUERY_FUNC_CAP_MAX_EQ_OFFSET
);
265 size
= dev
->caps
.reserved_eqs
;
266 MLX4_PUT(outbox
->buf
, size
, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET
);
268 size
= dev
->caps
.num_mpts
;
269 MLX4_PUT(outbox
->buf
, size
, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET
);
271 size
= dev
->caps
.num_mtts
;
272 MLX4_PUT(outbox
->buf
, size
, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET
);
274 size
= dev
->caps
.num_mgms
+ dev
->caps
.num_amgms
;
275 MLX4_PUT(outbox
->buf
, size
, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET
);
283 int mlx4_QUERY_FUNC_CAP(struct mlx4_dev
*dev
, u32 gen_or_port
,
284 struct mlx4_func_cap
*func_cap
)
286 struct mlx4_cmd_mailbox
*mailbox
;
288 u8 field
, op_modifier
;
292 op_modifier
= !!gen_or_port
; /* 0 = general, 1 = logical port */
294 mailbox
= mlx4_alloc_cmd_mailbox(dev
);
296 return PTR_ERR(mailbox
);
298 err
= mlx4_cmd_box(dev
, 0, mailbox
->dma
, gen_or_port
, op_modifier
,
299 MLX4_CMD_QUERY_FUNC_CAP
,
300 MLX4_CMD_TIME_CLASS_A
, MLX4_CMD_WRAPPED
);
304 outbox
= mailbox
->buf
;
307 MLX4_GET(field
, outbox
, QUERY_FUNC_CAP_FLAGS_OFFSET
);
308 if (!(field
& (QUERY_FUNC_CAP_FLAG_ETH
| QUERY_FUNC_CAP_FLAG_RDMA
))) {
309 mlx4_err(dev
, "The host supports neither eth nor rdma interfaces\n");
310 err
= -EPROTONOSUPPORT
;
313 func_cap
->flags
= field
;
315 MLX4_GET(field
, outbox
, QUERY_FUNC_CAP_NUM_PORTS_OFFSET
);
316 func_cap
->num_ports
= field
;
318 MLX4_GET(size
, outbox
, QUERY_FUNC_CAP_PF_BHVR_OFFSET
);
319 func_cap
->pf_context_behaviour
= size
;
321 MLX4_GET(size
, outbox
, QUERY_FUNC_CAP_QP_QUOTA_OFFSET
);
322 func_cap
->qp_quota
= size
& 0xFFFFFF;
324 MLX4_GET(size
, outbox
, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET
);
325 func_cap
->srq_quota
= size
& 0xFFFFFF;
327 MLX4_GET(size
, outbox
, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET
);
328 func_cap
->cq_quota
= size
& 0xFFFFFF;
330 MLX4_GET(size
, outbox
, QUERY_FUNC_CAP_MAX_EQ_OFFSET
);
331 func_cap
->max_eq
= size
& 0xFFFFFF;
333 MLX4_GET(size
, outbox
, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET
);
334 func_cap
->reserved_eq
= size
& 0xFFFFFF;
336 MLX4_GET(size
, outbox
, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET
);
337 func_cap
->mpt_quota
= size
& 0xFFFFFF;
339 MLX4_GET(size
, outbox
, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET
);
340 func_cap
->mtt_quota
= size
& 0xFFFFFF;
342 MLX4_GET(size
, outbox
, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET
);
343 func_cap
->mcg_quota
= size
& 0xFFFFFF;
347 /* logical port query */
348 if (gen_or_port
> dev
->caps
.num_ports
) {
353 if (dev
->caps
.port_type
[gen_or_port
] == MLX4_PORT_TYPE_ETH
) {
354 MLX4_GET(field
, outbox
, QUERY_FUNC_CAP_ETH_PROPS_OFFSET
);
355 if (field
& QUERY_FUNC_CAP_ETH_PROPS_FORCE_VLAN
) {
356 mlx4_err(dev
, "VLAN is enforced on this port\n");
357 err
= -EPROTONOSUPPORT
;
361 if (field
& QUERY_FUNC_CAP_ETH_PROPS_FORCE_MAC
) {
362 mlx4_err(dev
, "Force mac is enabled on this port\n");
363 err
= -EPROTONOSUPPORT
;
366 } else if (dev
->caps
.port_type
[gen_or_port
] == MLX4_PORT_TYPE_IB
) {
367 MLX4_GET(field
, outbox
, QUERY_FUNC_CAP_RDMA_PROPS_OFFSET
);
368 if (field
& QUERY_FUNC_CAP_RDMA_PROPS_FORCE_PHY_WQE_GID
) {
369 mlx4_err(dev
, "phy_wqe_gid is "
370 "enforced on this ib port\n");
371 err
= -EPROTONOSUPPORT
;
376 MLX4_GET(field
, outbox
, QUERY_FUNC_CAP_PHYS_PORT_OFFSET
);
377 func_cap
->physical_port
= field
;
378 if (func_cap
->physical_port
!= gen_or_port
) {
383 MLX4_GET(size
, outbox
, QUERY_FUNC_CAP_QP0_TUNNEL
);
384 func_cap
->qp0_tunnel_qpn
= size
& 0xFFFFFF;
386 MLX4_GET(size
, outbox
, QUERY_FUNC_CAP_QP0_PROXY
);
387 func_cap
->qp0_proxy_qpn
= size
& 0xFFFFFF;
389 MLX4_GET(size
, outbox
, QUERY_FUNC_CAP_QP1_TUNNEL
);
390 func_cap
->qp1_tunnel_qpn
= size
& 0xFFFFFF;
392 MLX4_GET(size
, outbox
, QUERY_FUNC_CAP_QP1_PROXY
);
393 func_cap
->qp1_proxy_qpn
= size
& 0xFFFFFF;
395 /* All other resources are allocated by the master, but we still report
396 * 'num' and 'reserved' capabilities as follows:
397 * - num remains the maximum resource index
398 * - 'num - reserved' is the total available objects of a resource, but
399 * resource indices may be less than 'reserved'
400 * TODO: set per-resource quotas */
403 mlx4_free_cmd_mailbox(dev
, mailbox
);
408 int mlx4_QUERY_DEV_CAP(struct mlx4_dev
*dev
, struct mlx4_dev_cap
*dev_cap
)
410 struct mlx4_cmd_mailbox
*mailbox
;
413 u32 field32
, flags
, ext_flags
;
419 #define QUERY_DEV_CAP_OUT_SIZE 0x100
420 #define QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET 0x10
421 #define QUERY_DEV_CAP_MAX_QP_SZ_OFFSET 0x11
422 #define QUERY_DEV_CAP_RSVD_QP_OFFSET 0x12
423 #define QUERY_DEV_CAP_MAX_QP_OFFSET 0x13
424 #define QUERY_DEV_CAP_RSVD_SRQ_OFFSET 0x14
425 #define QUERY_DEV_CAP_MAX_SRQ_OFFSET 0x15
426 #define QUERY_DEV_CAP_RSVD_EEC_OFFSET 0x16
427 #define QUERY_DEV_CAP_MAX_EEC_OFFSET 0x17
428 #define QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET 0x19
429 #define QUERY_DEV_CAP_RSVD_CQ_OFFSET 0x1a
430 #define QUERY_DEV_CAP_MAX_CQ_OFFSET 0x1b
431 #define QUERY_DEV_CAP_MAX_MPT_OFFSET 0x1d
432 #define QUERY_DEV_CAP_RSVD_EQ_OFFSET 0x1e
433 #define QUERY_DEV_CAP_MAX_EQ_OFFSET 0x1f
434 #define QUERY_DEV_CAP_RSVD_MTT_OFFSET 0x20
435 #define QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET 0x21
436 #define QUERY_DEV_CAP_RSVD_MRW_OFFSET 0x22
437 #define QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET 0x23
438 #define QUERY_DEV_CAP_MAX_AV_OFFSET 0x27
439 #define QUERY_DEV_CAP_MAX_REQ_QP_OFFSET 0x29
440 #define QUERY_DEV_CAP_MAX_RES_QP_OFFSET 0x2b
441 #define QUERY_DEV_CAP_MAX_GSO_OFFSET 0x2d
442 #define QUERY_DEV_CAP_RSS_OFFSET 0x2e
443 #define QUERY_DEV_CAP_MAX_RDMA_OFFSET 0x2f
444 #define QUERY_DEV_CAP_RSZ_SRQ_OFFSET 0x33
445 #define QUERY_DEV_CAP_ACK_DELAY_OFFSET 0x35
446 #define QUERY_DEV_CAP_MTU_WIDTH_OFFSET 0x36
447 #define QUERY_DEV_CAP_VL_PORT_OFFSET 0x37
448 #define QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET 0x38
449 #define QUERY_DEV_CAP_MAX_GID_OFFSET 0x3b
450 #define QUERY_DEV_CAP_RATE_SUPPORT_OFFSET 0x3c
451 #define QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET 0x3e
452 #define QUERY_DEV_CAP_MAX_PKEY_OFFSET 0x3f
453 #define QUERY_DEV_CAP_EXT_FLAGS_OFFSET 0x40
454 #define QUERY_DEV_CAP_FLAGS_OFFSET 0x44
455 #define QUERY_DEV_CAP_RSVD_UAR_OFFSET 0x48
456 #define QUERY_DEV_CAP_UAR_SZ_OFFSET 0x49
457 #define QUERY_DEV_CAP_PAGE_SZ_OFFSET 0x4b
458 #define QUERY_DEV_CAP_BF_OFFSET 0x4c
459 #define QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET 0x4d
460 #define QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET 0x4e
461 #define QUERY_DEV_CAP_LOG_MAX_BF_PAGES_OFFSET 0x4f
462 #define QUERY_DEV_CAP_MAX_SG_SQ_OFFSET 0x51
463 #define QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET 0x52
464 #define QUERY_DEV_CAP_MAX_SG_RQ_OFFSET 0x55
465 #define QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET 0x56
466 #define QUERY_DEV_CAP_MAX_QP_MCG_OFFSET 0x61
467 #define QUERY_DEV_CAP_RSVD_MCG_OFFSET 0x62
468 #define QUERY_DEV_CAP_MAX_MCG_OFFSET 0x63
469 #define QUERY_DEV_CAP_RSVD_PD_OFFSET 0x64
470 #define QUERY_DEV_CAP_MAX_PD_OFFSET 0x65
471 #define QUERY_DEV_CAP_RSVD_XRC_OFFSET 0x66
472 #define QUERY_DEV_CAP_MAX_XRC_OFFSET 0x67
473 #define QUERY_DEV_CAP_MAX_COUNTERS_OFFSET 0x68
474 #define QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET 0x70
475 #define QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET 0x76
476 #define QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET 0x77
477 #define QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET 0x80
478 #define QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET 0x82
479 #define QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET 0x84
480 #define QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET 0x86
481 #define QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET 0x88
482 #define QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET 0x8a
483 #define QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET 0x8c
484 #define QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET 0x8e
485 #define QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET 0x90
486 #define QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET 0x92
487 #define QUERY_DEV_CAP_BMME_FLAGS_OFFSET 0x94
488 #define QUERY_DEV_CAP_RSVD_LKEY_OFFSET 0x98
489 #define QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET 0xa0
490 #define QUERY_DEV_CAP_FW_REASSIGN_MAC 0x9d
493 mailbox
= mlx4_alloc_cmd_mailbox(dev
);
495 return PTR_ERR(mailbox
);
496 outbox
= mailbox
->buf
;
498 err
= mlx4_cmd_box(dev
, 0, mailbox
->dma
, 0, 0, MLX4_CMD_QUERY_DEV_CAP
,
499 MLX4_CMD_TIME_CLASS_A
, MLX4_CMD_NATIVE
);
503 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_RSVD_QP_OFFSET
);
504 dev_cap
->reserved_qps
= 1 << (field
& 0xf);
505 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_MAX_QP_OFFSET
);
506 dev_cap
->max_qps
= 1 << (field
& 0x1f);
507 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_RSVD_SRQ_OFFSET
);
508 dev_cap
->reserved_srqs
= 1 << (field
>> 4);
509 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_MAX_SRQ_OFFSET
);
510 dev_cap
->max_srqs
= 1 << (field
& 0x1f);
511 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET
);
512 dev_cap
->max_cq_sz
= 1 << field
;
513 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_RSVD_CQ_OFFSET
);
514 dev_cap
->reserved_cqs
= 1 << (field
& 0xf);
515 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_MAX_CQ_OFFSET
);
516 dev_cap
->max_cqs
= 1 << (field
& 0x1f);
517 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_MAX_MPT_OFFSET
);
518 dev_cap
->max_mpts
= 1 << (field
& 0x3f);
519 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_RSVD_EQ_OFFSET
);
520 dev_cap
->reserved_eqs
= field
& 0xf;
521 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_MAX_EQ_OFFSET
);
522 dev_cap
->max_eqs
= 1 << (field
& 0xf);
523 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_RSVD_MTT_OFFSET
);
524 dev_cap
->reserved_mtts
= 1 << (field
>> 4);
525 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET
);
526 dev_cap
->max_mrw_sz
= 1 << field
;
527 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_RSVD_MRW_OFFSET
);
528 dev_cap
->reserved_mrws
= 1 << (field
& 0xf);
529 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET
);
530 dev_cap
->max_mtt_seg
= 1 << (field
& 0x3f);
531 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_MAX_REQ_QP_OFFSET
);
532 dev_cap
->max_requester_per_qp
= 1 << (field
& 0x3f);
533 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_MAX_RES_QP_OFFSET
);
534 dev_cap
->max_responder_per_qp
= 1 << (field
& 0x3f);
535 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_MAX_GSO_OFFSET
);
538 dev_cap
->max_gso_sz
= 0;
540 dev_cap
->max_gso_sz
= 1 << field
;
542 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_RSS_OFFSET
);
544 dev_cap
->flags2
|= MLX4_DEV_CAP_FLAG2_RSS_XOR
;
546 dev_cap
->flags2
|= MLX4_DEV_CAP_FLAG2_RSS_TOP
;
549 dev_cap
->flags2
|= MLX4_DEV_CAP_FLAG2_RSS
;
550 dev_cap
->max_rss_tbl_sz
= 1 << field
;
552 dev_cap
->max_rss_tbl_sz
= 0;
553 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_MAX_RDMA_OFFSET
);
554 dev_cap
->max_rdma_global
= 1 << (field
& 0x3f);
555 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_ACK_DELAY_OFFSET
);
556 dev_cap
->local_ca_ack_delay
= field
& 0x1f;
557 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_VL_PORT_OFFSET
);
558 dev_cap
->num_ports
= field
& 0xf;
559 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET
);
560 dev_cap
->max_msg_sz
= 1 << (field
& 0x1f);
561 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET
);
563 dev_cap
->flags2
|= MLX4_DEV_CAP_FLAG2_FS_EN
;
564 dev_cap
->fs_log_max_ucast_qp_range_size
= field
& 0x1f;
565 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET
);
566 dev_cap
->fs_max_num_qp_per_entry
= field
;
567 MLX4_GET(stat_rate
, outbox
, QUERY_DEV_CAP_RATE_SUPPORT_OFFSET
);
568 dev_cap
->stat_rate_support
= stat_rate
;
569 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET
);
571 dev_cap
->flags2
|= MLX4_DEV_CAP_FLAG2_TS
;
572 MLX4_GET(ext_flags
, outbox
, QUERY_DEV_CAP_EXT_FLAGS_OFFSET
);
573 MLX4_GET(flags
, outbox
, QUERY_DEV_CAP_FLAGS_OFFSET
);
574 dev_cap
->flags
= flags
| (u64
)ext_flags
<< 32;
575 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_RSVD_UAR_OFFSET
);
576 dev_cap
->reserved_uars
= field
>> 4;
577 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_UAR_SZ_OFFSET
);
578 dev_cap
->uar_size
= 1 << ((field
& 0x3f) + 20);
579 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_PAGE_SZ_OFFSET
);
580 dev_cap
->min_page_sz
= 1 << field
;
582 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_BF_OFFSET
);
584 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET
);
585 dev_cap
->bf_reg_size
= 1 << (field
& 0x1f);
586 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET
);
587 if ((1 << (field
& 0x3f)) > (PAGE_SIZE
/ dev_cap
->bf_reg_size
))
589 dev_cap
->bf_regs_per_page
= 1 << (field
& 0x3f);
590 mlx4_dbg(dev
, "BlueFlame available (reg size %d, regs/page %d)\n",
591 dev_cap
->bf_reg_size
, dev_cap
->bf_regs_per_page
);
593 dev_cap
->bf_reg_size
= 0;
594 mlx4_dbg(dev
, "BlueFlame not available\n");
597 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_MAX_SG_SQ_OFFSET
);
598 dev_cap
->max_sq_sg
= field
;
599 MLX4_GET(size
, outbox
, QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET
);
600 dev_cap
->max_sq_desc_sz
= size
;
602 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_MAX_QP_MCG_OFFSET
);
603 dev_cap
->max_qp_per_mcg
= 1 << field
;
604 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_RSVD_MCG_OFFSET
);
605 dev_cap
->reserved_mgms
= field
& 0xf;
606 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_MAX_MCG_OFFSET
);
607 dev_cap
->max_mcgs
= 1 << field
;
608 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_RSVD_PD_OFFSET
);
609 dev_cap
->reserved_pds
= field
>> 4;
610 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_MAX_PD_OFFSET
);
611 dev_cap
->max_pds
= 1 << (field
& 0x3f);
612 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_RSVD_XRC_OFFSET
);
613 dev_cap
->reserved_xrcds
= field
>> 4;
614 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_MAX_XRC_OFFSET
);
615 dev_cap
->max_xrcds
= 1 << (field
& 0x1f);
617 MLX4_GET(size
, outbox
, QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET
);
618 dev_cap
->rdmarc_entry_sz
= size
;
619 MLX4_GET(size
, outbox
, QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET
);
620 dev_cap
->qpc_entry_sz
= size
;
621 MLX4_GET(size
, outbox
, QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET
);
622 dev_cap
->aux_entry_sz
= size
;
623 MLX4_GET(size
, outbox
, QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET
);
624 dev_cap
->altc_entry_sz
= size
;
625 MLX4_GET(size
, outbox
, QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET
);
626 dev_cap
->eqc_entry_sz
= size
;
627 MLX4_GET(size
, outbox
, QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET
);
628 dev_cap
->cqc_entry_sz
= size
;
629 MLX4_GET(size
, outbox
, QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET
);
630 dev_cap
->srq_entry_sz
= size
;
631 MLX4_GET(size
, outbox
, QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET
);
632 dev_cap
->cmpt_entry_sz
= size
;
633 MLX4_GET(size
, outbox
, QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET
);
634 dev_cap
->mtt_entry_sz
= size
;
635 MLX4_GET(size
, outbox
, QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET
);
636 dev_cap
->dmpt_entry_sz
= size
;
638 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET
);
639 dev_cap
->max_srq_sz
= 1 << field
;
640 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_MAX_QP_SZ_OFFSET
);
641 dev_cap
->max_qp_sz
= 1 << field
;
642 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_RSZ_SRQ_OFFSET
);
643 dev_cap
->resize_srq
= field
& 1;
644 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_MAX_SG_RQ_OFFSET
);
645 dev_cap
->max_rq_sg
= field
;
646 MLX4_GET(size
, outbox
, QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET
);
647 dev_cap
->max_rq_desc_sz
= size
;
649 MLX4_GET(dev_cap
->bmme_flags
, outbox
,
650 QUERY_DEV_CAP_BMME_FLAGS_OFFSET
);
651 MLX4_GET(dev_cap
->reserved_lkey
, outbox
,
652 QUERY_DEV_CAP_RSVD_LKEY_OFFSET
);
653 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_FW_REASSIGN_MAC
);
655 dev_cap
->flags2
|= MLX4_DEV_CAP_FLAGS2_REASSIGN_MAC_EN
;
656 MLX4_GET(dev_cap
->max_icm_sz
, outbox
,
657 QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET
);
658 if (dev_cap
->flags
& MLX4_DEV_CAP_FLAG_COUNTERS
)
659 MLX4_GET(dev_cap
->max_counters
, outbox
,
660 QUERY_DEV_CAP_MAX_COUNTERS_OFFSET
);
662 MLX4_GET(field32
, outbox
, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET
);
663 if (field32
& (1 << 16))
664 dev_cap
->flags2
|= MLX4_DEV_CAP_FLAG2_UPDATE_QP
;
665 if (field32
& (1 << 26))
666 dev_cap
->flags2
|= MLX4_DEV_CAP_FLAG2_VLAN_CONTROL
;
667 if (field32
& (1 << 20))
668 dev_cap
->flags2
|= MLX4_DEV_CAP_FLAG2_FSM
;
670 if (dev
->flags
& MLX4_FLAG_OLD_PORT_CMDS
) {
671 for (i
= 1; i
<= dev_cap
->num_ports
; ++i
) {
672 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_VL_PORT_OFFSET
);
673 dev_cap
->max_vl
[i
] = field
>> 4;
674 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_MTU_WIDTH_OFFSET
);
675 dev_cap
->ib_mtu
[i
] = field
>> 4;
676 dev_cap
->max_port_width
[i
] = field
& 0xf;
677 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_MAX_GID_OFFSET
);
678 dev_cap
->max_gids
[i
] = 1 << (field
& 0xf);
679 MLX4_GET(field
, outbox
, QUERY_DEV_CAP_MAX_PKEY_OFFSET
);
680 dev_cap
->max_pkeys
[i
] = 1 << (field
& 0xf);
683 #define QUERY_PORT_SUPPORTED_TYPE_OFFSET 0x00
684 #define QUERY_PORT_MTU_OFFSET 0x01
685 #define QUERY_PORT_ETH_MTU_OFFSET 0x02
686 #define QUERY_PORT_WIDTH_OFFSET 0x06
687 #define QUERY_PORT_MAX_GID_PKEY_OFFSET 0x07
688 #define QUERY_PORT_MAX_MACVLAN_OFFSET 0x0a
689 #define QUERY_PORT_MAX_VL_OFFSET 0x0b
690 #define QUERY_PORT_MAC_OFFSET 0x10
691 #define QUERY_PORT_TRANS_VENDOR_OFFSET 0x18
692 #define QUERY_PORT_WAVELENGTH_OFFSET 0x1c
693 #define QUERY_PORT_TRANS_CODE_OFFSET 0x20
695 for (i
= 1; i
<= dev_cap
->num_ports
; ++i
) {
696 err
= mlx4_cmd_box(dev
, 0, mailbox
->dma
, i
, 0, MLX4_CMD_QUERY_PORT
,
697 MLX4_CMD_TIME_CLASS_B
, MLX4_CMD_NATIVE
);
701 MLX4_GET(field
, outbox
, QUERY_PORT_SUPPORTED_TYPE_OFFSET
);
702 dev_cap
->supported_port_types
[i
] = field
& 3;
703 dev_cap
->suggested_type
[i
] = (field
>> 3) & 1;
704 dev_cap
->default_sense
[i
] = (field
>> 4) & 1;
705 MLX4_GET(field
, outbox
, QUERY_PORT_MTU_OFFSET
);
706 dev_cap
->ib_mtu
[i
] = field
& 0xf;
707 MLX4_GET(field
, outbox
, QUERY_PORT_WIDTH_OFFSET
);
708 dev_cap
->max_port_width
[i
] = field
& 0xf;
709 MLX4_GET(field
, outbox
, QUERY_PORT_MAX_GID_PKEY_OFFSET
);
710 dev_cap
->max_gids
[i
] = 1 << (field
>> 4);
711 dev_cap
->max_pkeys
[i
] = 1 << (field
& 0xf);
712 MLX4_GET(field
, outbox
, QUERY_PORT_MAX_VL_OFFSET
);
713 dev_cap
->max_vl
[i
] = field
& 0xf;
714 MLX4_GET(field
, outbox
, QUERY_PORT_MAX_MACVLAN_OFFSET
);
715 dev_cap
->log_max_macs
[i
] = field
& 0xf;
716 dev_cap
->log_max_vlans
[i
] = field
>> 4;
717 MLX4_GET(dev_cap
->eth_mtu
[i
], outbox
, QUERY_PORT_ETH_MTU_OFFSET
);
718 MLX4_GET(dev_cap
->def_mac
[i
], outbox
, QUERY_PORT_MAC_OFFSET
);
719 MLX4_GET(field32
, outbox
, QUERY_PORT_TRANS_VENDOR_OFFSET
);
720 dev_cap
->trans_type
[i
] = field32
>> 24;
721 dev_cap
->vendor_oui
[i
] = field32
& 0xffffff;
722 MLX4_GET(dev_cap
->wavelength
[i
], outbox
, QUERY_PORT_WAVELENGTH_OFFSET
);
723 MLX4_GET(dev_cap
->trans_code
[i
], outbox
, QUERY_PORT_TRANS_CODE_OFFSET
);
727 mlx4_dbg(dev
, "Base MM extensions: flags %08x, rsvd L_Key %08x\n",
728 dev_cap
->bmme_flags
, dev_cap
->reserved_lkey
);
731 * Each UAR has 4 EQ doorbells; so if a UAR is reserved, then
732 * we can't use any EQs whose doorbell falls on that page,
733 * even if the EQ itself isn't reserved.
735 dev_cap
->reserved_eqs
= max(dev_cap
->reserved_uars
* 4,
736 dev_cap
->reserved_eqs
);
738 mlx4_dbg(dev
, "Max ICM size %lld MB\n",
739 (unsigned long long) dev_cap
->max_icm_sz
>> 20);
740 mlx4_dbg(dev
, "Max QPs: %d, reserved QPs: %d, entry size: %d\n",
741 dev_cap
->max_qps
, dev_cap
->reserved_qps
, dev_cap
->qpc_entry_sz
);
742 mlx4_dbg(dev
, "Max SRQs: %d, reserved SRQs: %d, entry size: %d\n",
743 dev_cap
->max_srqs
, dev_cap
->reserved_srqs
, dev_cap
->srq_entry_sz
);
744 mlx4_dbg(dev
, "Max CQs: %d, reserved CQs: %d, entry size: %d\n",
745 dev_cap
->max_cqs
, dev_cap
->reserved_cqs
, dev_cap
->cqc_entry_sz
);
746 mlx4_dbg(dev
, "Max EQs: %d, reserved EQs: %d, entry size: %d\n",
747 dev_cap
->max_eqs
, dev_cap
->reserved_eqs
, dev_cap
->eqc_entry_sz
);
748 mlx4_dbg(dev
, "reserved MPTs: %d, reserved MTTs: %d\n",
749 dev_cap
->reserved_mrws
, dev_cap
->reserved_mtts
);
750 mlx4_dbg(dev
, "Max PDs: %d, reserved PDs: %d, reserved UARs: %d\n",
751 dev_cap
->max_pds
, dev_cap
->reserved_pds
, dev_cap
->reserved_uars
);
752 mlx4_dbg(dev
, "Max QP/MCG: %d, reserved MGMs: %d\n",
753 dev_cap
->max_pds
, dev_cap
->reserved_mgms
);
754 mlx4_dbg(dev
, "Max CQEs: %d, max WQEs: %d, max SRQ WQEs: %d\n",
755 dev_cap
->max_cq_sz
, dev_cap
->max_qp_sz
, dev_cap
->max_srq_sz
);
756 mlx4_dbg(dev
, "Local CA ACK delay: %d, max MTU: %d, port width cap: %d\n",
757 dev_cap
->local_ca_ack_delay
, 128 << dev_cap
->ib_mtu
[1],
758 dev_cap
->max_port_width
[1]);
759 mlx4_dbg(dev
, "Max SQ desc size: %d, max SQ S/G: %d\n",
760 dev_cap
->max_sq_desc_sz
, dev_cap
->max_sq_sg
);
761 mlx4_dbg(dev
, "Max RQ desc size: %d, max RQ S/G: %d\n",
762 dev_cap
->max_rq_desc_sz
, dev_cap
->max_rq_sg
);
763 mlx4_dbg(dev
, "Max GSO size: %d\n", dev_cap
->max_gso_sz
);
764 mlx4_dbg(dev
, "Max counters: %d\n", dev_cap
->max_counters
);
765 mlx4_dbg(dev
, "Max RSS Table size: %d\n", dev_cap
->max_rss_tbl_sz
);
767 dump_dev_cap_flags(dev
, dev_cap
->flags
);
768 dump_dev_cap_flags2(dev
, dev_cap
->flags2
);
771 mlx4_free_cmd_mailbox(dev
, mailbox
);
775 int mlx4_QUERY_DEV_CAP_wrapper(struct mlx4_dev
*dev
, int slave
,
776 struct mlx4_vhcr
*vhcr
,
777 struct mlx4_cmd_mailbox
*inbox
,
778 struct mlx4_cmd_mailbox
*outbox
,
779 struct mlx4_cmd_info
*cmd
)
786 err
= mlx4_cmd_box(dev
, 0, outbox
->dma
, 0, 0, MLX4_CMD_QUERY_DEV_CAP
,
787 MLX4_CMD_TIME_CLASS_A
, MLX4_CMD_NATIVE
);
791 /* add port mng change event capability and disable mw type 1
792 * unconditionally to slaves
794 MLX4_GET(flags
, outbox
->buf
, QUERY_DEV_CAP_EXT_FLAGS_OFFSET
);
795 flags
|= MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV
;
796 flags
&= ~MLX4_DEV_CAP_FLAG_MEM_WINDOW
;
797 MLX4_PUT(outbox
->buf
, flags
, QUERY_DEV_CAP_EXT_FLAGS_OFFSET
);
799 /* For guests, disable timestamp */
800 MLX4_GET(field
, outbox
->buf
, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET
);
802 MLX4_PUT(outbox
->buf
, field
, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET
);
804 /* For guests, report Blueflame disabled */
805 MLX4_GET(field
, outbox
->buf
, QUERY_DEV_CAP_BF_OFFSET
);
807 MLX4_PUT(outbox
->buf
, field
, QUERY_DEV_CAP_BF_OFFSET
);
809 /* For guests, disable mw type 2 */
810 MLX4_GET(bmme_flags
, outbox
, QUERY_DEV_CAP_BMME_FLAGS_OFFSET
);
811 bmme_flags
&= ~MLX4_BMME_FLAG_TYPE_2_WIN
;
812 MLX4_PUT(outbox
->buf
, bmme_flags
, QUERY_DEV_CAP_BMME_FLAGS_OFFSET
);
814 /* turn off device-managed steering capability if not enabled */
815 if (dev
->caps
.steering_mode
!= MLX4_STEERING_MODE_DEVICE_MANAGED
) {
816 MLX4_GET(field
, outbox
->buf
,
817 QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET
);
819 MLX4_PUT(outbox
->buf
, field
,
820 QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET
);
825 int mlx4_QUERY_PORT_wrapper(struct mlx4_dev
*dev
, int slave
,
826 struct mlx4_vhcr
*vhcr
,
827 struct mlx4_cmd_mailbox
*inbox
,
828 struct mlx4_cmd_mailbox
*outbox
,
829 struct mlx4_cmd_info
*cmd
)
831 struct mlx4_priv
*priv
= mlx4_priv(dev
);
836 int admin_link_state
;
838 #define MLX4_VF_PORT_NO_LINK_SENSE_MASK 0xE0
839 #define MLX4_PORT_LINK_UP_MASK 0x80
840 #define QUERY_PORT_CUR_MAX_PKEY_OFFSET 0x0c
841 #define QUERY_PORT_CUR_MAX_GID_OFFSET 0x0e
843 err
= mlx4_cmd_box(dev
, 0, outbox
->dma
, vhcr
->in_modifier
, 0,
844 MLX4_CMD_QUERY_PORT
, MLX4_CMD_TIME_CLASS_B
,
847 if (!err
&& dev
->caps
.function
!= slave
) {
848 def_mac
= priv
->mfunc
.master
.vf_oper
[slave
].vport
[vhcr
->in_modifier
].state
.mac
;
849 MLX4_PUT(outbox
->buf
, def_mac
, QUERY_PORT_MAC_OFFSET
);
851 /* get port type - currently only eth is enabled */
852 MLX4_GET(port_type
, outbox
->buf
,
853 QUERY_PORT_SUPPORTED_TYPE_OFFSET
);
855 /* No link sensing allowed */
856 port_type
&= MLX4_VF_PORT_NO_LINK_SENSE_MASK
;
857 /* set port type to currently operating port type */
858 port_type
|= (dev
->caps
.port_type
[vhcr
->in_modifier
] & 0x3);
860 admin_link_state
= priv
->mfunc
.master
.vf_oper
[slave
].vport
[vhcr
->in_modifier
].state
.link_state
;
861 if (IFLA_VF_LINK_STATE_ENABLE
== admin_link_state
)
862 port_type
|= MLX4_PORT_LINK_UP_MASK
;
863 else if (IFLA_VF_LINK_STATE_DISABLE
== admin_link_state
)
864 port_type
&= ~MLX4_PORT_LINK_UP_MASK
;
866 MLX4_PUT(outbox
->buf
, port_type
,
867 QUERY_PORT_SUPPORTED_TYPE_OFFSET
);
869 short_field
= 1; /* slave max gids */
870 MLX4_PUT(outbox
->buf
, short_field
,
871 QUERY_PORT_CUR_MAX_GID_OFFSET
);
873 short_field
= dev
->caps
.pkey_table_len
[vhcr
->in_modifier
];
874 MLX4_PUT(outbox
->buf
, short_field
,
875 QUERY_PORT_CUR_MAX_PKEY_OFFSET
);
881 int mlx4_get_slave_pkey_gid_tbl_len(struct mlx4_dev
*dev
, u8 port
,
882 int *gid_tbl_len
, int *pkey_tbl_len
)
884 struct mlx4_cmd_mailbox
*mailbox
;
889 mailbox
= mlx4_alloc_cmd_mailbox(dev
);
891 return PTR_ERR(mailbox
);
893 err
= mlx4_cmd_box(dev
, 0, mailbox
->dma
, port
, 0,
894 MLX4_CMD_QUERY_PORT
, MLX4_CMD_TIME_CLASS_B
,
899 outbox
= mailbox
->buf
;
901 MLX4_GET(field
, outbox
, QUERY_PORT_CUR_MAX_GID_OFFSET
);
902 *gid_tbl_len
= field
;
904 MLX4_GET(field
, outbox
, QUERY_PORT_CUR_MAX_PKEY_OFFSET
);
905 *pkey_tbl_len
= field
;
908 mlx4_free_cmd_mailbox(dev
, mailbox
);
911 EXPORT_SYMBOL(mlx4_get_slave_pkey_gid_tbl_len
);
913 int mlx4_map_cmd(struct mlx4_dev
*dev
, u16 op
, struct mlx4_icm
*icm
, u64 virt
)
915 struct mlx4_cmd_mailbox
*mailbox
;
916 struct mlx4_icm_iter iter
;
924 mailbox
= mlx4_alloc_cmd_mailbox(dev
);
926 return PTR_ERR(mailbox
);
927 memset(mailbox
->buf
, 0, MLX4_MAILBOX_SIZE
);
928 pages
= mailbox
->buf
;
930 for (mlx4_icm_first(icm
, &iter
);
931 !mlx4_icm_last(&iter
);
932 mlx4_icm_next(&iter
)) {
934 * We have to pass pages that are aligned to their
935 * size, so find the least significant 1 in the
936 * address or size and use that as our log2 size.
938 lg
= ffs(mlx4_icm_addr(&iter
) | mlx4_icm_size(&iter
)) - 1;
939 if (lg
< MLX4_ICM_PAGE_SHIFT
) {
940 mlx4_warn(dev
, "Got FW area not aligned to %d (%llx/%lx).\n",
942 (unsigned long long) mlx4_icm_addr(&iter
),
943 mlx4_icm_size(&iter
));
948 for (i
= 0; i
< mlx4_icm_size(&iter
) >> lg
; ++i
) {
950 pages
[nent
* 2] = cpu_to_be64(virt
);
954 pages
[nent
* 2 + 1] =
955 cpu_to_be64((mlx4_icm_addr(&iter
) + (i
<< lg
)) |
956 (lg
- MLX4_ICM_PAGE_SHIFT
));
957 ts
+= 1 << (lg
- 10);
960 if (++nent
== MLX4_MAILBOX_SIZE
/ 16) {
961 err
= mlx4_cmd(dev
, mailbox
->dma
, nent
, 0, op
,
962 MLX4_CMD_TIME_CLASS_B
,
972 err
= mlx4_cmd(dev
, mailbox
->dma
, nent
, 0, op
,
973 MLX4_CMD_TIME_CLASS_B
, MLX4_CMD_NATIVE
);
978 case MLX4_CMD_MAP_FA
:
979 mlx4_dbg(dev
, "Mapped %d chunks/%d KB for FW.\n", tc
, ts
);
981 case MLX4_CMD_MAP_ICM_AUX
:
982 mlx4_dbg(dev
, "Mapped %d chunks/%d KB for ICM aux.\n", tc
, ts
);
984 case MLX4_CMD_MAP_ICM
:
985 mlx4_dbg(dev
, "Mapped %d chunks/%d KB at %llx for ICM.\n",
986 tc
, ts
, (unsigned long long) virt
- (ts
<< 10));
991 mlx4_free_cmd_mailbox(dev
, mailbox
);
995 int mlx4_MAP_FA(struct mlx4_dev
*dev
, struct mlx4_icm
*icm
)
997 return mlx4_map_cmd(dev
, MLX4_CMD_MAP_FA
, icm
, -1);
1000 int mlx4_UNMAP_FA(struct mlx4_dev
*dev
)
1002 return mlx4_cmd(dev
, 0, 0, 0, MLX4_CMD_UNMAP_FA
,
1003 MLX4_CMD_TIME_CLASS_B
, MLX4_CMD_NATIVE
);
1007 int mlx4_RUN_FW(struct mlx4_dev
*dev
)
1009 return mlx4_cmd(dev
, 0, 0, 0, MLX4_CMD_RUN_FW
,
1010 MLX4_CMD_TIME_CLASS_A
, MLX4_CMD_NATIVE
);
1013 int mlx4_QUERY_FW(struct mlx4_dev
*dev
)
1015 struct mlx4_fw
*fw
= &mlx4_priv(dev
)->fw
;
1016 struct mlx4_cmd
*cmd
= &mlx4_priv(dev
)->cmd
;
1017 struct mlx4_cmd_mailbox
*mailbox
;
1024 #define QUERY_FW_OUT_SIZE 0x100
1025 #define QUERY_FW_VER_OFFSET 0x00
1026 #define QUERY_FW_PPF_ID 0x09
1027 #define QUERY_FW_CMD_IF_REV_OFFSET 0x0a
1028 #define QUERY_FW_MAX_CMD_OFFSET 0x0f
1029 #define QUERY_FW_ERR_START_OFFSET 0x30
1030 #define QUERY_FW_ERR_SIZE_OFFSET 0x38
1031 #define QUERY_FW_ERR_BAR_OFFSET 0x3c
1033 #define QUERY_FW_SIZE_OFFSET 0x00
1034 #define QUERY_FW_CLR_INT_BASE_OFFSET 0x20
1035 #define QUERY_FW_CLR_INT_BAR_OFFSET 0x28
1037 #define QUERY_FW_COMM_BASE_OFFSET 0x40
1038 #define QUERY_FW_COMM_BAR_OFFSET 0x48
1040 #define QUERY_FW_CLOCK_OFFSET 0x50
1041 #define QUERY_FW_CLOCK_BAR 0x58
1043 mailbox
= mlx4_alloc_cmd_mailbox(dev
);
1044 if (IS_ERR(mailbox
))
1045 return PTR_ERR(mailbox
);
1046 outbox
= mailbox
->buf
;
1048 err
= mlx4_cmd_box(dev
, 0, mailbox
->dma
, 0, 0, MLX4_CMD_QUERY_FW
,
1049 MLX4_CMD_TIME_CLASS_A
, MLX4_CMD_NATIVE
);
1053 MLX4_GET(fw_ver
, outbox
, QUERY_FW_VER_OFFSET
);
1055 * FW subminor version is at more significant bits than minor
1056 * version, so swap here.
1058 dev
->caps
.fw_ver
= (fw_ver
& 0xffff00000000ull
) |
1059 ((fw_ver
& 0xffff0000ull
) >> 16) |
1060 ((fw_ver
& 0x0000ffffull
) << 16);
1062 MLX4_GET(lg
, outbox
, QUERY_FW_PPF_ID
);
1063 dev
->caps
.function
= lg
;
1065 if (mlx4_is_slave(dev
))
1069 MLX4_GET(cmd_if_rev
, outbox
, QUERY_FW_CMD_IF_REV_OFFSET
);
1070 if (cmd_if_rev
< MLX4_COMMAND_INTERFACE_MIN_REV
||
1071 cmd_if_rev
> MLX4_COMMAND_INTERFACE_MAX_REV
) {
1072 mlx4_err(dev
, "Installed FW has unsupported "
1073 "command interface revision %d.\n",
1075 mlx4_err(dev
, "(Installed FW version is %d.%d.%03d)\n",
1076 (int) (dev
->caps
.fw_ver
>> 32),
1077 (int) (dev
->caps
.fw_ver
>> 16) & 0xffff,
1078 (int) dev
->caps
.fw_ver
& 0xffff);
1079 mlx4_err(dev
, "This driver version supports only revisions %d to %d.\n",
1080 MLX4_COMMAND_INTERFACE_MIN_REV
, MLX4_COMMAND_INTERFACE_MAX_REV
);
1085 if (cmd_if_rev
< MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS
)
1086 dev
->flags
|= MLX4_FLAG_OLD_PORT_CMDS
;
1088 MLX4_GET(lg
, outbox
, QUERY_FW_MAX_CMD_OFFSET
);
1089 cmd
->max_cmds
= 1 << lg
;
1091 mlx4_dbg(dev
, "FW version %d.%d.%03d (cmd intf rev %d), max commands %d\n",
1092 (int) (dev
->caps
.fw_ver
>> 32),
1093 (int) (dev
->caps
.fw_ver
>> 16) & 0xffff,
1094 (int) dev
->caps
.fw_ver
& 0xffff,
1095 cmd_if_rev
, cmd
->max_cmds
);
1097 MLX4_GET(fw
->catas_offset
, outbox
, QUERY_FW_ERR_START_OFFSET
);
1098 MLX4_GET(fw
->catas_size
, outbox
, QUERY_FW_ERR_SIZE_OFFSET
);
1099 MLX4_GET(fw
->catas_bar
, outbox
, QUERY_FW_ERR_BAR_OFFSET
);
1100 fw
->catas_bar
= (fw
->catas_bar
>> 6) * 2;
1102 mlx4_dbg(dev
, "Catastrophic error buffer at 0x%llx, size 0x%x, BAR %d\n",
1103 (unsigned long long) fw
->catas_offset
, fw
->catas_size
, fw
->catas_bar
);
1105 MLX4_GET(fw
->fw_pages
, outbox
, QUERY_FW_SIZE_OFFSET
);
1106 MLX4_GET(fw
->clr_int_base
, outbox
, QUERY_FW_CLR_INT_BASE_OFFSET
);
1107 MLX4_GET(fw
->clr_int_bar
, outbox
, QUERY_FW_CLR_INT_BAR_OFFSET
);
1108 fw
->clr_int_bar
= (fw
->clr_int_bar
>> 6) * 2;
1110 MLX4_GET(fw
->comm_base
, outbox
, QUERY_FW_COMM_BASE_OFFSET
);
1111 MLX4_GET(fw
->comm_bar
, outbox
, QUERY_FW_COMM_BAR_OFFSET
);
1112 fw
->comm_bar
= (fw
->comm_bar
>> 6) * 2;
1113 mlx4_dbg(dev
, "Communication vector bar:%d offset:0x%llx\n",
1114 fw
->comm_bar
, fw
->comm_base
);
1115 mlx4_dbg(dev
, "FW size %d KB\n", fw
->fw_pages
>> 2);
1117 MLX4_GET(fw
->clock_offset
, outbox
, QUERY_FW_CLOCK_OFFSET
);
1118 MLX4_GET(fw
->clock_bar
, outbox
, QUERY_FW_CLOCK_BAR
);
1119 fw
->clock_bar
= (fw
->clock_bar
>> 6) * 2;
1120 mlx4_dbg(dev
, "Internal clock bar:%d offset:0x%llx\n",
1121 fw
->clock_bar
, fw
->clock_offset
);
1124 * Round up number of system pages needed in case
1125 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE.
1128 ALIGN(fw
->fw_pages
, PAGE_SIZE
/ MLX4_ICM_PAGE_SIZE
) >>
1129 (PAGE_SHIFT
- MLX4_ICM_PAGE_SHIFT
);
1131 mlx4_dbg(dev
, "Clear int @ %llx, BAR %d\n",
1132 (unsigned long long) fw
->clr_int_base
, fw
->clr_int_bar
);
1135 mlx4_free_cmd_mailbox(dev
, mailbox
);
1139 int mlx4_QUERY_FW_wrapper(struct mlx4_dev
*dev
, int slave
,
1140 struct mlx4_vhcr
*vhcr
,
1141 struct mlx4_cmd_mailbox
*inbox
,
1142 struct mlx4_cmd_mailbox
*outbox
,
1143 struct mlx4_cmd_info
*cmd
)
1148 outbuf
= outbox
->buf
;
1149 err
= mlx4_cmd_box(dev
, 0, outbox
->dma
, 0, 0, MLX4_CMD_QUERY_FW
,
1150 MLX4_CMD_TIME_CLASS_A
, MLX4_CMD_NATIVE
);
1154 /* for slaves, set pci PPF ID to invalid and zero out everything
1155 * else except FW version */
1156 outbuf
[0] = outbuf
[1] = 0;
1157 memset(&outbuf
[8], 0, QUERY_FW_OUT_SIZE
- 8);
1158 outbuf
[QUERY_FW_PPF_ID
] = MLX4_INVALID_SLAVE_ID
;
1163 static void get_board_id(void *vsd
, char *board_id
)
1167 #define VSD_OFFSET_SIG1 0x00
1168 #define VSD_OFFSET_SIG2 0xde
1169 #define VSD_OFFSET_MLX_BOARD_ID 0xd0
1170 #define VSD_OFFSET_TS_BOARD_ID 0x20
1172 #define VSD_SIGNATURE_TOPSPIN 0x5ad
1174 memset(board_id
, 0, MLX4_BOARD_ID_LEN
);
1176 if (be16_to_cpup(vsd
+ VSD_OFFSET_SIG1
) == VSD_SIGNATURE_TOPSPIN
&&
1177 be16_to_cpup(vsd
+ VSD_OFFSET_SIG2
) == VSD_SIGNATURE_TOPSPIN
) {
1178 strlcpy(board_id
, vsd
+ VSD_OFFSET_TS_BOARD_ID
, MLX4_BOARD_ID_LEN
);
1181 * The board ID is a string but the firmware byte
1182 * swaps each 4-byte word before passing it back to
1183 * us. Therefore we need to swab it before printing.
1185 for (i
= 0; i
< 4; ++i
)
1186 ((u32
*) board_id
)[i
] =
1187 swab32(*(u32
*) (vsd
+ VSD_OFFSET_MLX_BOARD_ID
+ i
* 4));
1191 int mlx4_QUERY_ADAPTER(struct mlx4_dev
*dev
, struct mlx4_adapter
*adapter
)
1193 struct mlx4_cmd_mailbox
*mailbox
;
1197 #define QUERY_ADAPTER_OUT_SIZE 0x100
1198 #define QUERY_ADAPTER_INTA_PIN_OFFSET 0x10
1199 #define QUERY_ADAPTER_VSD_OFFSET 0x20
1201 mailbox
= mlx4_alloc_cmd_mailbox(dev
);
1202 if (IS_ERR(mailbox
))
1203 return PTR_ERR(mailbox
);
1204 outbox
= mailbox
->buf
;
1206 err
= mlx4_cmd_box(dev
, 0, mailbox
->dma
, 0, 0, MLX4_CMD_QUERY_ADAPTER
,
1207 MLX4_CMD_TIME_CLASS_A
, MLX4_CMD_NATIVE
);
1211 MLX4_GET(adapter
->inta_pin
, outbox
, QUERY_ADAPTER_INTA_PIN_OFFSET
);
1213 get_board_id(outbox
+ QUERY_ADAPTER_VSD_OFFSET
/ 4,
1217 mlx4_free_cmd_mailbox(dev
, mailbox
);
1221 int mlx4_INIT_HCA(struct mlx4_dev
*dev
, struct mlx4_init_hca_param
*param
)
1223 struct mlx4_cmd_mailbox
*mailbox
;
1227 #define INIT_HCA_IN_SIZE 0x200
1228 #define INIT_HCA_VERSION_OFFSET 0x000
1229 #define INIT_HCA_VERSION 2
1230 #define INIT_HCA_CACHELINE_SZ_OFFSET 0x0e
1231 #define INIT_HCA_FLAGS_OFFSET 0x014
1232 #define INIT_HCA_QPC_OFFSET 0x020
1233 #define INIT_HCA_QPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x10)
1234 #define INIT_HCA_LOG_QP_OFFSET (INIT_HCA_QPC_OFFSET + 0x17)
1235 #define INIT_HCA_SRQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x28)
1236 #define INIT_HCA_LOG_SRQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x2f)
1237 #define INIT_HCA_CQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x30)
1238 #define INIT_HCA_LOG_CQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x37)
1239 #define INIT_HCA_EQE_CQE_OFFSETS (INIT_HCA_QPC_OFFSET + 0x38)
1240 #define INIT_HCA_ALTC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x40)
1241 #define INIT_HCA_AUXC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x50)
1242 #define INIT_HCA_EQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x60)
1243 #define INIT_HCA_LOG_EQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x67)
1244 #define INIT_HCA_RDMARC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x70)
1245 #define INIT_HCA_LOG_RD_OFFSET (INIT_HCA_QPC_OFFSET + 0x77)
1246 #define INIT_HCA_MCAST_OFFSET 0x0c0
1247 #define INIT_HCA_MC_BASE_OFFSET (INIT_HCA_MCAST_OFFSET + 0x00)
1248 #define INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x12)
1249 #define INIT_HCA_LOG_MC_HASH_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x16)
1250 #define INIT_HCA_UC_STEERING_OFFSET (INIT_HCA_MCAST_OFFSET + 0x18)
1251 #define INIT_HCA_LOG_MC_TABLE_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x1b)
1252 #define INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN 0x6
1253 #define INIT_HCA_FS_PARAM_OFFSET 0x1d0
1254 #define INIT_HCA_FS_BASE_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x00)
1255 #define INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x12)
1256 #define INIT_HCA_FS_LOG_TABLE_SZ_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x1b)
1257 #define INIT_HCA_FS_ETH_BITS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x21)
1258 #define INIT_HCA_FS_ETH_NUM_ADDRS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x22)
1259 #define INIT_HCA_FS_IB_BITS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x25)
1260 #define INIT_HCA_FS_IB_NUM_ADDRS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x26)
1261 #define INIT_HCA_TPT_OFFSET 0x0f0
1262 #define INIT_HCA_DMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x00)
1263 #define INIT_HCA_TPT_MW_OFFSET (INIT_HCA_TPT_OFFSET + 0x08)
1264 #define INIT_HCA_LOG_MPT_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x0b)
1265 #define INIT_HCA_MTT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x10)
1266 #define INIT_HCA_CMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x18)
1267 #define INIT_HCA_UAR_OFFSET 0x120
1268 #define INIT_HCA_LOG_UAR_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0a)
1269 #define INIT_HCA_UAR_PAGE_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0b)
1271 mailbox
= mlx4_alloc_cmd_mailbox(dev
);
1272 if (IS_ERR(mailbox
))
1273 return PTR_ERR(mailbox
);
1274 inbox
= mailbox
->buf
;
1276 memset(inbox
, 0, INIT_HCA_IN_SIZE
);
1278 *((u8
*) mailbox
->buf
+ INIT_HCA_VERSION_OFFSET
) = INIT_HCA_VERSION
;
1280 *((u8
*) mailbox
->buf
+ INIT_HCA_CACHELINE_SZ_OFFSET
) =
1281 (ilog2(cache_line_size()) - 4) << 5;
1283 #if defined(__LITTLE_ENDIAN)
1284 *(inbox
+ INIT_HCA_FLAGS_OFFSET
/ 4) &= ~cpu_to_be32(1 << 1);
1285 #elif defined(__BIG_ENDIAN)
1286 *(inbox
+ INIT_HCA_FLAGS_OFFSET
/ 4) |= cpu_to_be32(1 << 1);
1288 #error Host endianness not defined
1290 /* Check port for UD address vector: */
1291 *(inbox
+ INIT_HCA_FLAGS_OFFSET
/ 4) |= cpu_to_be32(1);
1293 /* Enable IPoIB checksumming if we can: */
1294 if (dev
->caps
.flags
& MLX4_DEV_CAP_FLAG_IPOIB_CSUM
)
1295 *(inbox
+ INIT_HCA_FLAGS_OFFSET
/ 4) |= cpu_to_be32(1 << 3);
1297 /* Enable QoS support if module parameter set */
1299 *(inbox
+ INIT_HCA_FLAGS_OFFSET
/ 4) |= cpu_to_be32(1 << 2);
1301 /* enable counters */
1302 if (dev
->caps
.flags
& MLX4_DEV_CAP_FLAG_COUNTERS
)
1303 *(inbox
+ INIT_HCA_FLAGS_OFFSET
/ 4) |= cpu_to_be32(1 << 4);
1305 /* CX3 is capable of extending CQEs/EQEs from 32 to 64 bytes */
1306 if (dev
->caps
.flags
& MLX4_DEV_CAP_FLAG_64B_EQE
) {
1307 *(inbox
+ INIT_HCA_EQE_CQE_OFFSETS
/ 4) |= cpu_to_be32(1 << 29);
1308 dev
->caps
.eqe_size
= 64;
1309 dev
->caps
.eqe_factor
= 1;
1311 dev
->caps
.eqe_size
= 32;
1312 dev
->caps
.eqe_factor
= 0;
1315 if (dev
->caps
.flags
& MLX4_DEV_CAP_FLAG_64B_CQE
) {
1316 *(inbox
+ INIT_HCA_EQE_CQE_OFFSETS
/ 4) |= cpu_to_be32(1 << 30);
1317 dev
->caps
.cqe_size
= 64;
1318 dev
->caps
.userspace_caps
|= MLX4_USER_DEV_CAP_64B_CQE
;
1320 dev
->caps
.cqe_size
= 32;
1323 /* QPC/EEC/CQC/EQC/RDMARC attributes */
1325 MLX4_PUT(inbox
, param
->qpc_base
, INIT_HCA_QPC_BASE_OFFSET
);
1326 MLX4_PUT(inbox
, param
->log_num_qps
, INIT_HCA_LOG_QP_OFFSET
);
1327 MLX4_PUT(inbox
, param
->srqc_base
, INIT_HCA_SRQC_BASE_OFFSET
);
1328 MLX4_PUT(inbox
, param
->log_num_srqs
, INIT_HCA_LOG_SRQ_OFFSET
);
1329 MLX4_PUT(inbox
, param
->cqc_base
, INIT_HCA_CQC_BASE_OFFSET
);
1330 MLX4_PUT(inbox
, param
->log_num_cqs
, INIT_HCA_LOG_CQ_OFFSET
);
1331 MLX4_PUT(inbox
, param
->altc_base
, INIT_HCA_ALTC_BASE_OFFSET
);
1332 MLX4_PUT(inbox
, param
->auxc_base
, INIT_HCA_AUXC_BASE_OFFSET
);
1333 MLX4_PUT(inbox
, param
->eqc_base
, INIT_HCA_EQC_BASE_OFFSET
);
1334 MLX4_PUT(inbox
, param
->log_num_eqs
, INIT_HCA_LOG_EQ_OFFSET
);
1335 MLX4_PUT(inbox
, param
->rdmarc_base
, INIT_HCA_RDMARC_BASE_OFFSET
);
1336 MLX4_PUT(inbox
, param
->log_rd_per_qp
, INIT_HCA_LOG_RD_OFFSET
);
1338 /* steering attributes */
1339 if (dev
->caps
.steering_mode
==
1340 MLX4_STEERING_MODE_DEVICE_MANAGED
) {
1341 *(inbox
+ INIT_HCA_FLAGS_OFFSET
/ 4) |=
1343 INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN
);
1345 MLX4_PUT(inbox
, param
->mc_base
, INIT_HCA_FS_BASE_OFFSET
);
1346 MLX4_PUT(inbox
, param
->log_mc_entry_sz
,
1347 INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET
);
1348 MLX4_PUT(inbox
, param
->log_mc_table_sz
,
1349 INIT_HCA_FS_LOG_TABLE_SZ_OFFSET
);
1350 /* Enable Ethernet flow steering
1351 * with udp unicast and tcp unicast
1353 MLX4_PUT(inbox
, (u8
) (MLX4_FS_UDP_UC_EN
| MLX4_FS_TCP_UC_EN
),
1354 INIT_HCA_FS_ETH_BITS_OFFSET
);
1355 MLX4_PUT(inbox
, (u16
) MLX4_FS_NUM_OF_L2_ADDR
,
1356 INIT_HCA_FS_ETH_NUM_ADDRS_OFFSET
);
1357 /* Enable IPoIB flow steering
1358 * with udp unicast and tcp unicast
1360 MLX4_PUT(inbox
, (u8
) (MLX4_FS_UDP_UC_EN
| MLX4_FS_TCP_UC_EN
),
1361 INIT_HCA_FS_IB_BITS_OFFSET
);
1362 MLX4_PUT(inbox
, (u16
) MLX4_FS_NUM_OF_L2_ADDR
,
1363 INIT_HCA_FS_IB_NUM_ADDRS_OFFSET
);
1365 MLX4_PUT(inbox
, param
->mc_base
, INIT_HCA_MC_BASE_OFFSET
);
1366 MLX4_PUT(inbox
, param
->log_mc_entry_sz
,
1367 INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET
);
1368 MLX4_PUT(inbox
, param
->log_mc_hash_sz
,
1369 INIT_HCA_LOG_MC_HASH_SZ_OFFSET
);
1370 MLX4_PUT(inbox
, param
->log_mc_table_sz
,
1371 INIT_HCA_LOG_MC_TABLE_SZ_OFFSET
);
1372 if (dev
->caps
.steering_mode
== MLX4_STEERING_MODE_B0
)
1373 MLX4_PUT(inbox
, (u8
) (1 << 3),
1374 INIT_HCA_UC_STEERING_OFFSET
);
1377 /* TPT attributes */
1379 MLX4_PUT(inbox
, param
->dmpt_base
, INIT_HCA_DMPT_BASE_OFFSET
);
1380 MLX4_PUT(inbox
, param
->mw_enabled
, INIT_HCA_TPT_MW_OFFSET
);
1381 MLX4_PUT(inbox
, param
->log_mpt_sz
, INIT_HCA_LOG_MPT_SZ_OFFSET
);
1382 MLX4_PUT(inbox
, param
->mtt_base
, INIT_HCA_MTT_BASE_OFFSET
);
1383 MLX4_PUT(inbox
, param
->cmpt_base
, INIT_HCA_CMPT_BASE_OFFSET
);
1385 /* UAR attributes */
1387 MLX4_PUT(inbox
, param
->uar_page_sz
, INIT_HCA_UAR_PAGE_SZ_OFFSET
);
1388 MLX4_PUT(inbox
, param
->log_uar_sz
, INIT_HCA_LOG_UAR_SZ_OFFSET
);
1390 err
= mlx4_cmd(dev
, mailbox
->dma
, 0, 0, MLX4_CMD_INIT_HCA
, 10000,
1394 mlx4_err(dev
, "INIT_HCA returns %d\n", err
);
1396 mlx4_free_cmd_mailbox(dev
, mailbox
);
1400 int mlx4_QUERY_HCA(struct mlx4_dev
*dev
,
1401 struct mlx4_init_hca_param
*param
)
1403 struct mlx4_cmd_mailbox
*mailbox
;
1409 #define QUERY_HCA_GLOBAL_CAPS_OFFSET 0x04
1410 #define QUERY_HCA_CORE_CLOCK_OFFSET 0x0c
1412 mailbox
= mlx4_alloc_cmd_mailbox(dev
);
1413 if (IS_ERR(mailbox
))
1414 return PTR_ERR(mailbox
);
1415 outbox
= mailbox
->buf
;
1417 err
= mlx4_cmd_box(dev
, 0, mailbox
->dma
, 0, 0,
1419 MLX4_CMD_TIME_CLASS_B
,
1420 !mlx4_is_slave(dev
));
1424 MLX4_GET(param
->global_caps
, outbox
, QUERY_HCA_GLOBAL_CAPS_OFFSET
);
1425 MLX4_GET(param
->hca_core_clock
, outbox
, QUERY_HCA_CORE_CLOCK_OFFSET
);
1427 /* QPC/EEC/CQC/EQC/RDMARC attributes */
1429 MLX4_GET(param
->qpc_base
, outbox
, INIT_HCA_QPC_BASE_OFFSET
);
1430 MLX4_GET(param
->log_num_qps
, outbox
, INIT_HCA_LOG_QP_OFFSET
);
1431 MLX4_GET(param
->srqc_base
, outbox
, INIT_HCA_SRQC_BASE_OFFSET
);
1432 MLX4_GET(param
->log_num_srqs
, outbox
, INIT_HCA_LOG_SRQ_OFFSET
);
1433 MLX4_GET(param
->cqc_base
, outbox
, INIT_HCA_CQC_BASE_OFFSET
);
1434 MLX4_GET(param
->log_num_cqs
, outbox
, INIT_HCA_LOG_CQ_OFFSET
);
1435 MLX4_GET(param
->altc_base
, outbox
, INIT_HCA_ALTC_BASE_OFFSET
);
1436 MLX4_GET(param
->auxc_base
, outbox
, INIT_HCA_AUXC_BASE_OFFSET
);
1437 MLX4_GET(param
->eqc_base
, outbox
, INIT_HCA_EQC_BASE_OFFSET
);
1438 MLX4_GET(param
->log_num_eqs
, outbox
, INIT_HCA_LOG_EQ_OFFSET
);
1439 MLX4_GET(param
->rdmarc_base
, outbox
, INIT_HCA_RDMARC_BASE_OFFSET
);
1440 MLX4_GET(param
->log_rd_per_qp
, outbox
, INIT_HCA_LOG_RD_OFFSET
);
1442 MLX4_GET(dword_field
, outbox
, INIT_HCA_FLAGS_OFFSET
);
1443 if (dword_field
& (1 << INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN
)) {
1444 param
->steering_mode
= MLX4_STEERING_MODE_DEVICE_MANAGED
;
1446 MLX4_GET(byte_field
, outbox
, INIT_HCA_UC_STEERING_OFFSET
);
1447 if (byte_field
& 0x8)
1448 param
->steering_mode
= MLX4_STEERING_MODE_B0
;
1450 param
->steering_mode
= MLX4_STEERING_MODE_A0
;
1452 /* steering attributes */
1453 if (param
->steering_mode
== MLX4_STEERING_MODE_DEVICE_MANAGED
) {
1454 MLX4_GET(param
->mc_base
, outbox
, INIT_HCA_FS_BASE_OFFSET
);
1455 MLX4_GET(param
->log_mc_entry_sz
, outbox
,
1456 INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET
);
1457 MLX4_GET(param
->log_mc_table_sz
, outbox
,
1458 INIT_HCA_FS_LOG_TABLE_SZ_OFFSET
);
1460 MLX4_GET(param
->mc_base
, outbox
, INIT_HCA_MC_BASE_OFFSET
);
1461 MLX4_GET(param
->log_mc_entry_sz
, outbox
,
1462 INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET
);
1463 MLX4_GET(param
->log_mc_hash_sz
, outbox
,
1464 INIT_HCA_LOG_MC_HASH_SZ_OFFSET
);
1465 MLX4_GET(param
->log_mc_table_sz
, outbox
,
1466 INIT_HCA_LOG_MC_TABLE_SZ_OFFSET
);
1469 /* CX3 is capable of extending CQEs/EQEs from 32 to 64 bytes */
1470 MLX4_GET(byte_field
, outbox
, INIT_HCA_EQE_CQE_OFFSETS
);
1471 if (byte_field
& 0x20) /* 64-bytes eqe enabled */
1472 param
->dev_cap_enabled
|= MLX4_DEV_CAP_64B_EQE_ENABLED
;
1473 if (byte_field
& 0x40) /* 64-bytes cqe enabled */
1474 param
->dev_cap_enabled
|= MLX4_DEV_CAP_64B_CQE_ENABLED
;
1476 /* TPT attributes */
1478 MLX4_GET(param
->dmpt_base
, outbox
, INIT_HCA_DMPT_BASE_OFFSET
);
1479 MLX4_GET(param
->mw_enabled
, outbox
, INIT_HCA_TPT_MW_OFFSET
);
1480 MLX4_GET(param
->log_mpt_sz
, outbox
, INIT_HCA_LOG_MPT_SZ_OFFSET
);
1481 MLX4_GET(param
->mtt_base
, outbox
, INIT_HCA_MTT_BASE_OFFSET
);
1482 MLX4_GET(param
->cmpt_base
, outbox
, INIT_HCA_CMPT_BASE_OFFSET
);
1484 /* UAR attributes */
1486 MLX4_GET(param
->uar_page_sz
, outbox
, INIT_HCA_UAR_PAGE_SZ_OFFSET
);
1487 MLX4_GET(param
->log_uar_sz
, outbox
, INIT_HCA_LOG_UAR_SZ_OFFSET
);
1490 mlx4_free_cmd_mailbox(dev
, mailbox
);
1495 /* for IB-type ports only in SRIOV mode. Checks that both proxy QP0
1496 * and real QP0 are active, so that the paravirtualized QP0 is ready
1498 static int check_qp0_state(struct mlx4_dev
*dev
, int function
, int port
)
1500 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1501 /* irrelevant if not infiniband */
1502 if (priv
->mfunc
.master
.qp0_state
[port
].proxy_qp0_active
&&
1503 priv
->mfunc
.master
.qp0_state
[port
].qp0_active
)
1508 int mlx4_INIT_PORT_wrapper(struct mlx4_dev
*dev
, int slave
,
1509 struct mlx4_vhcr
*vhcr
,
1510 struct mlx4_cmd_mailbox
*inbox
,
1511 struct mlx4_cmd_mailbox
*outbox
,
1512 struct mlx4_cmd_info
*cmd
)
1514 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1515 int port
= vhcr
->in_modifier
;
1518 if (priv
->mfunc
.master
.slave_state
[slave
].init_port_mask
& (1 << port
))
1521 if (dev
->caps
.port_mask
[port
] != MLX4_PORT_TYPE_IB
) {
1522 /* Enable port only if it was previously disabled */
1523 if (!priv
->mfunc
.master
.init_port_ref
[port
]) {
1524 err
= mlx4_cmd(dev
, 0, port
, 0, MLX4_CMD_INIT_PORT
,
1525 MLX4_CMD_TIME_CLASS_A
, MLX4_CMD_NATIVE
);
1529 priv
->mfunc
.master
.slave_state
[slave
].init_port_mask
|= (1 << port
);
1531 if (slave
== mlx4_master_func_num(dev
)) {
1532 if (check_qp0_state(dev
, slave
, port
) &&
1533 !priv
->mfunc
.master
.qp0_state
[port
].port_active
) {
1534 err
= mlx4_cmd(dev
, 0, port
, 0, MLX4_CMD_INIT_PORT
,
1535 MLX4_CMD_TIME_CLASS_A
, MLX4_CMD_NATIVE
);
1538 priv
->mfunc
.master
.qp0_state
[port
].port_active
= 1;
1539 priv
->mfunc
.master
.slave_state
[slave
].init_port_mask
|= (1 << port
);
1542 priv
->mfunc
.master
.slave_state
[slave
].init_port_mask
|= (1 << port
);
1544 ++priv
->mfunc
.master
.init_port_ref
[port
];
1548 int mlx4_INIT_PORT(struct mlx4_dev
*dev
, int port
)
1550 struct mlx4_cmd_mailbox
*mailbox
;
1556 if (dev
->flags
& MLX4_FLAG_OLD_PORT_CMDS
) {
1557 #define INIT_PORT_IN_SIZE 256
1558 #define INIT_PORT_FLAGS_OFFSET 0x00
1559 #define INIT_PORT_FLAG_SIG (1 << 18)
1560 #define INIT_PORT_FLAG_NG (1 << 17)
1561 #define INIT_PORT_FLAG_G0 (1 << 16)
1562 #define INIT_PORT_VL_SHIFT 4
1563 #define INIT_PORT_PORT_WIDTH_SHIFT 8
1564 #define INIT_PORT_MTU_OFFSET 0x04
1565 #define INIT_PORT_MAX_GID_OFFSET 0x06
1566 #define INIT_PORT_MAX_PKEY_OFFSET 0x0a
1567 #define INIT_PORT_GUID0_OFFSET 0x10
1568 #define INIT_PORT_NODE_GUID_OFFSET 0x18
1569 #define INIT_PORT_SI_GUID_OFFSET 0x20
1571 mailbox
= mlx4_alloc_cmd_mailbox(dev
);
1572 if (IS_ERR(mailbox
))
1573 return PTR_ERR(mailbox
);
1574 inbox
= mailbox
->buf
;
1576 memset(inbox
, 0, INIT_PORT_IN_SIZE
);
1579 flags
|= (dev
->caps
.vl_cap
[port
] & 0xf) << INIT_PORT_VL_SHIFT
;
1580 flags
|= (dev
->caps
.port_width_cap
[port
] & 0xf) << INIT_PORT_PORT_WIDTH_SHIFT
;
1581 MLX4_PUT(inbox
, flags
, INIT_PORT_FLAGS_OFFSET
);
1583 field
= 128 << dev
->caps
.ib_mtu_cap
[port
];
1584 MLX4_PUT(inbox
, field
, INIT_PORT_MTU_OFFSET
);
1585 field
= dev
->caps
.gid_table_len
[port
];
1586 MLX4_PUT(inbox
, field
, INIT_PORT_MAX_GID_OFFSET
);
1587 field
= dev
->caps
.pkey_table_len
[port
];
1588 MLX4_PUT(inbox
, field
, INIT_PORT_MAX_PKEY_OFFSET
);
1590 err
= mlx4_cmd(dev
, mailbox
->dma
, port
, 0, MLX4_CMD_INIT_PORT
,
1591 MLX4_CMD_TIME_CLASS_A
, MLX4_CMD_NATIVE
);
1593 mlx4_free_cmd_mailbox(dev
, mailbox
);
1595 err
= mlx4_cmd(dev
, 0, port
, 0, MLX4_CMD_INIT_PORT
,
1596 MLX4_CMD_TIME_CLASS_A
, MLX4_CMD_WRAPPED
);
1600 EXPORT_SYMBOL_GPL(mlx4_INIT_PORT
);
1602 int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev
*dev
, int slave
,
1603 struct mlx4_vhcr
*vhcr
,
1604 struct mlx4_cmd_mailbox
*inbox
,
1605 struct mlx4_cmd_mailbox
*outbox
,
1606 struct mlx4_cmd_info
*cmd
)
1608 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1609 int port
= vhcr
->in_modifier
;
1612 if (!(priv
->mfunc
.master
.slave_state
[slave
].init_port_mask
&
1616 if (dev
->caps
.port_mask
[port
] != MLX4_PORT_TYPE_IB
) {
1617 if (priv
->mfunc
.master
.init_port_ref
[port
] == 1) {
1618 err
= mlx4_cmd(dev
, 0, port
, 0, MLX4_CMD_CLOSE_PORT
,
1619 1000, MLX4_CMD_NATIVE
);
1623 priv
->mfunc
.master
.slave_state
[slave
].init_port_mask
&= ~(1 << port
);
1625 /* infiniband port */
1626 if (slave
== mlx4_master_func_num(dev
)) {
1627 if (!priv
->mfunc
.master
.qp0_state
[port
].qp0_active
&&
1628 priv
->mfunc
.master
.qp0_state
[port
].port_active
) {
1629 err
= mlx4_cmd(dev
, 0, port
, 0, MLX4_CMD_CLOSE_PORT
,
1630 1000, MLX4_CMD_NATIVE
);
1633 priv
->mfunc
.master
.slave_state
[slave
].init_port_mask
&= ~(1 << port
);
1634 priv
->mfunc
.master
.qp0_state
[port
].port_active
= 0;
1637 priv
->mfunc
.master
.slave_state
[slave
].init_port_mask
&= ~(1 << port
);
1639 --priv
->mfunc
.master
.init_port_ref
[port
];
1643 int mlx4_CLOSE_PORT(struct mlx4_dev
*dev
, int port
)
1645 return mlx4_cmd(dev
, 0, port
, 0, MLX4_CMD_CLOSE_PORT
, 1000,
1648 EXPORT_SYMBOL_GPL(mlx4_CLOSE_PORT
);
1650 int mlx4_CLOSE_HCA(struct mlx4_dev
*dev
, int panic
)
1652 return mlx4_cmd(dev
, 0, 0, panic
, MLX4_CMD_CLOSE_HCA
, 1000,
1656 int mlx4_SET_ICM_SIZE(struct mlx4_dev
*dev
, u64 icm_size
, u64
*aux_pages
)
1658 int ret
= mlx4_cmd_imm(dev
, icm_size
, aux_pages
, 0, 0,
1659 MLX4_CMD_SET_ICM_SIZE
,
1660 MLX4_CMD_TIME_CLASS_A
, MLX4_CMD_NATIVE
);
1665 * Round up number of system pages needed in case
1666 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE.
1668 *aux_pages
= ALIGN(*aux_pages
, PAGE_SIZE
/ MLX4_ICM_PAGE_SIZE
) >>
1669 (PAGE_SHIFT
- MLX4_ICM_PAGE_SHIFT
);
1674 int mlx4_NOP(struct mlx4_dev
*dev
)
1676 /* Input modifier of 0x1f means "finish as soon as possible." */
1677 return mlx4_cmd(dev
, 0, 0x1f, 0, MLX4_CMD_NOP
, 100, MLX4_CMD_NATIVE
);
1680 #define MLX4_WOL_SETUP_MODE (5 << 28)
1681 int mlx4_wol_read(struct mlx4_dev
*dev
, u64
*config
, int port
)
1683 u32 in_mod
= MLX4_WOL_SETUP_MODE
| port
<< 8;
1685 return mlx4_cmd_imm(dev
, 0, config
, in_mod
, 0x3,
1686 MLX4_CMD_MOD_STAT_CFG
, MLX4_CMD_TIME_CLASS_A
,
1689 EXPORT_SYMBOL_GPL(mlx4_wol_read
);
1691 int mlx4_wol_write(struct mlx4_dev
*dev
, u64 config
, int port
)
1693 u32 in_mod
= MLX4_WOL_SETUP_MODE
| port
<< 8;
1695 return mlx4_cmd(dev
, config
, in_mod
, 0x1, MLX4_CMD_MOD_STAT_CFG
,
1696 MLX4_CMD_TIME_CLASS_A
, MLX4_CMD_NATIVE
);
1698 EXPORT_SYMBOL_GPL(mlx4_wol_write
);