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drivers/net: Add module.h to drivers who were implicitly using it
[deliverable/linux.git] / drivers / net / ethernet / mellanox / mlx4 / fw.c
1 /*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35 #include <linux/mlx4/cmd.h>
36 #include <linux/module.h>
37 #include <linux/cache.h>
38
39 #include "fw.h"
40 #include "icm.h"
41
42 enum {
43 MLX4_COMMAND_INTERFACE_MIN_REV = 2,
44 MLX4_COMMAND_INTERFACE_MAX_REV = 3,
45 MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS = 3,
46 };
47
48 extern void __buggy_use_of_MLX4_GET(void);
49 extern void __buggy_use_of_MLX4_PUT(void);
50
51 static int enable_qos;
52 module_param(enable_qos, bool, 0444);
53 MODULE_PARM_DESC(enable_qos, "Enable Quality of Service support in the HCA (default: off)");
54
55 #define MLX4_GET(dest, source, offset) \
56 do { \
57 void *__p = (char *) (source) + (offset); \
58 switch (sizeof (dest)) { \
59 case 1: (dest) = *(u8 *) __p; break; \
60 case 2: (dest) = be16_to_cpup(__p); break; \
61 case 4: (dest) = be32_to_cpup(__p); break; \
62 case 8: (dest) = be64_to_cpup(__p); break; \
63 default: __buggy_use_of_MLX4_GET(); \
64 } \
65 } while (0)
66
67 #define MLX4_PUT(dest, source, offset) \
68 do { \
69 void *__d = ((char *) (dest) + (offset)); \
70 switch (sizeof(source)) { \
71 case 1: *(u8 *) __d = (source); break; \
72 case 2: *(__be16 *) __d = cpu_to_be16(source); break; \
73 case 4: *(__be32 *) __d = cpu_to_be32(source); break; \
74 case 8: *(__be64 *) __d = cpu_to_be64(source); break; \
75 default: __buggy_use_of_MLX4_PUT(); \
76 } \
77 } while (0)
78
79 static void dump_dev_cap_flags(struct mlx4_dev *dev, u64 flags)
80 {
81 static const char *fname[] = {
82 [ 0] = "RC transport",
83 [ 1] = "UC transport",
84 [ 2] = "UD transport",
85 [ 3] = "XRC transport",
86 [ 4] = "reliable multicast",
87 [ 5] = "FCoIB support",
88 [ 6] = "SRQ support",
89 [ 7] = "IPoIB checksum offload",
90 [ 8] = "P_Key violation counter",
91 [ 9] = "Q_Key violation counter",
92 [10] = "VMM",
93 [12] = "DPDP",
94 [15] = "Big LSO headers",
95 [16] = "MW support",
96 [17] = "APM support",
97 [18] = "Atomic ops support",
98 [19] = "Raw multicast support",
99 [20] = "Address vector port checking support",
100 [21] = "UD multicast support",
101 [24] = "Demand paging support",
102 [25] = "Router support",
103 [30] = "IBoE support",
104 [32] = "Unicast loopback support",
105 [34] = "FCS header control",
106 [38] = "Wake On LAN support",
107 [40] = "UDP RSS support",
108 [41] = "Unicast VEP steering support",
109 [42] = "Multicast VEP steering support",
110 [48] = "Counters support",
111 };
112 int i;
113
114 mlx4_dbg(dev, "DEV_CAP flags:\n");
115 for (i = 0; i < ARRAY_SIZE(fname); ++i)
116 if (fname[i] && (flags & (1LL << i)))
117 mlx4_dbg(dev, " %s\n", fname[i]);
118 }
119
120 int mlx4_MOD_STAT_CFG(struct mlx4_dev *dev, struct mlx4_mod_stat_cfg *cfg)
121 {
122 struct mlx4_cmd_mailbox *mailbox;
123 u32 *inbox;
124 int err = 0;
125
126 #define MOD_STAT_CFG_IN_SIZE 0x100
127
128 #define MOD_STAT_CFG_PG_SZ_M_OFFSET 0x002
129 #define MOD_STAT_CFG_PG_SZ_OFFSET 0x003
130
131 mailbox = mlx4_alloc_cmd_mailbox(dev);
132 if (IS_ERR(mailbox))
133 return PTR_ERR(mailbox);
134 inbox = mailbox->buf;
135
136 memset(inbox, 0, MOD_STAT_CFG_IN_SIZE);
137
138 MLX4_PUT(inbox, cfg->log_pg_sz, MOD_STAT_CFG_PG_SZ_OFFSET);
139 MLX4_PUT(inbox, cfg->log_pg_sz_m, MOD_STAT_CFG_PG_SZ_M_OFFSET);
140
141 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_MOD_STAT_CFG,
142 MLX4_CMD_TIME_CLASS_A);
143
144 mlx4_free_cmd_mailbox(dev, mailbox);
145 return err;
146 }
147
148 int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
149 {
150 struct mlx4_cmd_mailbox *mailbox;
151 u32 *outbox;
152 u8 field;
153 u32 field32, flags, ext_flags;
154 u16 size;
155 u16 stat_rate;
156 int err;
157 int i;
158
159 #define QUERY_DEV_CAP_OUT_SIZE 0x100
160 #define QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET 0x10
161 #define QUERY_DEV_CAP_MAX_QP_SZ_OFFSET 0x11
162 #define QUERY_DEV_CAP_RSVD_QP_OFFSET 0x12
163 #define QUERY_DEV_CAP_MAX_QP_OFFSET 0x13
164 #define QUERY_DEV_CAP_RSVD_SRQ_OFFSET 0x14
165 #define QUERY_DEV_CAP_MAX_SRQ_OFFSET 0x15
166 #define QUERY_DEV_CAP_RSVD_EEC_OFFSET 0x16
167 #define QUERY_DEV_CAP_MAX_EEC_OFFSET 0x17
168 #define QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET 0x19
169 #define QUERY_DEV_CAP_RSVD_CQ_OFFSET 0x1a
170 #define QUERY_DEV_CAP_MAX_CQ_OFFSET 0x1b
171 #define QUERY_DEV_CAP_MAX_MPT_OFFSET 0x1d
172 #define QUERY_DEV_CAP_RSVD_EQ_OFFSET 0x1e
173 #define QUERY_DEV_CAP_MAX_EQ_OFFSET 0x1f
174 #define QUERY_DEV_CAP_RSVD_MTT_OFFSET 0x20
175 #define QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET 0x21
176 #define QUERY_DEV_CAP_RSVD_MRW_OFFSET 0x22
177 #define QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET 0x23
178 #define QUERY_DEV_CAP_MAX_AV_OFFSET 0x27
179 #define QUERY_DEV_CAP_MAX_REQ_QP_OFFSET 0x29
180 #define QUERY_DEV_CAP_MAX_RES_QP_OFFSET 0x2b
181 #define QUERY_DEV_CAP_MAX_GSO_OFFSET 0x2d
182 #define QUERY_DEV_CAP_MAX_RDMA_OFFSET 0x2f
183 #define QUERY_DEV_CAP_RSZ_SRQ_OFFSET 0x33
184 #define QUERY_DEV_CAP_ACK_DELAY_OFFSET 0x35
185 #define QUERY_DEV_CAP_MTU_WIDTH_OFFSET 0x36
186 #define QUERY_DEV_CAP_VL_PORT_OFFSET 0x37
187 #define QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET 0x38
188 #define QUERY_DEV_CAP_MAX_GID_OFFSET 0x3b
189 #define QUERY_DEV_CAP_RATE_SUPPORT_OFFSET 0x3c
190 #define QUERY_DEV_CAP_MAX_PKEY_OFFSET 0x3f
191 #define QUERY_DEV_CAP_EXT_FLAGS_OFFSET 0x40
192 #define QUERY_DEV_CAP_FLAGS_OFFSET 0x44
193 #define QUERY_DEV_CAP_RSVD_UAR_OFFSET 0x48
194 #define QUERY_DEV_CAP_UAR_SZ_OFFSET 0x49
195 #define QUERY_DEV_CAP_PAGE_SZ_OFFSET 0x4b
196 #define QUERY_DEV_CAP_BF_OFFSET 0x4c
197 #define QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET 0x4d
198 #define QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET 0x4e
199 #define QUERY_DEV_CAP_LOG_MAX_BF_PAGES_OFFSET 0x4f
200 #define QUERY_DEV_CAP_MAX_SG_SQ_OFFSET 0x51
201 #define QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET 0x52
202 #define QUERY_DEV_CAP_MAX_SG_RQ_OFFSET 0x55
203 #define QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET 0x56
204 #define QUERY_DEV_CAP_MAX_QP_MCG_OFFSET 0x61
205 #define QUERY_DEV_CAP_RSVD_MCG_OFFSET 0x62
206 #define QUERY_DEV_CAP_MAX_MCG_OFFSET 0x63
207 #define QUERY_DEV_CAP_RSVD_PD_OFFSET 0x64
208 #define QUERY_DEV_CAP_MAX_PD_OFFSET 0x65
209 #define QUERY_DEV_CAP_MAX_COUNTERS_OFFSET 0x68
210 #define QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET 0x80
211 #define QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET 0x82
212 #define QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET 0x84
213 #define QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET 0x86
214 #define QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET 0x88
215 #define QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET 0x8a
216 #define QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET 0x8c
217 #define QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET 0x8e
218 #define QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET 0x90
219 #define QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET 0x92
220 #define QUERY_DEV_CAP_BMME_FLAGS_OFFSET 0x94
221 #define QUERY_DEV_CAP_RSVD_LKEY_OFFSET 0x98
222 #define QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET 0xa0
223
224 mailbox = mlx4_alloc_cmd_mailbox(dev);
225 if (IS_ERR(mailbox))
226 return PTR_ERR(mailbox);
227 outbox = mailbox->buf;
228
229 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP,
230 MLX4_CMD_TIME_CLASS_A);
231 if (err)
232 goto out;
233
234 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_QP_OFFSET);
235 dev_cap->reserved_qps = 1 << (field & 0xf);
236 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_OFFSET);
237 dev_cap->max_qps = 1 << (field & 0x1f);
238 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_SRQ_OFFSET);
239 dev_cap->reserved_srqs = 1 << (field >> 4);
240 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_OFFSET);
241 dev_cap->max_srqs = 1 << (field & 0x1f);
242 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET);
243 dev_cap->max_cq_sz = 1 << field;
244 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_CQ_OFFSET);
245 dev_cap->reserved_cqs = 1 << (field & 0xf);
246 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_OFFSET);
247 dev_cap->max_cqs = 1 << (field & 0x1f);
248 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MPT_OFFSET);
249 dev_cap->max_mpts = 1 << (field & 0x3f);
250 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_EQ_OFFSET);
251 dev_cap->reserved_eqs = field & 0xf;
252 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_EQ_OFFSET);
253 dev_cap->max_eqs = 1 << (field & 0xf);
254 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MTT_OFFSET);
255 dev_cap->reserved_mtts = 1 << (field >> 4);
256 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET);
257 dev_cap->max_mrw_sz = 1 << field;
258 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MRW_OFFSET);
259 dev_cap->reserved_mrws = 1 << (field & 0xf);
260 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET);
261 dev_cap->max_mtt_seg = 1 << (field & 0x3f);
262 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_REQ_QP_OFFSET);
263 dev_cap->max_requester_per_qp = 1 << (field & 0x3f);
264 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RES_QP_OFFSET);
265 dev_cap->max_responder_per_qp = 1 << (field & 0x3f);
266 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GSO_OFFSET);
267 field &= 0x1f;
268 if (!field)
269 dev_cap->max_gso_sz = 0;
270 else
271 dev_cap->max_gso_sz = 1 << field;
272
273 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RDMA_OFFSET);
274 dev_cap->max_rdma_global = 1 << (field & 0x3f);
275 MLX4_GET(field, outbox, QUERY_DEV_CAP_ACK_DELAY_OFFSET);
276 dev_cap->local_ca_ack_delay = field & 0x1f;
277 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET);
278 dev_cap->num_ports = field & 0xf;
279 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET);
280 dev_cap->max_msg_sz = 1 << (field & 0x1f);
281 MLX4_GET(stat_rate, outbox, QUERY_DEV_CAP_RATE_SUPPORT_OFFSET);
282 dev_cap->stat_rate_support = stat_rate;
283 MLX4_GET(ext_flags, outbox, QUERY_DEV_CAP_EXT_FLAGS_OFFSET);
284 MLX4_GET(flags, outbox, QUERY_DEV_CAP_FLAGS_OFFSET);
285 dev_cap->flags = flags | (u64)ext_flags << 32;
286 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_UAR_OFFSET);
287 dev_cap->reserved_uars = field >> 4;
288 MLX4_GET(field, outbox, QUERY_DEV_CAP_UAR_SZ_OFFSET);
289 dev_cap->uar_size = 1 << ((field & 0x3f) + 20);
290 MLX4_GET(field, outbox, QUERY_DEV_CAP_PAGE_SZ_OFFSET);
291 dev_cap->min_page_sz = 1 << field;
292
293 MLX4_GET(field, outbox, QUERY_DEV_CAP_BF_OFFSET);
294 if (field & 0x80) {
295 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET);
296 dev_cap->bf_reg_size = 1 << (field & 0x1f);
297 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET);
298 if ((1 << (field & 0x3f)) > (PAGE_SIZE / dev_cap->bf_reg_size))
299 field = 3;
300 dev_cap->bf_regs_per_page = 1 << (field & 0x3f);
301 mlx4_dbg(dev, "BlueFlame available (reg size %d, regs/page %d)\n",
302 dev_cap->bf_reg_size, dev_cap->bf_regs_per_page);
303 } else {
304 dev_cap->bf_reg_size = 0;
305 mlx4_dbg(dev, "BlueFlame not available\n");
306 }
307
308 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_SQ_OFFSET);
309 dev_cap->max_sq_sg = field;
310 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET);
311 dev_cap->max_sq_desc_sz = size;
312
313 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_MCG_OFFSET);
314 dev_cap->max_qp_per_mcg = 1 << field;
315 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MCG_OFFSET);
316 dev_cap->reserved_mgms = field & 0xf;
317 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MCG_OFFSET);
318 dev_cap->max_mcgs = 1 << field;
319 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_PD_OFFSET);
320 dev_cap->reserved_pds = field >> 4;
321 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PD_OFFSET);
322 dev_cap->max_pds = 1 << (field & 0x3f);
323
324 MLX4_GET(size, outbox, QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET);
325 dev_cap->rdmarc_entry_sz = size;
326 MLX4_GET(size, outbox, QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET);
327 dev_cap->qpc_entry_sz = size;
328 MLX4_GET(size, outbox, QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET);
329 dev_cap->aux_entry_sz = size;
330 MLX4_GET(size, outbox, QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET);
331 dev_cap->altc_entry_sz = size;
332 MLX4_GET(size, outbox, QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET);
333 dev_cap->eqc_entry_sz = size;
334 MLX4_GET(size, outbox, QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET);
335 dev_cap->cqc_entry_sz = size;
336 MLX4_GET(size, outbox, QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET);
337 dev_cap->srq_entry_sz = size;
338 MLX4_GET(size, outbox, QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET);
339 dev_cap->cmpt_entry_sz = size;
340 MLX4_GET(size, outbox, QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET);
341 dev_cap->mtt_entry_sz = size;
342 MLX4_GET(size, outbox, QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET);
343 dev_cap->dmpt_entry_sz = size;
344
345 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET);
346 dev_cap->max_srq_sz = 1 << field;
347 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_SZ_OFFSET);
348 dev_cap->max_qp_sz = 1 << field;
349 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSZ_SRQ_OFFSET);
350 dev_cap->resize_srq = field & 1;
351 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_RQ_OFFSET);
352 dev_cap->max_rq_sg = field;
353 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET);
354 dev_cap->max_rq_desc_sz = size;
355
356 MLX4_GET(dev_cap->bmme_flags, outbox,
357 QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
358 MLX4_GET(dev_cap->reserved_lkey, outbox,
359 QUERY_DEV_CAP_RSVD_LKEY_OFFSET);
360 MLX4_GET(dev_cap->max_icm_sz, outbox,
361 QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET);
362 if (dev_cap->flags & MLX4_DEV_CAP_FLAG_COUNTERS)
363 MLX4_GET(dev_cap->max_counters, outbox,
364 QUERY_DEV_CAP_MAX_COUNTERS_OFFSET);
365
366 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
367 for (i = 1; i <= dev_cap->num_ports; ++i) {
368 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET);
369 dev_cap->max_vl[i] = field >> 4;
370 MLX4_GET(field, outbox, QUERY_DEV_CAP_MTU_WIDTH_OFFSET);
371 dev_cap->ib_mtu[i] = field >> 4;
372 dev_cap->max_port_width[i] = field & 0xf;
373 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GID_OFFSET);
374 dev_cap->max_gids[i] = 1 << (field & 0xf);
375 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PKEY_OFFSET);
376 dev_cap->max_pkeys[i] = 1 << (field & 0xf);
377 }
378 } else {
379 #define QUERY_PORT_SUPPORTED_TYPE_OFFSET 0x00
380 #define QUERY_PORT_MTU_OFFSET 0x01
381 #define QUERY_PORT_ETH_MTU_OFFSET 0x02
382 #define QUERY_PORT_WIDTH_OFFSET 0x06
383 #define QUERY_PORT_MAX_GID_PKEY_OFFSET 0x07
384 #define QUERY_PORT_MAX_MACVLAN_OFFSET 0x0a
385 #define QUERY_PORT_MAX_VL_OFFSET 0x0b
386 #define QUERY_PORT_MAC_OFFSET 0x10
387 #define QUERY_PORT_TRANS_VENDOR_OFFSET 0x18
388 #define QUERY_PORT_WAVELENGTH_OFFSET 0x1c
389 #define QUERY_PORT_TRANS_CODE_OFFSET 0x20
390
391 for (i = 1; i <= dev_cap->num_ports; ++i) {
392 err = mlx4_cmd_box(dev, 0, mailbox->dma, i, 0, MLX4_CMD_QUERY_PORT,
393 MLX4_CMD_TIME_CLASS_B);
394 if (err)
395 goto out;
396
397 MLX4_GET(field, outbox, QUERY_PORT_SUPPORTED_TYPE_OFFSET);
398 dev_cap->supported_port_types[i] = field & 3;
399 MLX4_GET(field, outbox, QUERY_PORT_MTU_OFFSET);
400 dev_cap->ib_mtu[i] = field & 0xf;
401 MLX4_GET(field, outbox, QUERY_PORT_WIDTH_OFFSET);
402 dev_cap->max_port_width[i] = field & 0xf;
403 MLX4_GET(field, outbox, QUERY_PORT_MAX_GID_PKEY_OFFSET);
404 dev_cap->max_gids[i] = 1 << (field >> 4);
405 dev_cap->max_pkeys[i] = 1 << (field & 0xf);
406 MLX4_GET(field, outbox, QUERY_PORT_MAX_VL_OFFSET);
407 dev_cap->max_vl[i] = field & 0xf;
408 MLX4_GET(field, outbox, QUERY_PORT_MAX_MACVLAN_OFFSET);
409 dev_cap->log_max_macs[i] = field & 0xf;
410 dev_cap->log_max_vlans[i] = field >> 4;
411 MLX4_GET(dev_cap->eth_mtu[i], outbox, QUERY_PORT_ETH_MTU_OFFSET);
412 MLX4_GET(dev_cap->def_mac[i], outbox, QUERY_PORT_MAC_OFFSET);
413 MLX4_GET(field32, outbox, QUERY_PORT_TRANS_VENDOR_OFFSET);
414 dev_cap->trans_type[i] = field32 >> 24;
415 dev_cap->vendor_oui[i] = field32 & 0xffffff;
416 MLX4_GET(dev_cap->wavelength[i], outbox, QUERY_PORT_WAVELENGTH_OFFSET);
417 MLX4_GET(dev_cap->trans_code[i], outbox, QUERY_PORT_TRANS_CODE_OFFSET);
418 }
419 }
420
421 mlx4_dbg(dev, "Base MM extensions: flags %08x, rsvd L_Key %08x\n",
422 dev_cap->bmme_flags, dev_cap->reserved_lkey);
423
424 /*
425 * Each UAR has 4 EQ doorbells; so if a UAR is reserved, then
426 * we can't use any EQs whose doorbell falls on that page,
427 * even if the EQ itself isn't reserved.
428 */
429 dev_cap->reserved_eqs = max(dev_cap->reserved_uars * 4,
430 dev_cap->reserved_eqs);
431
432 mlx4_dbg(dev, "Max ICM size %lld MB\n",
433 (unsigned long long) dev_cap->max_icm_sz >> 20);
434 mlx4_dbg(dev, "Max QPs: %d, reserved QPs: %d, entry size: %d\n",
435 dev_cap->max_qps, dev_cap->reserved_qps, dev_cap->qpc_entry_sz);
436 mlx4_dbg(dev, "Max SRQs: %d, reserved SRQs: %d, entry size: %d\n",
437 dev_cap->max_srqs, dev_cap->reserved_srqs, dev_cap->srq_entry_sz);
438 mlx4_dbg(dev, "Max CQs: %d, reserved CQs: %d, entry size: %d\n",
439 dev_cap->max_cqs, dev_cap->reserved_cqs, dev_cap->cqc_entry_sz);
440 mlx4_dbg(dev, "Max EQs: %d, reserved EQs: %d, entry size: %d\n",
441 dev_cap->max_eqs, dev_cap->reserved_eqs, dev_cap->eqc_entry_sz);
442 mlx4_dbg(dev, "reserved MPTs: %d, reserved MTTs: %d\n",
443 dev_cap->reserved_mrws, dev_cap->reserved_mtts);
444 mlx4_dbg(dev, "Max PDs: %d, reserved PDs: %d, reserved UARs: %d\n",
445 dev_cap->max_pds, dev_cap->reserved_pds, dev_cap->reserved_uars);
446 mlx4_dbg(dev, "Max QP/MCG: %d, reserved MGMs: %d\n",
447 dev_cap->max_pds, dev_cap->reserved_mgms);
448 mlx4_dbg(dev, "Max CQEs: %d, max WQEs: %d, max SRQ WQEs: %d\n",
449 dev_cap->max_cq_sz, dev_cap->max_qp_sz, dev_cap->max_srq_sz);
450 mlx4_dbg(dev, "Local CA ACK delay: %d, max MTU: %d, port width cap: %d\n",
451 dev_cap->local_ca_ack_delay, 128 << dev_cap->ib_mtu[1],
452 dev_cap->max_port_width[1]);
453 mlx4_dbg(dev, "Max SQ desc size: %d, max SQ S/G: %d\n",
454 dev_cap->max_sq_desc_sz, dev_cap->max_sq_sg);
455 mlx4_dbg(dev, "Max RQ desc size: %d, max RQ S/G: %d\n",
456 dev_cap->max_rq_desc_sz, dev_cap->max_rq_sg);
457 mlx4_dbg(dev, "Max GSO size: %d\n", dev_cap->max_gso_sz);
458 mlx4_dbg(dev, "Max counters: %d\n", dev_cap->max_counters);
459
460 dump_dev_cap_flags(dev, dev_cap->flags);
461
462 out:
463 mlx4_free_cmd_mailbox(dev, mailbox);
464 return err;
465 }
466
467 int mlx4_map_cmd(struct mlx4_dev *dev, u16 op, struct mlx4_icm *icm, u64 virt)
468 {
469 struct mlx4_cmd_mailbox *mailbox;
470 struct mlx4_icm_iter iter;
471 __be64 *pages;
472 int lg;
473 int nent = 0;
474 int i;
475 int err = 0;
476 int ts = 0, tc = 0;
477
478 mailbox = mlx4_alloc_cmd_mailbox(dev);
479 if (IS_ERR(mailbox))
480 return PTR_ERR(mailbox);
481 memset(mailbox->buf, 0, MLX4_MAILBOX_SIZE);
482 pages = mailbox->buf;
483
484 for (mlx4_icm_first(icm, &iter);
485 !mlx4_icm_last(&iter);
486 mlx4_icm_next(&iter)) {
487 /*
488 * We have to pass pages that are aligned to their
489 * size, so find the least significant 1 in the
490 * address or size and use that as our log2 size.
491 */
492 lg = ffs(mlx4_icm_addr(&iter) | mlx4_icm_size(&iter)) - 1;
493 if (lg < MLX4_ICM_PAGE_SHIFT) {
494 mlx4_warn(dev, "Got FW area not aligned to %d (%llx/%lx).\n",
495 MLX4_ICM_PAGE_SIZE,
496 (unsigned long long) mlx4_icm_addr(&iter),
497 mlx4_icm_size(&iter));
498 err = -EINVAL;
499 goto out;
500 }
501
502 for (i = 0; i < mlx4_icm_size(&iter) >> lg; ++i) {
503 if (virt != -1) {
504 pages[nent * 2] = cpu_to_be64(virt);
505 virt += 1 << lg;
506 }
507
508 pages[nent * 2 + 1] =
509 cpu_to_be64((mlx4_icm_addr(&iter) + (i << lg)) |
510 (lg - MLX4_ICM_PAGE_SHIFT));
511 ts += 1 << (lg - 10);
512 ++tc;
513
514 if (++nent == MLX4_MAILBOX_SIZE / 16) {
515 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op,
516 MLX4_CMD_TIME_CLASS_B);
517 if (err)
518 goto out;
519 nent = 0;
520 }
521 }
522 }
523
524 if (nent)
525 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op, MLX4_CMD_TIME_CLASS_B);
526 if (err)
527 goto out;
528
529 switch (op) {
530 case MLX4_CMD_MAP_FA:
531 mlx4_dbg(dev, "Mapped %d chunks/%d KB for FW.\n", tc, ts);
532 break;
533 case MLX4_CMD_MAP_ICM_AUX:
534 mlx4_dbg(dev, "Mapped %d chunks/%d KB for ICM aux.\n", tc, ts);
535 break;
536 case MLX4_CMD_MAP_ICM:
537 mlx4_dbg(dev, "Mapped %d chunks/%d KB at %llx for ICM.\n",
538 tc, ts, (unsigned long long) virt - (ts << 10));
539 break;
540 }
541
542 out:
543 mlx4_free_cmd_mailbox(dev, mailbox);
544 return err;
545 }
546
547 int mlx4_MAP_FA(struct mlx4_dev *dev, struct mlx4_icm *icm)
548 {
549 return mlx4_map_cmd(dev, MLX4_CMD_MAP_FA, icm, -1);
550 }
551
552 int mlx4_UNMAP_FA(struct mlx4_dev *dev)
553 {
554 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_UNMAP_FA, MLX4_CMD_TIME_CLASS_B);
555 }
556
557
558 int mlx4_RUN_FW(struct mlx4_dev *dev)
559 {
560 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_RUN_FW, MLX4_CMD_TIME_CLASS_A);
561 }
562
563 int mlx4_QUERY_FW(struct mlx4_dev *dev)
564 {
565 struct mlx4_fw *fw = &mlx4_priv(dev)->fw;
566 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
567 struct mlx4_cmd_mailbox *mailbox;
568 u32 *outbox;
569 int err = 0;
570 u64 fw_ver;
571 u16 cmd_if_rev;
572 u8 lg;
573
574 #define QUERY_FW_OUT_SIZE 0x100
575 #define QUERY_FW_VER_OFFSET 0x00
576 #define QUERY_FW_CMD_IF_REV_OFFSET 0x0a
577 #define QUERY_FW_MAX_CMD_OFFSET 0x0f
578 #define QUERY_FW_ERR_START_OFFSET 0x30
579 #define QUERY_FW_ERR_SIZE_OFFSET 0x38
580 #define QUERY_FW_ERR_BAR_OFFSET 0x3c
581
582 #define QUERY_FW_SIZE_OFFSET 0x00
583 #define QUERY_FW_CLR_INT_BASE_OFFSET 0x20
584 #define QUERY_FW_CLR_INT_BAR_OFFSET 0x28
585
586 mailbox = mlx4_alloc_cmd_mailbox(dev);
587 if (IS_ERR(mailbox))
588 return PTR_ERR(mailbox);
589 outbox = mailbox->buf;
590
591 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_FW,
592 MLX4_CMD_TIME_CLASS_A);
593 if (err)
594 goto out;
595
596 MLX4_GET(fw_ver, outbox, QUERY_FW_VER_OFFSET);
597 /*
598 * FW subminor version is at more significant bits than minor
599 * version, so swap here.
600 */
601 dev->caps.fw_ver = (fw_ver & 0xffff00000000ull) |
602 ((fw_ver & 0xffff0000ull) >> 16) |
603 ((fw_ver & 0x0000ffffull) << 16);
604
605 MLX4_GET(cmd_if_rev, outbox, QUERY_FW_CMD_IF_REV_OFFSET);
606 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_MIN_REV ||
607 cmd_if_rev > MLX4_COMMAND_INTERFACE_MAX_REV) {
608 mlx4_err(dev, "Installed FW has unsupported "
609 "command interface revision %d.\n",
610 cmd_if_rev);
611 mlx4_err(dev, "(Installed FW version is %d.%d.%03d)\n",
612 (int) (dev->caps.fw_ver >> 32),
613 (int) (dev->caps.fw_ver >> 16) & 0xffff,
614 (int) dev->caps.fw_ver & 0xffff);
615 mlx4_err(dev, "This driver version supports only revisions %d to %d.\n",
616 MLX4_COMMAND_INTERFACE_MIN_REV, MLX4_COMMAND_INTERFACE_MAX_REV);
617 err = -ENODEV;
618 goto out;
619 }
620
621 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS)
622 dev->flags |= MLX4_FLAG_OLD_PORT_CMDS;
623
624 MLX4_GET(lg, outbox, QUERY_FW_MAX_CMD_OFFSET);
625 cmd->max_cmds = 1 << lg;
626
627 mlx4_dbg(dev, "FW version %d.%d.%03d (cmd intf rev %d), max commands %d\n",
628 (int) (dev->caps.fw_ver >> 32),
629 (int) (dev->caps.fw_ver >> 16) & 0xffff,
630 (int) dev->caps.fw_ver & 0xffff,
631 cmd_if_rev, cmd->max_cmds);
632
633 MLX4_GET(fw->catas_offset, outbox, QUERY_FW_ERR_START_OFFSET);
634 MLX4_GET(fw->catas_size, outbox, QUERY_FW_ERR_SIZE_OFFSET);
635 MLX4_GET(fw->catas_bar, outbox, QUERY_FW_ERR_BAR_OFFSET);
636 fw->catas_bar = (fw->catas_bar >> 6) * 2;
637
638 mlx4_dbg(dev, "Catastrophic error buffer at 0x%llx, size 0x%x, BAR %d\n",
639 (unsigned long long) fw->catas_offset, fw->catas_size, fw->catas_bar);
640
641 MLX4_GET(fw->fw_pages, outbox, QUERY_FW_SIZE_OFFSET);
642 MLX4_GET(fw->clr_int_base, outbox, QUERY_FW_CLR_INT_BASE_OFFSET);
643 MLX4_GET(fw->clr_int_bar, outbox, QUERY_FW_CLR_INT_BAR_OFFSET);
644 fw->clr_int_bar = (fw->clr_int_bar >> 6) * 2;
645
646 mlx4_dbg(dev, "FW size %d KB\n", fw->fw_pages >> 2);
647
648 /*
649 * Round up number of system pages needed in case
650 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE.
651 */
652 fw->fw_pages =
653 ALIGN(fw->fw_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >>
654 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT);
655
656 mlx4_dbg(dev, "Clear int @ %llx, BAR %d\n",
657 (unsigned long long) fw->clr_int_base, fw->clr_int_bar);
658
659 out:
660 mlx4_free_cmd_mailbox(dev, mailbox);
661 return err;
662 }
663
664 static void get_board_id(void *vsd, char *board_id)
665 {
666 int i;
667
668 #define VSD_OFFSET_SIG1 0x00
669 #define VSD_OFFSET_SIG2 0xde
670 #define VSD_OFFSET_MLX_BOARD_ID 0xd0
671 #define VSD_OFFSET_TS_BOARD_ID 0x20
672
673 #define VSD_SIGNATURE_TOPSPIN 0x5ad
674
675 memset(board_id, 0, MLX4_BOARD_ID_LEN);
676
677 if (be16_to_cpup(vsd + VSD_OFFSET_SIG1) == VSD_SIGNATURE_TOPSPIN &&
678 be16_to_cpup(vsd + VSD_OFFSET_SIG2) == VSD_SIGNATURE_TOPSPIN) {
679 strlcpy(board_id, vsd + VSD_OFFSET_TS_BOARD_ID, MLX4_BOARD_ID_LEN);
680 } else {
681 /*
682 * The board ID is a string but the firmware byte
683 * swaps each 4-byte word before passing it back to
684 * us. Therefore we need to swab it before printing.
685 */
686 for (i = 0; i < 4; ++i)
687 ((u32 *) board_id)[i] =
688 swab32(*(u32 *) (vsd + VSD_OFFSET_MLX_BOARD_ID + i * 4));
689 }
690 }
691
692 int mlx4_QUERY_ADAPTER(struct mlx4_dev *dev, struct mlx4_adapter *adapter)
693 {
694 struct mlx4_cmd_mailbox *mailbox;
695 u32 *outbox;
696 int err;
697
698 #define QUERY_ADAPTER_OUT_SIZE 0x100
699 #define QUERY_ADAPTER_INTA_PIN_OFFSET 0x10
700 #define QUERY_ADAPTER_VSD_OFFSET 0x20
701
702 mailbox = mlx4_alloc_cmd_mailbox(dev);
703 if (IS_ERR(mailbox))
704 return PTR_ERR(mailbox);
705 outbox = mailbox->buf;
706
707 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_ADAPTER,
708 MLX4_CMD_TIME_CLASS_A);
709 if (err)
710 goto out;
711
712 MLX4_GET(adapter->inta_pin, outbox, QUERY_ADAPTER_INTA_PIN_OFFSET);
713
714 get_board_id(outbox + QUERY_ADAPTER_VSD_OFFSET / 4,
715 adapter->board_id);
716
717 out:
718 mlx4_free_cmd_mailbox(dev, mailbox);
719 return err;
720 }
721
722 int mlx4_INIT_HCA(struct mlx4_dev *dev, struct mlx4_init_hca_param *param)
723 {
724 struct mlx4_cmd_mailbox *mailbox;
725 __be32 *inbox;
726 int err;
727
728 #define INIT_HCA_IN_SIZE 0x200
729 #define INIT_HCA_VERSION_OFFSET 0x000
730 #define INIT_HCA_VERSION 2
731 #define INIT_HCA_CACHELINE_SZ_OFFSET 0x0e
732 #define INIT_HCA_FLAGS_OFFSET 0x014
733 #define INIT_HCA_QPC_OFFSET 0x020
734 #define INIT_HCA_QPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x10)
735 #define INIT_HCA_LOG_QP_OFFSET (INIT_HCA_QPC_OFFSET + 0x17)
736 #define INIT_HCA_SRQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x28)
737 #define INIT_HCA_LOG_SRQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x2f)
738 #define INIT_HCA_CQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x30)
739 #define INIT_HCA_LOG_CQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x37)
740 #define INIT_HCA_ALTC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x40)
741 #define INIT_HCA_AUXC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x50)
742 #define INIT_HCA_EQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x60)
743 #define INIT_HCA_LOG_EQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x67)
744 #define INIT_HCA_RDMARC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x70)
745 #define INIT_HCA_LOG_RD_OFFSET (INIT_HCA_QPC_OFFSET + 0x77)
746 #define INIT_HCA_MCAST_OFFSET 0x0c0
747 #define INIT_HCA_MC_BASE_OFFSET (INIT_HCA_MCAST_OFFSET + 0x00)
748 #define INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x12)
749 #define INIT_HCA_LOG_MC_HASH_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x16)
750 #define INIT_HCA_UC_STEERING_OFFSET (INIT_HCA_MCAST_OFFSET + 0x18)
751 #define INIT_HCA_LOG_MC_TABLE_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x1b)
752 #define INIT_HCA_TPT_OFFSET 0x0f0
753 #define INIT_HCA_DMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x00)
754 #define INIT_HCA_LOG_MPT_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x0b)
755 #define INIT_HCA_MTT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x10)
756 #define INIT_HCA_CMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x18)
757 #define INIT_HCA_UAR_OFFSET 0x120
758 #define INIT_HCA_LOG_UAR_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0a)
759 #define INIT_HCA_UAR_PAGE_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0b)
760
761 mailbox = mlx4_alloc_cmd_mailbox(dev);
762 if (IS_ERR(mailbox))
763 return PTR_ERR(mailbox);
764 inbox = mailbox->buf;
765
766 memset(inbox, 0, INIT_HCA_IN_SIZE);
767
768 *((u8 *) mailbox->buf + INIT_HCA_VERSION_OFFSET) = INIT_HCA_VERSION;
769
770 *((u8 *) mailbox->buf + INIT_HCA_CACHELINE_SZ_OFFSET) =
771 (ilog2(cache_line_size()) - 4) << 5;
772
773 #if defined(__LITTLE_ENDIAN)
774 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) &= ~cpu_to_be32(1 << 1);
775 #elif defined(__BIG_ENDIAN)
776 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 1);
777 #else
778 #error Host endianness not defined
779 #endif
780 /* Check port for UD address vector: */
781 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1);
782
783 /* Enable IPoIB checksumming if we can: */
784 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_IPOIB_CSUM)
785 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 3);
786
787 /* Enable QoS support if module parameter set */
788 if (enable_qos)
789 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 2);
790
791 /* enable counters */
792 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS)
793 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 4);
794
795 /* QPC/EEC/CQC/EQC/RDMARC attributes */
796
797 MLX4_PUT(inbox, param->qpc_base, INIT_HCA_QPC_BASE_OFFSET);
798 MLX4_PUT(inbox, param->log_num_qps, INIT_HCA_LOG_QP_OFFSET);
799 MLX4_PUT(inbox, param->srqc_base, INIT_HCA_SRQC_BASE_OFFSET);
800 MLX4_PUT(inbox, param->log_num_srqs, INIT_HCA_LOG_SRQ_OFFSET);
801 MLX4_PUT(inbox, param->cqc_base, INIT_HCA_CQC_BASE_OFFSET);
802 MLX4_PUT(inbox, param->log_num_cqs, INIT_HCA_LOG_CQ_OFFSET);
803 MLX4_PUT(inbox, param->altc_base, INIT_HCA_ALTC_BASE_OFFSET);
804 MLX4_PUT(inbox, param->auxc_base, INIT_HCA_AUXC_BASE_OFFSET);
805 MLX4_PUT(inbox, param->eqc_base, INIT_HCA_EQC_BASE_OFFSET);
806 MLX4_PUT(inbox, param->log_num_eqs, INIT_HCA_LOG_EQ_OFFSET);
807 MLX4_PUT(inbox, param->rdmarc_base, INIT_HCA_RDMARC_BASE_OFFSET);
808 MLX4_PUT(inbox, param->log_rd_per_qp, INIT_HCA_LOG_RD_OFFSET);
809
810 /* multicast attributes */
811
812 MLX4_PUT(inbox, param->mc_base, INIT_HCA_MC_BASE_OFFSET);
813 MLX4_PUT(inbox, param->log_mc_entry_sz, INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET);
814 MLX4_PUT(inbox, param->log_mc_hash_sz, INIT_HCA_LOG_MC_HASH_SZ_OFFSET);
815 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER)
816 MLX4_PUT(inbox, (u8) (1 << 3), INIT_HCA_UC_STEERING_OFFSET);
817 MLX4_PUT(inbox, param->log_mc_table_sz, INIT_HCA_LOG_MC_TABLE_SZ_OFFSET);
818
819 /* TPT attributes */
820
821 MLX4_PUT(inbox, param->dmpt_base, INIT_HCA_DMPT_BASE_OFFSET);
822 MLX4_PUT(inbox, param->log_mpt_sz, INIT_HCA_LOG_MPT_SZ_OFFSET);
823 MLX4_PUT(inbox, param->mtt_base, INIT_HCA_MTT_BASE_OFFSET);
824 MLX4_PUT(inbox, param->cmpt_base, INIT_HCA_CMPT_BASE_OFFSET);
825
826 /* UAR attributes */
827
828 MLX4_PUT(inbox, (u8) (PAGE_SHIFT - 12), INIT_HCA_UAR_PAGE_SZ_OFFSET);
829 MLX4_PUT(inbox, param->log_uar_sz, INIT_HCA_LOG_UAR_SZ_OFFSET);
830
831 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_INIT_HCA, 10000);
832
833 if (err)
834 mlx4_err(dev, "INIT_HCA returns %d\n", err);
835
836 mlx4_free_cmd_mailbox(dev, mailbox);
837 return err;
838 }
839
840 int mlx4_INIT_PORT(struct mlx4_dev *dev, int port)
841 {
842 struct mlx4_cmd_mailbox *mailbox;
843 u32 *inbox;
844 int err;
845 u32 flags;
846 u16 field;
847
848 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
849 #define INIT_PORT_IN_SIZE 256
850 #define INIT_PORT_FLAGS_OFFSET 0x00
851 #define INIT_PORT_FLAG_SIG (1 << 18)
852 #define INIT_PORT_FLAG_NG (1 << 17)
853 #define INIT_PORT_FLAG_G0 (1 << 16)
854 #define INIT_PORT_VL_SHIFT 4
855 #define INIT_PORT_PORT_WIDTH_SHIFT 8
856 #define INIT_PORT_MTU_OFFSET 0x04
857 #define INIT_PORT_MAX_GID_OFFSET 0x06
858 #define INIT_PORT_MAX_PKEY_OFFSET 0x0a
859 #define INIT_PORT_GUID0_OFFSET 0x10
860 #define INIT_PORT_NODE_GUID_OFFSET 0x18
861 #define INIT_PORT_SI_GUID_OFFSET 0x20
862
863 mailbox = mlx4_alloc_cmd_mailbox(dev);
864 if (IS_ERR(mailbox))
865 return PTR_ERR(mailbox);
866 inbox = mailbox->buf;
867
868 memset(inbox, 0, INIT_PORT_IN_SIZE);
869
870 flags = 0;
871 flags |= (dev->caps.vl_cap[port] & 0xf) << INIT_PORT_VL_SHIFT;
872 flags |= (dev->caps.port_width_cap[port] & 0xf) << INIT_PORT_PORT_WIDTH_SHIFT;
873 MLX4_PUT(inbox, flags, INIT_PORT_FLAGS_OFFSET);
874
875 field = 128 << dev->caps.ib_mtu_cap[port];
876 MLX4_PUT(inbox, field, INIT_PORT_MTU_OFFSET);
877 field = dev->caps.gid_table_len[port];
878 MLX4_PUT(inbox, field, INIT_PORT_MAX_GID_OFFSET);
879 field = dev->caps.pkey_table_len[port];
880 MLX4_PUT(inbox, field, INIT_PORT_MAX_PKEY_OFFSET);
881
882 err = mlx4_cmd(dev, mailbox->dma, port, 0, MLX4_CMD_INIT_PORT,
883 MLX4_CMD_TIME_CLASS_A);
884
885 mlx4_free_cmd_mailbox(dev, mailbox);
886 } else
887 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
888 MLX4_CMD_TIME_CLASS_A);
889
890 return err;
891 }
892 EXPORT_SYMBOL_GPL(mlx4_INIT_PORT);
893
894 int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port)
895 {
896 return mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, 1000);
897 }
898 EXPORT_SYMBOL_GPL(mlx4_CLOSE_PORT);
899
900 int mlx4_CLOSE_HCA(struct mlx4_dev *dev, int panic)
901 {
902 return mlx4_cmd(dev, 0, 0, panic, MLX4_CMD_CLOSE_HCA, 1000);
903 }
904
905 int mlx4_SET_ICM_SIZE(struct mlx4_dev *dev, u64 icm_size, u64 *aux_pages)
906 {
907 int ret = mlx4_cmd_imm(dev, icm_size, aux_pages, 0, 0,
908 MLX4_CMD_SET_ICM_SIZE,
909 MLX4_CMD_TIME_CLASS_A);
910 if (ret)
911 return ret;
912
913 /*
914 * Round up number of system pages needed in case
915 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE.
916 */
917 *aux_pages = ALIGN(*aux_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >>
918 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT);
919
920 return 0;
921 }
922
923 int mlx4_NOP(struct mlx4_dev *dev)
924 {
925 /* Input modifier of 0x1f means "finish as soon as possible." */
926 return mlx4_cmd(dev, 0, 0x1f, 0, MLX4_CMD_NOP, 100);
927 }
928
929 #define MLX4_WOL_SETUP_MODE (5 << 28)
930 int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port)
931 {
932 u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8;
933
934 return mlx4_cmd_imm(dev, 0, config, in_mod, 0x3,
935 MLX4_CMD_MOD_STAT_CFG, MLX4_CMD_TIME_CLASS_A);
936 }
937 EXPORT_SYMBOL_GPL(mlx4_wol_read);
938
939 int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port)
940 {
941 u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8;
942
943 return mlx4_cmd(dev, config, in_mod, 0x1, MLX4_CMD_MOD_STAT_CFG,
944 MLX4_CMD_TIME_CLASS_A);
945 }
946 EXPORT_SYMBOL_GPL(mlx4_wol_write);
Linux kernel - Deliverables
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