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c3e70bc2d8757fb32dee1902bc1433076e771c8f
[deliverable/linux.git] / drivers / net / ethernet / mellanox / mlx4 / fw.c
1 /*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35 #include <linux/etherdevice.h>
36 #include <linux/mlx4/cmd.h>
37 #include <linux/module.h>
38 #include <linux/cache.h>
39
40 #include "fw.h"
41 #include "icm.h"
42
43 enum {
44 MLX4_COMMAND_INTERFACE_MIN_REV = 2,
45 MLX4_COMMAND_INTERFACE_MAX_REV = 3,
46 MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS = 3,
47 };
48
49 extern void __buggy_use_of_MLX4_GET(void);
50 extern void __buggy_use_of_MLX4_PUT(void);
51
52 static bool enable_qos;
53 module_param(enable_qos, bool, 0444);
54 MODULE_PARM_DESC(enable_qos, "Enable Quality of Service support in the HCA (default: off)");
55
56 #define MLX4_GET(dest, source, offset) \
57 do { \
58 void *__p = (char *) (source) + (offset); \
59 switch (sizeof (dest)) { \
60 case 1: (dest) = *(u8 *) __p; break; \
61 case 2: (dest) = be16_to_cpup(__p); break; \
62 case 4: (dest) = be32_to_cpup(__p); break; \
63 case 8: (dest) = be64_to_cpup(__p); break; \
64 default: __buggy_use_of_MLX4_GET(); \
65 } \
66 } while (0)
67
68 #define MLX4_PUT(dest, source, offset) \
69 do { \
70 void *__d = ((char *) (dest) + (offset)); \
71 switch (sizeof(source)) { \
72 case 1: *(u8 *) __d = (source); break; \
73 case 2: *(__be16 *) __d = cpu_to_be16(source); break; \
74 case 4: *(__be32 *) __d = cpu_to_be32(source); break; \
75 case 8: *(__be64 *) __d = cpu_to_be64(source); break; \
76 default: __buggy_use_of_MLX4_PUT(); \
77 } \
78 } while (0)
79
80 static void dump_dev_cap_flags(struct mlx4_dev *dev, u64 flags)
81 {
82 static const char *fname[] = {
83 [ 0] = "RC transport",
84 [ 1] = "UC transport",
85 [ 2] = "UD transport",
86 [ 3] = "XRC transport",
87 [ 4] = "reliable multicast",
88 [ 5] = "FCoIB support",
89 [ 6] = "SRQ support",
90 [ 7] = "IPoIB checksum offload",
91 [ 8] = "P_Key violation counter",
92 [ 9] = "Q_Key violation counter",
93 [10] = "VMM",
94 [12] = "Dual Port Different Protocol (DPDP) support",
95 [15] = "Big LSO headers",
96 [16] = "MW support",
97 [17] = "APM support",
98 [18] = "Atomic ops support",
99 [19] = "Raw multicast support",
100 [20] = "Address vector port checking support",
101 [21] = "UD multicast support",
102 [24] = "Demand paging support",
103 [25] = "Router support",
104 [30] = "IBoE support",
105 [32] = "Unicast loopback support",
106 [34] = "FCS header control",
107 [38] = "Wake On LAN support",
108 [40] = "UDP RSS support",
109 [41] = "Unicast VEP steering support",
110 [42] = "Multicast VEP steering support",
111 [48] = "Counters support",
112 [53] = "Port ETS Scheduler support",
113 [55] = "Port link type sensing support",
114 [59] = "Port management change event support",
115 [61] = "64 byte EQE support",
116 [62] = "64 byte CQE support",
117 };
118 int i;
119
120 mlx4_dbg(dev, "DEV_CAP flags:\n");
121 for (i = 0; i < ARRAY_SIZE(fname); ++i)
122 if (fname[i] && (flags & (1LL << i)))
123 mlx4_dbg(dev, " %s\n", fname[i]);
124 }
125
126 static void dump_dev_cap_flags2(struct mlx4_dev *dev, u64 flags)
127 {
128 static const char * const fname[] = {
129 [0] = "RSS support",
130 [1] = "RSS Toeplitz Hash Function support",
131 [2] = "RSS XOR Hash Function support",
132 [3] = "Device manage flow steering support",
133 [4] = "Automatic MAC reassignment support",
134 [5] = "Time stamping support",
135 [6] = "VST (control vlan insertion/stripping) support",
136 [7] = "FSM (MAC anti-spoofing) support",
137 [8] = "Dynamic QP updates support"
138 };
139 int i;
140
141 for (i = 0; i < ARRAY_SIZE(fname); ++i)
142 if (fname[i] && (flags & (1LL << i)))
143 mlx4_dbg(dev, " %s\n", fname[i]);
144 }
145
146 int mlx4_MOD_STAT_CFG(struct mlx4_dev *dev, struct mlx4_mod_stat_cfg *cfg)
147 {
148 struct mlx4_cmd_mailbox *mailbox;
149 u32 *inbox;
150 int err = 0;
151
152 #define MOD_STAT_CFG_IN_SIZE 0x100
153
154 #define MOD_STAT_CFG_PG_SZ_M_OFFSET 0x002
155 #define MOD_STAT_CFG_PG_SZ_OFFSET 0x003
156
157 mailbox = mlx4_alloc_cmd_mailbox(dev);
158 if (IS_ERR(mailbox))
159 return PTR_ERR(mailbox);
160 inbox = mailbox->buf;
161
162 memset(inbox, 0, MOD_STAT_CFG_IN_SIZE);
163
164 MLX4_PUT(inbox, cfg->log_pg_sz, MOD_STAT_CFG_PG_SZ_OFFSET);
165 MLX4_PUT(inbox, cfg->log_pg_sz_m, MOD_STAT_CFG_PG_SZ_M_OFFSET);
166
167 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_MOD_STAT_CFG,
168 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
169
170 mlx4_free_cmd_mailbox(dev, mailbox);
171 return err;
172 }
173
174 int mlx4_QUERY_FUNC_CAP_wrapper(struct mlx4_dev *dev, int slave,
175 struct mlx4_vhcr *vhcr,
176 struct mlx4_cmd_mailbox *inbox,
177 struct mlx4_cmd_mailbox *outbox,
178 struct mlx4_cmd_info *cmd)
179 {
180 struct mlx4_priv *priv = mlx4_priv(dev);
181 u8 field;
182 u32 size;
183 int err = 0;
184
185 #define QUERY_FUNC_CAP_FLAGS_OFFSET 0x0
186 #define QUERY_FUNC_CAP_NUM_PORTS_OFFSET 0x1
187 #define QUERY_FUNC_CAP_PF_BHVR_OFFSET 0x4
188 #define QUERY_FUNC_CAP_FMR_OFFSET 0x8
189 #define QUERY_FUNC_CAP_QP_QUOTA_OFFSET_DEP 0x10
190 #define QUERY_FUNC_CAP_CQ_QUOTA_OFFSET_DEP 0x14
191 #define QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET_DEP 0x18
192 #define QUERY_FUNC_CAP_MPT_QUOTA_OFFSET_DEP 0x20
193 #define QUERY_FUNC_CAP_MTT_QUOTA_OFFSET_DEP 0x24
194 #define QUERY_FUNC_CAP_MCG_QUOTA_OFFSET_DEP 0x28
195 #define QUERY_FUNC_CAP_MAX_EQ_OFFSET 0x2c
196 #define QUERY_FUNC_CAP_RESERVED_EQ_OFFSET 0x30
197
198 #define QUERY_FUNC_CAP_QP_QUOTA_OFFSET 0x50
199 #define QUERY_FUNC_CAP_CQ_QUOTA_OFFSET 0x54
200 #define QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET 0x58
201 #define QUERY_FUNC_CAP_MPT_QUOTA_OFFSET 0x60
202 #define QUERY_FUNC_CAP_MTT_QUOTA_OFFSET 0x64
203 #define QUERY_FUNC_CAP_MCG_QUOTA_OFFSET 0x68
204
205 #define QUERY_FUNC_CAP_FMR_FLAG 0x80
206 #define QUERY_FUNC_CAP_FLAG_RDMA 0x40
207 #define QUERY_FUNC_CAP_FLAG_ETH 0x80
208 #define QUERY_FUNC_CAP_FLAG_QUOTAS 0x10
209
210 /* when opcode modifier = 1 */
211 #define QUERY_FUNC_CAP_PHYS_PORT_OFFSET 0x3
212 #define QUERY_FUNC_CAP_RDMA_PROPS_OFFSET 0x8
213 #define QUERY_FUNC_CAP_ETH_PROPS_OFFSET 0xc
214
215 #define QUERY_FUNC_CAP_QP0_TUNNEL 0x10
216 #define QUERY_FUNC_CAP_QP0_PROXY 0x14
217 #define QUERY_FUNC_CAP_QP1_TUNNEL 0x18
218 #define QUERY_FUNC_CAP_QP1_PROXY 0x1c
219
220 #define QUERY_FUNC_CAP_ETH_PROPS_FORCE_MAC 0x40
221 #define QUERY_FUNC_CAP_ETH_PROPS_FORCE_VLAN 0x80
222
223 #define QUERY_FUNC_CAP_RDMA_PROPS_FORCE_PHY_WQE_GID 0x80
224
225 if (vhcr->op_modifier == 1) {
226 field = 0;
227 /* ensure force vlan and force mac bits are not set */
228 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_ETH_PROPS_OFFSET);
229 /* ensure that phy_wqe_gid bit is not set */
230 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_RDMA_PROPS_OFFSET);
231
232 field = vhcr->in_modifier; /* phys-port = logical-port */
233 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_PHYS_PORT_OFFSET);
234
235 /* size is now the QP number */
236 size = dev->phys_caps.base_tunnel_sqpn + 8 * slave + field - 1;
237 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP0_TUNNEL);
238
239 size += 2;
240 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP1_TUNNEL);
241
242 size = dev->phys_caps.base_proxy_sqpn + 8 * slave + field - 1;
243 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP0_PROXY);
244
245 size += 2;
246 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP1_PROXY);
247
248 } else if (vhcr->op_modifier == 0) {
249 /* enable rdma and ethernet interfaces, and new quota locations */
250 field = (QUERY_FUNC_CAP_FLAG_ETH | QUERY_FUNC_CAP_FLAG_RDMA |
251 QUERY_FUNC_CAP_FLAG_QUOTAS);
252 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FLAGS_OFFSET);
253
254 field = dev->caps.num_ports;
255 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_NUM_PORTS_OFFSET);
256
257 size = dev->caps.function_caps; /* set PF behaviours */
258 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_PF_BHVR_OFFSET);
259
260 field = 0; /* protected FMR support not available as yet */
261 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FMR_OFFSET);
262
263 size = priv->mfunc.master.res_tracker.res_alloc[RES_QP].quota[slave];
264 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP_QUOTA_OFFSET);
265 size = dev->caps.num_qps;
266 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP_QUOTA_OFFSET_DEP);
267
268 size = priv->mfunc.master.res_tracker.res_alloc[RES_SRQ].quota[slave];
269 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET);
270 size = dev->caps.num_srqs;
271 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET_DEP);
272
273 size = priv->mfunc.master.res_tracker.res_alloc[RES_CQ].quota[slave];
274 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET);
275 size = dev->caps.num_cqs;
276 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET_DEP);
277
278 size = dev->caps.num_eqs;
279 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MAX_EQ_OFFSET);
280
281 size = dev->caps.reserved_eqs;
282 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET);
283
284 size = priv->mfunc.master.res_tracker.res_alloc[RES_MPT].quota[slave];
285 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET);
286 size = dev->caps.num_mpts;
287 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET_DEP);
288
289 size = priv->mfunc.master.res_tracker.res_alloc[RES_MTT].quota[slave];
290 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET);
291 size = dev->caps.num_mtts;
292 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET_DEP);
293
294 size = dev->caps.num_mgms + dev->caps.num_amgms;
295 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET);
296 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET_DEP);
297
298 } else
299 err = -EINVAL;
300
301 return err;
302 }
303
304 int mlx4_QUERY_FUNC_CAP(struct mlx4_dev *dev, u32 gen_or_port,
305 struct mlx4_func_cap *func_cap)
306 {
307 struct mlx4_cmd_mailbox *mailbox;
308 u32 *outbox;
309 u8 field, op_modifier;
310 u32 size;
311 int err = 0, quotas = 0;
312
313 op_modifier = !!gen_or_port; /* 0 = general, 1 = logical port */
314
315 mailbox = mlx4_alloc_cmd_mailbox(dev);
316 if (IS_ERR(mailbox))
317 return PTR_ERR(mailbox);
318
319 err = mlx4_cmd_box(dev, 0, mailbox->dma, gen_or_port, op_modifier,
320 MLX4_CMD_QUERY_FUNC_CAP,
321 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
322 if (err)
323 goto out;
324
325 outbox = mailbox->buf;
326
327 if (!op_modifier) {
328 MLX4_GET(field, outbox, QUERY_FUNC_CAP_FLAGS_OFFSET);
329 if (!(field & (QUERY_FUNC_CAP_FLAG_ETH | QUERY_FUNC_CAP_FLAG_RDMA))) {
330 mlx4_err(dev, "The host supports neither eth nor rdma interfaces\n");
331 err = -EPROTONOSUPPORT;
332 goto out;
333 }
334 func_cap->flags = field;
335 quotas = !!(func_cap->flags & QUERY_FUNC_CAP_FLAG_QUOTAS);
336
337 MLX4_GET(field, outbox, QUERY_FUNC_CAP_NUM_PORTS_OFFSET);
338 func_cap->num_ports = field;
339
340 MLX4_GET(size, outbox, QUERY_FUNC_CAP_PF_BHVR_OFFSET);
341 func_cap->pf_context_behaviour = size;
342
343 if (quotas) {
344 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP_QUOTA_OFFSET);
345 func_cap->qp_quota = size & 0xFFFFFF;
346
347 MLX4_GET(size, outbox, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET);
348 func_cap->srq_quota = size & 0xFFFFFF;
349
350 MLX4_GET(size, outbox, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET);
351 func_cap->cq_quota = size & 0xFFFFFF;
352
353 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET);
354 func_cap->mpt_quota = size & 0xFFFFFF;
355
356 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET);
357 func_cap->mtt_quota = size & 0xFFFFFF;
358
359 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET);
360 func_cap->mcg_quota = size & 0xFFFFFF;
361
362 } else {
363 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP_QUOTA_OFFSET_DEP);
364 func_cap->qp_quota = size & 0xFFFFFF;
365
366 MLX4_GET(size, outbox, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET_DEP);
367 func_cap->srq_quota = size & 0xFFFFFF;
368
369 MLX4_GET(size, outbox, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET_DEP);
370 func_cap->cq_quota = size & 0xFFFFFF;
371
372 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET_DEP);
373 func_cap->mpt_quota = size & 0xFFFFFF;
374
375 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET_DEP);
376 func_cap->mtt_quota = size & 0xFFFFFF;
377
378 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET_DEP);
379 func_cap->mcg_quota = size & 0xFFFFFF;
380 }
381 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MAX_EQ_OFFSET);
382 func_cap->max_eq = size & 0xFFFFFF;
383
384 MLX4_GET(size, outbox, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET);
385 func_cap->reserved_eq = size & 0xFFFFFF;
386
387 goto out;
388 }
389
390 /* logical port query */
391 if (gen_or_port > dev->caps.num_ports) {
392 err = -EINVAL;
393 goto out;
394 }
395
396 if (dev->caps.port_type[gen_or_port] == MLX4_PORT_TYPE_ETH) {
397 MLX4_GET(field, outbox, QUERY_FUNC_CAP_ETH_PROPS_OFFSET);
398 if (field & QUERY_FUNC_CAP_ETH_PROPS_FORCE_VLAN) {
399 mlx4_err(dev, "VLAN is enforced on this port\n");
400 err = -EPROTONOSUPPORT;
401 goto out;
402 }
403
404 if (field & QUERY_FUNC_CAP_ETH_PROPS_FORCE_MAC) {
405 mlx4_err(dev, "Force mac is enabled on this port\n");
406 err = -EPROTONOSUPPORT;
407 goto out;
408 }
409 } else if (dev->caps.port_type[gen_or_port] == MLX4_PORT_TYPE_IB) {
410 MLX4_GET(field, outbox, QUERY_FUNC_CAP_RDMA_PROPS_OFFSET);
411 if (field & QUERY_FUNC_CAP_RDMA_PROPS_FORCE_PHY_WQE_GID) {
412 mlx4_err(dev, "phy_wqe_gid is "
413 "enforced on this ib port\n");
414 err = -EPROTONOSUPPORT;
415 goto out;
416 }
417 }
418
419 MLX4_GET(field, outbox, QUERY_FUNC_CAP_PHYS_PORT_OFFSET);
420 func_cap->physical_port = field;
421 if (func_cap->physical_port != gen_or_port) {
422 err = -ENOSYS;
423 goto out;
424 }
425
426 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP0_TUNNEL);
427 func_cap->qp0_tunnel_qpn = size & 0xFFFFFF;
428
429 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP0_PROXY);
430 func_cap->qp0_proxy_qpn = size & 0xFFFFFF;
431
432 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP1_TUNNEL);
433 func_cap->qp1_tunnel_qpn = size & 0xFFFFFF;
434
435 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP1_PROXY);
436 func_cap->qp1_proxy_qpn = size & 0xFFFFFF;
437
438 /* All other resources are allocated by the master, but we still report
439 * 'num' and 'reserved' capabilities as follows:
440 * - num remains the maximum resource index
441 * - 'num - reserved' is the total available objects of a resource, but
442 * resource indices may be less than 'reserved'
443 * TODO: set per-resource quotas */
444
445 out:
446 mlx4_free_cmd_mailbox(dev, mailbox);
447
448 return err;
449 }
450
451 int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
452 {
453 struct mlx4_cmd_mailbox *mailbox;
454 u32 *outbox;
455 u8 field;
456 u32 field32, flags, ext_flags;
457 u16 size;
458 u16 stat_rate;
459 int err;
460 int i;
461
462 #define QUERY_DEV_CAP_OUT_SIZE 0x100
463 #define QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET 0x10
464 #define QUERY_DEV_CAP_MAX_QP_SZ_OFFSET 0x11
465 #define QUERY_DEV_CAP_RSVD_QP_OFFSET 0x12
466 #define QUERY_DEV_CAP_MAX_QP_OFFSET 0x13
467 #define QUERY_DEV_CAP_RSVD_SRQ_OFFSET 0x14
468 #define QUERY_DEV_CAP_MAX_SRQ_OFFSET 0x15
469 #define QUERY_DEV_CAP_RSVD_EEC_OFFSET 0x16
470 #define QUERY_DEV_CAP_MAX_EEC_OFFSET 0x17
471 #define QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET 0x19
472 #define QUERY_DEV_CAP_RSVD_CQ_OFFSET 0x1a
473 #define QUERY_DEV_CAP_MAX_CQ_OFFSET 0x1b
474 #define QUERY_DEV_CAP_MAX_MPT_OFFSET 0x1d
475 #define QUERY_DEV_CAP_RSVD_EQ_OFFSET 0x1e
476 #define QUERY_DEV_CAP_MAX_EQ_OFFSET 0x1f
477 #define QUERY_DEV_CAP_RSVD_MTT_OFFSET 0x20
478 #define QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET 0x21
479 #define QUERY_DEV_CAP_RSVD_MRW_OFFSET 0x22
480 #define QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET 0x23
481 #define QUERY_DEV_CAP_MAX_AV_OFFSET 0x27
482 #define QUERY_DEV_CAP_MAX_REQ_QP_OFFSET 0x29
483 #define QUERY_DEV_CAP_MAX_RES_QP_OFFSET 0x2b
484 #define QUERY_DEV_CAP_MAX_GSO_OFFSET 0x2d
485 #define QUERY_DEV_CAP_RSS_OFFSET 0x2e
486 #define QUERY_DEV_CAP_MAX_RDMA_OFFSET 0x2f
487 #define QUERY_DEV_CAP_RSZ_SRQ_OFFSET 0x33
488 #define QUERY_DEV_CAP_ACK_DELAY_OFFSET 0x35
489 #define QUERY_DEV_CAP_MTU_WIDTH_OFFSET 0x36
490 #define QUERY_DEV_CAP_VL_PORT_OFFSET 0x37
491 #define QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET 0x38
492 #define QUERY_DEV_CAP_MAX_GID_OFFSET 0x3b
493 #define QUERY_DEV_CAP_RATE_SUPPORT_OFFSET 0x3c
494 #define QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET 0x3e
495 #define QUERY_DEV_CAP_MAX_PKEY_OFFSET 0x3f
496 #define QUERY_DEV_CAP_EXT_FLAGS_OFFSET 0x40
497 #define QUERY_DEV_CAP_FLAGS_OFFSET 0x44
498 #define QUERY_DEV_CAP_RSVD_UAR_OFFSET 0x48
499 #define QUERY_DEV_CAP_UAR_SZ_OFFSET 0x49
500 #define QUERY_DEV_CAP_PAGE_SZ_OFFSET 0x4b
501 #define QUERY_DEV_CAP_BF_OFFSET 0x4c
502 #define QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET 0x4d
503 #define QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET 0x4e
504 #define QUERY_DEV_CAP_LOG_MAX_BF_PAGES_OFFSET 0x4f
505 #define QUERY_DEV_CAP_MAX_SG_SQ_OFFSET 0x51
506 #define QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET 0x52
507 #define QUERY_DEV_CAP_MAX_SG_RQ_OFFSET 0x55
508 #define QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET 0x56
509 #define QUERY_DEV_CAP_MAX_QP_MCG_OFFSET 0x61
510 #define QUERY_DEV_CAP_RSVD_MCG_OFFSET 0x62
511 #define QUERY_DEV_CAP_MAX_MCG_OFFSET 0x63
512 #define QUERY_DEV_CAP_RSVD_PD_OFFSET 0x64
513 #define QUERY_DEV_CAP_MAX_PD_OFFSET 0x65
514 #define QUERY_DEV_CAP_RSVD_XRC_OFFSET 0x66
515 #define QUERY_DEV_CAP_MAX_XRC_OFFSET 0x67
516 #define QUERY_DEV_CAP_MAX_COUNTERS_OFFSET 0x68
517 #define QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET 0x70
518 #define QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET 0x76
519 #define QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET 0x77
520 #define QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET 0x80
521 #define QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET 0x82
522 #define QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET 0x84
523 #define QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET 0x86
524 #define QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET 0x88
525 #define QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET 0x8a
526 #define QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET 0x8c
527 #define QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET 0x8e
528 #define QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET 0x90
529 #define QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET 0x92
530 #define QUERY_DEV_CAP_BMME_FLAGS_OFFSET 0x94
531 #define QUERY_DEV_CAP_RSVD_LKEY_OFFSET 0x98
532 #define QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET 0xa0
533 #define QUERY_DEV_CAP_FW_REASSIGN_MAC 0x9d
534
535 dev_cap->flags2 = 0;
536 mailbox = mlx4_alloc_cmd_mailbox(dev);
537 if (IS_ERR(mailbox))
538 return PTR_ERR(mailbox);
539 outbox = mailbox->buf;
540
541 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP,
542 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
543 if (err)
544 goto out;
545
546 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_QP_OFFSET);
547 dev_cap->reserved_qps = 1 << (field & 0xf);
548 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_OFFSET);
549 dev_cap->max_qps = 1 << (field & 0x1f);
550 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_SRQ_OFFSET);
551 dev_cap->reserved_srqs = 1 << (field >> 4);
552 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_OFFSET);
553 dev_cap->max_srqs = 1 << (field & 0x1f);
554 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET);
555 dev_cap->max_cq_sz = 1 << field;
556 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_CQ_OFFSET);
557 dev_cap->reserved_cqs = 1 << (field & 0xf);
558 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_OFFSET);
559 dev_cap->max_cqs = 1 << (field & 0x1f);
560 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MPT_OFFSET);
561 dev_cap->max_mpts = 1 << (field & 0x3f);
562 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_EQ_OFFSET);
563 dev_cap->reserved_eqs = field & 0xf;
564 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_EQ_OFFSET);
565 dev_cap->max_eqs = 1 << (field & 0xf);
566 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MTT_OFFSET);
567 dev_cap->reserved_mtts = 1 << (field >> 4);
568 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET);
569 dev_cap->max_mrw_sz = 1 << field;
570 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MRW_OFFSET);
571 dev_cap->reserved_mrws = 1 << (field & 0xf);
572 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET);
573 dev_cap->max_mtt_seg = 1 << (field & 0x3f);
574 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_REQ_QP_OFFSET);
575 dev_cap->max_requester_per_qp = 1 << (field & 0x3f);
576 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RES_QP_OFFSET);
577 dev_cap->max_responder_per_qp = 1 << (field & 0x3f);
578 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GSO_OFFSET);
579 field &= 0x1f;
580 if (!field)
581 dev_cap->max_gso_sz = 0;
582 else
583 dev_cap->max_gso_sz = 1 << field;
584
585 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSS_OFFSET);
586 if (field & 0x20)
587 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_XOR;
588 if (field & 0x10)
589 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_TOP;
590 field &= 0xf;
591 if (field) {
592 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS;
593 dev_cap->max_rss_tbl_sz = 1 << field;
594 } else
595 dev_cap->max_rss_tbl_sz = 0;
596 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RDMA_OFFSET);
597 dev_cap->max_rdma_global = 1 << (field & 0x3f);
598 MLX4_GET(field, outbox, QUERY_DEV_CAP_ACK_DELAY_OFFSET);
599 dev_cap->local_ca_ack_delay = field & 0x1f;
600 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET);
601 dev_cap->num_ports = field & 0xf;
602 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET);
603 dev_cap->max_msg_sz = 1 << (field & 0x1f);
604 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET);
605 if (field & 0x80)
606 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FS_EN;
607 dev_cap->fs_log_max_ucast_qp_range_size = field & 0x1f;
608 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET);
609 dev_cap->fs_max_num_qp_per_entry = field;
610 MLX4_GET(stat_rate, outbox, QUERY_DEV_CAP_RATE_SUPPORT_OFFSET);
611 dev_cap->stat_rate_support = stat_rate;
612 MLX4_GET(field, outbox, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET);
613 if (field & 0x80)
614 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_TS;
615 MLX4_GET(ext_flags, outbox, QUERY_DEV_CAP_EXT_FLAGS_OFFSET);
616 MLX4_GET(flags, outbox, QUERY_DEV_CAP_FLAGS_OFFSET);
617 dev_cap->flags = flags | (u64)ext_flags << 32;
618 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_UAR_OFFSET);
619 dev_cap->reserved_uars = field >> 4;
620 MLX4_GET(field, outbox, QUERY_DEV_CAP_UAR_SZ_OFFSET);
621 dev_cap->uar_size = 1 << ((field & 0x3f) + 20);
622 MLX4_GET(field, outbox, QUERY_DEV_CAP_PAGE_SZ_OFFSET);
623 dev_cap->min_page_sz = 1 << field;
624
625 MLX4_GET(field, outbox, QUERY_DEV_CAP_BF_OFFSET);
626 if (field & 0x80) {
627 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET);
628 dev_cap->bf_reg_size = 1 << (field & 0x1f);
629 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET);
630 if ((1 << (field & 0x3f)) > (PAGE_SIZE / dev_cap->bf_reg_size))
631 field = 3;
632 dev_cap->bf_regs_per_page = 1 << (field & 0x3f);
633 mlx4_dbg(dev, "BlueFlame available (reg size %d, regs/page %d)\n",
634 dev_cap->bf_reg_size, dev_cap->bf_regs_per_page);
635 } else {
636 dev_cap->bf_reg_size = 0;
637 mlx4_dbg(dev, "BlueFlame not available\n");
638 }
639
640 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_SQ_OFFSET);
641 dev_cap->max_sq_sg = field;
642 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET);
643 dev_cap->max_sq_desc_sz = size;
644
645 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_MCG_OFFSET);
646 dev_cap->max_qp_per_mcg = 1 << field;
647 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MCG_OFFSET);
648 dev_cap->reserved_mgms = field & 0xf;
649 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MCG_OFFSET);
650 dev_cap->max_mcgs = 1 << field;
651 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_PD_OFFSET);
652 dev_cap->reserved_pds = field >> 4;
653 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PD_OFFSET);
654 dev_cap->max_pds = 1 << (field & 0x3f);
655 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_XRC_OFFSET);
656 dev_cap->reserved_xrcds = field >> 4;
657 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_XRC_OFFSET);
658 dev_cap->max_xrcds = 1 << (field & 0x1f);
659
660 MLX4_GET(size, outbox, QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET);
661 dev_cap->rdmarc_entry_sz = size;
662 MLX4_GET(size, outbox, QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET);
663 dev_cap->qpc_entry_sz = size;
664 MLX4_GET(size, outbox, QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET);
665 dev_cap->aux_entry_sz = size;
666 MLX4_GET(size, outbox, QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET);
667 dev_cap->altc_entry_sz = size;
668 MLX4_GET(size, outbox, QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET);
669 dev_cap->eqc_entry_sz = size;
670 MLX4_GET(size, outbox, QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET);
671 dev_cap->cqc_entry_sz = size;
672 MLX4_GET(size, outbox, QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET);
673 dev_cap->srq_entry_sz = size;
674 MLX4_GET(size, outbox, QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET);
675 dev_cap->cmpt_entry_sz = size;
676 MLX4_GET(size, outbox, QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET);
677 dev_cap->mtt_entry_sz = size;
678 MLX4_GET(size, outbox, QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET);
679 dev_cap->dmpt_entry_sz = size;
680
681 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET);
682 dev_cap->max_srq_sz = 1 << field;
683 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_SZ_OFFSET);
684 dev_cap->max_qp_sz = 1 << field;
685 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSZ_SRQ_OFFSET);
686 dev_cap->resize_srq = field & 1;
687 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_RQ_OFFSET);
688 dev_cap->max_rq_sg = field;
689 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET);
690 dev_cap->max_rq_desc_sz = size;
691
692 MLX4_GET(dev_cap->bmme_flags, outbox,
693 QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
694 MLX4_GET(dev_cap->reserved_lkey, outbox,
695 QUERY_DEV_CAP_RSVD_LKEY_OFFSET);
696 MLX4_GET(field, outbox, QUERY_DEV_CAP_FW_REASSIGN_MAC);
697 if (field & 1<<6)
698 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN;
699 MLX4_GET(dev_cap->max_icm_sz, outbox,
700 QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET);
701 if (dev_cap->flags & MLX4_DEV_CAP_FLAG_COUNTERS)
702 MLX4_GET(dev_cap->max_counters, outbox,
703 QUERY_DEV_CAP_MAX_COUNTERS_OFFSET);
704
705 MLX4_GET(field32, outbox, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET);
706 if (field32 & (1 << 16))
707 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_UPDATE_QP;
708 if (field32 & (1 << 26))
709 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_VLAN_CONTROL;
710 if (field32 & (1 << 20))
711 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FSM;
712
713 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
714 for (i = 1; i <= dev_cap->num_ports; ++i) {
715 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET);
716 dev_cap->max_vl[i] = field >> 4;
717 MLX4_GET(field, outbox, QUERY_DEV_CAP_MTU_WIDTH_OFFSET);
718 dev_cap->ib_mtu[i] = field >> 4;
719 dev_cap->max_port_width[i] = field & 0xf;
720 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GID_OFFSET);
721 dev_cap->max_gids[i] = 1 << (field & 0xf);
722 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PKEY_OFFSET);
723 dev_cap->max_pkeys[i] = 1 << (field & 0xf);
724 }
725 } else {
726 #define QUERY_PORT_SUPPORTED_TYPE_OFFSET 0x00
727 #define QUERY_PORT_MTU_OFFSET 0x01
728 #define QUERY_PORT_ETH_MTU_OFFSET 0x02
729 #define QUERY_PORT_WIDTH_OFFSET 0x06
730 #define QUERY_PORT_MAX_GID_PKEY_OFFSET 0x07
731 #define QUERY_PORT_MAX_MACVLAN_OFFSET 0x0a
732 #define QUERY_PORT_MAX_VL_OFFSET 0x0b
733 #define QUERY_PORT_MAC_OFFSET 0x10
734 #define QUERY_PORT_TRANS_VENDOR_OFFSET 0x18
735 #define QUERY_PORT_WAVELENGTH_OFFSET 0x1c
736 #define QUERY_PORT_TRANS_CODE_OFFSET 0x20
737
738 for (i = 1; i <= dev_cap->num_ports; ++i) {
739 err = mlx4_cmd_box(dev, 0, mailbox->dma, i, 0, MLX4_CMD_QUERY_PORT,
740 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
741 if (err)
742 goto out;
743
744 MLX4_GET(field, outbox, QUERY_PORT_SUPPORTED_TYPE_OFFSET);
745 dev_cap->supported_port_types[i] = field & 3;
746 dev_cap->suggested_type[i] = (field >> 3) & 1;
747 dev_cap->default_sense[i] = (field >> 4) & 1;
748 MLX4_GET(field, outbox, QUERY_PORT_MTU_OFFSET);
749 dev_cap->ib_mtu[i] = field & 0xf;
750 MLX4_GET(field, outbox, QUERY_PORT_WIDTH_OFFSET);
751 dev_cap->max_port_width[i] = field & 0xf;
752 MLX4_GET(field, outbox, QUERY_PORT_MAX_GID_PKEY_OFFSET);
753 dev_cap->max_gids[i] = 1 << (field >> 4);
754 dev_cap->max_pkeys[i] = 1 << (field & 0xf);
755 MLX4_GET(field, outbox, QUERY_PORT_MAX_VL_OFFSET);
756 dev_cap->max_vl[i] = field & 0xf;
757 MLX4_GET(field, outbox, QUERY_PORT_MAX_MACVLAN_OFFSET);
758 dev_cap->log_max_macs[i] = field & 0xf;
759 dev_cap->log_max_vlans[i] = field >> 4;
760 MLX4_GET(dev_cap->eth_mtu[i], outbox, QUERY_PORT_ETH_MTU_OFFSET);
761 MLX4_GET(dev_cap->def_mac[i], outbox, QUERY_PORT_MAC_OFFSET);
762 MLX4_GET(field32, outbox, QUERY_PORT_TRANS_VENDOR_OFFSET);
763 dev_cap->trans_type[i] = field32 >> 24;
764 dev_cap->vendor_oui[i] = field32 & 0xffffff;
765 MLX4_GET(dev_cap->wavelength[i], outbox, QUERY_PORT_WAVELENGTH_OFFSET);
766 MLX4_GET(dev_cap->trans_code[i], outbox, QUERY_PORT_TRANS_CODE_OFFSET);
767 }
768 }
769
770 mlx4_dbg(dev, "Base MM extensions: flags %08x, rsvd L_Key %08x\n",
771 dev_cap->bmme_flags, dev_cap->reserved_lkey);
772
773 /*
774 * Each UAR has 4 EQ doorbells; so if a UAR is reserved, then
775 * we can't use any EQs whose doorbell falls on that page,
776 * even if the EQ itself isn't reserved.
777 */
778 dev_cap->reserved_eqs = max(dev_cap->reserved_uars * 4,
779 dev_cap->reserved_eqs);
780
781 mlx4_dbg(dev, "Max ICM size %lld MB\n",
782 (unsigned long long) dev_cap->max_icm_sz >> 20);
783 mlx4_dbg(dev, "Max QPs: %d, reserved QPs: %d, entry size: %d\n",
784 dev_cap->max_qps, dev_cap->reserved_qps, dev_cap->qpc_entry_sz);
785 mlx4_dbg(dev, "Max SRQs: %d, reserved SRQs: %d, entry size: %d\n",
786 dev_cap->max_srqs, dev_cap->reserved_srqs, dev_cap->srq_entry_sz);
787 mlx4_dbg(dev, "Max CQs: %d, reserved CQs: %d, entry size: %d\n",
788 dev_cap->max_cqs, dev_cap->reserved_cqs, dev_cap->cqc_entry_sz);
789 mlx4_dbg(dev, "Max EQs: %d, reserved EQs: %d, entry size: %d\n",
790 dev_cap->max_eqs, dev_cap->reserved_eqs, dev_cap->eqc_entry_sz);
791 mlx4_dbg(dev, "reserved MPTs: %d, reserved MTTs: %d\n",
792 dev_cap->reserved_mrws, dev_cap->reserved_mtts);
793 mlx4_dbg(dev, "Max PDs: %d, reserved PDs: %d, reserved UARs: %d\n",
794 dev_cap->max_pds, dev_cap->reserved_pds, dev_cap->reserved_uars);
795 mlx4_dbg(dev, "Max QP/MCG: %d, reserved MGMs: %d\n",
796 dev_cap->max_pds, dev_cap->reserved_mgms);
797 mlx4_dbg(dev, "Max CQEs: %d, max WQEs: %d, max SRQ WQEs: %d\n",
798 dev_cap->max_cq_sz, dev_cap->max_qp_sz, dev_cap->max_srq_sz);
799 mlx4_dbg(dev, "Local CA ACK delay: %d, max MTU: %d, port width cap: %d\n",
800 dev_cap->local_ca_ack_delay, 128 << dev_cap->ib_mtu[1],
801 dev_cap->max_port_width[1]);
802 mlx4_dbg(dev, "Max SQ desc size: %d, max SQ S/G: %d\n",
803 dev_cap->max_sq_desc_sz, dev_cap->max_sq_sg);
804 mlx4_dbg(dev, "Max RQ desc size: %d, max RQ S/G: %d\n",
805 dev_cap->max_rq_desc_sz, dev_cap->max_rq_sg);
806 mlx4_dbg(dev, "Max GSO size: %d\n", dev_cap->max_gso_sz);
807 mlx4_dbg(dev, "Max counters: %d\n", dev_cap->max_counters);
808 mlx4_dbg(dev, "Max RSS Table size: %d\n", dev_cap->max_rss_tbl_sz);
809
810 dump_dev_cap_flags(dev, dev_cap->flags);
811 dump_dev_cap_flags2(dev, dev_cap->flags2);
812
813 out:
814 mlx4_free_cmd_mailbox(dev, mailbox);
815 return err;
816 }
817
818 int mlx4_QUERY_DEV_CAP_wrapper(struct mlx4_dev *dev, int slave,
819 struct mlx4_vhcr *vhcr,
820 struct mlx4_cmd_mailbox *inbox,
821 struct mlx4_cmd_mailbox *outbox,
822 struct mlx4_cmd_info *cmd)
823 {
824 u64 flags;
825 int err = 0;
826 u8 field;
827 u32 bmme_flags;
828
829 err = mlx4_cmd_box(dev, 0, outbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP,
830 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
831 if (err)
832 return err;
833
834 /* add port mng change event capability and disable mw type 1
835 * unconditionally to slaves
836 */
837 MLX4_GET(flags, outbox->buf, QUERY_DEV_CAP_EXT_FLAGS_OFFSET);
838 flags |= MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV;
839 flags &= ~MLX4_DEV_CAP_FLAG_MEM_WINDOW;
840 MLX4_PUT(outbox->buf, flags, QUERY_DEV_CAP_EXT_FLAGS_OFFSET);
841
842 /* For guests, disable timestamp */
843 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET);
844 field &= 0x7f;
845 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET);
846
847 /* For guests, report Blueflame disabled */
848 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_BF_OFFSET);
849 field &= 0x7f;
850 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_BF_OFFSET);
851
852 /* For guests, disable mw type 2 */
853 MLX4_GET(bmme_flags, outbox, QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
854 bmme_flags &= ~MLX4_BMME_FLAG_TYPE_2_WIN;
855 MLX4_PUT(outbox->buf, bmme_flags, QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
856
857 /* turn off device-managed steering capability if not enabled */
858 if (dev->caps.steering_mode != MLX4_STEERING_MODE_DEVICE_MANAGED) {
859 MLX4_GET(field, outbox->buf,
860 QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET);
861 field &= 0x7f;
862 MLX4_PUT(outbox->buf, field,
863 QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET);
864 }
865 return 0;
866 }
867
868 int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave,
869 struct mlx4_vhcr *vhcr,
870 struct mlx4_cmd_mailbox *inbox,
871 struct mlx4_cmd_mailbox *outbox,
872 struct mlx4_cmd_info *cmd)
873 {
874 struct mlx4_priv *priv = mlx4_priv(dev);
875 u64 def_mac;
876 u8 port_type;
877 u16 short_field;
878 int err;
879 int admin_link_state;
880
881 #define MLX4_VF_PORT_NO_LINK_SENSE_MASK 0xE0
882 #define MLX4_PORT_LINK_UP_MASK 0x80
883 #define QUERY_PORT_CUR_MAX_PKEY_OFFSET 0x0c
884 #define QUERY_PORT_CUR_MAX_GID_OFFSET 0x0e
885
886 err = mlx4_cmd_box(dev, 0, outbox->dma, vhcr->in_modifier, 0,
887 MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B,
888 MLX4_CMD_NATIVE);
889
890 if (!err && dev->caps.function != slave) {
891 def_mac = priv->mfunc.master.vf_oper[slave].vport[vhcr->in_modifier].state.mac;
892 MLX4_PUT(outbox->buf, def_mac, QUERY_PORT_MAC_OFFSET);
893
894 /* get port type - currently only eth is enabled */
895 MLX4_GET(port_type, outbox->buf,
896 QUERY_PORT_SUPPORTED_TYPE_OFFSET);
897
898 /* No link sensing allowed */
899 port_type &= MLX4_VF_PORT_NO_LINK_SENSE_MASK;
900 /* set port type to currently operating port type */
901 port_type |= (dev->caps.port_type[vhcr->in_modifier] & 0x3);
902
903 admin_link_state = priv->mfunc.master.vf_oper[slave].vport[vhcr->in_modifier].state.link_state;
904 if (IFLA_VF_LINK_STATE_ENABLE == admin_link_state)
905 port_type |= MLX4_PORT_LINK_UP_MASK;
906 else if (IFLA_VF_LINK_STATE_DISABLE == admin_link_state)
907 port_type &= ~MLX4_PORT_LINK_UP_MASK;
908
909 MLX4_PUT(outbox->buf, port_type,
910 QUERY_PORT_SUPPORTED_TYPE_OFFSET);
911
912 short_field = 1; /* slave max gids */
913 MLX4_PUT(outbox->buf, short_field,
914 QUERY_PORT_CUR_MAX_GID_OFFSET);
915
916 short_field = dev->caps.pkey_table_len[vhcr->in_modifier];
917 MLX4_PUT(outbox->buf, short_field,
918 QUERY_PORT_CUR_MAX_PKEY_OFFSET);
919 }
920
921 return err;
922 }
923
924 int mlx4_get_slave_pkey_gid_tbl_len(struct mlx4_dev *dev, u8 port,
925 int *gid_tbl_len, int *pkey_tbl_len)
926 {
927 struct mlx4_cmd_mailbox *mailbox;
928 u32 *outbox;
929 u16 field;
930 int err;
931
932 mailbox = mlx4_alloc_cmd_mailbox(dev);
933 if (IS_ERR(mailbox))
934 return PTR_ERR(mailbox);
935
936 err = mlx4_cmd_box(dev, 0, mailbox->dma, port, 0,
937 MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B,
938 MLX4_CMD_WRAPPED);
939 if (err)
940 goto out;
941
942 outbox = mailbox->buf;
943
944 MLX4_GET(field, outbox, QUERY_PORT_CUR_MAX_GID_OFFSET);
945 *gid_tbl_len = field;
946
947 MLX4_GET(field, outbox, QUERY_PORT_CUR_MAX_PKEY_OFFSET);
948 *pkey_tbl_len = field;
949
950 out:
951 mlx4_free_cmd_mailbox(dev, mailbox);
952 return err;
953 }
954 EXPORT_SYMBOL(mlx4_get_slave_pkey_gid_tbl_len);
955
956 int mlx4_map_cmd(struct mlx4_dev *dev, u16 op, struct mlx4_icm *icm, u64 virt)
957 {
958 struct mlx4_cmd_mailbox *mailbox;
959 struct mlx4_icm_iter iter;
960 __be64 *pages;
961 int lg;
962 int nent = 0;
963 int i;
964 int err = 0;
965 int ts = 0, tc = 0;
966
967 mailbox = mlx4_alloc_cmd_mailbox(dev);
968 if (IS_ERR(mailbox))
969 return PTR_ERR(mailbox);
970 memset(mailbox->buf, 0, MLX4_MAILBOX_SIZE);
971 pages = mailbox->buf;
972
973 for (mlx4_icm_first(icm, &iter);
974 !mlx4_icm_last(&iter);
975 mlx4_icm_next(&iter)) {
976 /*
977 * We have to pass pages that are aligned to their
978 * size, so find the least significant 1 in the
979 * address or size and use that as our log2 size.
980 */
981 lg = ffs(mlx4_icm_addr(&iter) | mlx4_icm_size(&iter)) - 1;
982 if (lg < MLX4_ICM_PAGE_SHIFT) {
983 mlx4_warn(dev, "Got FW area not aligned to %d (%llx/%lx).\n",
984 MLX4_ICM_PAGE_SIZE,
985 (unsigned long long) mlx4_icm_addr(&iter),
986 mlx4_icm_size(&iter));
987 err = -EINVAL;
988 goto out;
989 }
990
991 for (i = 0; i < mlx4_icm_size(&iter) >> lg; ++i) {
992 if (virt != -1) {
993 pages[nent * 2] = cpu_to_be64(virt);
994 virt += 1 << lg;
995 }
996
997 pages[nent * 2 + 1] =
998 cpu_to_be64((mlx4_icm_addr(&iter) + (i << lg)) |
999 (lg - MLX4_ICM_PAGE_SHIFT));
1000 ts += 1 << (lg - 10);
1001 ++tc;
1002
1003 if (++nent == MLX4_MAILBOX_SIZE / 16) {
1004 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op,
1005 MLX4_CMD_TIME_CLASS_B,
1006 MLX4_CMD_NATIVE);
1007 if (err)
1008 goto out;
1009 nent = 0;
1010 }
1011 }
1012 }
1013
1014 if (nent)
1015 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op,
1016 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
1017 if (err)
1018 goto out;
1019
1020 switch (op) {
1021 case MLX4_CMD_MAP_FA:
1022 mlx4_dbg(dev, "Mapped %d chunks/%d KB for FW.\n", tc, ts);
1023 break;
1024 case MLX4_CMD_MAP_ICM_AUX:
1025 mlx4_dbg(dev, "Mapped %d chunks/%d KB for ICM aux.\n", tc, ts);
1026 break;
1027 case MLX4_CMD_MAP_ICM:
1028 mlx4_dbg(dev, "Mapped %d chunks/%d KB at %llx for ICM.\n",
1029 tc, ts, (unsigned long long) virt - (ts << 10));
1030 break;
1031 }
1032
1033 out:
1034 mlx4_free_cmd_mailbox(dev, mailbox);
1035 return err;
1036 }
1037
1038 int mlx4_MAP_FA(struct mlx4_dev *dev, struct mlx4_icm *icm)
1039 {
1040 return mlx4_map_cmd(dev, MLX4_CMD_MAP_FA, icm, -1);
1041 }
1042
1043 int mlx4_UNMAP_FA(struct mlx4_dev *dev)
1044 {
1045 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_UNMAP_FA,
1046 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
1047 }
1048
1049
1050 int mlx4_RUN_FW(struct mlx4_dev *dev)
1051 {
1052 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_RUN_FW,
1053 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1054 }
1055
1056 int mlx4_QUERY_FW(struct mlx4_dev *dev)
1057 {
1058 struct mlx4_fw *fw = &mlx4_priv(dev)->fw;
1059 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
1060 struct mlx4_cmd_mailbox *mailbox;
1061 u32 *outbox;
1062 int err = 0;
1063 u64 fw_ver;
1064 u16 cmd_if_rev;
1065 u8 lg;
1066
1067 #define QUERY_FW_OUT_SIZE 0x100
1068 #define QUERY_FW_VER_OFFSET 0x00
1069 #define QUERY_FW_PPF_ID 0x09
1070 #define QUERY_FW_CMD_IF_REV_OFFSET 0x0a
1071 #define QUERY_FW_MAX_CMD_OFFSET 0x0f
1072 #define QUERY_FW_ERR_START_OFFSET 0x30
1073 #define QUERY_FW_ERR_SIZE_OFFSET 0x38
1074 #define QUERY_FW_ERR_BAR_OFFSET 0x3c
1075
1076 #define QUERY_FW_SIZE_OFFSET 0x00
1077 #define QUERY_FW_CLR_INT_BASE_OFFSET 0x20
1078 #define QUERY_FW_CLR_INT_BAR_OFFSET 0x28
1079
1080 #define QUERY_FW_COMM_BASE_OFFSET 0x40
1081 #define QUERY_FW_COMM_BAR_OFFSET 0x48
1082
1083 #define QUERY_FW_CLOCK_OFFSET 0x50
1084 #define QUERY_FW_CLOCK_BAR 0x58
1085
1086 mailbox = mlx4_alloc_cmd_mailbox(dev);
1087 if (IS_ERR(mailbox))
1088 return PTR_ERR(mailbox);
1089 outbox = mailbox->buf;
1090
1091 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_FW,
1092 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1093 if (err)
1094 goto out;
1095
1096 MLX4_GET(fw_ver, outbox, QUERY_FW_VER_OFFSET);
1097 /*
1098 * FW subminor version is at more significant bits than minor
1099 * version, so swap here.
1100 */
1101 dev->caps.fw_ver = (fw_ver & 0xffff00000000ull) |
1102 ((fw_ver & 0xffff0000ull) >> 16) |
1103 ((fw_ver & 0x0000ffffull) << 16);
1104
1105 MLX4_GET(lg, outbox, QUERY_FW_PPF_ID);
1106 dev->caps.function = lg;
1107
1108 if (mlx4_is_slave(dev))
1109 goto out;
1110
1111
1112 MLX4_GET(cmd_if_rev, outbox, QUERY_FW_CMD_IF_REV_OFFSET);
1113 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_MIN_REV ||
1114 cmd_if_rev > MLX4_COMMAND_INTERFACE_MAX_REV) {
1115 mlx4_err(dev, "Installed FW has unsupported "
1116 "command interface revision %d.\n",
1117 cmd_if_rev);
1118 mlx4_err(dev, "(Installed FW version is %d.%d.%03d)\n",
1119 (int) (dev->caps.fw_ver >> 32),
1120 (int) (dev->caps.fw_ver >> 16) & 0xffff,
1121 (int) dev->caps.fw_ver & 0xffff);
1122 mlx4_err(dev, "This driver version supports only revisions %d to %d.\n",
1123 MLX4_COMMAND_INTERFACE_MIN_REV, MLX4_COMMAND_INTERFACE_MAX_REV);
1124 err = -ENODEV;
1125 goto out;
1126 }
1127
1128 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS)
1129 dev->flags |= MLX4_FLAG_OLD_PORT_CMDS;
1130
1131 MLX4_GET(lg, outbox, QUERY_FW_MAX_CMD_OFFSET);
1132 cmd->max_cmds = 1 << lg;
1133
1134 mlx4_dbg(dev, "FW version %d.%d.%03d (cmd intf rev %d), max commands %d\n",
1135 (int) (dev->caps.fw_ver >> 32),
1136 (int) (dev->caps.fw_ver >> 16) & 0xffff,
1137 (int) dev->caps.fw_ver & 0xffff,
1138 cmd_if_rev, cmd->max_cmds);
1139
1140 MLX4_GET(fw->catas_offset, outbox, QUERY_FW_ERR_START_OFFSET);
1141 MLX4_GET(fw->catas_size, outbox, QUERY_FW_ERR_SIZE_OFFSET);
1142 MLX4_GET(fw->catas_bar, outbox, QUERY_FW_ERR_BAR_OFFSET);
1143 fw->catas_bar = (fw->catas_bar >> 6) * 2;
1144
1145 mlx4_dbg(dev, "Catastrophic error buffer at 0x%llx, size 0x%x, BAR %d\n",
1146 (unsigned long long) fw->catas_offset, fw->catas_size, fw->catas_bar);
1147
1148 MLX4_GET(fw->fw_pages, outbox, QUERY_FW_SIZE_OFFSET);
1149 MLX4_GET(fw->clr_int_base, outbox, QUERY_FW_CLR_INT_BASE_OFFSET);
1150 MLX4_GET(fw->clr_int_bar, outbox, QUERY_FW_CLR_INT_BAR_OFFSET);
1151 fw->clr_int_bar = (fw->clr_int_bar >> 6) * 2;
1152
1153 MLX4_GET(fw->comm_base, outbox, QUERY_FW_COMM_BASE_OFFSET);
1154 MLX4_GET(fw->comm_bar, outbox, QUERY_FW_COMM_BAR_OFFSET);
1155 fw->comm_bar = (fw->comm_bar >> 6) * 2;
1156 mlx4_dbg(dev, "Communication vector bar:%d offset:0x%llx\n",
1157 fw->comm_bar, fw->comm_base);
1158 mlx4_dbg(dev, "FW size %d KB\n", fw->fw_pages >> 2);
1159
1160 MLX4_GET(fw->clock_offset, outbox, QUERY_FW_CLOCK_OFFSET);
1161 MLX4_GET(fw->clock_bar, outbox, QUERY_FW_CLOCK_BAR);
1162 fw->clock_bar = (fw->clock_bar >> 6) * 2;
1163 mlx4_dbg(dev, "Internal clock bar:%d offset:0x%llx\n",
1164 fw->clock_bar, fw->clock_offset);
1165
1166 /*
1167 * Round up number of system pages needed in case
1168 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE.
1169 */
1170 fw->fw_pages =
1171 ALIGN(fw->fw_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >>
1172 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT);
1173
1174 mlx4_dbg(dev, "Clear int @ %llx, BAR %d\n",
1175 (unsigned long long) fw->clr_int_base, fw->clr_int_bar);
1176
1177 out:
1178 mlx4_free_cmd_mailbox(dev, mailbox);
1179 return err;
1180 }
1181
1182 int mlx4_QUERY_FW_wrapper(struct mlx4_dev *dev, int slave,
1183 struct mlx4_vhcr *vhcr,
1184 struct mlx4_cmd_mailbox *inbox,
1185 struct mlx4_cmd_mailbox *outbox,
1186 struct mlx4_cmd_info *cmd)
1187 {
1188 u8 *outbuf;
1189 int err;
1190
1191 outbuf = outbox->buf;
1192 err = mlx4_cmd_box(dev, 0, outbox->dma, 0, 0, MLX4_CMD_QUERY_FW,
1193 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1194 if (err)
1195 return err;
1196
1197 /* for slaves, set pci PPF ID to invalid and zero out everything
1198 * else except FW version */
1199 outbuf[0] = outbuf[1] = 0;
1200 memset(&outbuf[8], 0, QUERY_FW_OUT_SIZE - 8);
1201 outbuf[QUERY_FW_PPF_ID] = MLX4_INVALID_SLAVE_ID;
1202
1203 return 0;
1204 }
1205
1206 static void get_board_id(void *vsd, char *board_id)
1207 {
1208 int i;
1209
1210 #define VSD_OFFSET_SIG1 0x00
1211 #define VSD_OFFSET_SIG2 0xde
1212 #define VSD_OFFSET_MLX_BOARD_ID 0xd0
1213 #define VSD_OFFSET_TS_BOARD_ID 0x20
1214
1215 #define VSD_SIGNATURE_TOPSPIN 0x5ad
1216
1217 memset(board_id, 0, MLX4_BOARD_ID_LEN);
1218
1219 if (be16_to_cpup(vsd + VSD_OFFSET_SIG1) == VSD_SIGNATURE_TOPSPIN &&
1220 be16_to_cpup(vsd + VSD_OFFSET_SIG2) == VSD_SIGNATURE_TOPSPIN) {
1221 strlcpy(board_id, vsd + VSD_OFFSET_TS_BOARD_ID, MLX4_BOARD_ID_LEN);
1222 } else {
1223 /*
1224 * The board ID is a string but the firmware byte
1225 * swaps each 4-byte word before passing it back to
1226 * us. Therefore we need to swab it before printing.
1227 */
1228 for (i = 0; i < 4; ++i)
1229 ((u32 *) board_id)[i] =
1230 swab32(*(u32 *) (vsd + VSD_OFFSET_MLX_BOARD_ID + i * 4));
1231 }
1232 }
1233
1234 int mlx4_QUERY_ADAPTER(struct mlx4_dev *dev, struct mlx4_adapter *adapter)
1235 {
1236 struct mlx4_cmd_mailbox *mailbox;
1237 u32 *outbox;
1238 int err;
1239
1240 #define QUERY_ADAPTER_OUT_SIZE 0x100
1241 #define QUERY_ADAPTER_INTA_PIN_OFFSET 0x10
1242 #define QUERY_ADAPTER_VSD_OFFSET 0x20
1243
1244 mailbox = mlx4_alloc_cmd_mailbox(dev);
1245 if (IS_ERR(mailbox))
1246 return PTR_ERR(mailbox);
1247 outbox = mailbox->buf;
1248
1249 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_ADAPTER,
1250 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1251 if (err)
1252 goto out;
1253
1254 MLX4_GET(adapter->inta_pin, outbox, QUERY_ADAPTER_INTA_PIN_OFFSET);
1255
1256 get_board_id(outbox + QUERY_ADAPTER_VSD_OFFSET / 4,
1257 adapter->board_id);
1258
1259 out:
1260 mlx4_free_cmd_mailbox(dev, mailbox);
1261 return err;
1262 }
1263
1264 int mlx4_INIT_HCA(struct mlx4_dev *dev, struct mlx4_init_hca_param *param)
1265 {
1266 struct mlx4_cmd_mailbox *mailbox;
1267 __be32 *inbox;
1268 int err;
1269
1270 #define INIT_HCA_IN_SIZE 0x200
1271 #define INIT_HCA_VERSION_OFFSET 0x000
1272 #define INIT_HCA_VERSION 2
1273 #define INIT_HCA_CACHELINE_SZ_OFFSET 0x0e
1274 #define INIT_HCA_FLAGS_OFFSET 0x014
1275 #define INIT_HCA_QPC_OFFSET 0x020
1276 #define INIT_HCA_QPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x10)
1277 #define INIT_HCA_LOG_QP_OFFSET (INIT_HCA_QPC_OFFSET + 0x17)
1278 #define INIT_HCA_SRQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x28)
1279 #define INIT_HCA_LOG_SRQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x2f)
1280 #define INIT_HCA_CQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x30)
1281 #define INIT_HCA_LOG_CQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x37)
1282 #define INIT_HCA_EQE_CQE_OFFSETS (INIT_HCA_QPC_OFFSET + 0x38)
1283 #define INIT_HCA_ALTC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x40)
1284 #define INIT_HCA_AUXC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x50)
1285 #define INIT_HCA_EQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x60)
1286 #define INIT_HCA_LOG_EQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x67)
1287 #define INIT_HCA_RDMARC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x70)
1288 #define INIT_HCA_LOG_RD_OFFSET (INIT_HCA_QPC_OFFSET + 0x77)
1289 #define INIT_HCA_MCAST_OFFSET 0x0c0
1290 #define INIT_HCA_MC_BASE_OFFSET (INIT_HCA_MCAST_OFFSET + 0x00)
1291 #define INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x12)
1292 #define INIT_HCA_LOG_MC_HASH_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x16)
1293 #define INIT_HCA_UC_STEERING_OFFSET (INIT_HCA_MCAST_OFFSET + 0x18)
1294 #define INIT_HCA_LOG_MC_TABLE_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x1b)
1295 #define INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN 0x6
1296 #define INIT_HCA_FS_PARAM_OFFSET 0x1d0
1297 #define INIT_HCA_FS_BASE_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x00)
1298 #define INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x12)
1299 #define INIT_HCA_FS_LOG_TABLE_SZ_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x1b)
1300 #define INIT_HCA_FS_ETH_BITS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x21)
1301 #define INIT_HCA_FS_ETH_NUM_ADDRS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x22)
1302 #define INIT_HCA_FS_IB_BITS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x25)
1303 #define INIT_HCA_FS_IB_NUM_ADDRS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x26)
1304 #define INIT_HCA_TPT_OFFSET 0x0f0
1305 #define INIT_HCA_DMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x00)
1306 #define INIT_HCA_TPT_MW_OFFSET (INIT_HCA_TPT_OFFSET + 0x08)
1307 #define INIT_HCA_LOG_MPT_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x0b)
1308 #define INIT_HCA_MTT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x10)
1309 #define INIT_HCA_CMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x18)
1310 #define INIT_HCA_UAR_OFFSET 0x120
1311 #define INIT_HCA_LOG_UAR_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0a)
1312 #define INIT_HCA_UAR_PAGE_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0b)
1313
1314 mailbox = mlx4_alloc_cmd_mailbox(dev);
1315 if (IS_ERR(mailbox))
1316 return PTR_ERR(mailbox);
1317 inbox = mailbox->buf;
1318
1319 memset(inbox, 0, INIT_HCA_IN_SIZE);
1320
1321 *((u8 *) mailbox->buf + INIT_HCA_VERSION_OFFSET) = INIT_HCA_VERSION;
1322
1323 *((u8 *) mailbox->buf + INIT_HCA_CACHELINE_SZ_OFFSET) =
1324 (ilog2(cache_line_size()) - 4) << 5;
1325
1326 #if defined(__LITTLE_ENDIAN)
1327 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) &= ~cpu_to_be32(1 << 1);
1328 #elif defined(__BIG_ENDIAN)
1329 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 1);
1330 #else
1331 #error Host endianness not defined
1332 #endif
1333 /* Check port for UD address vector: */
1334 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1);
1335
1336 /* Enable IPoIB checksumming if we can: */
1337 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_IPOIB_CSUM)
1338 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 3);
1339
1340 /* Enable QoS support if module parameter set */
1341 if (enable_qos)
1342 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 2);
1343
1344 /* enable counters */
1345 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS)
1346 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 4);
1347
1348 /* CX3 is capable of extending CQEs/EQEs from 32 to 64 bytes */
1349 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_64B_EQE) {
1350 *(inbox + INIT_HCA_EQE_CQE_OFFSETS / 4) |= cpu_to_be32(1 << 29);
1351 dev->caps.eqe_size = 64;
1352 dev->caps.eqe_factor = 1;
1353 } else {
1354 dev->caps.eqe_size = 32;
1355 dev->caps.eqe_factor = 0;
1356 }
1357
1358 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_64B_CQE) {
1359 *(inbox + INIT_HCA_EQE_CQE_OFFSETS / 4) |= cpu_to_be32(1 << 30);
1360 dev->caps.cqe_size = 64;
1361 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_64B_CQE;
1362 } else {
1363 dev->caps.cqe_size = 32;
1364 }
1365
1366 /* QPC/EEC/CQC/EQC/RDMARC attributes */
1367
1368 MLX4_PUT(inbox, param->qpc_base, INIT_HCA_QPC_BASE_OFFSET);
1369 MLX4_PUT(inbox, param->log_num_qps, INIT_HCA_LOG_QP_OFFSET);
1370 MLX4_PUT(inbox, param->srqc_base, INIT_HCA_SRQC_BASE_OFFSET);
1371 MLX4_PUT(inbox, param->log_num_srqs, INIT_HCA_LOG_SRQ_OFFSET);
1372 MLX4_PUT(inbox, param->cqc_base, INIT_HCA_CQC_BASE_OFFSET);
1373 MLX4_PUT(inbox, param->log_num_cqs, INIT_HCA_LOG_CQ_OFFSET);
1374 MLX4_PUT(inbox, param->altc_base, INIT_HCA_ALTC_BASE_OFFSET);
1375 MLX4_PUT(inbox, param->auxc_base, INIT_HCA_AUXC_BASE_OFFSET);
1376 MLX4_PUT(inbox, param->eqc_base, INIT_HCA_EQC_BASE_OFFSET);
1377 MLX4_PUT(inbox, param->log_num_eqs, INIT_HCA_LOG_EQ_OFFSET);
1378 MLX4_PUT(inbox, param->rdmarc_base, INIT_HCA_RDMARC_BASE_OFFSET);
1379 MLX4_PUT(inbox, param->log_rd_per_qp, INIT_HCA_LOG_RD_OFFSET);
1380
1381 /* steering attributes */
1382 if (dev->caps.steering_mode ==
1383 MLX4_STEERING_MODE_DEVICE_MANAGED) {
1384 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |=
1385 cpu_to_be32(1 <<
1386 INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN);
1387
1388 MLX4_PUT(inbox, param->mc_base, INIT_HCA_FS_BASE_OFFSET);
1389 MLX4_PUT(inbox, param->log_mc_entry_sz,
1390 INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET);
1391 MLX4_PUT(inbox, param->log_mc_table_sz,
1392 INIT_HCA_FS_LOG_TABLE_SZ_OFFSET);
1393 /* Enable Ethernet flow steering
1394 * with udp unicast and tcp unicast
1395 */
1396 MLX4_PUT(inbox, (u8) (MLX4_FS_UDP_UC_EN | MLX4_FS_TCP_UC_EN),
1397 INIT_HCA_FS_ETH_BITS_OFFSET);
1398 MLX4_PUT(inbox, (u16) MLX4_FS_NUM_OF_L2_ADDR,
1399 INIT_HCA_FS_ETH_NUM_ADDRS_OFFSET);
1400 /* Enable IPoIB flow steering
1401 * with udp unicast and tcp unicast
1402 */
1403 MLX4_PUT(inbox, (u8) (MLX4_FS_UDP_UC_EN | MLX4_FS_TCP_UC_EN),
1404 INIT_HCA_FS_IB_BITS_OFFSET);
1405 MLX4_PUT(inbox, (u16) MLX4_FS_NUM_OF_L2_ADDR,
1406 INIT_HCA_FS_IB_NUM_ADDRS_OFFSET);
1407 } else {
1408 MLX4_PUT(inbox, param->mc_base, INIT_HCA_MC_BASE_OFFSET);
1409 MLX4_PUT(inbox, param->log_mc_entry_sz,
1410 INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET);
1411 MLX4_PUT(inbox, param->log_mc_hash_sz,
1412 INIT_HCA_LOG_MC_HASH_SZ_OFFSET);
1413 MLX4_PUT(inbox, param->log_mc_table_sz,
1414 INIT_HCA_LOG_MC_TABLE_SZ_OFFSET);
1415 if (dev->caps.steering_mode == MLX4_STEERING_MODE_B0)
1416 MLX4_PUT(inbox, (u8) (1 << 3),
1417 INIT_HCA_UC_STEERING_OFFSET);
1418 }
1419
1420 /* TPT attributes */
1421
1422 MLX4_PUT(inbox, param->dmpt_base, INIT_HCA_DMPT_BASE_OFFSET);
1423 MLX4_PUT(inbox, param->mw_enabled, INIT_HCA_TPT_MW_OFFSET);
1424 MLX4_PUT(inbox, param->log_mpt_sz, INIT_HCA_LOG_MPT_SZ_OFFSET);
1425 MLX4_PUT(inbox, param->mtt_base, INIT_HCA_MTT_BASE_OFFSET);
1426 MLX4_PUT(inbox, param->cmpt_base, INIT_HCA_CMPT_BASE_OFFSET);
1427
1428 /* UAR attributes */
1429
1430 MLX4_PUT(inbox, param->uar_page_sz, INIT_HCA_UAR_PAGE_SZ_OFFSET);
1431 MLX4_PUT(inbox, param->log_uar_sz, INIT_HCA_LOG_UAR_SZ_OFFSET);
1432
1433 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_INIT_HCA, 10000,
1434 MLX4_CMD_NATIVE);
1435
1436 if (err)
1437 mlx4_err(dev, "INIT_HCA returns %d\n", err);
1438
1439 mlx4_free_cmd_mailbox(dev, mailbox);
1440 return err;
1441 }
1442
1443 int mlx4_QUERY_HCA(struct mlx4_dev *dev,
1444 struct mlx4_init_hca_param *param)
1445 {
1446 struct mlx4_cmd_mailbox *mailbox;
1447 __be32 *outbox;
1448 u32 dword_field;
1449 int err;
1450 u8 byte_field;
1451
1452 #define QUERY_HCA_GLOBAL_CAPS_OFFSET 0x04
1453 #define QUERY_HCA_CORE_CLOCK_OFFSET 0x0c
1454
1455 mailbox = mlx4_alloc_cmd_mailbox(dev);
1456 if (IS_ERR(mailbox))
1457 return PTR_ERR(mailbox);
1458 outbox = mailbox->buf;
1459
1460 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0,
1461 MLX4_CMD_QUERY_HCA,
1462 MLX4_CMD_TIME_CLASS_B,
1463 !mlx4_is_slave(dev));
1464 if (err)
1465 goto out;
1466
1467 MLX4_GET(param->global_caps, outbox, QUERY_HCA_GLOBAL_CAPS_OFFSET);
1468 MLX4_GET(param->hca_core_clock, outbox, QUERY_HCA_CORE_CLOCK_OFFSET);
1469
1470 /* QPC/EEC/CQC/EQC/RDMARC attributes */
1471
1472 MLX4_GET(param->qpc_base, outbox, INIT_HCA_QPC_BASE_OFFSET);
1473 MLX4_GET(param->log_num_qps, outbox, INIT_HCA_LOG_QP_OFFSET);
1474 MLX4_GET(param->srqc_base, outbox, INIT_HCA_SRQC_BASE_OFFSET);
1475 MLX4_GET(param->log_num_srqs, outbox, INIT_HCA_LOG_SRQ_OFFSET);
1476 MLX4_GET(param->cqc_base, outbox, INIT_HCA_CQC_BASE_OFFSET);
1477 MLX4_GET(param->log_num_cqs, outbox, INIT_HCA_LOG_CQ_OFFSET);
1478 MLX4_GET(param->altc_base, outbox, INIT_HCA_ALTC_BASE_OFFSET);
1479 MLX4_GET(param->auxc_base, outbox, INIT_HCA_AUXC_BASE_OFFSET);
1480 MLX4_GET(param->eqc_base, outbox, INIT_HCA_EQC_BASE_OFFSET);
1481 MLX4_GET(param->log_num_eqs, outbox, INIT_HCA_LOG_EQ_OFFSET);
1482 MLX4_GET(param->rdmarc_base, outbox, INIT_HCA_RDMARC_BASE_OFFSET);
1483 MLX4_GET(param->log_rd_per_qp, outbox, INIT_HCA_LOG_RD_OFFSET);
1484
1485 MLX4_GET(dword_field, outbox, INIT_HCA_FLAGS_OFFSET);
1486 if (dword_field & (1 << INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN)) {
1487 param->steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED;
1488 } else {
1489 MLX4_GET(byte_field, outbox, INIT_HCA_UC_STEERING_OFFSET);
1490 if (byte_field & 0x8)
1491 param->steering_mode = MLX4_STEERING_MODE_B0;
1492 else
1493 param->steering_mode = MLX4_STEERING_MODE_A0;
1494 }
1495 /* steering attributes */
1496 if (param->steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) {
1497 MLX4_GET(param->mc_base, outbox, INIT_HCA_FS_BASE_OFFSET);
1498 MLX4_GET(param->log_mc_entry_sz, outbox,
1499 INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET);
1500 MLX4_GET(param->log_mc_table_sz, outbox,
1501 INIT_HCA_FS_LOG_TABLE_SZ_OFFSET);
1502 } else {
1503 MLX4_GET(param->mc_base, outbox, INIT_HCA_MC_BASE_OFFSET);
1504 MLX4_GET(param->log_mc_entry_sz, outbox,
1505 INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET);
1506 MLX4_GET(param->log_mc_hash_sz, outbox,
1507 INIT_HCA_LOG_MC_HASH_SZ_OFFSET);
1508 MLX4_GET(param->log_mc_table_sz, outbox,
1509 INIT_HCA_LOG_MC_TABLE_SZ_OFFSET);
1510 }
1511
1512 /* CX3 is capable of extending CQEs/EQEs from 32 to 64 bytes */
1513 MLX4_GET(byte_field, outbox, INIT_HCA_EQE_CQE_OFFSETS);
1514 if (byte_field & 0x20) /* 64-bytes eqe enabled */
1515 param->dev_cap_enabled |= MLX4_DEV_CAP_64B_EQE_ENABLED;
1516 if (byte_field & 0x40) /* 64-bytes cqe enabled */
1517 param->dev_cap_enabled |= MLX4_DEV_CAP_64B_CQE_ENABLED;
1518
1519 /* TPT attributes */
1520
1521 MLX4_GET(param->dmpt_base, outbox, INIT_HCA_DMPT_BASE_OFFSET);
1522 MLX4_GET(param->mw_enabled, outbox, INIT_HCA_TPT_MW_OFFSET);
1523 MLX4_GET(param->log_mpt_sz, outbox, INIT_HCA_LOG_MPT_SZ_OFFSET);
1524 MLX4_GET(param->mtt_base, outbox, INIT_HCA_MTT_BASE_OFFSET);
1525 MLX4_GET(param->cmpt_base, outbox, INIT_HCA_CMPT_BASE_OFFSET);
1526
1527 /* UAR attributes */
1528
1529 MLX4_GET(param->uar_page_sz, outbox, INIT_HCA_UAR_PAGE_SZ_OFFSET);
1530 MLX4_GET(param->log_uar_sz, outbox, INIT_HCA_LOG_UAR_SZ_OFFSET);
1531
1532 out:
1533 mlx4_free_cmd_mailbox(dev, mailbox);
1534
1535 return err;
1536 }
1537
1538 /* for IB-type ports only in SRIOV mode. Checks that both proxy QP0
1539 * and real QP0 are active, so that the paravirtualized QP0 is ready
1540 * to operate */
1541 static int check_qp0_state(struct mlx4_dev *dev, int function, int port)
1542 {
1543 struct mlx4_priv *priv = mlx4_priv(dev);
1544 /* irrelevant if not infiniband */
1545 if (priv->mfunc.master.qp0_state[port].proxy_qp0_active &&
1546 priv->mfunc.master.qp0_state[port].qp0_active)
1547 return 1;
1548 return 0;
1549 }
1550
1551 int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave,
1552 struct mlx4_vhcr *vhcr,
1553 struct mlx4_cmd_mailbox *inbox,
1554 struct mlx4_cmd_mailbox *outbox,
1555 struct mlx4_cmd_info *cmd)
1556 {
1557 struct mlx4_priv *priv = mlx4_priv(dev);
1558 int port = vhcr->in_modifier;
1559 int err;
1560
1561 if (priv->mfunc.master.slave_state[slave].init_port_mask & (1 << port))
1562 return 0;
1563
1564 if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB) {
1565 /* Enable port only if it was previously disabled */
1566 if (!priv->mfunc.master.init_port_ref[port]) {
1567 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
1568 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1569 if (err)
1570 return err;
1571 }
1572 priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port);
1573 } else {
1574 if (slave == mlx4_master_func_num(dev)) {
1575 if (check_qp0_state(dev, slave, port) &&
1576 !priv->mfunc.master.qp0_state[port].port_active) {
1577 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
1578 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1579 if (err)
1580 return err;
1581 priv->mfunc.master.qp0_state[port].port_active = 1;
1582 priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port);
1583 }
1584 } else
1585 priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port);
1586 }
1587 ++priv->mfunc.master.init_port_ref[port];
1588 return 0;
1589 }
1590
1591 int mlx4_INIT_PORT(struct mlx4_dev *dev, int port)
1592 {
1593 struct mlx4_cmd_mailbox *mailbox;
1594 u32 *inbox;
1595 int err;
1596 u32 flags;
1597 u16 field;
1598
1599 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
1600 #define INIT_PORT_IN_SIZE 256
1601 #define INIT_PORT_FLAGS_OFFSET 0x00
1602 #define INIT_PORT_FLAG_SIG (1 << 18)
1603 #define INIT_PORT_FLAG_NG (1 << 17)
1604 #define INIT_PORT_FLAG_G0 (1 << 16)
1605 #define INIT_PORT_VL_SHIFT 4
1606 #define INIT_PORT_PORT_WIDTH_SHIFT 8
1607 #define INIT_PORT_MTU_OFFSET 0x04
1608 #define INIT_PORT_MAX_GID_OFFSET 0x06
1609 #define INIT_PORT_MAX_PKEY_OFFSET 0x0a
1610 #define INIT_PORT_GUID0_OFFSET 0x10
1611 #define INIT_PORT_NODE_GUID_OFFSET 0x18
1612 #define INIT_PORT_SI_GUID_OFFSET 0x20
1613
1614 mailbox = mlx4_alloc_cmd_mailbox(dev);
1615 if (IS_ERR(mailbox))
1616 return PTR_ERR(mailbox);
1617 inbox = mailbox->buf;
1618
1619 memset(inbox, 0, INIT_PORT_IN_SIZE);
1620
1621 flags = 0;
1622 flags |= (dev->caps.vl_cap[port] & 0xf) << INIT_PORT_VL_SHIFT;
1623 flags |= (dev->caps.port_width_cap[port] & 0xf) << INIT_PORT_PORT_WIDTH_SHIFT;
1624 MLX4_PUT(inbox, flags, INIT_PORT_FLAGS_OFFSET);
1625
1626 field = 128 << dev->caps.ib_mtu_cap[port];
1627 MLX4_PUT(inbox, field, INIT_PORT_MTU_OFFSET);
1628 field = dev->caps.gid_table_len[port];
1629 MLX4_PUT(inbox, field, INIT_PORT_MAX_GID_OFFSET);
1630 field = dev->caps.pkey_table_len[port];
1631 MLX4_PUT(inbox, field, INIT_PORT_MAX_PKEY_OFFSET);
1632
1633 err = mlx4_cmd(dev, mailbox->dma, port, 0, MLX4_CMD_INIT_PORT,
1634 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1635
1636 mlx4_free_cmd_mailbox(dev, mailbox);
1637 } else
1638 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
1639 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
1640
1641 return err;
1642 }
1643 EXPORT_SYMBOL_GPL(mlx4_INIT_PORT);
1644
1645 int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave,
1646 struct mlx4_vhcr *vhcr,
1647 struct mlx4_cmd_mailbox *inbox,
1648 struct mlx4_cmd_mailbox *outbox,
1649 struct mlx4_cmd_info *cmd)
1650 {
1651 struct mlx4_priv *priv = mlx4_priv(dev);
1652 int port = vhcr->in_modifier;
1653 int err;
1654
1655 if (!(priv->mfunc.master.slave_state[slave].init_port_mask &
1656 (1 << port)))
1657 return 0;
1658
1659 if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB) {
1660 if (priv->mfunc.master.init_port_ref[port] == 1) {
1661 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT,
1662 1000, MLX4_CMD_NATIVE);
1663 if (err)
1664 return err;
1665 }
1666 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port);
1667 } else {
1668 /* infiniband port */
1669 if (slave == mlx4_master_func_num(dev)) {
1670 if (!priv->mfunc.master.qp0_state[port].qp0_active &&
1671 priv->mfunc.master.qp0_state[port].port_active) {
1672 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT,
1673 1000, MLX4_CMD_NATIVE);
1674 if (err)
1675 return err;
1676 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port);
1677 priv->mfunc.master.qp0_state[port].port_active = 0;
1678 }
1679 } else
1680 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port);
1681 }
1682 --priv->mfunc.master.init_port_ref[port];
1683 return 0;
1684 }
1685
1686 int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port)
1687 {
1688 return mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, 1000,
1689 MLX4_CMD_WRAPPED);
1690 }
1691 EXPORT_SYMBOL_GPL(mlx4_CLOSE_PORT);
1692
1693 int mlx4_CLOSE_HCA(struct mlx4_dev *dev, int panic)
1694 {
1695 return mlx4_cmd(dev, 0, 0, panic, MLX4_CMD_CLOSE_HCA, 1000,
1696 MLX4_CMD_NATIVE);
1697 }
1698
1699 int mlx4_SET_ICM_SIZE(struct mlx4_dev *dev, u64 icm_size, u64 *aux_pages)
1700 {
1701 int ret = mlx4_cmd_imm(dev, icm_size, aux_pages, 0, 0,
1702 MLX4_CMD_SET_ICM_SIZE,
1703 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1704 if (ret)
1705 return ret;
1706
1707 /*
1708 * Round up number of system pages needed in case
1709 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE.
1710 */
1711 *aux_pages = ALIGN(*aux_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >>
1712 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT);
1713
1714 return 0;
1715 }
1716
1717 int mlx4_NOP(struct mlx4_dev *dev)
1718 {
1719 /* Input modifier of 0x1f means "finish as soon as possible." */
1720 return mlx4_cmd(dev, 0, 0x1f, 0, MLX4_CMD_NOP, 100, MLX4_CMD_NATIVE);
1721 }
1722
1723 #define MLX4_WOL_SETUP_MODE (5 << 28)
1724 int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port)
1725 {
1726 u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8;
1727
1728 return mlx4_cmd_imm(dev, 0, config, in_mod, 0x3,
1729 MLX4_CMD_MOD_STAT_CFG, MLX4_CMD_TIME_CLASS_A,
1730 MLX4_CMD_NATIVE);
1731 }
1732 EXPORT_SYMBOL_GPL(mlx4_wol_read);
1733
1734 int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port)
1735 {
1736 u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8;
1737
1738 return mlx4_cmd(dev, config, in_mod, 0x1, MLX4_CMD_MOD_STAT_CFG,
1739 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1740 }
1741 EXPORT_SYMBOL_GPL(mlx4_wol_write);
1742
1743 enum {
1744 ADD_TO_MCG = 0x26,
1745 };
1746
1747
1748 void mlx4_opreq_action(struct work_struct *work)
1749 {
1750 struct mlx4_priv *priv = container_of(work, struct mlx4_priv,
1751 opreq_task);
1752 struct mlx4_dev *dev = &priv->dev;
1753 int num_tasks = atomic_read(&priv->opreq_count);
1754 struct mlx4_cmd_mailbox *mailbox;
1755 struct mlx4_mgm *mgm;
1756 u32 *outbox;
1757 u32 modifier;
1758 u16 token;
1759 u16 type;
1760 int err;
1761 u32 num_qps;
1762 struct mlx4_qp qp;
1763 int i;
1764 u8 rem_mcg;
1765 u8 prot;
1766
1767 #define GET_OP_REQ_MODIFIER_OFFSET 0x08
1768 #define GET_OP_REQ_TOKEN_OFFSET 0x14
1769 #define GET_OP_REQ_TYPE_OFFSET 0x1a
1770 #define GET_OP_REQ_DATA_OFFSET 0x20
1771
1772 mailbox = mlx4_alloc_cmd_mailbox(dev);
1773 if (IS_ERR(mailbox)) {
1774 mlx4_err(dev, "Failed to allocate mailbox for GET_OP_REQ\n");
1775 return;
1776 }
1777 outbox = mailbox->buf;
1778
1779 while (num_tasks) {
1780 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0,
1781 MLX4_CMD_GET_OP_REQ, MLX4_CMD_TIME_CLASS_A,
1782 MLX4_CMD_NATIVE);
1783 if (err) {
1784 mlx4_err(dev, "Failed to retreive required operation: %d\n",
1785 err);
1786 return;
1787 }
1788 MLX4_GET(modifier, outbox, GET_OP_REQ_MODIFIER_OFFSET);
1789 MLX4_GET(token, outbox, GET_OP_REQ_TOKEN_OFFSET);
1790 MLX4_GET(type, outbox, GET_OP_REQ_TYPE_OFFSET);
1791 type &= 0xfff;
1792
1793 switch (type) {
1794 case ADD_TO_MCG:
1795 if (dev->caps.steering_mode ==
1796 MLX4_STEERING_MODE_DEVICE_MANAGED) {
1797 mlx4_warn(dev, "ADD MCG operation is not supported in DEVICE_MANAGED steering mode\n");
1798 err = EPERM;
1799 break;
1800 }
1801 mgm = (struct mlx4_mgm *)((u8 *)(outbox) +
1802 GET_OP_REQ_DATA_OFFSET);
1803 num_qps = be32_to_cpu(mgm->members_count) &
1804 MGM_QPN_MASK;
1805 rem_mcg = ((u8 *)(&mgm->members_count))[0] & 1;
1806 prot = ((u8 *)(&mgm->members_count))[0] >> 6;
1807
1808 for (i = 0; i < num_qps; i++) {
1809 qp.qpn = be32_to_cpu(mgm->qp[i]);
1810 if (rem_mcg)
1811 err = mlx4_multicast_detach(dev, &qp,
1812 mgm->gid,
1813 prot, 0);
1814 else
1815 err = mlx4_multicast_attach(dev, &qp,
1816 mgm->gid,
1817 mgm->gid[5]
1818 , 0, prot,
1819 NULL);
1820 if (err)
1821 break;
1822 }
1823 break;
1824 default:
1825 mlx4_warn(dev, "Bad type for required operation\n");
1826 err = EINVAL;
1827 break;
1828 }
1829 err = mlx4_cmd(dev, 0, ((u32) err | cpu_to_be32(token) << 16),
1830 1, MLX4_CMD_GET_OP_REQ, MLX4_CMD_TIME_CLASS_A,
1831 MLX4_CMD_NATIVE);
1832 if (err) {
1833 mlx4_err(dev, "Failed to acknowledge required request: %d\n",
1834 err);
1835 goto out;
1836 }
1837 memset(outbox, 0, 0xffc);
1838 num_tasks = atomic_dec_return(&priv->opreq_count);
1839 }
1840
1841 out:
1842 mlx4_free_cmd_mailbox(dev, mailbox);
1843 }
Linux kernel - Deliverables
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