projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
mlx4: Use port management change event instead of smp_snoop
[deliverable/linux.git] / drivers / net / ethernet / mellanox / mlx4 / fw.c
1 /*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35 #include <linux/etherdevice.h>
36 #include <linux/mlx4/cmd.h>
37 #include <linux/module.h>
38 #include <linux/cache.h>
39
40 #include "fw.h"
41 #include "icm.h"
42
43 enum {
44 MLX4_COMMAND_INTERFACE_MIN_REV = 2,
45 MLX4_COMMAND_INTERFACE_MAX_REV = 3,
46 MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS = 3,
47 };
48
49 extern void __buggy_use_of_MLX4_GET(void);
50 extern void __buggy_use_of_MLX4_PUT(void);
51
52 static bool enable_qos;
53 module_param(enable_qos, bool, 0444);
54 MODULE_PARM_DESC(enable_qos, "Enable Quality of Service support in the HCA (default: off)");
55
56 #define MLX4_GET(dest, source, offset) \
57 do { \
58 void *__p = (char *) (source) + (offset); \
59 switch (sizeof (dest)) { \
60 case 1: (dest) = *(u8 *) __p; break; \
61 case 2: (dest) = be16_to_cpup(__p); break; \
62 case 4: (dest) = be32_to_cpup(__p); break; \
63 case 8: (dest) = be64_to_cpup(__p); break; \
64 default: __buggy_use_of_MLX4_GET(); \
65 } \
66 } while (0)
67
68 #define MLX4_PUT(dest, source, offset) \
69 do { \
70 void *__d = ((char *) (dest) + (offset)); \
71 switch (sizeof(source)) { \
72 case 1: *(u8 *) __d = (source); break; \
73 case 2: *(__be16 *) __d = cpu_to_be16(source); break; \
74 case 4: *(__be32 *) __d = cpu_to_be32(source); break; \
75 case 8: *(__be64 *) __d = cpu_to_be64(source); break; \
76 default: __buggy_use_of_MLX4_PUT(); \
77 } \
78 } while (0)
79
80 static void dump_dev_cap_flags(struct mlx4_dev *dev, u64 flags)
81 {
82 static const char *fname[] = {
83 [ 0] = "RC transport",
84 [ 1] = "UC transport",
85 [ 2] = "UD transport",
86 [ 3] = "XRC transport",
87 [ 4] = "reliable multicast",
88 [ 5] = "FCoIB support",
89 [ 6] = "SRQ support",
90 [ 7] = "IPoIB checksum offload",
91 [ 8] = "P_Key violation counter",
92 [ 9] = "Q_Key violation counter",
93 [10] = "VMM",
94 [12] = "DPDP",
95 [15] = "Big LSO headers",
96 [16] = "MW support",
97 [17] = "APM support",
98 [18] = "Atomic ops support",
99 [19] = "Raw multicast support",
100 [20] = "Address vector port checking support",
101 [21] = "UD multicast support",
102 [24] = "Demand paging support",
103 [25] = "Router support",
104 [30] = "IBoE support",
105 [32] = "Unicast loopback support",
106 [34] = "FCS header control",
107 [38] = "Wake On LAN support",
108 [40] = "UDP RSS support",
109 [41] = "Unicast VEP steering support",
110 [42] = "Multicast VEP steering support",
111 [48] = "Counters support",
112 [59] = "Port management change event support",
113 };
114 int i;
115
116 mlx4_dbg(dev, "DEV_CAP flags:\n");
117 for (i = 0; i < ARRAY_SIZE(fname); ++i)
118 if (fname[i] && (flags & (1LL << i)))
119 mlx4_dbg(dev, " %s\n", fname[i]);
120 }
121
122 static void dump_dev_cap_flags2(struct mlx4_dev *dev, u64 flags)
123 {
124 static const char * const fname[] = {
125 [0] = "RSS support",
126 [1] = "RSS Toeplitz Hash Function support",
127 [2] = "RSS XOR Hash Function support"
128 };
129 int i;
130
131 for (i = 0; i < ARRAY_SIZE(fname); ++i)
132 if (fname[i] && (flags & (1LL << i)))
133 mlx4_dbg(dev, " %s\n", fname[i]);
134 }
135
136 int mlx4_MOD_STAT_CFG(struct mlx4_dev *dev, struct mlx4_mod_stat_cfg *cfg)
137 {
138 struct mlx4_cmd_mailbox *mailbox;
139 u32 *inbox;
140 int err = 0;
141
142 #define MOD_STAT_CFG_IN_SIZE 0x100
143
144 #define MOD_STAT_CFG_PG_SZ_M_OFFSET 0x002
145 #define MOD_STAT_CFG_PG_SZ_OFFSET 0x003
146
147 mailbox = mlx4_alloc_cmd_mailbox(dev);
148 if (IS_ERR(mailbox))
149 return PTR_ERR(mailbox);
150 inbox = mailbox->buf;
151
152 memset(inbox, 0, MOD_STAT_CFG_IN_SIZE);
153
154 MLX4_PUT(inbox, cfg->log_pg_sz, MOD_STAT_CFG_PG_SZ_OFFSET);
155 MLX4_PUT(inbox, cfg->log_pg_sz_m, MOD_STAT_CFG_PG_SZ_M_OFFSET);
156
157 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_MOD_STAT_CFG,
158 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
159
160 mlx4_free_cmd_mailbox(dev, mailbox);
161 return err;
162 }
163
164 int mlx4_QUERY_FUNC_CAP_wrapper(struct mlx4_dev *dev, int slave,
165 struct mlx4_vhcr *vhcr,
166 struct mlx4_cmd_mailbox *inbox,
167 struct mlx4_cmd_mailbox *outbox,
168 struct mlx4_cmd_info *cmd)
169 {
170 u8 field;
171 u32 size;
172 int err = 0;
173
174 #define QUERY_FUNC_CAP_FLAGS_OFFSET 0x0
175 #define QUERY_FUNC_CAP_NUM_PORTS_OFFSET 0x1
176 #define QUERY_FUNC_CAP_PF_BHVR_OFFSET 0x4
177 #define QUERY_FUNC_CAP_QP_QUOTA_OFFSET 0x10
178 #define QUERY_FUNC_CAP_CQ_QUOTA_OFFSET 0x14
179 #define QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET 0x18
180 #define QUERY_FUNC_CAP_MPT_QUOTA_OFFSET 0x20
181 #define QUERY_FUNC_CAP_MTT_QUOTA_OFFSET 0x24
182 #define QUERY_FUNC_CAP_MCG_QUOTA_OFFSET 0x28
183 #define QUERY_FUNC_CAP_MAX_EQ_OFFSET 0x2c
184 #define QUERY_FUNC_CAP_RESERVED_EQ_OFFSET 0X30
185
186 #define QUERY_FUNC_CAP_PHYS_PORT_OFFSET 0x3
187 #define QUERY_FUNC_CAP_ETH_PROPS_OFFSET 0xc
188
189 if (vhcr->op_modifier == 1) {
190 field = vhcr->in_modifier;
191 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_PHYS_PORT_OFFSET);
192
193 field = 0; /* ensure fvl bit is not set */
194 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_ETH_PROPS_OFFSET);
195 } else if (vhcr->op_modifier == 0) {
196 field = 1 << 7; /* enable only ethernet interface */
197 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FLAGS_OFFSET);
198
199 field = dev->caps.num_ports;
200 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_NUM_PORTS_OFFSET);
201
202 size = 0; /* no PF behavious is set for now */
203 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_PF_BHVR_OFFSET);
204
205 size = dev->caps.num_qps;
206 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP_QUOTA_OFFSET);
207
208 size = dev->caps.num_srqs;
209 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET);
210
211 size = dev->caps.num_cqs;
212 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET);
213
214 size = dev->caps.num_eqs;
215 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MAX_EQ_OFFSET);
216
217 size = dev->caps.reserved_eqs;
218 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET);
219
220 size = dev->caps.num_mpts;
221 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET);
222
223 size = dev->caps.num_mtts;
224 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET);
225
226 size = dev->caps.num_mgms + dev->caps.num_amgms;
227 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET);
228
229 } else
230 err = -EINVAL;
231
232 return err;
233 }
234
235 int mlx4_QUERY_FUNC_CAP(struct mlx4_dev *dev, struct mlx4_func_cap *func_cap)
236 {
237 struct mlx4_cmd_mailbox *mailbox;
238 u32 *outbox;
239 u8 field;
240 u32 size;
241 int i;
242 int err = 0;
243
244
245 mailbox = mlx4_alloc_cmd_mailbox(dev);
246 if (IS_ERR(mailbox))
247 return PTR_ERR(mailbox);
248
249 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_FUNC_CAP,
250 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
251 if (err)
252 goto out;
253
254 outbox = mailbox->buf;
255
256 MLX4_GET(field, outbox, QUERY_FUNC_CAP_FLAGS_OFFSET);
257 if (!(field & (1 << 7))) {
258 mlx4_err(dev, "The host doesn't support eth interface\n");
259 err = -EPROTONOSUPPORT;
260 goto out;
261 }
262
263 MLX4_GET(field, outbox, QUERY_FUNC_CAP_NUM_PORTS_OFFSET);
264 func_cap->num_ports = field;
265
266 MLX4_GET(size, outbox, QUERY_FUNC_CAP_PF_BHVR_OFFSET);
267 func_cap->pf_context_behaviour = size;
268
269 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP_QUOTA_OFFSET);
270 func_cap->qp_quota = size & 0xFFFFFF;
271
272 MLX4_GET(size, outbox, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET);
273 func_cap->srq_quota = size & 0xFFFFFF;
274
275 MLX4_GET(size, outbox, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET);
276 func_cap->cq_quota = size & 0xFFFFFF;
277
278 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MAX_EQ_OFFSET);
279 func_cap->max_eq = size & 0xFFFFFF;
280
281 MLX4_GET(size, outbox, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET);
282 func_cap->reserved_eq = size & 0xFFFFFF;
283
284 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET);
285 func_cap->mpt_quota = size & 0xFFFFFF;
286
287 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET);
288 func_cap->mtt_quota = size & 0xFFFFFF;
289
290 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET);
291 func_cap->mcg_quota = size & 0xFFFFFF;
292
293 for (i = 1; i <= func_cap->num_ports; ++i) {
294 err = mlx4_cmd_box(dev, 0, mailbox->dma, i, 1,
295 MLX4_CMD_QUERY_FUNC_CAP,
296 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
297 if (err)
298 goto out;
299
300 MLX4_GET(field, outbox, QUERY_FUNC_CAP_ETH_PROPS_OFFSET);
301 if (field & (1 << 7)) {
302 mlx4_err(dev, "VLAN is enforced on this port\n");
303 err = -EPROTONOSUPPORT;
304 goto out;
305 }
306
307 if (field & (1 << 6)) {
308 mlx4_err(dev, "Force mac is enabled on this port\n");
309 err = -EPROTONOSUPPORT;
310 goto out;
311 }
312
313 MLX4_GET(field, outbox, QUERY_FUNC_CAP_PHYS_PORT_OFFSET);
314 func_cap->physical_port[i] = field;
315 }
316
317 /* All other resources are allocated by the master, but we still report
318 * 'num' and 'reserved' capabilities as follows:
319 * - num remains the maximum resource index
320 * - 'num - reserved' is the total available objects of a resource, but
321 * resource indices may be less than 'reserved'
322 * TODO: set per-resource quotas */
323
324 out:
325 mlx4_free_cmd_mailbox(dev, mailbox);
326
327 return err;
328 }
329
330 int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
331 {
332 struct mlx4_cmd_mailbox *mailbox;
333 u32 *outbox;
334 u8 field;
335 u32 field32, flags, ext_flags;
336 u16 size;
337 u16 stat_rate;
338 int err;
339 int i;
340
341 #define QUERY_DEV_CAP_OUT_SIZE 0x100
342 #define QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET 0x10
343 #define QUERY_DEV_CAP_MAX_QP_SZ_OFFSET 0x11
344 #define QUERY_DEV_CAP_RSVD_QP_OFFSET 0x12
345 #define QUERY_DEV_CAP_MAX_QP_OFFSET 0x13
346 #define QUERY_DEV_CAP_RSVD_SRQ_OFFSET 0x14
347 #define QUERY_DEV_CAP_MAX_SRQ_OFFSET 0x15
348 #define QUERY_DEV_CAP_RSVD_EEC_OFFSET 0x16
349 #define QUERY_DEV_CAP_MAX_EEC_OFFSET 0x17
350 #define QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET 0x19
351 #define QUERY_DEV_CAP_RSVD_CQ_OFFSET 0x1a
352 #define QUERY_DEV_CAP_MAX_CQ_OFFSET 0x1b
353 #define QUERY_DEV_CAP_MAX_MPT_OFFSET 0x1d
354 #define QUERY_DEV_CAP_RSVD_EQ_OFFSET 0x1e
355 #define QUERY_DEV_CAP_MAX_EQ_OFFSET 0x1f
356 #define QUERY_DEV_CAP_RSVD_MTT_OFFSET 0x20
357 #define QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET 0x21
358 #define QUERY_DEV_CAP_RSVD_MRW_OFFSET 0x22
359 #define QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET 0x23
360 #define QUERY_DEV_CAP_MAX_AV_OFFSET 0x27
361 #define QUERY_DEV_CAP_MAX_REQ_QP_OFFSET 0x29
362 #define QUERY_DEV_CAP_MAX_RES_QP_OFFSET 0x2b
363 #define QUERY_DEV_CAP_MAX_GSO_OFFSET 0x2d
364 #define QUERY_DEV_CAP_RSS_OFFSET 0x2e
365 #define QUERY_DEV_CAP_MAX_RDMA_OFFSET 0x2f
366 #define QUERY_DEV_CAP_RSZ_SRQ_OFFSET 0x33
367 #define QUERY_DEV_CAP_ACK_DELAY_OFFSET 0x35
368 #define QUERY_DEV_CAP_MTU_WIDTH_OFFSET 0x36
369 #define QUERY_DEV_CAP_VL_PORT_OFFSET 0x37
370 #define QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET 0x38
371 #define QUERY_DEV_CAP_MAX_GID_OFFSET 0x3b
372 #define QUERY_DEV_CAP_RATE_SUPPORT_OFFSET 0x3c
373 #define QUERY_DEV_CAP_MAX_PKEY_OFFSET 0x3f
374 #define QUERY_DEV_CAP_EXT_FLAGS_OFFSET 0x40
375 #define QUERY_DEV_CAP_FLAGS_OFFSET 0x44
376 #define QUERY_DEV_CAP_RSVD_UAR_OFFSET 0x48
377 #define QUERY_DEV_CAP_UAR_SZ_OFFSET 0x49
378 #define QUERY_DEV_CAP_PAGE_SZ_OFFSET 0x4b
379 #define QUERY_DEV_CAP_BF_OFFSET 0x4c
380 #define QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET 0x4d
381 #define QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET 0x4e
382 #define QUERY_DEV_CAP_LOG_MAX_BF_PAGES_OFFSET 0x4f
383 #define QUERY_DEV_CAP_MAX_SG_SQ_OFFSET 0x51
384 #define QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET 0x52
385 #define QUERY_DEV_CAP_MAX_SG_RQ_OFFSET 0x55
386 #define QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET 0x56
387 #define QUERY_DEV_CAP_MAX_QP_MCG_OFFSET 0x61
388 #define QUERY_DEV_CAP_RSVD_MCG_OFFSET 0x62
389 #define QUERY_DEV_CAP_MAX_MCG_OFFSET 0x63
390 #define QUERY_DEV_CAP_RSVD_PD_OFFSET 0x64
391 #define QUERY_DEV_CAP_MAX_PD_OFFSET 0x65
392 #define QUERY_DEV_CAP_RSVD_XRC_OFFSET 0x66
393 #define QUERY_DEV_CAP_MAX_XRC_OFFSET 0x67
394 #define QUERY_DEV_CAP_MAX_COUNTERS_OFFSET 0x68
395 #define QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET 0x80
396 #define QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET 0x82
397 #define QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET 0x84
398 #define QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET 0x86
399 #define QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET 0x88
400 #define QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET 0x8a
401 #define QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET 0x8c
402 #define QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET 0x8e
403 #define QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET 0x90
404 #define QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET 0x92
405 #define QUERY_DEV_CAP_BMME_FLAGS_OFFSET 0x94
406 #define QUERY_DEV_CAP_RSVD_LKEY_OFFSET 0x98
407 #define QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET 0xa0
408
409 dev_cap->flags2 = 0;
410 mailbox = mlx4_alloc_cmd_mailbox(dev);
411 if (IS_ERR(mailbox))
412 return PTR_ERR(mailbox);
413 outbox = mailbox->buf;
414
415 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP,
416 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
417 if (err)
418 goto out;
419
420 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_QP_OFFSET);
421 dev_cap->reserved_qps = 1 << (field & 0xf);
422 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_OFFSET);
423 dev_cap->max_qps = 1 << (field & 0x1f);
424 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_SRQ_OFFSET);
425 dev_cap->reserved_srqs = 1 << (field >> 4);
426 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_OFFSET);
427 dev_cap->max_srqs = 1 << (field & 0x1f);
428 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET);
429 dev_cap->max_cq_sz = 1 << field;
430 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_CQ_OFFSET);
431 dev_cap->reserved_cqs = 1 << (field & 0xf);
432 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_OFFSET);
433 dev_cap->max_cqs = 1 << (field & 0x1f);
434 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MPT_OFFSET);
435 dev_cap->max_mpts = 1 << (field & 0x3f);
436 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_EQ_OFFSET);
437 dev_cap->reserved_eqs = field & 0xf;
438 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_EQ_OFFSET);
439 dev_cap->max_eqs = 1 << (field & 0xf);
440 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MTT_OFFSET);
441 dev_cap->reserved_mtts = 1 << (field >> 4);
442 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET);
443 dev_cap->max_mrw_sz = 1 << field;
444 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MRW_OFFSET);
445 dev_cap->reserved_mrws = 1 << (field & 0xf);
446 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET);
447 dev_cap->max_mtt_seg = 1 << (field & 0x3f);
448 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_REQ_QP_OFFSET);
449 dev_cap->max_requester_per_qp = 1 << (field & 0x3f);
450 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RES_QP_OFFSET);
451 dev_cap->max_responder_per_qp = 1 << (field & 0x3f);
452 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GSO_OFFSET);
453 field &= 0x1f;
454 if (!field)
455 dev_cap->max_gso_sz = 0;
456 else
457 dev_cap->max_gso_sz = 1 << field;
458
459 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSS_OFFSET);
460 if (field & 0x20)
461 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_XOR;
462 if (field & 0x10)
463 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_TOP;
464 field &= 0xf;
465 if (field) {
466 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS;
467 dev_cap->max_rss_tbl_sz = 1 << field;
468 } else
469 dev_cap->max_rss_tbl_sz = 0;
470 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RDMA_OFFSET);
471 dev_cap->max_rdma_global = 1 << (field & 0x3f);
472 MLX4_GET(field, outbox, QUERY_DEV_CAP_ACK_DELAY_OFFSET);
473 dev_cap->local_ca_ack_delay = field & 0x1f;
474 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET);
475 dev_cap->num_ports = field & 0xf;
476 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET);
477 dev_cap->max_msg_sz = 1 << (field & 0x1f);
478 MLX4_GET(stat_rate, outbox, QUERY_DEV_CAP_RATE_SUPPORT_OFFSET);
479 dev_cap->stat_rate_support = stat_rate;
480 MLX4_GET(ext_flags, outbox, QUERY_DEV_CAP_EXT_FLAGS_OFFSET);
481 MLX4_GET(flags, outbox, QUERY_DEV_CAP_FLAGS_OFFSET);
482 dev_cap->flags = flags | (u64)ext_flags << 32;
483 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_UAR_OFFSET);
484 dev_cap->reserved_uars = field >> 4;
485 MLX4_GET(field, outbox, QUERY_DEV_CAP_UAR_SZ_OFFSET);
486 dev_cap->uar_size = 1 << ((field & 0x3f) + 20);
487 MLX4_GET(field, outbox, QUERY_DEV_CAP_PAGE_SZ_OFFSET);
488 dev_cap->min_page_sz = 1 << field;
489
490 MLX4_GET(field, outbox, QUERY_DEV_CAP_BF_OFFSET);
491 if (field & 0x80) {
492 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET);
493 dev_cap->bf_reg_size = 1 << (field & 0x1f);
494 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET);
495 if ((1 << (field & 0x3f)) > (PAGE_SIZE / dev_cap->bf_reg_size))
496 field = 3;
497 dev_cap->bf_regs_per_page = 1 << (field & 0x3f);
498 mlx4_dbg(dev, "BlueFlame available (reg size %d, regs/page %d)\n",
499 dev_cap->bf_reg_size, dev_cap->bf_regs_per_page);
500 } else {
501 dev_cap->bf_reg_size = 0;
502 mlx4_dbg(dev, "BlueFlame not available\n");
503 }
504
505 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_SQ_OFFSET);
506 dev_cap->max_sq_sg = field;
507 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET);
508 dev_cap->max_sq_desc_sz = size;
509
510 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_MCG_OFFSET);
511 dev_cap->max_qp_per_mcg = 1 << field;
512 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MCG_OFFSET);
513 dev_cap->reserved_mgms = field & 0xf;
514 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MCG_OFFSET);
515 dev_cap->max_mcgs = 1 << field;
516 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_PD_OFFSET);
517 dev_cap->reserved_pds = field >> 4;
518 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PD_OFFSET);
519 dev_cap->max_pds = 1 << (field & 0x3f);
520 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_XRC_OFFSET);
521 dev_cap->reserved_xrcds = field >> 4;
522 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PD_OFFSET);
523 dev_cap->max_xrcds = 1 << (field & 0x1f);
524
525 MLX4_GET(size, outbox, QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET);
526 dev_cap->rdmarc_entry_sz = size;
527 MLX4_GET(size, outbox, QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET);
528 dev_cap->qpc_entry_sz = size;
529 MLX4_GET(size, outbox, QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET);
530 dev_cap->aux_entry_sz = size;
531 MLX4_GET(size, outbox, QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET);
532 dev_cap->altc_entry_sz = size;
533 MLX4_GET(size, outbox, QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET);
534 dev_cap->eqc_entry_sz = size;
535 MLX4_GET(size, outbox, QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET);
536 dev_cap->cqc_entry_sz = size;
537 MLX4_GET(size, outbox, QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET);
538 dev_cap->srq_entry_sz = size;
539 MLX4_GET(size, outbox, QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET);
540 dev_cap->cmpt_entry_sz = size;
541 MLX4_GET(size, outbox, QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET);
542 dev_cap->mtt_entry_sz = size;
543 MLX4_GET(size, outbox, QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET);
544 dev_cap->dmpt_entry_sz = size;
545
546 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET);
547 dev_cap->max_srq_sz = 1 << field;
548 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_SZ_OFFSET);
549 dev_cap->max_qp_sz = 1 << field;
550 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSZ_SRQ_OFFSET);
551 dev_cap->resize_srq = field & 1;
552 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_RQ_OFFSET);
553 dev_cap->max_rq_sg = field;
554 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET);
555 dev_cap->max_rq_desc_sz = size;
556
557 MLX4_GET(dev_cap->bmme_flags, outbox,
558 QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
559 MLX4_GET(dev_cap->reserved_lkey, outbox,
560 QUERY_DEV_CAP_RSVD_LKEY_OFFSET);
561 MLX4_GET(dev_cap->max_icm_sz, outbox,
562 QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET);
563 if (dev_cap->flags & MLX4_DEV_CAP_FLAG_COUNTERS)
564 MLX4_GET(dev_cap->max_counters, outbox,
565 QUERY_DEV_CAP_MAX_COUNTERS_OFFSET);
566
567 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
568 for (i = 1; i <= dev_cap->num_ports; ++i) {
569 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET);
570 dev_cap->max_vl[i] = field >> 4;
571 MLX4_GET(field, outbox, QUERY_DEV_CAP_MTU_WIDTH_OFFSET);
572 dev_cap->ib_mtu[i] = field >> 4;
573 dev_cap->max_port_width[i] = field & 0xf;
574 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GID_OFFSET);
575 dev_cap->max_gids[i] = 1 << (field & 0xf);
576 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PKEY_OFFSET);
577 dev_cap->max_pkeys[i] = 1 << (field & 0xf);
578 }
579 } else {
580 #define QUERY_PORT_SUPPORTED_TYPE_OFFSET 0x00
581 #define QUERY_PORT_MTU_OFFSET 0x01
582 #define QUERY_PORT_ETH_MTU_OFFSET 0x02
583 #define QUERY_PORT_WIDTH_OFFSET 0x06
584 #define QUERY_PORT_MAX_GID_PKEY_OFFSET 0x07
585 #define QUERY_PORT_MAX_MACVLAN_OFFSET 0x0a
586 #define QUERY_PORT_MAX_VL_OFFSET 0x0b
587 #define QUERY_PORT_MAC_OFFSET 0x10
588 #define QUERY_PORT_TRANS_VENDOR_OFFSET 0x18
589 #define QUERY_PORT_WAVELENGTH_OFFSET 0x1c
590 #define QUERY_PORT_TRANS_CODE_OFFSET 0x20
591
592 for (i = 1; i <= dev_cap->num_ports; ++i) {
593 err = mlx4_cmd_box(dev, 0, mailbox->dma, i, 0, MLX4_CMD_QUERY_PORT,
594 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
595 if (err)
596 goto out;
597
598 MLX4_GET(field, outbox, QUERY_PORT_SUPPORTED_TYPE_OFFSET);
599 dev_cap->supported_port_types[i] = field & 3;
600 dev_cap->suggested_type[i] = (field >> 3) & 1;
601 dev_cap->default_sense[i] = (field >> 4) & 1;
602 MLX4_GET(field, outbox, QUERY_PORT_MTU_OFFSET);
603 dev_cap->ib_mtu[i] = field & 0xf;
604 MLX4_GET(field, outbox, QUERY_PORT_WIDTH_OFFSET);
605 dev_cap->max_port_width[i] = field & 0xf;
606 MLX4_GET(field, outbox, QUERY_PORT_MAX_GID_PKEY_OFFSET);
607 dev_cap->max_gids[i] = 1 << (field >> 4);
608 dev_cap->max_pkeys[i] = 1 << (field & 0xf);
609 MLX4_GET(field, outbox, QUERY_PORT_MAX_VL_OFFSET);
610 dev_cap->max_vl[i] = field & 0xf;
611 MLX4_GET(field, outbox, QUERY_PORT_MAX_MACVLAN_OFFSET);
612 dev_cap->log_max_macs[i] = field & 0xf;
613 dev_cap->log_max_vlans[i] = field >> 4;
614 MLX4_GET(dev_cap->eth_mtu[i], outbox, QUERY_PORT_ETH_MTU_OFFSET);
615 MLX4_GET(dev_cap->def_mac[i], outbox, QUERY_PORT_MAC_OFFSET);
616 MLX4_GET(field32, outbox, QUERY_PORT_TRANS_VENDOR_OFFSET);
617 dev_cap->trans_type[i] = field32 >> 24;
618 dev_cap->vendor_oui[i] = field32 & 0xffffff;
619 MLX4_GET(dev_cap->wavelength[i], outbox, QUERY_PORT_WAVELENGTH_OFFSET);
620 MLX4_GET(dev_cap->trans_code[i], outbox, QUERY_PORT_TRANS_CODE_OFFSET);
621 }
622 }
623
624 mlx4_dbg(dev, "Base MM extensions: flags %08x, rsvd L_Key %08x\n",
625 dev_cap->bmme_flags, dev_cap->reserved_lkey);
626
627 /*
628 * Each UAR has 4 EQ doorbells; so if a UAR is reserved, then
629 * we can't use any EQs whose doorbell falls on that page,
630 * even if the EQ itself isn't reserved.
631 */
632 dev_cap->reserved_eqs = max(dev_cap->reserved_uars * 4,
633 dev_cap->reserved_eqs);
634
635 mlx4_dbg(dev, "Max ICM size %lld MB\n",
636 (unsigned long long) dev_cap->max_icm_sz >> 20);
637 mlx4_dbg(dev, "Max QPs: %d, reserved QPs: %d, entry size: %d\n",
638 dev_cap->max_qps, dev_cap->reserved_qps, dev_cap->qpc_entry_sz);
639 mlx4_dbg(dev, "Max SRQs: %d, reserved SRQs: %d, entry size: %d\n",
640 dev_cap->max_srqs, dev_cap->reserved_srqs, dev_cap->srq_entry_sz);
641 mlx4_dbg(dev, "Max CQs: %d, reserved CQs: %d, entry size: %d\n",
642 dev_cap->max_cqs, dev_cap->reserved_cqs, dev_cap->cqc_entry_sz);
643 mlx4_dbg(dev, "Max EQs: %d, reserved EQs: %d, entry size: %d\n",
644 dev_cap->max_eqs, dev_cap->reserved_eqs, dev_cap->eqc_entry_sz);
645 mlx4_dbg(dev, "reserved MPTs: %d, reserved MTTs: %d\n",
646 dev_cap->reserved_mrws, dev_cap->reserved_mtts);
647 mlx4_dbg(dev, "Max PDs: %d, reserved PDs: %d, reserved UARs: %d\n",
648 dev_cap->max_pds, dev_cap->reserved_pds, dev_cap->reserved_uars);
649 mlx4_dbg(dev, "Max QP/MCG: %d, reserved MGMs: %d\n",
650 dev_cap->max_pds, dev_cap->reserved_mgms);
651 mlx4_dbg(dev, "Max CQEs: %d, max WQEs: %d, max SRQ WQEs: %d\n",
652 dev_cap->max_cq_sz, dev_cap->max_qp_sz, dev_cap->max_srq_sz);
653 mlx4_dbg(dev, "Local CA ACK delay: %d, max MTU: %d, port width cap: %d\n",
654 dev_cap->local_ca_ack_delay, 128 << dev_cap->ib_mtu[1],
655 dev_cap->max_port_width[1]);
656 mlx4_dbg(dev, "Max SQ desc size: %d, max SQ S/G: %d\n",
657 dev_cap->max_sq_desc_sz, dev_cap->max_sq_sg);
658 mlx4_dbg(dev, "Max RQ desc size: %d, max RQ S/G: %d\n",
659 dev_cap->max_rq_desc_sz, dev_cap->max_rq_sg);
660 mlx4_dbg(dev, "Max GSO size: %d\n", dev_cap->max_gso_sz);
661 mlx4_dbg(dev, "Max counters: %d\n", dev_cap->max_counters);
662 mlx4_dbg(dev, "Max RSS Table size: %d\n", dev_cap->max_rss_tbl_sz);
663
664 dump_dev_cap_flags(dev, dev_cap->flags);
665 dump_dev_cap_flags2(dev, dev_cap->flags2);
666
667 out:
668 mlx4_free_cmd_mailbox(dev, mailbox);
669 return err;
670 }
671
672 int mlx4_QUERY_DEV_CAP_wrapper(struct mlx4_dev *dev, int slave,
673 struct mlx4_vhcr *vhcr,
674 struct mlx4_cmd_mailbox *inbox,
675 struct mlx4_cmd_mailbox *outbox,
676 struct mlx4_cmd_info *cmd)
677 {
678 int err = 0;
679 u8 field;
680
681 err = mlx4_cmd_box(dev, 0, outbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP,
682 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
683 if (err)
684 return err;
685
686 /* For guests, report Blueflame disabled */
687 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_BF_OFFSET);
688 field &= 0x7f;
689 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_BF_OFFSET);
690
691 return 0;
692 }
693
694 int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave,
695 struct mlx4_vhcr *vhcr,
696 struct mlx4_cmd_mailbox *inbox,
697 struct mlx4_cmd_mailbox *outbox,
698 struct mlx4_cmd_info *cmd)
699 {
700 u64 def_mac;
701 u8 port_type;
702 int err;
703
704 #define MLX4_PORT_SUPPORT_IB (1 << 0)
705 #define MLX4_PORT_SUGGEST_TYPE (1 << 3)
706 #define MLX4_PORT_DEFAULT_SENSE (1 << 4)
707 #define MLX4_VF_PORT_ETH_ONLY_MASK (0xff & ~MLX4_PORT_SUPPORT_IB & \
708 ~MLX4_PORT_SUGGEST_TYPE & \
709 ~MLX4_PORT_DEFAULT_SENSE)
710
711 err = mlx4_cmd_box(dev, 0, outbox->dma, vhcr->in_modifier, 0,
712 MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B,
713 MLX4_CMD_NATIVE);
714
715 if (!err && dev->caps.function != slave) {
716 /* set slave default_mac address */
717 MLX4_GET(def_mac, outbox->buf, QUERY_PORT_MAC_OFFSET);
718 def_mac += slave << 8;
719 MLX4_PUT(outbox->buf, def_mac, QUERY_PORT_MAC_OFFSET);
720
721 /* get port type - currently only eth is enabled */
722 MLX4_GET(port_type, outbox->buf,
723 QUERY_PORT_SUPPORTED_TYPE_OFFSET);
724
725 /* Allow only Eth port, no link sensing allowed */
726 port_type &= MLX4_VF_PORT_ETH_ONLY_MASK;
727
728 /* check eth is enabled for this port */
729 if (!(port_type & 2))
730 mlx4_dbg(dev, "QUERY PORT: eth not supported by host");
731
732 MLX4_PUT(outbox->buf, port_type,
733 QUERY_PORT_SUPPORTED_TYPE_OFFSET);
734 }
735
736 return err;
737 }
738
739 int mlx4_map_cmd(struct mlx4_dev *dev, u16 op, struct mlx4_icm *icm, u64 virt)
740 {
741 struct mlx4_cmd_mailbox *mailbox;
742 struct mlx4_icm_iter iter;
743 __be64 *pages;
744 int lg;
745 int nent = 0;
746 int i;
747 int err = 0;
748 int ts = 0, tc = 0;
749
750 mailbox = mlx4_alloc_cmd_mailbox(dev);
751 if (IS_ERR(mailbox))
752 return PTR_ERR(mailbox);
753 memset(mailbox->buf, 0, MLX4_MAILBOX_SIZE);
754 pages = mailbox->buf;
755
756 for (mlx4_icm_first(icm, &iter);
757 !mlx4_icm_last(&iter);
758 mlx4_icm_next(&iter)) {
759 /*
760 * We have to pass pages that are aligned to their
761 * size, so find the least significant 1 in the
762 * address or size and use that as our log2 size.
763 */
764 lg = ffs(mlx4_icm_addr(&iter) | mlx4_icm_size(&iter)) - 1;
765 if (lg < MLX4_ICM_PAGE_SHIFT) {
766 mlx4_warn(dev, "Got FW area not aligned to %d (%llx/%lx).\n",
767 MLX4_ICM_PAGE_SIZE,
768 (unsigned long long) mlx4_icm_addr(&iter),
769 mlx4_icm_size(&iter));
770 err = -EINVAL;
771 goto out;
772 }
773
774 for (i = 0; i < mlx4_icm_size(&iter) >> lg; ++i) {
775 if (virt != -1) {
776 pages[nent * 2] = cpu_to_be64(virt);
777 virt += 1 << lg;
778 }
779
780 pages[nent * 2 + 1] =
781 cpu_to_be64((mlx4_icm_addr(&iter) + (i << lg)) |
782 (lg - MLX4_ICM_PAGE_SHIFT));
783 ts += 1 << (lg - 10);
784 ++tc;
785
786 if (++nent == MLX4_MAILBOX_SIZE / 16) {
787 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op,
788 MLX4_CMD_TIME_CLASS_B,
789 MLX4_CMD_NATIVE);
790 if (err)
791 goto out;
792 nent = 0;
793 }
794 }
795 }
796
797 if (nent)
798 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op,
799 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
800 if (err)
801 goto out;
802
803 switch (op) {
804 case MLX4_CMD_MAP_FA:
805 mlx4_dbg(dev, "Mapped %d chunks/%d KB for FW.\n", tc, ts);
806 break;
807 case MLX4_CMD_MAP_ICM_AUX:
808 mlx4_dbg(dev, "Mapped %d chunks/%d KB for ICM aux.\n", tc, ts);
809 break;
810 case MLX4_CMD_MAP_ICM:
811 mlx4_dbg(dev, "Mapped %d chunks/%d KB at %llx for ICM.\n",
812 tc, ts, (unsigned long long) virt - (ts << 10));
813 break;
814 }
815
816 out:
817 mlx4_free_cmd_mailbox(dev, mailbox);
818 return err;
819 }
820
821 int mlx4_MAP_FA(struct mlx4_dev *dev, struct mlx4_icm *icm)
822 {
823 return mlx4_map_cmd(dev, MLX4_CMD_MAP_FA, icm, -1);
824 }
825
826 int mlx4_UNMAP_FA(struct mlx4_dev *dev)
827 {
828 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_UNMAP_FA,
829 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
830 }
831
832
833 int mlx4_RUN_FW(struct mlx4_dev *dev)
834 {
835 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_RUN_FW,
836 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
837 }
838
839 int mlx4_QUERY_FW(struct mlx4_dev *dev)
840 {
841 struct mlx4_fw *fw = &mlx4_priv(dev)->fw;
842 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
843 struct mlx4_cmd_mailbox *mailbox;
844 u32 *outbox;
845 int err = 0;
846 u64 fw_ver;
847 u16 cmd_if_rev;
848 u8 lg;
849
850 #define QUERY_FW_OUT_SIZE 0x100
851 #define QUERY_FW_VER_OFFSET 0x00
852 #define QUERY_FW_PPF_ID 0x09
853 #define QUERY_FW_CMD_IF_REV_OFFSET 0x0a
854 #define QUERY_FW_MAX_CMD_OFFSET 0x0f
855 #define QUERY_FW_ERR_START_OFFSET 0x30
856 #define QUERY_FW_ERR_SIZE_OFFSET 0x38
857 #define QUERY_FW_ERR_BAR_OFFSET 0x3c
858
859 #define QUERY_FW_SIZE_OFFSET 0x00
860 #define QUERY_FW_CLR_INT_BASE_OFFSET 0x20
861 #define QUERY_FW_CLR_INT_BAR_OFFSET 0x28
862
863 #define QUERY_FW_COMM_BASE_OFFSET 0x40
864 #define QUERY_FW_COMM_BAR_OFFSET 0x48
865
866 mailbox = mlx4_alloc_cmd_mailbox(dev);
867 if (IS_ERR(mailbox))
868 return PTR_ERR(mailbox);
869 outbox = mailbox->buf;
870
871 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_FW,
872 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
873 if (err)
874 goto out;
875
876 MLX4_GET(fw_ver, outbox, QUERY_FW_VER_OFFSET);
877 /*
878 * FW subminor version is at more significant bits than minor
879 * version, so swap here.
880 */
881 dev->caps.fw_ver = (fw_ver & 0xffff00000000ull) |
882 ((fw_ver & 0xffff0000ull) >> 16) |
883 ((fw_ver & 0x0000ffffull) << 16);
884
885 MLX4_GET(lg, outbox, QUERY_FW_PPF_ID);
886 dev->caps.function = lg;
887
888 if (mlx4_is_slave(dev))
889 goto out;
890
891
892 MLX4_GET(cmd_if_rev, outbox, QUERY_FW_CMD_IF_REV_OFFSET);
893 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_MIN_REV ||
894 cmd_if_rev > MLX4_COMMAND_INTERFACE_MAX_REV) {
895 mlx4_err(dev, "Installed FW has unsupported "
896 "command interface revision %d.\n",
897 cmd_if_rev);
898 mlx4_err(dev, "(Installed FW version is %d.%d.%03d)\n",
899 (int) (dev->caps.fw_ver >> 32),
900 (int) (dev->caps.fw_ver >> 16) & 0xffff,
901 (int) dev->caps.fw_ver & 0xffff);
902 mlx4_err(dev, "This driver version supports only revisions %d to %d.\n",
903 MLX4_COMMAND_INTERFACE_MIN_REV, MLX4_COMMAND_INTERFACE_MAX_REV);
904 err = -ENODEV;
905 goto out;
906 }
907
908 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS)
909 dev->flags |= MLX4_FLAG_OLD_PORT_CMDS;
910
911 MLX4_GET(lg, outbox, QUERY_FW_MAX_CMD_OFFSET);
912 cmd->max_cmds = 1 << lg;
913
914 mlx4_dbg(dev, "FW version %d.%d.%03d (cmd intf rev %d), max commands %d\n",
915 (int) (dev->caps.fw_ver >> 32),
916 (int) (dev->caps.fw_ver >> 16) & 0xffff,
917 (int) dev->caps.fw_ver & 0xffff,
918 cmd_if_rev, cmd->max_cmds);
919
920 MLX4_GET(fw->catas_offset, outbox, QUERY_FW_ERR_START_OFFSET);
921 MLX4_GET(fw->catas_size, outbox, QUERY_FW_ERR_SIZE_OFFSET);
922 MLX4_GET(fw->catas_bar, outbox, QUERY_FW_ERR_BAR_OFFSET);
923 fw->catas_bar = (fw->catas_bar >> 6) * 2;
924
925 mlx4_dbg(dev, "Catastrophic error buffer at 0x%llx, size 0x%x, BAR %d\n",
926 (unsigned long long) fw->catas_offset, fw->catas_size, fw->catas_bar);
927
928 MLX4_GET(fw->fw_pages, outbox, QUERY_FW_SIZE_OFFSET);
929 MLX4_GET(fw->clr_int_base, outbox, QUERY_FW_CLR_INT_BASE_OFFSET);
930 MLX4_GET(fw->clr_int_bar, outbox, QUERY_FW_CLR_INT_BAR_OFFSET);
931 fw->clr_int_bar = (fw->clr_int_bar >> 6) * 2;
932
933 MLX4_GET(fw->comm_base, outbox, QUERY_FW_COMM_BASE_OFFSET);
934 MLX4_GET(fw->comm_bar, outbox, QUERY_FW_COMM_BAR_OFFSET);
935 fw->comm_bar = (fw->comm_bar >> 6) * 2;
936 mlx4_dbg(dev, "Communication vector bar:%d offset:0x%llx\n",
937 fw->comm_bar, fw->comm_base);
938 mlx4_dbg(dev, "FW size %d KB\n", fw->fw_pages >> 2);
939
940 /*
941 * Round up number of system pages needed in case
942 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE.
943 */
944 fw->fw_pages =
945 ALIGN(fw->fw_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >>
946 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT);
947
948 mlx4_dbg(dev, "Clear int @ %llx, BAR %d\n",
949 (unsigned long long) fw->clr_int_base, fw->clr_int_bar);
950
951 out:
952 mlx4_free_cmd_mailbox(dev, mailbox);
953 return err;
954 }
955
956 int mlx4_QUERY_FW_wrapper(struct mlx4_dev *dev, int slave,
957 struct mlx4_vhcr *vhcr,
958 struct mlx4_cmd_mailbox *inbox,
959 struct mlx4_cmd_mailbox *outbox,
960 struct mlx4_cmd_info *cmd)
961 {
962 u8 *outbuf;
963 int err;
964
965 outbuf = outbox->buf;
966 err = mlx4_cmd_box(dev, 0, outbox->dma, 0, 0, MLX4_CMD_QUERY_FW,
967 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
968 if (err)
969 return err;
970
971 /* for slaves, set pci PPF ID to invalid and zero out everything
972 * else except FW version */
973 outbuf[0] = outbuf[1] = 0;
974 memset(&outbuf[8], 0, QUERY_FW_OUT_SIZE - 8);
975 outbuf[QUERY_FW_PPF_ID] = MLX4_INVALID_SLAVE_ID;
976
977 return 0;
978 }
979
980 static void get_board_id(void *vsd, char *board_id)
981 {
982 int i;
983
984 #define VSD_OFFSET_SIG1 0x00
985 #define VSD_OFFSET_SIG2 0xde
986 #define VSD_OFFSET_MLX_BOARD_ID 0xd0
987 #define VSD_OFFSET_TS_BOARD_ID 0x20
988
989 #define VSD_SIGNATURE_TOPSPIN 0x5ad
990
991 memset(board_id, 0, MLX4_BOARD_ID_LEN);
992
993 if (be16_to_cpup(vsd + VSD_OFFSET_SIG1) == VSD_SIGNATURE_TOPSPIN &&
994 be16_to_cpup(vsd + VSD_OFFSET_SIG2) == VSD_SIGNATURE_TOPSPIN) {
995 strlcpy(board_id, vsd + VSD_OFFSET_TS_BOARD_ID, MLX4_BOARD_ID_LEN);
996 } else {
997 /*
998 * The board ID is a string but the firmware byte
999 * swaps each 4-byte word before passing it back to
1000 * us. Therefore we need to swab it before printing.
1001 */
1002 for (i = 0; i < 4; ++i)
1003 ((u32 *) board_id)[i] =
1004 swab32(*(u32 *) (vsd + VSD_OFFSET_MLX_BOARD_ID + i * 4));
1005 }
1006 }
1007
1008 int mlx4_QUERY_ADAPTER(struct mlx4_dev *dev, struct mlx4_adapter *adapter)
1009 {
1010 struct mlx4_cmd_mailbox *mailbox;
1011 u32 *outbox;
1012 int err;
1013
1014 #define QUERY_ADAPTER_OUT_SIZE 0x100
1015 #define QUERY_ADAPTER_INTA_PIN_OFFSET 0x10
1016 #define QUERY_ADAPTER_VSD_OFFSET 0x20
1017
1018 mailbox = mlx4_alloc_cmd_mailbox(dev);
1019 if (IS_ERR(mailbox))
1020 return PTR_ERR(mailbox);
1021 outbox = mailbox->buf;
1022
1023 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_ADAPTER,
1024 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1025 if (err)
1026 goto out;
1027
1028 MLX4_GET(adapter->inta_pin, outbox, QUERY_ADAPTER_INTA_PIN_OFFSET);
1029
1030 get_board_id(outbox + QUERY_ADAPTER_VSD_OFFSET / 4,
1031 adapter->board_id);
1032
1033 out:
1034 mlx4_free_cmd_mailbox(dev, mailbox);
1035 return err;
1036 }
1037
1038 int mlx4_INIT_HCA(struct mlx4_dev *dev, struct mlx4_init_hca_param *param)
1039 {
1040 struct mlx4_cmd_mailbox *mailbox;
1041 __be32 *inbox;
1042 int err;
1043
1044 #define INIT_HCA_IN_SIZE 0x200
1045 #define INIT_HCA_VERSION_OFFSET 0x000
1046 #define INIT_HCA_VERSION 2
1047 #define INIT_HCA_CACHELINE_SZ_OFFSET 0x0e
1048 #define INIT_HCA_FLAGS_OFFSET 0x014
1049 #define INIT_HCA_QPC_OFFSET 0x020
1050 #define INIT_HCA_QPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x10)
1051 #define INIT_HCA_LOG_QP_OFFSET (INIT_HCA_QPC_OFFSET + 0x17)
1052 #define INIT_HCA_SRQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x28)
1053 #define INIT_HCA_LOG_SRQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x2f)
1054 #define INIT_HCA_CQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x30)
1055 #define INIT_HCA_LOG_CQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x37)
1056 #define INIT_HCA_EQE_CQE_OFFSETS (INIT_HCA_QPC_OFFSET + 0x38)
1057 #define INIT_HCA_ALTC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x40)
1058 #define INIT_HCA_AUXC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x50)
1059 #define INIT_HCA_EQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x60)
1060 #define INIT_HCA_LOG_EQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x67)
1061 #define INIT_HCA_RDMARC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x70)
1062 #define INIT_HCA_LOG_RD_OFFSET (INIT_HCA_QPC_OFFSET + 0x77)
1063 #define INIT_HCA_MCAST_OFFSET 0x0c0
1064 #define INIT_HCA_MC_BASE_OFFSET (INIT_HCA_MCAST_OFFSET + 0x00)
1065 #define INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x12)
1066 #define INIT_HCA_LOG_MC_HASH_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x16)
1067 #define INIT_HCA_UC_STEERING_OFFSET (INIT_HCA_MCAST_OFFSET + 0x18)
1068 #define INIT_HCA_LOG_MC_TABLE_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x1b)
1069 #define INIT_HCA_TPT_OFFSET 0x0f0
1070 #define INIT_HCA_DMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x00)
1071 #define INIT_HCA_LOG_MPT_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x0b)
1072 #define INIT_HCA_MTT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x10)
1073 #define INIT_HCA_CMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x18)
1074 #define INIT_HCA_UAR_OFFSET 0x120
1075 #define INIT_HCA_LOG_UAR_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0a)
1076 #define INIT_HCA_UAR_PAGE_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0b)
1077
1078 mailbox = mlx4_alloc_cmd_mailbox(dev);
1079 if (IS_ERR(mailbox))
1080 return PTR_ERR(mailbox);
1081 inbox = mailbox->buf;
1082
1083 memset(inbox, 0, INIT_HCA_IN_SIZE);
1084
1085 *((u8 *) mailbox->buf + INIT_HCA_VERSION_OFFSET) = INIT_HCA_VERSION;
1086
1087 *((u8 *) mailbox->buf + INIT_HCA_CACHELINE_SZ_OFFSET) =
1088 (ilog2(cache_line_size()) - 4) << 5;
1089
1090 #if defined(__LITTLE_ENDIAN)
1091 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) &= ~cpu_to_be32(1 << 1);
1092 #elif defined(__BIG_ENDIAN)
1093 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 1);
1094 #else
1095 #error Host endianness not defined
1096 #endif
1097 /* Check port for UD address vector: */
1098 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1);
1099
1100 /* Enable IPoIB checksumming if we can: */
1101 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_IPOIB_CSUM)
1102 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 3);
1103
1104 /* Enable QoS support if module parameter set */
1105 if (enable_qos)
1106 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 2);
1107
1108 /* enable counters */
1109 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS)
1110 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 4);
1111
1112 /* QPC/EEC/CQC/EQC/RDMARC attributes */
1113
1114 MLX4_PUT(inbox, param->qpc_base, INIT_HCA_QPC_BASE_OFFSET);
1115 MLX4_PUT(inbox, param->log_num_qps, INIT_HCA_LOG_QP_OFFSET);
1116 MLX4_PUT(inbox, param->srqc_base, INIT_HCA_SRQC_BASE_OFFSET);
1117 MLX4_PUT(inbox, param->log_num_srqs, INIT_HCA_LOG_SRQ_OFFSET);
1118 MLX4_PUT(inbox, param->cqc_base, INIT_HCA_CQC_BASE_OFFSET);
1119 MLX4_PUT(inbox, param->log_num_cqs, INIT_HCA_LOG_CQ_OFFSET);
1120 MLX4_PUT(inbox, param->altc_base, INIT_HCA_ALTC_BASE_OFFSET);
1121 MLX4_PUT(inbox, param->auxc_base, INIT_HCA_AUXC_BASE_OFFSET);
1122 MLX4_PUT(inbox, param->eqc_base, INIT_HCA_EQC_BASE_OFFSET);
1123 MLX4_PUT(inbox, param->log_num_eqs, INIT_HCA_LOG_EQ_OFFSET);
1124 MLX4_PUT(inbox, param->rdmarc_base, INIT_HCA_RDMARC_BASE_OFFSET);
1125 MLX4_PUT(inbox, param->log_rd_per_qp, INIT_HCA_LOG_RD_OFFSET);
1126
1127 /* multicast attributes */
1128
1129 MLX4_PUT(inbox, param->mc_base, INIT_HCA_MC_BASE_OFFSET);
1130 MLX4_PUT(inbox, param->log_mc_entry_sz, INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET);
1131 MLX4_PUT(inbox, param->log_mc_hash_sz, INIT_HCA_LOG_MC_HASH_SZ_OFFSET);
1132 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER)
1133 MLX4_PUT(inbox, (u8) (1 << 3), INIT_HCA_UC_STEERING_OFFSET);
1134 MLX4_PUT(inbox, param->log_mc_table_sz, INIT_HCA_LOG_MC_TABLE_SZ_OFFSET);
1135
1136 /* TPT attributes */
1137
1138 MLX4_PUT(inbox, param->dmpt_base, INIT_HCA_DMPT_BASE_OFFSET);
1139 MLX4_PUT(inbox, param->log_mpt_sz, INIT_HCA_LOG_MPT_SZ_OFFSET);
1140 MLX4_PUT(inbox, param->mtt_base, INIT_HCA_MTT_BASE_OFFSET);
1141 MLX4_PUT(inbox, param->cmpt_base, INIT_HCA_CMPT_BASE_OFFSET);
1142
1143 /* UAR attributes */
1144
1145 MLX4_PUT(inbox, param->uar_page_sz, INIT_HCA_UAR_PAGE_SZ_OFFSET);
1146 MLX4_PUT(inbox, param->log_uar_sz, INIT_HCA_LOG_UAR_SZ_OFFSET);
1147
1148 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_INIT_HCA, 10000,
1149 MLX4_CMD_NATIVE);
1150
1151 if (err)
1152 mlx4_err(dev, "INIT_HCA returns %d\n", err);
1153
1154 mlx4_free_cmd_mailbox(dev, mailbox);
1155 return err;
1156 }
1157
1158 int mlx4_QUERY_HCA(struct mlx4_dev *dev,
1159 struct mlx4_init_hca_param *param)
1160 {
1161 struct mlx4_cmd_mailbox *mailbox;
1162 __be32 *outbox;
1163 int err;
1164
1165 #define QUERY_HCA_GLOBAL_CAPS_OFFSET 0x04
1166
1167 mailbox = mlx4_alloc_cmd_mailbox(dev);
1168 if (IS_ERR(mailbox))
1169 return PTR_ERR(mailbox);
1170 outbox = mailbox->buf;
1171
1172 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0,
1173 MLX4_CMD_QUERY_HCA,
1174 MLX4_CMD_TIME_CLASS_B,
1175 !mlx4_is_slave(dev));
1176 if (err)
1177 goto out;
1178
1179 MLX4_GET(param->global_caps, outbox, QUERY_HCA_GLOBAL_CAPS_OFFSET);
1180
1181 /* QPC/EEC/CQC/EQC/RDMARC attributes */
1182
1183 MLX4_GET(param->qpc_base, outbox, INIT_HCA_QPC_BASE_OFFSET);
1184 MLX4_GET(param->log_num_qps, outbox, INIT_HCA_LOG_QP_OFFSET);
1185 MLX4_GET(param->srqc_base, outbox, INIT_HCA_SRQC_BASE_OFFSET);
1186 MLX4_GET(param->log_num_srqs, outbox, INIT_HCA_LOG_SRQ_OFFSET);
1187 MLX4_GET(param->cqc_base, outbox, INIT_HCA_CQC_BASE_OFFSET);
1188 MLX4_GET(param->log_num_cqs, outbox, INIT_HCA_LOG_CQ_OFFSET);
1189 MLX4_GET(param->altc_base, outbox, INIT_HCA_ALTC_BASE_OFFSET);
1190 MLX4_GET(param->auxc_base, outbox, INIT_HCA_AUXC_BASE_OFFSET);
1191 MLX4_GET(param->eqc_base, outbox, INIT_HCA_EQC_BASE_OFFSET);
1192 MLX4_GET(param->log_num_eqs, outbox, INIT_HCA_LOG_EQ_OFFSET);
1193 MLX4_GET(param->rdmarc_base, outbox, INIT_HCA_RDMARC_BASE_OFFSET);
1194 MLX4_GET(param->log_rd_per_qp, outbox, INIT_HCA_LOG_RD_OFFSET);
1195
1196 /* multicast attributes */
1197
1198 MLX4_GET(param->mc_base, outbox, INIT_HCA_MC_BASE_OFFSET);
1199 MLX4_GET(param->log_mc_entry_sz, outbox,
1200 INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET);
1201 MLX4_GET(param->log_mc_hash_sz, outbox,
1202 INIT_HCA_LOG_MC_HASH_SZ_OFFSET);
1203 MLX4_GET(param->log_mc_table_sz, outbox,
1204 INIT_HCA_LOG_MC_TABLE_SZ_OFFSET);
1205
1206 /* TPT attributes */
1207
1208 MLX4_GET(param->dmpt_base, outbox, INIT_HCA_DMPT_BASE_OFFSET);
1209 MLX4_GET(param->log_mpt_sz, outbox, INIT_HCA_LOG_MPT_SZ_OFFSET);
1210 MLX4_GET(param->mtt_base, outbox, INIT_HCA_MTT_BASE_OFFSET);
1211 MLX4_GET(param->cmpt_base, outbox, INIT_HCA_CMPT_BASE_OFFSET);
1212
1213 /* UAR attributes */
1214
1215 MLX4_GET(param->uar_page_sz, outbox, INIT_HCA_UAR_PAGE_SZ_OFFSET);
1216 MLX4_GET(param->log_uar_sz, outbox, INIT_HCA_LOG_UAR_SZ_OFFSET);
1217
1218 out:
1219 mlx4_free_cmd_mailbox(dev, mailbox);
1220
1221 return err;
1222 }
1223
1224 int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave,
1225 struct mlx4_vhcr *vhcr,
1226 struct mlx4_cmd_mailbox *inbox,
1227 struct mlx4_cmd_mailbox *outbox,
1228 struct mlx4_cmd_info *cmd)
1229 {
1230 struct mlx4_priv *priv = mlx4_priv(dev);
1231 int port = vhcr->in_modifier;
1232 int err;
1233
1234 if (priv->mfunc.master.slave_state[slave].init_port_mask & (1 << port))
1235 return 0;
1236
1237 if (dev->caps.port_mask[port] == MLX4_PORT_TYPE_IB)
1238 return -ENODEV;
1239
1240 /* Enable port only if it was previously disabled */
1241 if (!priv->mfunc.master.init_port_ref[port]) {
1242 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
1243 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1244 if (err)
1245 return err;
1246 }
1247 priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port);
1248 ++priv->mfunc.master.init_port_ref[port];
1249 return 0;
1250 }
1251
1252 int mlx4_INIT_PORT(struct mlx4_dev *dev, int port)
1253 {
1254 struct mlx4_cmd_mailbox *mailbox;
1255 u32 *inbox;
1256 int err;
1257 u32 flags;
1258 u16 field;
1259
1260 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
1261 #define INIT_PORT_IN_SIZE 256
1262 #define INIT_PORT_FLAGS_OFFSET 0x00
1263 #define INIT_PORT_FLAG_SIG (1 << 18)
1264 #define INIT_PORT_FLAG_NG (1 << 17)
1265 #define INIT_PORT_FLAG_G0 (1 << 16)
1266 #define INIT_PORT_VL_SHIFT 4
1267 #define INIT_PORT_PORT_WIDTH_SHIFT 8
1268 #define INIT_PORT_MTU_OFFSET 0x04
1269 #define INIT_PORT_MAX_GID_OFFSET 0x06
1270 #define INIT_PORT_MAX_PKEY_OFFSET 0x0a
1271 #define INIT_PORT_GUID0_OFFSET 0x10
1272 #define INIT_PORT_NODE_GUID_OFFSET 0x18
1273 #define INIT_PORT_SI_GUID_OFFSET 0x20
1274
1275 mailbox = mlx4_alloc_cmd_mailbox(dev);
1276 if (IS_ERR(mailbox))
1277 return PTR_ERR(mailbox);
1278 inbox = mailbox->buf;
1279
1280 memset(inbox, 0, INIT_PORT_IN_SIZE);
1281
1282 flags = 0;
1283 flags |= (dev->caps.vl_cap[port] & 0xf) << INIT_PORT_VL_SHIFT;
1284 flags |= (dev->caps.port_width_cap[port] & 0xf) << INIT_PORT_PORT_WIDTH_SHIFT;
1285 MLX4_PUT(inbox, flags, INIT_PORT_FLAGS_OFFSET);
1286
1287 field = 128 << dev->caps.ib_mtu_cap[port];
1288 MLX4_PUT(inbox, field, INIT_PORT_MTU_OFFSET);
1289 field = dev->caps.gid_table_len[port];
1290 MLX4_PUT(inbox, field, INIT_PORT_MAX_GID_OFFSET);
1291 field = dev->caps.pkey_table_len[port];
1292 MLX4_PUT(inbox, field, INIT_PORT_MAX_PKEY_OFFSET);
1293
1294 err = mlx4_cmd(dev, mailbox->dma, port, 0, MLX4_CMD_INIT_PORT,
1295 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1296
1297 mlx4_free_cmd_mailbox(dev, mailbox);
1298 } else
1299 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
1300 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
1301
1302 return err;
1303 }
1304 EXPORT_SYMBOL_GPL(mlx4_INIT_PORT);
1305
1306 int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave,
1307 struct mlx4_vhcr *vhcr,
1308 struct mlx4_cmd_mailbox *inbox,
1309 struct mlx4_cmd_mailbox *outbox,
1310 struct mlx4_cmd_info *cmd)
1311 {
1312 struct mlx4_priv *priv = mlx4_priv(dev);
1313 int port = vhcr->in_modifier;
1314 int err;
1315
1316 if (!(priv->mfunc.master.slave_state[slave].init_port_mask &
1317 (1 << port)))
1318 return 0;
1319
1320 if (dev->caps.port_mask[port] == MLX4_PORT_TYPE_IB)
1321 return -ENODEV;
1322 if (priv->mfunc.master.init_port_ref[port] == 1) {
1323 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, 1000,
1324 MLX4_CMD_NATIVE);
1325 if (err)
1326 return err;
1327 }
1328 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port);
1329 --priv->mfunc.master.init_port_ref[port];
1330 return 0;
1331 }
1332
1333 int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port)
1334 {
1335 return mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, 1000,
1336 MLX4_CMD_WRAPPED);
1337 }
1338 EXPORT_SYMBOL_GPL(mlx4_CLOSE_PORT);
1339
1340 int mlx4_CLOSE_HCA(struct mlx4_dev *dev, int panic)
1341 {
1342 return mlx4_cmd(dev, 0, 0, panic, MLX4_CMD_CLOSE_HCA, 1000,
1343 MLX4_CMD_NATIVE);
1344 }
1345
1346 int mlx4_SET_ICM_SIZE(struct mlx4_dev *dev, u64 icm_size, u64 *aux_pages)
1347 {
1348 int ret = mlx4_cmd_imm(dev, icm_size, aux_pages, 0, 0,
1349 MLX4_CMD_SET_ICM_SIZE,
1350 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1351 if (ret)
1352 return ret;
1353
1354 /*
1355 * Round up number of system pages needed in case
1356 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE.
1357 */
1358 *aux_pages = ALIGN(*aux_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >>
1359 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT);
1360
1361 return 0;
1362 }
1363
1364 int mlx4_NOP(struct mlx4_dev *dev)
1365 {
1366 /* Input modifier of 0x1f means "finish as soon as possible." */
1367 return mlx4_cmd(dev, 0, 0x1f, 0, MLX4_CMD_NOP, 100, MLX4_CMD_NATIVE);
1368 }
1369
1370 #define MLX4_WOL_SETUP_MODE (5 << 28)
1371 int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port)
1372 {
1373 u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8;
1374
1375 return mlx4_cmd_imm(dev, 0, config, in_mod, 0x3,
1376 MLX4_CMD_MOD_STAT_CFG, MLX4_CMD_TIME_CLASS_A,
1377 MLX4_CMD_NATIVE);
1378 }
1379 EXPORT_SYMBOL_GPL(mlx4_wol_read);
1380
1381 int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port)
1382 {
1383 u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8;
1384
1385 return mlx4_cmd(dev, config, in_mod, 0x1, MLX4_CMD_MOD_STAT_CFG,
1386 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1387 }
1388 EXPORT_SYMBOL_GPL(mlx4_wol_write);
Linux kernel - Deliverables
This page took 0.062004 seconds and 5 git commands to generate.