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mlx4: Structures and init/teardown for VF resource quotas
[deliverable/linux.git] / drivers / net / ethernet / mellanox / mlx4 / fw.c
1 /*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35 #include <linux/etherdevice.h>
36 #include <linux/mlx4/cmd.h>
37 #include <linux/module.h>
38 #include <linux/cache.h>
39
40 #include "fw.h"
41 #include "icm.h"
42
43 enum {
44 MLX4_COMMAND_INTERFACE_MIN_REV = 2,
45 MLX4_COMMAND_INTERFACE_MAX_REV = 3,
46 MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS = 3,
47 };
48
49 extern void __buggy_use_of_MLX4_GET(void);
50 extern void __buggy_use_of_MLX4_PUT(void);
51
52 static bool enable_qos;
53 module_param(enable_qos, bool, 0444);
54 MODULE_PARM_DESC(enable_qos, "Enable Quality of Service support in the HCA (default: off)");
55
56 #define MLX4_GET(dest, source, offset) \
57 do { \
58 void *__p = (char *) (source) + (offset); \
59 switch (sizeof (dest)) { \
60 case 1: (dest) = *(u8 *) __p; break; \
61 case 2: (dest) = be16_to_cpup(__p); break; \
62 case 4: (dest) = be32_to_cpup(__p); break; \
63 case 8: (dest) = be64_to_cpup(__p); break; \
64 default: __buggy_use_of_MLX4_GET(); \
65 } \
66 } while (0)
67
68 #define MLX4_PUT(dest, source, offset) \
69 do { \
70 void *__d = ((char *) (dest) + (offset)); \
71 switch (sizeof(source)) { \
72 case 1: *(u8 *) __d = (source); break; \
73 case 2: *(__be16 *) __d = cpu_to_be16(source); break; \
74 case 4: *(__be32 *) __d = cpu_to_be32(source); break; \
75 case 8: *(__be64 *) __d = cpu_to_be64(source); break; \
76 default: __buggy_use_of_MLX4_PUT(); \
77 } \
78 } while (0)
79
80 static void dump_dev_cap_flags(struct mlx4_dev *dev, u64 flags)
81 {
82 static const char *fname[] = {
83 [ 0] = "RC transport",
84 [ 1] = "UC transport",
85 [ 2] = "UD transport",
86 [ 3] = "XRC transport",
87 [ 4] = "reliable multicast",
88 [ 5] = "FCoIB support",
89 [ 6] = "SRQ support",
90 [ 7] = "IPoIB checksum offload",
91 [ 8] = "P_Key violation counter",
92 [ 9] = "Q_Key violation counter",
93 [10] = "VMM",
94 [12] = "Dual Port Different Protocol (DPDP) support",
95 [15] = "Big LSO headers",
96 [16] = "MW support",
97 [17] = "APM support",
98 [18] = "Atomic ops support",
99 [19] = "Raw multicast support",
100 [20] = "Address vector port checking support",
101 [21] = "UD multicast support",
102 [24] = "Demand paging support",
103 [25] = "Router support",
104 [30] = "IBoE support",
105 [32] = "Unicast loopback support",
106 [34] = "FCS header control",
107 [38] = "Wake On LAN support",
108 [40] = "UDP RSS support",
109 [41] = "Unicast VEP steering support",
110 [42] = "Multicast VEP steering support",
111 [48] = "Counters support",
112 [53] = "Port ETS Scheduler support",
113 [55] = "Port link type sensing support",
114 [59] = "Port management change event support",
115 [61] = "64 byte EQE support",
116 [62] = "64 byte CQE support",
117 };
118 int i;
119
120 mlx4_dbg(dev, "DEV_CAP flags:\n");
121 for (i = 0; i < ARRAY_SIZE(fname); ++i)
122 if (fname[i] && (flags & (1LL << i)))
123 mlx4_dbg(dev, " %s\n", fname[i]);
124 }
125
126 static void dump_dev_cap_flags2(struct mlx4_dev *dev, u64 flags)
127 {
128 static const char * const fname[] = {
129 [0] = "RSS support",
130 [1] = "RSS Toeplitz Hash Function support",
131 [2] = "RSS XOR Hash Function support",
132 [3] = "Device manage flow steering support",
133 [4] = "Automatic MAC reassignment support",
134 [5] = "Time stamping support",
135 [6] = "VST (control vlan insertion/stripping) support",
136 [7] = "FSM (MAC anti-spoofing) support",
137 [8] = "Dynamic QP updates support"
138 };
139 int i;
140
141 for (i = 0; i < ARRAY_SIZE(fname); ++i)
142 if (fname[i] && (flags & (1LL << i)))
143 mlx4_dbg(dev, " %s\n", fname[i]);
144 }
145
146 int mlx4_MOD_STAT_CFG(struct mlx4_dev *dev, struct mlx4_mod_stat_cfg *cfg)
147 {
148 struct mlx4_cmd_mailbox *mailbox;
149 u32 *inbox;
150 int err = 0;
151
152 #define MOD_STAT_CFG_IN_SIZE 0x100
153
154 #define MOD_STAT_CFG_PG_SZ_M_OFFSET 0x002
155 #define MOD_STAT_CFG_PG_SZ_OFFSET 0x003
156
157 mailbox = mlx4_alloc_cmd_mailbox(dev);
158 if (IS_ERR(mailbox))
159 return PTR_ERR(mailbox);
160 inbox = mailbox->buf;
161
162 memset(inbox, 0, MOD_STAT_CFG_IN_SIZE);
163
164 MLX4_PUT(inbox, cfg->log_pg_sz, MOD_STAT_CFG_PG_SZ_OFFSET);
165 MLX4_PUT(inbox, cfg->log_pg_sz_m, MOD_STAT_CFG_PG_SZ_M_OFFSET);
166
167 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_MOD_STAT_CFG,
168 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
169
170 mlx4_free_cmd_mailbox(dev, mailbox);
171 return err;
172 }
173
174 int mlx4_QUERY_FUNC_CAP_wrapper(struct mlx4_dev *dev, int slave,
175 struct mlx4_vhcr *vhcr,
176 struct mlx4_cmd_mailbox *inbox,
177 struct mlx4_cmd_mailbox *outbox,
178 struct mlx4_cmd_info *cmd)
179 {
180 struct mlx4_priv *priv = mlx4_priv(dev);
181 u8 field;
182 u32 size;
183 int err = 0;
184
185 #define QUERY_FUNC_CAP_FLAGS_OFFSET 0x0
186 #define QUERY_FUNC_CAP_NUM_PORTS_OFFSET 0x1
187 #define QUERY_FUNC_CAP_PF_BHVR_OFFSET 0x4
188 #define QUERY_FUNC_CAP_FMR_OFFSET 0x8
189 #define QUERY_FUNC_CAP_QP_QUOTA_OFFSET 0x10
190 #define QUERY_FUNC_CAP_CQ_QUOTA_OFFSET 0x14
191 #define QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET 0x18
192 #define QUERY_FUNC_CAP_MPT_QUOTA_OFFSET 0x20
193 #define QUERY_FUNC_CAP_MTT_QUOTA_OFFSET 0x24
194 #define QUERY_FUNC_CAP_MCG_QUOTA_OFFSET 0x28
195 #define QUERY_FUNC_CAP_MAX_EQ_OFFSET 0x2c
196 #define QUERY_FUNC_CAP_RESERVED_EQ_OFFSET 0x30
197
198 #define QUERY_FUNC_CAP_FMR_FLAG 0x80
199 #define QUERY_FUNC_CAP_FLAG_RDMA 0x40
200 #define QUERY_FUNC_CAP_FLAG_ETH 0x80
201
202 /* when opcode modifier = 1 */
203 #define QUERY_FUNC_CAP_PHYS_PORT_OFFSET 0x3
204 #define QUERY_FUNC_CAP_RDMA_PROPS_OFFSET 0x8
205 #define QUERY_FUNC_CAP_ETH_PROPS_OFFSET 0xc
206
207 #define QUERY_FUNC_CAP_QP0_TUNNEL 0x10
208 #define QUERY_FUNC_CAP_QP0_PROXY 0x14
209 #define QUERY_FUNC_CAP_QP1_TUNNEL 0x18
210 #define QUERY_FUNC_CAP_QP1_PROXY 0x1c
211
212 #define QUERY_FUNC_CAP_ETH_PROPS_FORCE_MAC 0x40
213 #define QUERY_FUNC_CAP_ETH_PROPS_FORCE_VLAN 0x80
214
215 #define QUERY_FUNC_CAP_RDMA_PROPS_FORCE_PHY_WQE_GID 0x80
216
217 if (vhcr->op_modifier == 1) {
218 field = 0;
219 /* ensure force vlan and force mac bits are not set */
220 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_ETH_PROPS_OFFSET);
221 /* ensure that phy_wqe_gid bit is not set */
222 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_RDMA_PROPS_OFFSET);
223
224 field = vhcr->in_modifier; /* phys-port = logical-port */
225 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_PHYS_PORT_OFFSET);
226
227 /* size is now the QP number */
228 size = dev->phys_caps.base_tunnel_sqpn + 8 * slave + field - 1;
229 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP0_TUNNEL);
230
231 size += 2;
232 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP1_TUNNEL);
233
234 size = dev->phys_caps.base_proxy_sqpn + 8 * slave + field - 1;
235 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP0_PROXY);
236
237 size += 2;
238 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP1_PROXY);
239
240 } else if (vhcr->op_modifier == 0) {
241 /* enable rdma and ethernet interfaces */
242 field = (QUERY_FUNC_CAP_FLAG_ETH | QUERY_FUNC_CAP_FLAG_RDMA);
243 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FLAGS_OFFSET);
244
245 field = dev->caps.num_ports;
246 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_NUM_PORTS_OFFSET);
247
248 size = dev->caps.function_caps; /* set PF behaviours */
249 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_PF_BHVR_OFFSET);
250
251 field = 0; /* protected FMR support not available as yet */
252 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FMR_OFFSET);
253
254 size = priv->mfunc.master.res_tracker.res_alloc[RES_QP].quota[slave];
255 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP_QUOTA_OFFSET);
256
257 size = priv->mfunc.master.res_tracker.res_alloc[RES_SRQ].quota[slave];
258 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET);
259
260 size = priv->mfunc.master.res_tracker.res_alloc[RES_CQ].quota[slave];
261 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET);
262
263 size = dev->caps.num_eqs;
264 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MAX_EQ_OFFSET);
265
266 size = dev->caps.reserved_eqs;
267 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET);
268
269 size = priv->mfunc.master.res_tracker.res_alloc[RES_MPT].quota[slave];
270 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET);
271
272 size = priv->mfunc.master.res_tracker.res_alloc[RES_MTT].quota[slave];
273 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET);
274
275 size = dev->caps.num_mgms + dev->caps.num_amgms;
276 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET);
277
278 } else
279 err = -EINVAL;
280
281 return err;
282 }
283
284 int mlx4_QUERY_FUNC_CAP(struct mlx4_dev *dev, u32 gen_or_port,
285 struct mlx4_func_cap *func_cap)
286 {
287 struct mlx4_cmd_mailbox *mailbox;
288 u32 *outbox;
289 u8 field, op_modifier;
290 u32 size;
291 int err = 0;
292
293 op_modifier = !!gen_or_port; /* 0 = general, 1 = logical port */
294
295 mailbox = mlx4_alloc_cmd_mailbox(dev);
296 if (IS_ERR(mailbox))
297 return PTR_ERR(mailbox);
298
299 err = mlx4_cmd_box(dev, 0, mailbox->dma, gen_or_port, op_modifier,
300 MLX4_CMD_QUERY_FUNC_CAP,
301 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
302 if (err)
303 goto out;
304
305 outbox = mailbox->buf;
306
307 if (!op_modifier) {
308 MLX4_GET(field, outbox, QUERY_FUNC_CAP_FLAGS_OFFSET);
309 if (!(field & (QUERY_FUNC_CAP_FLAG_ETH | QUERY_FUNC_CAP_FLAG_RDMA))) {
310 mlx4_err(dev, "The host supports neither eth nor rdma interfaces\n");
311 err = -EPROTONOSUPPORT;
312 goto out;
313 }
314 func_cap->flags = field;
315
316 MLX4_GET(field, outbox, QUERY_FUNC_CAP_NUM_PORTS_OFFSET);
317 func_cap->num_ports = field;
318
319 MLX4_GET(size, outbox, QUERY_FUNC_CAP_PF_BHVR_OFFSET);
320 func_cap->pf_context_behaviour = size;
321
322 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP_QUOTA_OFFSET);
323 func_cap->qp_quota = size & 0xFFFFFF;
324
325 MLX4_GET(size, outbox, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET);
326 func_cap->srq_quota = size & 0xFFFFFF;
327
328 MLX4_GET(size, outbox, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET);
329 func_cap->cq_quota = size & 0xFFFFFF;
330
331 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MAX_EQ_OFFSET);
332 func_cap->max_eq = size & 0xFFFFFF;
333
334 MLX4_GET(size, outbox, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET);
335 func_cap->reserved_eq = size & 0xFFFFFF;
336
337 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET);
338 func_cap->mpt_quota = size & 0xFFFFFF;
339
340 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET);
341 func_cap->mtt_quota = size & 0xFFFFFF;
342
343 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET);
344 func_cap->mcg_quota = size & 0xFFFFFF;
345 goto out;
346 }
347
348 /* logical port query */
349 if (gen_or_port > dev->caps.num_ports) {
350 err = -EINVAL;
351 goto out;
352 }
353
354 if (dev->caps.port_type[gen_or_port] == MLX4_PORT_TYPE_ETH) {
355 MLX4_GET(field, outbox, QUERY_FUNC_CAP_ETH_PROPS_OFFSET);
356 if (field & QUERY_FUNC_CAP_ETH_PROPS_FORCE_VLAN) {
357 mlx4_err(dev, "VLAN is enforced on this port\n");
358 err = -EPROTONOSUPPORT;
359 goto out;
360 }
361
362 if (field & QUERY_FUNC_CAP_ETH_PROPS_FORCE_MAC) {
363 mlx4_err(dev, "Force mac is enabled on this port\n");
364 err = -EPROTONOSUPPORT;
365 goto out;
366 }
367 } else if (dev->caps.port_type[gen_or_port] == MLX4_PORT_TYPE_IB) {
368 MLX4_GET(field, outbox, QUERY_FUNC_CAP_RDMA_PROPS_OFFSET);
369 if (field & QUERY_FUNC_CAP_RDMA_PROPS_FORCE_PHY_WQE_GID) {
370 mlx4_err(dev, "phy_wqe_gid is "
371 "enforced on this ib port\n");
372 err = -EPROTONOSUPPORT;
373 goto out;
374 }
375 }
376
377 MLX4_GET(field, outbox, QUERY_FUNC_CAP_PHYS_PORT_OFFSET);
378 func_cap->physical_port = field;
379 if (func_cap->physical_port != gen_or_port) {
380 err = -ENOSYS;
381 goto out;
382 }
383
384 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP0_TUNNEL);
385 func_cap->qp0_tunnel_qpn = size & 0xFFFFFF;
386
387 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP0_PROXY);
388 func_cap->qp0_proxy_qpn = size & 0xFFFFFF;
389
390 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP1_TUNNEL);
391 func_cap->qp1_tunnel_qpn = size & 0xFFFFFF;
392
393 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP1_PROXY);
394 func_cap->qp1_proxy_qpn = size & 0xFFFFFF;
395
396 /* All other resources are allocated by the master, but we still report
397 * 'num' and 'reserved' capabilities as follows:
398 * - num remains the maximum resource index
399 * - 'num - reserved' is the total available objects of a resource, but
400 * resource indices may be less than 'reserved'
401 * TODO: set per-resource quotas */
402
403 out:
404 mlx4_free_cmd_mailbox(dev, mailbox);
405
406 return err;
407 }
408
409 int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
410 {
411 struct mlx4_cmd_mailbox *mailbox;
412 u32 *outbox;
413 u8 field;
414 u32 field32, flags, ext_flags;
415 u16 size;
416 u16 stat_rate;
417 int err;
418 int i;
419
420 #define QUERY_DEV_CAP_OUT_SIZE 0x100
421 #define QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET 0x10
422 #define QUERY_DEV_CAP_MAX_QP_SZ_OFFSET 0x11
423 #define QUERY_DEV_CAP_RSVD_QP_OFFSET 0x12
424 #define QUERY_DEV_CAP_MAX_QP_OFFSET 0x13
425 #define QUERY_DEV_CAP_RSVD_SRQ_OFFSET 0x14
426 #define QUERY_DEV_CAP_MAX_SRQ_OFFSET 0x15
427 #define QUERY_DEV_CAP_RSVD_EEC_OFFSET 0x16
428 #define QUERY_DEV_CAP_MAX_EEC_OFFSET 0x17
429 #define QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET 0x19
430 #define QUERY_DEV_CAP_RSVD_CQ_OFFSET 0x1a
431 #define QUERY_DEV_CAP_MAX_CQ_OFFSET 0x1b
432 #define QUERY_DEV_CAP_MAX_MPT_OFFSET 0x1d
433 #define QUERY_DEV_CAP_RSVD_EQ_OFFSET 0x1e
434 #define QUERY_DEV_CAP_MAX_EQ_OFFSET 0x1f
435 #define QUERY_DEV_CAP_RSVD_MTT_OFFSET 0x20
436 #define QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET 0x21
437 #define QUERY_DEV_CAP_RSVD_MRW_OFFSET 0x22
438 #define QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET 0x23
439 #define QUERY_DEV_CAP_MAX_AV_OFFSET 0x27
440 #define QUERY_DEV_CAP_MAX_REQ_QP_OFFSET 0x29
441 #define QUERY_DEV_CAP_MAX_RES_QP_OFFSET 0x2b
442 #define QUERY_DEV_CAP_MAX_GSO_OFFSET 0x2d
443 #define QUERY_DEV_CAP_RSS_OFFSET 0x2e
444 #define QUERY_DEV_CAP_MAX_RDMA_OFFSET 0x2f
445 #define QUERY_DEV_CAP_RSZ_SRQ_OFFSET 0x33
446 #define QUERY_DEV_CAP_ACK_DELAY_OFFSET 0x35
447 #define QUERY_DEV_CAP_MTU_WIDTH_OFFSET 0x36
448 #define QUERY_DEV_CAP_VL_PORT_OFFSET 0x37
449 #define QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET 0x38
450 #define QUERY_DEV_CAP_MAX_GID_OFFSET 0x3b
451 #define QUERY_DEV_CAP_RATE_SUPPORT_OFFSET 0x3c
452 #define QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET 0x3e
453 #define QUERY_DEV_CAP_MAX_PKEY_OFFSET 0x3f
454 #define QUERY_DEV_CAP_EXT_FLAGS_OFFSET 0x40
455 #define QUERY_DEV_CAP_FLAGS_OFFSET 0x44
456 #define QUERY_DEV_CAP_RSVD_UAR_OFFSET 0x48
457 #define QUERY_DEV_CAP_UAR_SZ_OFFSET 0x49
458 #define QUERY_DEV_CAP_PAGE_SZ_OFFSET 0x4b
459 #define QUERY_DEV_CAP_BF_OFFSET 0x4c
460 #define QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET 0x4d
461 #define QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET 0x4e
462 #define QUERY_DEV_CAP_LOG_MAX_BF_PAGES_OFFSET 0x4f
463 #define QUERY_DEV_CAP_MAX_SG_SQ_OFFSET 0x51
464 #define QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET 0x52
465 #define QUERY_DEV_CAP_MAX_SG_RQ_OFFSET 0x55
466 #define QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET 0x56
467 #define QUERY_DEV_CAP_MAX_QP_MCG_OFFSET 0x61
468 #define QUERY_DEV_CAP_RSVD_MCG_OFFSET 0x62
469 #define QUERY_DEV_CAP_MAX_MCG_OFFSET 0x63
470 #define QUERY_DEV_CAP_RSVD_PD_OFFSET 0x64
471 #define QUERY_DEV_CAP_MAX_PD_OFFSET 0x65
472 #define QUERY_DEV_CAP_RSVD_XRC_OFFSET 0x66
473 #define QUERY_DEV_CAP_MAX_XRC_OFFSET 0x67
474 #define QUERY_DEV_CAP_MAX_COUNTERS_OFFSET 0x68
475 #define QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET 0x70
476 #define QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET 0x76
477 #define QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET 0x77
478 #define QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET 0x80
479 #define QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET 0x82
480 #define QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET 0x84
481 #define QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET 0x86
482 #define QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET 0x88
483 #define QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET 0x8a
484 #define QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET 0x8c
485 #define QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET 0x8e
486 #define QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET 0x90
487 #define QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET 0x92
488 #define QUERY_DEV_CAP_BMME_FLAGS_OFFSET 0x94
489 #define QUERY_DEV_CAP_RSVD_LKEY_OFFSET 0x98
490 #define QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET 0xa0
491 #define QUERY_DEV_CAP_FW_REASSIGN_MAC 0x9d
492
493 dev_cap->flags2 = 0;
494 mailbox = mlx4_alloc_cmd_mailbox(dev);
495 if (IS_ERR(mailbox))
496 return PTR_ERR(mailbox);
497 outbox = mailbox->buf;
498
499 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP,
500 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
501 if (err)
502 goto out;
503
504 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_QP_OFFSET);
505 dev_cap->reserved_qps = 1 << (field & 0xf);
506 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_OFFSET);
507 dev_cap->max_qps = 1 << (field & 0x1f);
508 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_SRQ_OFFSET);
509 dev_cap->reserved_srqs = 1 << (field >> 4);
510 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_OFFSET);
511 dev_cap->max_srqs = 1 << (field & 0x1f);
512 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET);
513 dev_cap->max_cq_sz = 1 << field;
514 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_CQ_OFFSET);
515 dev_cap->reserved_cqs = 1 << (field & 0xf);
516 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_OFFSET);
517 dev_cap->max_cqs = 1 << (field & 0x1f);
518 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MPT_OFFSET);
519 dev_cap->max_mpts = 1 << (field & 0x3f);
520 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_EQ_OFFSET);
521 dev_cap->reserved_eqs = field & 0xf;
522 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_EQ_OFFSET);
523 dev_cap->max_eqs = 1 << (field & 0xf);
524 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MTT_OFFSET);
525 dev_cap->reserved_mtts = 1 << (field >> 4);
526 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET);
527 dev_cap->max_mrw_sz = 1 << field;
528 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MRW_OFFSET);
529 dev_cap->reserved_mrws = 1 << (field & 0xf);
530 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET);
531 dev_cap->max_mtt_seg = 1 << (field & 0x3f);
532 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_REQ_QP_OFFSET);
533 dev_cap->max_requester_per_qp = 1 << (field & 0x3f);
534 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RES_QP_OFFSET);
535 dev_cap->max_responder_per_qp = 1 << (field & 0x3f);
536 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GSO_OFFSET);
537 field &= 0x1f;
538 if (!field)
539 dev_cap->max_gso_sz = 0;
540 else
541 dev_cap->max_gso_sz = 1 << field;
542
543 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSS_OFFSET);
544 if (field & 0x20)
545 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_XOR;
546 if (field & 0x10)
547 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_TOP;
548 field &= 0xf;
549 if (field) {
550 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS;
551 dev_cap->max_rss_tbl_sz = 1 << field;
552 } else
553 dev_cap->max_rss_tbl_sz = 0;
554 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RDMA_OFFSET);
555 dev_cap->max_rdma_global = 1 << (field & 0x3f);
556 MLX4_GET(field, outbox, QUERY_DEV_CAP_ACK_DELAY_OFFSET);
557 dev_cap->local_ca_ack_delay = field & 0x1f;
558 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET);
559 dev_cap->num_ports = field & 0xf;
560 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET);
561 dev_cap->max_msg_sz = 1 << (field & 0x1f);
562 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET);
563 if (field & 0x80)
564 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FS_EN;
565 dev_cap->fs_log_max_ucast_qp_range_size = field & 0x1f;
566 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET);
567 dev_cap->fs_max_num_qp_per_entry = field;
568 MLX4_GET(stat_rate, outbox, QUERY_DEV_CAP_RATE_SUPPORT_OFFSET);
569 dev_cap->stat_rate_support = stat_rate;
570 MLX4_GET(field, outbox, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET);
571 if (field & 0x80)
572 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_TS;
573 MLX4_GET(ext_flags, outbox, QUERY_DEV_CAP_EXT_FLAGS_OFFSET);
574 MLX4_GET(flags, outbox, QUERY_DEV_CAP_FLAGS_OFFSET);
575 dev_cap->flags = flags | (u64)ext_flags << 32;
576 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_UAR_OFFSET);
577 dev_cap->reserved_uars = field >> 4;
578 MLX4_GET(field, outbox, QUERY_DEV_CAP_UAR_SZ_OFFSET);
579 dev_cap->uar_size = 1 << ((field & 0x3f) + 20);
580 MLX4_GET(field, outbox, QUERY_DEV_CAP_PAGE_SZ_OFFSET);
581 dev_cap->min_page_sz = 1 << field;
582
583 MLX4_GET(field, outbox, QUERY_DEV_CAP_BF_OFFSET);
584 if (field & 0x80) {
585 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET);
586 dev_cap->bf_reg_size = 1 << (field & 0x1f);
587 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET);
588 if ((1 << (field & 0x3f)) > (PAGE_SIZE / dev_cap->bf_reg_size))
589 field = 3;
590 dev_cap->bf_regs_per_page = 1 << (field & 0x3f);
591 mlx4_dbg(dev, "BlueFlame available (reg size %d, regs/page %d)\n",
592 dev_cap->bf_reg_size, dev_cap->bf_regs_per_page);
593 } else {
594 dev_cap->bf_reg_size = 0;
595 mlx4_dbg(dev, "BlueFlame not available\n");
596 }
597
598 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_SQ_OFFSET);
599 dev_cap->max_sq_sg = field;
600 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET);
601 dev_cap->max_sq_desc_sz = size;
602
603 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_MCG_OFFSET);
604 dev_cap->max_qp_per_mcg = 1 << field;
605 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MCG_OFFSET);
606 dev_cap->reserved_mgms = field & 0xf;
607 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MCG_OFFSET);
608 dev_cap->max_mcgs = 1 << field;
609 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_PD_OFFSET);
610 dev_cap->reserved_pds = field >> 4;
611 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PD_OFFSET);
612 dev_cap->max_pds = 1 << (field & 0x3f);
613 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_XRC_OFFSET);
614 dev_cap->reserved_xrcds = field >> 4;
615 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_XRC_OFFSET);
616 dev_cap->max_xrcds = 1 << (field & 0x1f);
617
618 MLX4_GET(size, outbox, QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET);
619 dev_cap->rdmarc_entry_sz = size;
620 MLX4_GET(size, outbox, QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET);
621 dev_cap->qpc_entry_sz = size;
622 MLX4_GET(size, outbox, QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET);
623 dev_cap->aux_entry_sz = size;
624 MLX4_GET(size, outbox, QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET);
625 dev_cap->altc_entry_sz = size;
626 MLX4_GET(size, outbox, QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET);
627 dev_cap->eqc_entry_sz = size;
628 MLX4_GET(size, outbox, QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET);
629 dev_cap->cqc_entry_sz = size;
630 MLX4_GET(size, outbox, QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET);
631 dev_cap->srq_entry_sz = size;
632 MLX4_GET(size, outbox, QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET);
633 dev_cap->cmpt_entry_sz = size;
634 MLX4_GET(size, outbox, QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET);
635 dev_cap->mtt_entry_sz = size;
636 MLX4_GET(size, outbox, QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET);
637 dev_cap->dmpt_entry_sz = size;
638
639 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET);
640 dev_cap->max_srq_sz = 1 << field;
641 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_SZ_OFFSET);
642 dev_cap->max_qp_sz = 1 << field;
643 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSZ_SRQ_OFFSET);
644 dev_cap->resize_srq = field & 1;
645 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_RQ_OFFSET);
646 dev_cap->max_rq_sg = field;
647 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET);
648 dev_cap->max_rq_desc_sz = size;
649
650 MLX4_GET(dev_cap->bmme_flags, outbox,
651 QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
652 MLX4_GET(dev_cap->reserved_lkey, outbox,
653 QUERY_DEV_CAP_RSVD_LKEY_OFFSET);
654 MLX4_GET(field, outbox, QUERY_DEV_CAP_FW_REASSIGN_MAC);
655 if (field & 1<<6)
656 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN;
657 MLX4_GET(dev_cap->max_icm_sz, outbox,
658 QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET);
659 if (dev_cap->flags & MLX4_DEV_CAP_FLAG_COUNTERS)
660 MLX4_GET(dev_cap->max_counters, outbox,
661 QUERY_DEV_CAP_MAX_COUNTERS_OFFSET);
662
663 MLX4_GET(field32, outbox, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET);
664 if (field32 & (1 << 16))
665 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_UPDATE_QP;
666 if (field32 & (1 << 26))
667 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_VLAN_CONTROL;
668 if (field32 & (1 << 20))
669 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FSM;
670
671 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
672 for (i = 1; i <= dev_cap->num_ports; ++i) {
673 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET);
674 dev_cap->max_vl[i] = field >> 4;
675 MLX4_GET(field, outbox, QUERY_DEV_CAP_MTU_WIDTH_OFFSET);
676 dev_cap->ib_mtu[i] = field >> 4;
677 dev_cap->max_port_width[i] = field & 0xf;
678 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GID_OFFSET);
679 dev_cap->max_gids[i] = 1 << (field & 0xf);
680 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PKEY_OFFSET);
681 dev_cap->max_pkeys[i] = 1 << (field & 0xf);
682 }
683 } else {
684 #define QUERY_PORT_SUPPORTED_TYPE_OFFSET 0x00
685 #define QUERY_PORT_MTU_OFFSET 0x01
686 #define QUERY_PORT_ETH_MTU_OFFSET 0x02
687 #define QUERY_PORT_WIDTH_OFFSET 0x06
688 #define QUERY_PORT_MAX_GID_PKEY_OFFSET 0x07
689 #define QUERY_PORT_MAX_MACVLAN_OFFSET 0x0a
690 #define QUERY_PORT_MAX_VL_OFFSET 0x0b
691 #define QUERY_PORT_MAC_OFFSET 0x10
692 #define QUERY_PORT_TRANS_VENDOR_OFFSET 0x18
693 #define QUERY_PORT_WAVELENGTH_OFFSET 0x1c
694 #define QUERY_PORT_TRANS_CODE_OFFSET 0x20
695
696 for (i = 1; i <= dev_cap->num_ports; ++i) {
697 err = mlx4_cmd_box(dev, 0, mailbox->dma, i, 0, MLX4_CMD_QUERY_PORT,
698 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
699 if (err)
700 goto out;
701
702 MLX4_GET(field, outbox, QUERY_PORT_SUPPORTED_TYPE_OFFSET);
703 dev_cap->supported_port_types[i] = field & 3;
704 dev_cap->suggested_type[i] = (field >> 3) & 1;
705 dev_cap->default_sense[i] = (field >> 4) & 1;
706 MLX4_GET(field, outbox, QUERY_PORT_MTU_OFFSET);
707 dev_cap->ib_mtu[i] = field & 0xf;
708 MLX4_GET(field, outbox, QUERY_PORT_WIDTH_OFFSET);
709 dev_cap->max_port_width[i] = field & 0xf;
710 MLX4_GET(field, outbox, QUERY_PORT_MAX_GID_PKEY_OFFSET);
711 dev_cap->max_gids[i] = 1 << (field >> 4);
712 dev_cap->max_pkeys[i] = 1 << (field & 0xf);
713 MLX4_GET(field, outbox, QUERY_PORT_MAX_VL_OFFSET);
714 dev_cap->max_vl[i] = field & 0xf;
715 MLX4_GET(field, outbox, QUERY_PORT_MAX_MACVLAN_OFFSET);
716 dev_cap->log_max_macs[i] = field & 0xf;
717 dev_cap->log_max_vlans[i] = field >> 4;
718 MLX4_GET(dev_cap->eth_mtu[i], outbox, QUERY_PORT_ETH_MTU_OFFSET);
719 MLX4_GET(dev_cap->def_mac[i], outbox, QUERY_PORT_MAC_OFFSET);
720 MLX4_GET(field32, outbox, QUERY_PORT_TRANS_VENDOR_OFFSET);
721 dev_cap->trans_type[i] = field32 >> 24;
722 dev_cap->vendor_oui[i] = field32 & 0xffffff;
723 MLX4_GET(dev_cap->wavelength[i], outbox, QUERY_PORT_WAVELENGTH_OFFSET);
724 MLX4_GET(dev_cap->trans_code[i], outbox, QUERY_PORT_TRANS_CODE_OFFSET);
725 }
726 }
727
728 mlx4_dbg(dev, "Base MM extensions: flags %08x, rsvd L_Key %08x\n",
729 dev_cap->bmme_flags, dev_cap->reserved_lkey);
730
731 /*
732 * Each UAR has 4 EQ doorbells; so if a UAR is reserved, then
733 * we can't use any EQs whose doorbell falls on that page,
734 * even if the EQ itself isn't reserved.
735 */
736 dev_cap->reserved_eqs = max(dev_cap->reserved_uars * 4,
737 dev_cap->reserved_eqs);
738
739 mlx4_dbg(dev, "Max ICM size %lld MB\n",
740 (unsigned long long) dev_cap->max_icm_sz >> 20);
741 mlx4_dbg(dev, "Max QPs: %d, reserved QPs: %d, entry size: %d\n",
742 dev_cap->max_qps, dev_cap->reserved_qps, dev_cap->qpc_entry_sz);
743 mlx4_dbg(dev, "Max SRQs: %d, reserved SRQs: %d, entry size: %d\n",
744 dev_cap->max_srqs, dev_cap->reserved_srqs, dev_cap->srq_entry_sz);
745 mlx4_dbg(dev, "Max CQs: %d, reserved CQs: %d, entry size: %d\n",
746 dev_cap->max_cqs, dev_cap->reserved_cqs, dev_cap->cqc_entry_sz);
747 mlx4_dbg(dev, "Max EQs: %d, reserved EQs: %d, entry size: %d\n",
748 dev_cap->max_eqs, dev_cap->reserved_eqs, dev_cap->eqc_entry_sz);
749 mlx4_dbg(dev, "reserved MPTs: %d, reserved MTTs: %d\n",
750 dev_cap->reserved_mrws, dev_cap->reserved_mtts);
751 mlx4_dbg(dev, "Max PDs: %d, reserved PDs: %d, reserved UARs: %d\n",
752 dev_cap->max_pds, dev_cap->reserved_pds, dev_cap->reserved_uars);
753 mlx4_dbg(dev, "Max QP/MCG: %d, reserved MGMs: %d\n",
754 dev_cap->max_pds, dev_cap->reserved_mgms);
755 mlx4_dbg(dev, "Max CQEs: %d, max WQEs: %d, max SRQ WQEs: %d\n",
756 dev_cap->max_cq_sz, dev_cap->max_qp_sz, dev_cap->max_srq_sz);
757 mlx4_dbg(dev, "Local CA ACK delay: %d, max MTU: %d, port width cap: %d\n",
758 dev_cap->local_ca_ack_delay, 128 << dev_cap->ib_mtu[1],
759 dev_cap->max_port_width[1]);
760 mlx4_dbg(dev, "Max SQ desc size: %d, max SQ S/G: %d\n",
761 dev_cap->max_sq_desc_sz, dev_cap->max_sq_sg);
762 mlx4_dbg(dev, "Max RQ desc size: %d, max RQ S/G: %d\n",
763 dev_cap->max_rq_desc_sz, dev_cap->max_rq_sg);
764 mlx4_dbg(dev, "Max GSO size: %d\n", dev_cap->max_gso_sz);
765 mlx4_dbg(dev, "Max counters: %d\n", dev_cap->max_counters);
766 mlx4_dbg(dev, "Max RSS Table size: %d\n", dev_cap->max_rss_tbl_sz);
767
768 dump_dev_cap_flags(dev, dev_cap->flags);
769 dump_dev_cap_flags2(dev, dev_cap->flags2);
770
771 out:
772 mlx4_free_cmd_mailbox(dev, mailbox);
773 return err;
774 }
775
776 int mlx4_QUERY_DEV_CAP_wrapper(struct mlx4_dev *dev, int slave,
777 struct mlx4_vhcr *vhcr,
778 struct mlx4_cmd_mailbox *inbox,
779 struct mlx4_cmd_mailbox *outbox,
780 struct mlx4_cmd_info *cmd)
781 {
782 u64 flags;
783 int err = 0;
784 u8 field;
785 u32 bmme_flags;
786
787 err = mlx4_cmd_box(dev, 0, outbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP,
788 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
789 if (err)
790 return err;
791
792 /* add port mng change event capability and disable mw type 1
793 * unconditionally to slaves
794 */
795 MLX4_GET(flags, outbox->buf, QUERY_DEV_CAP_EXT_FLAGS_OFFSET);
796 flags |= MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV;
797 flags &= ~MLX4_DEV_CAP_FLAG_MEM_WINDOW;
798 MLX4_PUT(outbox->buf, flags, QUERY_DEV_CAP_EXT_FLAGS_OFFSET);
799
800 /* For guests, disable timestamp */
801 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET);
802 field &= 0x7f;
803 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET);
804
805 /* For guests, report Blueflame disabled */
806 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_BF_OFFSET);
807 field &= 0x7f;
808 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_BF_OFFSET);
809
810 /* For guests, disable mw type 2 */
811 MLX4_GET(bmme_flags, outbox, QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
812 bmme_flags &= ~MLX4_BMME_FLAG_TYPE_2_WIN;
813 MLX4_PUT(outbox->buf, bmme_flags, QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
814
815 /* turn off device-managed steering capability if not enabled */
816 if (dev->caps.steering_mode != MLX4_STEERING_MODE_DEVICE_MANAGED) {
817 MLX4_GET(field, outbox->buf,
818 QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET);
819 field &= 0x7f;
820 MLX4_PUT(outbox->buf, field,
821 QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET);
822 }
823 return 0;
824 }
825
826 int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave,
827 struct mlx4_vhcr *vhcr,
828 struct mlx4_cmd_mailbox *inbox,
829 struct mlx4_cmd_mailbox *outbox,
830 struct mlx4_cmd_info *cmd)
831 {
832 struct mlx4_priv *priv = mlx4_priv(dev);
833 u64 def_mac;
834 u8 port_type;
835 u16 short_field;
836 int err;
837 int admin_link_state;
838
839 #define MLX4_VF_PORT_NO_LINK_SENSE_MASK 0xE0
840 #define MLX4_PORT_LINK_UP_MASK 0x80
841 #define QUERY_PORT_CUR_MAX_PKEY_OFFSET 0x0c
842 #define QUERY_PORT_CUR_MAX_GID_OFFSET 0x0e
843
844 err = mlx4_cmd_box(dev, 0, outbox->dma, vhcr->in_modifier, 0,
845 MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B,
846 MLX4_CMD_NATIVE);
847
848 if (!err && dev->caps.function != slave) {
849 def_mac = priv->mfunc.master.vf_oper[slave].vport[vhcr->in_modifier].state.mac;
850 MLX4_PUT(outbox->buf, def_mac, QUERY_PORT_MAC_OFFSET);
851
852 /* get port type - currently only eth is enabled */
853 MLX4_GET(port_type, outbox->buf,
854 QUERY_PORT_SUPPORTED_TYPE_OFFSET);
855
856 /* No link sensing allowed */
857 port_type &= MLX4_VF_PORT_NO_LINK_SENSE_MASK;
858 /* set port type to currently operating port type */
859 port_type |= (dev->caps.port_type[vhcr->in_modifier] & 0x3);
860
861 admin_link_state = priv->mfunc.master.vf_oper[slave].vport[vhcr->in_modifier].state.link_state;
862 if (IFLA_VF_LINK_STATE_ENABLE == admin_link_state)
863 port_type |= MLX4_PORT_LINK_UP_MASK;
864 else if (IFLA_VF_LINK_STATE_DISABLE == admin_link_state)
865 port_type &= ~MLX4_PORT_LINK_UP_MASK;
866
867 MLX4_PUT(outbox->buf, port_type,
868 QUERY_PORT_SUPPORTED_TYPE_OFFSET);
869
870 short_field = 1; /* slave max gids */
871 MLX4_PUT(outbox->buf, short_field,
872 QUERY_PORT_CUR_MAX_GID_OFFSET);
873
874 short_field = dev->caps.pkey_table_len[vhcr->in_modifier];
875 MLX4_PUT(outbox->buf, short_field,
876 QUERY_PORT_CUR_MAX_PKEY_OFFSET);
877 }
878
879 return err;
880 }
881
882 int mlx4_get_slave_pkey_gid_tbl_len(struct mlx4_dev *dev, u8 port,
883 int *gid_tbl_len, int *pkey_tbl_len)
884 {
885 struct mlx4_cmd_mailbox *mailbox;
886 u32 *outbox;
887 u16 field;
888 int err;
889
890 mailbox = mlx4_alloc_cmd_mailbox(dev);
891 if (IS_ERR(mailbox))
892 return PTR_ERR(mailbox);
893
894 err = mlx4_cmd_box(dev, 0, mailbox->dma, port, 0,
895 MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B,
896 MLX4_CMD_WRAPPED);
897 if (err)
898 goto out;
899
900 outbox = mailbox->buf;
901
902 MLX4_GET(field, outbox, QUERY_PORT_CUR_MAX_GID_OFFSET);
903 *gid_tbl_len = field;
904
905 MLX4_GET(field, outbox, QUERY_PORT_CUR_MAX_PKEY_OFFSET);
906 *pkey_tbl_len = field;
907
908 out:
909 mlx4_free_cmd_mailbox(dev, mailbox);
910 return err;
911 }
912 EXPORT_SYMBOL(mlx4_get_slave_pkey_gid_tbl_len);
913
914 int mlx4_map_cmd(struct mlx4_dev *dev, u16 op, struct mlx4_icm *icm, u64 virt)
915 {
916 struct mlx4_cmd_mailbox *mailbox;
917 struct mlx4_icm_iter iter;
918 __be64 *pages;
919 int lg;
920 int nent = 0;
921 int i;
922 int err = 0;
923 int ts = 0, tc = 0;
924
925 mailbox = mlx4_alloc_cmd_mailbox(dev);
926 if (IS_ERR(mailbox))
927 return PTR_ERR(mailbox);
928 memset(mailbox->buf, 0, MLX4_MAILBOX_SIZE);
929 pages = mailbox->buf;
930
931 for (mlx4_icm_first(icm, &iter);
932 !mlx4_icm_last(&iter);
933 mlx4_icm_next(&iter)) {
934 /*
935 * We have to pass pages that are aligned to their
936 * size, so find the least significant 1 in the
937 * address or size and use that as our log2 size.
938 */
939 lg = ffs(mlx4_icm_addr(&iter) | mlx4_icm_size(&iter)) - 1;
940 if (lg < MLX4_ICM_PAGE_SHIFT) {
941 mlx4_warn(dev, "Got FW area not aligned to %d (%llx/%lx).\n",
942 MLX4_ICM_PAGE_SIZE,
943 (unsigned long long) mlx4_icm_addr(&iter),
944 mlx4_icm_size(&iter));
945 err = -EINVAL;
946 goto out;
947 }
948
949 for (i = 0; i < mlx4_icm_size(&iter) >> lg; ++i) {
950 if (virt != -1) {
951 pages[nent * 2] = cpu_to_be64(virt);
952 virt += 1 << lg;
953 }
954
955 pages[nent * 2 + 1] =
956 cpu_to_be64((mlx4_icm_addr(&iter) + (i << lg)) |
957 (lg - MLX4_ICM_PAGE_SHIFT));
958 ts += 1 << (lg - 10);
959 ++tc;
960
961 if (++nent == MLX4_MAILBOX_SIZE / 16) {
962 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op,
963 MLX4_CMD_TIME_CLASS_B,
964 MLX4_CMD_NATIVE);
965 if (err)
966 goto out;
967 nent = 0;
968 }
969 }
970 }
971
972 if (nent)
973 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op,
974 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
975 if (err)
976 goto out;
977
978 switch (op) {
979 case MLX4_CMD_MAP_FA:
980 mlx4_dbg(dev, "Mapped %d chunks/%d KB for FW.\n", tc, ts);
981 break;
982 case MLX4_CMD_MAP_ICM_AUX:
983 mlx4_dbg(dev, "Mapped %d chunks/%d KB for ICM aux.\n", tc, ts);
984 break;
985 case MLX4_CMD_MAP_ICM:
986 mlx4_dbg(dev, "Mapped %d chunks/%d KB at %llx for ICM.\n",
987 tc, ts, (unsigned long long) virt - (ts << 10));
988 break;
989 }
990
991 out:
992 mlx4_free_cmd_mailbox(dev, mailbox);
993 return err;
994 }
995
996 int mlx4_MAP_FA(struct mlx4_dev *dev, struct mlx4_icm *icm)
997 {
998 return mlx4_map_cmd(dev, MLX4_CMD_MAP_FA, icm, -1);
999 }
1000
1001 int mlx4_UNMAP_FA(struct mlx4_dev *dev)
1002 {
1003 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_UNMAP_FA,
1004 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
1005 }
1006
1007
1008 int mlx4_RUN_FW(struct mlx4_dev *dev)
1009 {
1010 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_RUN_FW,
1011 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1012 }
1013
1014 int mlx4_QUERY_FW(struct mlx4_dev *dev)
1015 {
1016 struct mlx4_fw *fw = &mlx4_priv(dev)->fw;
1017 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
1018 struct mlx4_cmd_mailbox *mailbox;
1019 u32 *outbox;
1020 int err = 0;
1021 u64 fw_ver;
1022 u16 cmd_if_rev;
1023 u8 lg;
1024
1025 #define QUERY_FW_OUT_SIZE 0x100
1026 #define QUERY_FW_VER_OFFSET 0x00
1027 #define QUERY_FW_PPF_ID 0x09
1028 #define QUERY_FW_CMD_IF_REV_OFFSET 0x0a
1029 #define QUERY_FW_MAX_CMD_OFFSET 0x0f
1030 #define QUERY_FW_ERR_START_OFFSET 0x30
1031 #define QUERY_FW_ERR_SIZE_OFFSET 0x38
1032 #define QUERY_FW_ERR_BAR_OFFSET 0x3c
1033
1034 #define QUERY_FW_SIZE_OFFSET 0x00
1035 #define QUERY_FW_CLR_INT_BASE_OFFSET 0x20
1036 #define QUERY_FW_CLR_INT_BAR_OFFSET 0x28
1037
1038 #define QUERY_FW_COMM_BASE_OFFSET 0x40
1039 #define QUERY_FW_COMM_BAR_OFFSET 0x48
1040
1041 #define QUERY_FW_CLOCK_OFFSET 0x50
1042 #define QUERY_FW_CLOCK_BAR 0x58
1043
1044 mailbox = mlx4_alloc_cmd_mailbox(dev);
1045 if (IS_ERR(mailbox))
1046 return PTR_ERR(mailbox);
1047 outbox = mailbox->buf;
1048
1049 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_FW,
1050 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1051 if (err)
1052 goto out;
1053
1054 MLX4_GET(fw_ver, outbox, QUERY_FW_VER_OFFSET);
1055 /*
1056 * FW subminor version is at more significant bits than minor
1057 * version, so swap here.
1058 */
1059 dev->caps.fw_ver = (fw_ver & 0xffff00000000ull) |
1060 ((fw_ver & 0xffff0000ull) >> 16) |
1061 ((fw_ver & 0x0000ffffull) << 16);
1062
1063 MLX4_GET(lg, outbox, QUERY_FW_PPF_ID);
1064 dev->caps.function = lg;
1065
1066 if (mlx4_is_slave(dev))
1067 goto out;
1068
1069
1070 MLX4_GET(cmd_if_rev, outbox, QUERY_FW_CMD_IF_REV_OFFSET);
1071 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_MIN_REV ||
1072 cmd_if_rev > MLX4_COMMAND_INTERFACE_MAX_REV) {
1073 mlx4_err(dev, "Installed FW has unsupported "
1074 "command interface revision %d.\n",
1075 cmd_if_rev);
1076 mlx4_err(dev, "(Installed FW version is %d.%d.%03d)\n",
1077 (int) (dev->caps.fw_ver >> 32),
1078 (int) (dev->caps.fw_ver >> 16) & 0xffff,
1079 (int) dev->caps.fw_ver & 0xffff);
1080 mlx4_err(dev, "This driver version supports only revisions %d to %d.\n",
1081 MLX4_COMMAND_INTERFACE_MIN_REV, MLX4_COMMAND_INTERFACE_MAX_REV);
1082 err = -ENODEV;
1083 goto out;
1084 }
1085
1086 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS)
1087 dev->flags |= MLX4_FLAG_OLD_PORT_CMDS;
1088
1089 MLX4_GET(lg, outbox, QUERY_FW_MAX_CMD_OFFSET);
1090 cmd->max_cmds = 1 << lg;
1091
1092 mlx4_dbg(dev, "FW version %d.%d.%03d (cmd intf rev %d), max commands %d\n",
1093 (int) (dev->caps.fw_ver >> 32),
1094 (int) (dev->caps.fw_ver >> 16) & 0xffff,
1095 (int) dev->caps.fw_ver & 0xffff,
1096 cmd_if_rev, cmd->max_cmds);
1097
1098 MLX4_GET(fw->catas_offset, outbox, QUERY_FW_ERR_START_OFFSET);
1099 MLX4_GET(fw->catas_size, outbox, QUERY_FW_ERR_SIZE_OFFSET);
1100 MLX4_GET(fw->catas_bar, outbox, QUERY_FW_ERR_BAR_OFFSET);
1101 fw->catas_bar = (fw->catas_bar >> 6) * 2;
1102
1103 mlx4_dbg(dev, "Catastrophic error buffer at 0x%llx, size 0x%x, BAR %d\n",
1104 (unsigned long long) fw->catas_offset, fw->catas_size, fw->catas_bar);
1105
1106 MLX4_GET(fw->fw_pages, outbox, QUERY_FW_SIZE_OFFSET);
1107 MLX4_GET(fw->clr_int_base, outbox, QUERY_FW_CLR_INT_BASE_OFFSET);
1108 MLX4_GET(fw->clr_int_bar, outbox, QUERY_FW_CLR_INT_BAR_OFFSET);
1109 fw->clr_int_bar = (fw->clr_int_bar >> 6) * 2;
1110
1111 MLX4_GET(fw->comm_base, outbox, QUERY_FW_COMM_BASE_OFFSET);
1112 MLX4_GET(fw->comm_bar, outbox, QUERY_FW_COMM_BAR_OFFSET);
1113 fw->comm_bar = (fw->comm_bar >> 6) * 2;
1114 mlx4_dbg(dev, "Communication vector bar:%d offset:0x%llx\n",
1115 fw->comm_bar, fw->comm_base);
1116 mlx4_dbg(dev, "FW size %d KB\n", fw->fw_pages >> 2);
1117
1118 MLX4_GET(fw->clock_offset, outbox, QUERY_FW_CLOCK_OFFSET);
1119 MLX4_GET(fw->clock_bar, outbox, QUERY_FW_CLOCK_BAR);
1120 fw->clock_bar = (fw->clock_bar >> 6) * 2;
1121 mlx4_dbg(dev, "Internal clock bar:%d offset:0x%llx\n",
1122 fw->clock_bar, fw->clock_offset);
1123
1124 /*
1125 * Round up number of system pages needed in case
1126 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE.
1127 */
1128 fw->fw_pages =
1129 ALIGN(fw->fw_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >>
1130 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT);
1131
1132 mlx4_dbg(dev, "Clear int @ %llx, BAR %d\n",
1133 (unsigned long long) fw->clr_int_base, fw->clr_int_bar);
1134
1135 out:
1136 mlx4_free_cmd_mailbox(dev, mailbox);
1137 return err;
1138 }
1139
1140 int mlx4_QUERY_FW_wrapper(struct mlx4_dev *dev, int slave,
1141 struct mlx4_vhcr *vhcr,
1142 struct mlx4_cmd_mailbox *inbox,
1143 struct mlx4_cmd_mailbox *outbox,
1144 struct mlx4_cmd_info *cmd)
1145 {
1146 u8 *outbuf;
1147 int err;
1148
1149 outbuf = outbox->buf;
1150 err = mlx4_cmd_box(dev, 0, outbox->dma, 0, 0, MLX4_CMD_QUERY_FW,
1151 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1152 if (err)
1153 return err;
1154
1155 /* for slaves, set pci PPF ID to invalid and zero out everything
1156 * else except FW version */
1157 outbuf[0] = outbuf[1] = 0;
1158 memset(&outbuf[8], 0, QUERY_FW_OUT_SIZE - 8);
1159 outbuf[QUERY_FW_PPF_ID] = MLX4_INVALID_SLAVE_ID;
1160
1161 return 0;
1162 }
1163
1164 static void get_board_id(void *vsd, char *board_id)
1165 {
1166 int i;
1167
1168 #define VSD_OFFSET_SIG1 0x00
1169 #define VSD_OFFSET_SIG2 0xde
1170 #define VSD_OFFSET_MLX_BOARD_ID 0xd0
1171 #define VSD_OFFSET_TS_BOARD_ID 0x20
1172
1173 #define VSD_SIGNATURE_TOPSPIN 0x5ad
1174
1175 memset(board_id, 0, MLX4_BOARD_ID_LEN);
1176
1177 if (be16_to_cpup(vsd + VSD_OFFSET_SIG1) == VSD_SIGNATURE_TOPSPIN &&
1178 be16_to_cpup(vsd + VSD_OFFSET_SIG2) == VSD_SIGNATURE_TOPSPIN) {
1179 strlcpy(board_id, vsd + VSD_OFFSET_TS_BOARD_ID, MLX4_BOARD_ID_LEN);
1180 } else {
1181 /*
1182 * The board ID is a string but the firmware byte
1183 * swaps each 4-byte word before passing it back to
1184 * us. Therefore we need to swab it before printing.
1185 */
1186 for (i = 0; i < 4; ++i)
1187 ((u32 *) board_id)[i] =
1188 swab32(*(u32 *) (vsd + VSD_OFFSET_MLX_BOARD_ID + i * 4));
1189 }
1190 }
1191
1192 int mlx4_QUERY_ADAPTER(struct mlx4_dev *dev, struct mlx4_adapter *adapter)
1193 {
1194 struct mlx4_cmd_mailbox *mailbox;
1195 u32 *outbox;
1196 int err;
1197
1198 #define QUERY_ADAPTER_OUT_SIZE 0x100
1199 #define QUERY_ADAPTER_INTA_PIN_OFFSET 0x10
1200 #define QUERY_ADAPTER_VSD_OFFSET 0x20
1201
1202 mailbox = mlx4_alloc_cmd_mailbox(dev);
1203 if (IS_ERR(mailbox))
1204 return PTR_ERR(mailbox);
1205 outbox = mailbox->buf;
1206
1207 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_ADAPTER,
1208 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1209 if (err)
1210 goto out;
1211
1212 MLX4_GET(adapter->inta_pin, outbox, QUERY_ADAPTER_INTA_PIN_OFFSET);
1213
1214 get_board_id(outbox + QUERY_ADAPTER_VSD_OFFSET / 4,
1215 adapter->board_id);
1216
1217 out:
1218 mlx4_free_cmd_mailbox(dev, mailbox);
1219 return err;
1220 }
1221
1222 int mlx4_INIT_HCA(struct mlx4_dev *dev, struct mlx4_init_hca_param *param)
1223 {
1224 struct mlx4_cmd_mailbox *mailbox;
1225 __be32 *inbox;
1226 int err;
1227
1228 #define INIT_HCA_IN_SIZE 0x200
1229 #define INIT_HCA_VERSION_OFFSET 0x000
1230 #define INIT_HCA_VERSION 2
1231 #define INIT_HCA_CACHELINE_SZ_OFFSET 0x0e
1232 #define INIT_HCA_FLAGS_OFFSET 0x014
1233 #define INIT_HCA_QPC_OFFSET 0x020
1234 #define INIT_HCA_QPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x10)
1235 #define INIT_HCA_LOG_QP_OFFSET (INIT_HCA_QPC_OFFSET + 0x17)
1236 #define INIT_HCA_SRQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x28)
1237 #define INIT_HCA_LOG_SRQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x2f)
1238 #define INIT_HCA_CQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x30)
1239 #define INIT_HCA_LOG_CQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x37)
1240 #define INIT_HCA_EQE_CQE_OFFSETS (INIT_HCA_QPC_OFFSET + 0x38)
1241 #define INIT_HCA_ALTC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x40)
1242 #define INIT_HCA_AUXC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x50)
1243 #define INIT_HCA_EQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x60)
1244 #define INIT_HCA_LOG_EQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x67)
1245 #define INIT_HCA_RDMARC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x70)
1246 #define INIT_HCA_LOG_RD_OFFSET (INIT_HCA_QPC_OFFSET + 0x77)
1247 #define INIT_HCA_MCAST_OFFSET 0x0c0
1248 #define INIT_HCA_MC_BASE_OFFSET (INIT_HCA_MCAST_OFFSET + 0x00)
1249 #define INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x12)
1250 #define INIT_HCA_LOG_MC_HASH_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x16)
1251 #define INIT_HCA_UC_STEERING_OFFSET (INIT_HCA_MCAST_OFFSET + 0x18)
1252 #define INIT_HCA_LOG_MC_TABLE_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x1b)
1253 #define INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN 0x6
1254 #define INIT_HCA_FS_PARAM_OFFSET 0x1d0
1255 #define INIT_HCA_FS_BASE_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x00)
1256 #define INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x12)
1257 #define INIT_HCA_FS_LOG_TABLE_SZ_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x1b)
1258 #define INIT_HCA_FS_ETH_BITS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x21)
1259 #define INIT_HCA_FS_ETH_NUM_ADDRS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x22)
1260 #define INIT_HCA_FS_IB_BITS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x25)
1261 #define INIT_HCA_FS_IB_NUM_ADDRS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x26)
1262 #define INIT_HCA_TPT_OFFSET 0x0f0
1263 #define INIT_HCA_DMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x00)
1264 #define INIT_HCA_TPT_MW_OFFSET (INIT_HCA_TPT_OFFSET + 0x08)
1265 #define INIT_HCA_LOG_MPT_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x0b)
1266 #define INIT_HCA_MTT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x10)
1267 #define INIT_HCA_CMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x18)
1268 #define INIT_HCA_UAR_OFFSET 0x120
1269 #define INIT_HCA_LOG_UAR_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0a)
1270 #define INIT_HCA_UAR_PAGE_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0b)
1271
1272 mailbox = mlx4_alloc_cmd_mailbox(dev);
1273 if (IS_ERR(mailbox))
1274 return PTR_ERR(mailbox);
1275 inbox = mailbox->buf;
1276
1277 memset(inbox, 0, INIT_HCA_IN_SIZE);
1278
1279 *((u8 *) mailbox->buf + INIT_HCA_VERSION_OFFSET) = INIT_HCA_VERSION;
1280
1281 *((u8 *) mailbox->buf + INIT_HCA_CACHELINE_SZ_OFFSET) =
1282 (ilog2(cache_line_size()) - 4) << 5;
1283
1284 #if defined(__LITTLE_ENDIAN)
1285 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) &= ~cpu_to_be32(1 << 1);
1286 #elif defined(__BIG_ENDIAN)
1287 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 1);
1288 #else
1289 #error Host endianness not defined
1290 #endif
1291 /* Check port for UD address vector: */
1292 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1);
1293
1294 /* Enable IPoIB checksumming if we can: */
1295 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_IPOIB_CSUM)
1296 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 3);
1297
1298 /* Enable QoS support if module parameter set */
1299 if (enable_qos)
1300 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 2);
1301
1302 /* enable counters */
1303 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS)
1304 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 4);
1305
1306 /* CX3 is capable of extending CQEs/EQEs from 32 to 64 bytes */
1307 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_64B_EQE) {
1308 *(inbox + INIT_HCA_EQE_CQE_OFFSETS / 4) |= cpu_to_be32(1 << 29);
1309 dev->caps.eqe_size = 64;
1310 dev->caps.eqe_factor = 1;
1311 } else {
1312 dev->caps.eqe_size = 32;
1313 dev->caps.eqe_factor = 0;
1314 }
1315
1316 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_64B_CQE) {
1317 *(inbox + INIT_HCA_EQE_CQE_OFFSETS / 4) |= cpu_to_be32(1 << 30);
1318 dev->caps.cqe_size = 64;
1319 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_64B_CQE;
1320 } else {
1321 dev->caps.cqe_size = 32;
1322 }
1323
1324 /* QPC/EEC/CQC/EQC/RDMARC attributes */
1325
1326 MLX4_PUT(inbox, param->qpc_base, INIT_HCA_QPC_BASE_OFFSET);
1327 MLX4_PUT(inbox, param->log_num_qps, INIT_HCA_LOG_QP_OFFSET);
1328 MLX4_PUT(inbox, param->srqc_base, INIT_HCA_SRQC_BASE_OFFSET);
1329 MLX4_PUT(inbox, param->log_num_srqs, INIT_HCA_LOG_SRQ_OFFSET);
1330 MLX4_PUT(inbox, param->cqc_base, INIT_HCA_CQC_BASE_OFFSET);
1331 MLX4_PUT(inbox, param->log_num_cqs, INIT_HCA_LOG_CQ_OFFSET);
1332 MLX4_PUT(inbox, param->altc_base, INIT_HCA_ALTC_BASE_OFFSET);
1333 MLX4_PUT(inbox, param->auxc_base, INIT_HCA_AUXC_BASE_OFFSET);
1334 MLX4_PUT(inbox, param->eqc_base, INIT_HCA_EQC_BASE_OFFSET);
1335 MLX4_PUT(inbox, param->log_num_eqs, INIT_HCA_LOG_EQ_OFFSET);
1336 MLX4_PUT(inbox, param->rdmarc_base, INIT_HCA_RDMARC_BASE_OFFSET);
1337 MLX4_PUT(inbox, param->log_rd_per_qp, INIT_HCA_LOG_RD_OFFSET);
1338
1339 /* steering attributes */
1340 if (dev->caps.steering_mode ==
1341 MLX4_STEERING_MODE_DEVICE_MANAGED) {
1342 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |=
1343 cpu_to_be32(1 <<
1344 INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN);
1345
1346 MLX4_PUT(inbox, param->mc_base, INIT_HCA_FS_BASE_OFFSET);
1347 MLX4_PUT(inbox, param->log_mc_entry_sz,
1348 INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET);
1349 MLX4_PUT(inbox, param->log_mc_table_sz,
1350 INIT_HCA_FS_LOG_TABLE_SZ_OFFSET);
1351 /* Enable Ethernet flow steering
1352 * with udp unicast and tcp unicast
1353 */
1354 MLX4_PUT(inbox, (u8) (MLX4_FS_UDP_UC_EN | MLX4_FS_TCP_UC_EN),
1355 INIT_HCA_FS_ETH_BITS_OFFSET);
1356 MLX4_PUT(inbox, (u16) MLX4_FS_NUM_OF_L2_ADDR,
1357 INIT_HCA_FS_ETH_NUM_ADDRS_OFFSET);
1358 /* Enable IPoIB flow steering
1359 * with udp unicast and tcp unicast
1360 */
1361 MLX4_PUT(inbox, (u8) (MLX4_FS_UDP_UC_EN | MLX4_FS_TCP_UC_EN),
1362 INIT_HCA_FS_IB_BITS_OFFSET);
1363 MLX4_PUT(inbox, (u16) MLX4_FS_NUM_OF_L2_ADDR,
1364 INIT_HCA_FS_IB_NUM_ADDRS_OFFSET);
1365 } else {
1366 MLX4_PUT(inbox, param->mc_base, INIT_HCA_MC_BASE_OFFSET);
1367 MLX4_PUT(inbox, param->log_mc_entry_sz,
1368 INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET);
1369 MLX4_PUT(inbox, param->log_mc_hash_sz,
1370 INIT_HCA_LOG_MC_HASH_SZ_OFFSET);
1371 MLX4_PUT(inbox, param->log_mc_table_sz,
1372 INIT_HCA_LOG_MC_TABLE_SZ_OFFSET);
1373 if (dev->caps.steering_mode == MLX4_STEERING_MODE_B0)
1374 MLX4_PUT(inbox, (u8) (1 << 3),
1375 INIT_HCA_UC_STEERING_OFFSET);
1376 }
1377
1378 /* TPT attributes */
1379
1380 MLX4_PUT(inbox, param->dmpt_base, INIT_HCA_DMPT_BASE_OFFSET);
1381 MLX4_PUT(inbox, param->mw_enabled, INIT_HCA_TPT_MW_OFFSET);
1382 MLX4_PUT(inbox, param->log_mpt_sz, INIT_HCA_LOG_MPT_SZ_OFFSET);
1383 MLX4_PUT(inbox, param->mtt_base, INIT_HCA_MTT_BASE_OFFSET);
1384 MLX4_PUT(inbox, param->cmpt_base, INIT_HCA_CMPT_BASE_OFFSET);
1385
1386 /* UAR attributes */
1387
1388 MLX4_PUT(inbox, param->uar_page_sz, INIT_HCA_UAR_PAGE_SZ_OFFSET);
1389 MLX4_PUT(inbox, param->log_uar_sz, INIT_HCA_LOG_UAR_SZ_OFFSET);
1390
1391 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_INIT_HCA, 10000,
1392 MLX4_CMD_NATIVE);
1393
1394 if (err)
1395 mlx4_err(dev, "INIT_HCA returns %d\n", err);
1396
1397 mlx4_free_cmd_mailbox(dev, mailbox);
1398 return err;
1399 }
1400
1401 int mlx4_QUERY_HCA(struct mlx4_dev *dev,
1402 struct mlx4_init_hca_param *param)
1403 {
1404 struct mlx4_cmd_mailbox *mailbox;
1405 __be32 *outbox;
1406 u32 dword_field;
1407 int err;
1408 u8 byte_field;
1409
1410 #define QUERY_HCA_GLOBAL_CAPS_OFFSET 0x04
1411 #define QUERY_HCA_CORE_CLOCK_OFFSET 0x0c
1412
1413 mailbox = mlx4_alloc_cmd_mailbox(dev);
1414 if (IS_ERR(mailbox))
1415 return PTR_ERR(mailbox);
1416 outbox = mailbox->buf;
1417
1418 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0,
1419 MLX4_CMD_QUERY_HCA,
1420 MLX4_CMD_TIME_CLASS_B,
1421 !mlx4_is_slave(dev));
1422 if (err)
1423 goto out;
1424
1425 MLX4_GET(param->global_caps, outbox, QUERY_HCA_GLOBAL_CAPS_OFFSET);
1426 MLX4_GET(param->hca_core_clock, outbox, QUERY_HCA_CORE_CLOCK_OFFSET);
1427
1428 /* QPC/EEC/CQC/EQC/RDMARC attributes */
1429
1430 MLX4_GET(param->qpc_base, outbox, INIT_HCA_QPC_BASE_OFFSET);
1431 MLX4_GET(param->log_num_qps, outbox, INIT_HCA_LOG_QP_OFFSET);
1432 MLX4_GET(param->srqc_base, outbox, INIT_HCA_SRQC_BASE_OFFSET);
1433 MLX4_GET(param->log_num_srqs, outbox, INIT_HCA_LOG_SRQ_OFFSET);
1434 MLX4_GET(param->cqc_base, outbox, INIT_HCA_CQC_BASE_OFFSET);
1435 MLX4_GET(param->log_num_cqs, outbox, INIT_HCA_LOG_CQ_OFFSET);
1436 MLX4_GET(param->altc_base, outbox, INIT_HCA_ALTC_BASE_OFFSET);
1437 MLX4_GET(param->auxc_base, outbox, INIT_HCA_AUXC_BASE_OFFSET);
1438 MLX4_GET(param->eqc_base, outbox, INIT_HCA_EQC_BASE_OFFSET);
1439 MLX4_GET(param->log_num_eqs, outbox, INIT_HCA_LOG_EQ_OFFSET);
1440 MLX4_GET(param->rdmarc_base, outbox, INIT_HCA_RDMARC_BASE_OFFSET);
1441 MLX4_GET(param->log_rd_per_qp, outbox, INIT_HCA_LOG_RD_OFFSET);
1442
1443 MLX4_GET(dword_field, outbox, INIT_HCA_FLAGS_OFFSET);
1444 if (dword_field & (1 << INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN)) {
1445 param->steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED;
1446 } else {
1447 MLX4_GET(byte_field, outbox, INIT_HCA_UC_STEERING_OFFSET);
1448 if (byte_field & 0x8)
1449 param->steering_mode = MLX4_STEERING_MODE_B0;
1450 else
1451 param->steering_mode = MLX4_STEERING_MODE_A0;
1452 }
1453 /* steering attributes */
1454 if (param->steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) {
1455 MLX4_GET(param->mc_base, outbox, INIT_HCA_FS_BASE_OFFSET);
1456 MLX4_GET(param->log_mc_entry_sz, outbox,
1457 INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET);
1458 MLX4_GET(param->log_mc_table_sz, outbox,
1459 INIT_HCA_FS_LOG_TABLE_SZ_OFFSET);
1460 } else {
1461 MLX4_GET(param->mc_base, outbox, INIT_HCA_MC_BASE_OFFSET);
1462 MLX4_GET(param->log_mc_entry_sz, outbox,
1463 INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET);
1464 MLX4_GET(param->log_mc_hash_sz, outbox,
1465 INIT_HCA_LOG_MC_HASH_SZ_OFFSET);
1466 MLX4_GET(param->log_mc_table_sz, outbox,
1467 INIT_HCA_LOG_MC_TABLE_SZ_OFFSET);
1468 }
1469
1470 /* CX3 is capable of extending CQEs/EQEs from 32 to 64 bytes */
1471 MLX4_GET(byte_field, outbox, INIT_HCA_EQE_CQE_OFFSETS);
1472 if (byte_field & 0x20) /* 64-bytes eqe enabled */
1473 param->dev_cap_enabled |= MLX4_DEV_CAP_64B_EQE_ENABLED;
1474 if (byte_field & 0x40) /* 64-bytes cqe enabled */
1475 param->dev_cap_enabled |= MLX4_DEV_CAP_64B_CQE_ENABLED;
1476
1477 /* TPT attributes */
1478
1479 MLX4_GET(param->dmpt_base, outbox, INIT_HCA_DMPT_BASE_OFFSET);
1480 MLX4_GET(param->mw_enabled, outbox, INIT_HCA_TPT_MW_OFFSET);
1481 MLX4_GET(param->log_mpt_sz, outbox, INIT_HCA_LOG_MPT_SZ_OFFSET);
1482 MLX4_GET(param->mtt_base, outbox, INIT_HCA_MTT_BASE_OFFSET);
1483 MLX4_GET(param->cmpt_base, outbox, INIT_HCA_CMPT_BASE_OFFSET);
1484
1485 /* UAR attributes */
1486
1487 MLX4_GET(param->uar_page_sz, outbox, INIT_HCA_UAR_PAGE_SZ_OFFSET);
1488 MLX4_GET(param->log_uar_sz, outbox, INIT_HCA_LOG_UAR_SZ_OFFSET);
1489
1490 out:
1491 mlx4_free_cmd_mailbox(dev, mailbox);
1492
1493 return err;
1494 }
1495
1496 /* for IB-type ports only in SRIOV mode. Checks that both proxy QP0
1497 * and real QP0 are active, so that the paravirtualized QP0 is ready
1498 * to operate */
1499 static int check_qp0_state(struct mlx4_dev *dev, int function, int port)
1500 {
1501 struct mlx4_priv *priv = mlx4_priv(dev);
1502 /* irrelevant if not infiniband */
1503 if (priv->mfunc.master.qp0_state[port].proxy_qp0_active &&
1504 priv->mfunc.master.qp0_state[port].qp0_active)
1505 return 1;
1506 return 0;
1507 }
1508
1509 int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave,
1510 struct mlx4_vhcr *vhcr,
1511 struct mlx4_cmd_mailbox *inbox,
1512 struct mlx4_cmd_mailbox *outbox,
1513 struct mlx4_cmd_info *cmd)
1514 {
1515 struct mlx4_priv *priv = mlx4_priv(dev);
1516 int port = vhcr->in_modifier;
1517 int err;
1518
1519 if (priv->mfunc.master.slave_state[slave].init_port_mask & (1 << port))
1520 return 0;
1521
1522 if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB) {
1523 /* Enable port only if it was previously disabled */
1524 if (!priv->mfunc.master.init_port_ref[port]) {
1525 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
1526 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1527 if (err)
1528 return err;
1529 }
1530 priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port);
1531 } else {
1532 if (slave == mlx4_master_func_num(dev)) {
1533 if (check_qp0_state(dev, slave, port) &&
1534 !priv->mfunc.master.qp0_state[port].port_active) {
1535 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
1536 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1537 if (err)
1538 return err;
1539 priv->mfunc.master.qp0_state[port].port_active = 1;
1540 priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port);
1541 }
1542 } else
1543 priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port);
1544 }
1545 ++priv->mfunc.master.init_port_ref[port];
1546 return 0;
1547 }
1548
1549 int mlx4_INIT_PORT(struct mlx4_dev *dev, int port)
1550 {
1551 struct mlx4_cmd_mailbox *mailbox;
1552 u32 *inbox;
1553 int err;
1554 u32 flags;
1555 u16 field;
1556
1557 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
1558 #define INIT_PORT_IN_SIZE 256
1559 #define INIT_PORT_FLAGS_OFFSET 0x00
1560 #define INIT_PORT_FLAG_SIG (1 << 18)
1561 #define INIT_PORT_FLAG_NG (1 << 17)
1562 #define INIT_PORT_FLAG_G0 (1 << 16)
1563 #define INIT_PORT_VL_SHIFT 4
1564 #define INIT_PORT_PORT_WIDTH_SHIFT 8
1565 #define INIT_PORT_MTU_OFFSET 0x04
1566 #define INIT_PORT_MAX_GID_OFFSET 0x06
1567 #define INIT_PORT_MAX_PKEY_OFFSET 0x0a
1568 #define INIT_PORT_GUID0_OFFSET 0x10
1569 #define INIT_PORT_NODE_GUID_OFFSET 0x18
1570 #define INIT_PORT_SI_GUID_OFFSET 0x20
1571
1572 mailbox = mlx4_alloc_cmd_mailbox(dev);
1573 if (IS_ERR(mailbox))
1574 return PTR_ERR(mailbox);
1575 inbox = mailbox->buf;
1576
1577 memset(inbox, 0, INIT_PORT_IN_SIZE);
1578
1579 flags = 0;
1580 flags |= (dev->caps.vl_cap[port] & 0xf) << INIT_PORT_VL_SHIFT;
1581 flags |= (dev->caps.port_width_cap[port] & 0xf) << INIT_PORT_PORT_WIDTH_SHIFT;
1582 MLX4_PUT(inbox, flags, INIT_PORT_FLAGS_OFFSET);
1583
1584 field = 128 << dev->caps.ib_mtu_cap[port];
1585 MLX4_PUT(inbox, field, INIT_PORT_MTU_OFFSET);
1586 field = dev->caps.gid_table_len[port];
1587 MLX4_PUT(inbox, field, INIT_PORT_MAX_GID_OFFSET);
1588 field = dev->caps.pkey_table_len[port];
1589 MLX4_PUT(inbox, field, INIT_PORT_MAX_PKEY_OFFSET);
1590
1591 err = mlx4_cmd(dev, mailbox->dma, port, 0, MLX4_CMD_INIT_PORT,
1592 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1593
1594 mlx4_free_cmd_mailbox(dev, mailbox);
1595 } else
1596 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
1597 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
1598
1599 return err;
1600 }
1601 EXPORT_SYMBOL_GPL(mlx4_INIT_PORT);
1602
1603 int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave,
1604 struct mlx4_vhcr *vhcr,
1605 struct mlx4_cmd_mailbox *inbox,
1606 struct mlx4_cmd_mailbox *outbox,
1607 struct mlx4_cmd_info *cmd)
1608 {
1609 struct mlx4_priv *priv = mlx4_priv(dev);
1610 int port = vhcr->in_modifier;
1611 int err;
1612
1613 if (!(priv->mfunc.master.slave_state[slave].init_port_mask &
1614 (1 << port)))
1615 return 0;
1616
1617 if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB) {
1618 if (priv->mfunc.master.init_port_ref[port] == 1) {
1619 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT,
1620 1000, MLX4_CMD_NATIVE);
1621 if (err)
1622 return err;
1623 }
1624 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port);
1625 } else {
1626 /* infiniband port */
1627 if (slave == mlx4_master_func_num(dev)) {
1628 if (!priv->mfunc.master.qp0_state[port].qp0_active &&
1629 priv->mfunc.master.qp0_state[port].port_active) {
1630 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT,
1631 1000, MLX4_CMD_NATIVE);
1632 if (err)
1633 return err;
1634 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port);
1635 priv->mfunc.master.qp0_state[port].port_active = 0;
1636 }
1637 } else
1638 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port);
1639 }
1640 --priv->mfunc.master.init_port_ref[port];
1641 return 0;
1642 }
1643
1644 int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port)
1645 {
1646 return mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, 1000,
1647 MLX4_CMD_WRAPPED);
1648 }
1649 EXPORT_SYMBOL_GPL(mlx4_CLOSE_PORT);
1650
1651 int mlx4_CLOSE_HCA(struct mlx4_dev *dev, int panic)
1652 {
1653 return mlx4_cmd(dev, 0, 0, panic, MLX4_CMD_CLOSE_HCA, 1000,
1654 MLX4_CMD_NATIVE);
1655 }
1656
1657 int mlx4_SET_ICM_SIZE(struct mlx4_dev *dev, u64 icm_size, u64 *aux_pages)
1658 {
1659 int ret = mlx4_cmd_imm(dev, icm_size, aux_pages, 0, 0,
1660 MLX4_CMD_SET_ICM_SIZE,
1661 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1662 if (ret)
1663 return ret;
1664
1665 /*
1666 * Round up number of system pages needed in case
1667 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE.
1668 */
1669 *aux_pages = ALIGN(*aux_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >>
1670 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT);
1671
1672 return 0;
1673 }
1674
1675 int mlx4_NOP(struct mlx4_dev *dev)
1676 {
1677 /* Input modifier of 0x1f means "finish as soon as possible." */
1678 return mlx4_cmd(dev, 0, 0x1f, 0, MLX4_CMD_NOP, 100, MLX4_CMD_NATIVE);
1679 }
1680
1681 #define MLX4_WOL_SETUP_MODE (5 << 28)
1682 int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port)
1683 {
1684 u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8;
1685
1686 return mlx4_cmd_imm(dev, 0, config, in_mod, 0x3,
1687 MLX4_CMD_MOD_STAT_CFG, MLX4_CMD_TIME_CLASS_A,
1688 MLX4_CMD_NATIVE);
1689 }
1690 EXPORT_SYMBOL_GPL(mlx4_wol_read);
1691
1692 int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port)
1693 {
1694 u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8;
1695
1696 return mlx4_cmd(dev, config, in_mod, 0x1, MLX4_CMD_MOD_STAT_CFG,
1697 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1698 }
1699 EXPORT_SYMBOL_GPL(mlx4_wol_write);
1700
1701 enum {
1702 ADD_TO_MCG = 0x26,
1703 };
1704
1705
1706 void mlx4_opreq_action(struct work_struct *work)
1707 {
1708 struct mlx4_priv *priv = container_of(work, struct mlx4_priv,
1709 opreq_task);
1710 struct mlx4_dev *dev = &priv->dev;
1711 int num_tasks = atomic_read(&priv->opreq_count);
1712 struct mlx4_cmd_mailbox *mailbox;
1713 struct mlx4_mgm *mgm;
1714 u32 *outbox;
1715 u32 modifier;
1716 u16 token;
1717 u16 type;
1718 int err;
1719 u32 num_qps;
1720 struct mlx4_qp qp;
1721 int i;
1722 u8 rem_mcg;
1723 u8 prot;
1724
1725 #define GET_OP_REQ_MODIFIER_OFFSET 0x08
1726 #define GET_OP_REQ_TOKEN_OFFSET 0x14
1727 #define GET_OP_REQ_TYPE_OFFSET 0x1a
1728 #define GET_OP_REQ_DATA_OFFSET 0x20
1729
1730 mailbox = mlx4_alloc_cmd_mailbox(dev);
1731 if (IS_ERR(mailbox)) {
1732 mlx4_err(dev, "Failed to allocate mailbox for GET_OP_REQ\n");
1733 return;
1734 }
1735 outbox = mailbox->buf;
1736
1737 while (num_tasks) {
1738 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0,
1739 MLX4_CMD_GET_OP_REQ, MLX4_CMD_TIME_CLASS_A,
1740 MLX4_CMD_NATIVE);
1741 if (err) {
1742 mlx4_err(dev, "Failed to retreive required operation: %d\n",
1743 err);
1744 return;
1745 }
1746 MLX4_GET(modifier, outbox, GET_OP_REQ_MODIFIER_OFFSET);
1747 MLX4_GET(token, outbox, GET_OP_REQ_TOKEN_OFFSET);
1748 MLX4_GET(type, outbox, GET_OP_REQ_TYPE_OFFSET);
1749 type &= 0xfff;
1750
1751 switch (type) {
1752 case ADD_TO_MCG:
1753 if (dev->caps.steering_mode ==
1754 MLX4_STEERING_MODE_DEVICE_MANAGED) {
1755 mlx4_warn(dev, "ADD MCG operation is not supported in DEVICE_MANAGED steering mode\n");
1756 err = EPERM;
1757 break;
1758 }
1759 mgm = (struct mlx4_mgm *)((u8 *)(outbox) +
1760 GET_OP_REQ_DATA_OFFSET);
1761 num_qps = be32_to_cpu(mgm->members_count) &
1762 MGM_QPN_MASK;
1763 rem_mcg = ((u8 *)(&mgm->members_count))[0] & 1;
1764 prot = ((u8 *)(&mgm->members_count))[0] >> 6;
1765
1766 for (i = 0; i < num_qps; i++) {
1767 qp.qpn = be32_to_cpu(mgm->qp[i]);
1768 if (rem_mcg)
1769 err = mlx4_multicast_detach(dev, &qp,
1770 mgm->gid,
1771 prot, 0);
1772 else
1773 err = mlx4_multicast_attach(dev, &qp,
1774 mgm->gid,
1775 mgm->gid[5]
1776 , 0, prot,
1777 NULL);
1778 if (err)
1779 break;
1780 }
1781 break;
1782 default:
1783 mlx4_warn(dev, "Bad type for required operation\n");
1784 err = EINVAL;
1785 break;
1786 }
1787 err = mlx4_cmd(dev, 0, ((u32) err | cpu_to_be32(token) << 16),
1788 1, MLX4_CMD_GET_OP_REQ, MLX4_CMD_TIME_CLASS_A,
1789 MLX4_CMD_NATIVE);
1790 if (err) {
1791 mlx4_err(dev, "Failed to acknowledge required request: %d\n",
1792 err);
1793 goto out;
1794 }
1795 memset(outbox, 0, 0xffc);
1796 num_tasks = atomic_dec_return(&priv->opreq_count);
1797 }
1798
1799 out:
1800 mlx4_free_cmd_mailbox(dev, mailbox);
1801 }
Linux kernel - Deliverables
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