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Merge tag 'random_for_linus_stable' of git://git.kernel.org/pub/scm/linux/kernel...
[deliverable/linux.git] / drivers / net / ethernet / mellanox / mlx4 / fw.c
1 /*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35 #include <linux/etherdevice.h>
36 #include <linux/mlx4/cmd.h>
37 #include <linux/module.h>
38 #include <linux/cache.h>
39
40 #include "fw.h"
41 #include "icm.h"
42
43 enum {
44 MLX4_COMMAND_INTERFACE_MIN_REV = 2,
45 MLX4_COMMAND_INTERFACE_MAX_REV = 3,
46 MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS = 3,
47 };
48
49 extern void __buggy_use_of_MLX4_GET(void);
50 extern void __buggy_use_of_MLX4_PUT(void);
51
52 static bool enable_qos = true;
53 module_param(enable_qos, bool, 0444);
54 MODULE_PARM_DESC(enable_qos, "Enable Enhanced QoS support (default: on)");
55
56 #define MLX4_GET(dest, source, offset) \
57 do { \
58 void *__p = (char *) (source) + (offset); \
59 u64 val; \
60 switch (sizeof (dest)) { \
61 case 1: (dest) = *(u8 *) __p; break; \
62 case 2: (dest) = be16_to_cpup(__p); break; \
63 case 4: (dest) = be32_to_cpup(__p); break; \
64 case 8: val = get_unaligned((u64 *)__p); \
65 (dest) = be64_to_cpu(val); break; \
66 default: __buggy_use_of_MLX4_GET(); \
67 } \
68 } while (0)
69
70 #define MLX4_PUT(dest, source, offset) \
71 do { \
72 void *__d = ((char *) (dest) + (offset)); \
73 switch (sizeof(source)) { \
74 case 1: *(u8 *) __d = (source); break; \
75 case 2: *(__be16 *) __d = cpu_to_be16(source); break; \
76 case 4: *(__be32 *) __d = cpu_to_be32(source); break; \
77 case 8: *(__be64 *) __d = cpu_to_be64(source); break; \
78 default: __buggy_use_of_MLX4_PUT(); \
79 } \
80 } while (0)
81
82 static void dump_dev_cap_flags(struct mlx4_dev *dev, u64 flags)
83 {
84 static const char *fname[] = {
85 [ 0] = "RC transport",
86 [ 1] = "UC transport",
87 [ 2] = "UD transport",
88 [ 3] = "XRC transport",
89 [ 6] = "SRQ support",
90 [ 7] = "IPoIB checksum offload",
91 [ 8] = "P_Key violation counter",
92 [ 9] = "Q_Key violation counter",
93 [12] = "Dual Port Different Protocol (DPDP) support",
94 [15] = "Big LSO headers",
95 [16] = "MW support",
96 [17] = "APM support",
97 [18] = "Atomic ops support",
98 [19] = "Raw multicast support",
99 [20] = "Address vector port checking support",
100 [21] = "UD multicast support",
101 [30] = "IBoE support",
102 [32] = "Unicast loopback support",
103 [34] = "FCS header control",
104 [37] = "Wake On LAN (port1) support",
105 [38] = "Wake On LAN (port2) support",
106 [40] = "UDP RSS support",
107 [41] = "Unicast VEP steering support",
108 [42] = "Multicast VEP steering support",
109 [48] = "Counters support",
110 [52] = "RSS IP fragments support",
111 [53] = "Port ETS Scheduler support",
112 [55] = "Port link type sensing support",
113 [59] = "Port management change event support",
114 [61] = "64 byte EQE support",
115 [62] = "64 byte CQE support",
116 };
117 int i;
118
119 mlx4_dbg(dev, "DEV_CAP flags:\n");
120 for (i = 0; i < ARRAY_SIZE(fname); ++i)
121 if (fname[i] && (flags & (1LL << i)))
122 mlx4_dbg(dev, " %s\n", fname[i]);
123 }
124
125 static void dump_dev_cap_flags2(struct mlx4_dev *dev, u64 flags)
126 {
127 static const char * const fname[] = {
128 [0] = "RSS support",
129 [1] = "RSS Toeplitz Hash Function support",
130 [2] = "RSS XOR Hash Function support",
131 [3] = "Device managed flow steering support",
132 [4] = "Automatic MAC reassignment support",
133 [5] = "Time stamping support",
134 [6] = "VST (control vlan insertion/stripping) support",
135 [7] = "FSM (MAC anti-spoofing) support",
136 [8] = "Dynamic QP updates support",
137 [9] = "Device managed flow steering IPoIB support",
138 [10] = "TCP/IP offloads/flow-steering for VXLAN support",
139 [11] = "MAD DEMUX (Secure-Host) support",
140 [12] = "Large cache line (>64B) CQE stride support",
141 [13] = "Large cache line (>64B) EQE stride support",
142 [14] = "Ethernet protocol control support",
143 [15] = "Ethernet Backplane autoneg support",
144 [16] = "CONFIG DEV support",
145 [17] = "Asymmetric EQs support",
146 [18] = "More than 80 VFs support",
147 [19] = "Performance optimized for limited rule configuration flow steering support",
148 [20] = "Recoverable error events support",
149 [21] = "Port Remap support",
150 [22] = "QCN support",
151 [23] = "QP rate limiting support",
152 [24] = "Ethernet Flow control statistics support",
153 [25] = "Granular QoS per VF support",
154 [26] = "Port ETS Scheduler support",
155 [27] = "Port beacon support",
156 [28] = "RX-ALL support",
157 [29] = "802.1ad offload support",
158 [31] = "Modifying loopback source checks using UPDATE_QP support",
159 [32] = "Loopback source checks support",
160 [33] = "RoCEv2 support",
161 [34] = "DMFS Sniffer support (UC & MC)"
162 };
163 int i;
164
165 for (i = 0; i < ARRAY_SIZE(fname); ++i)
166 if (fname[i] && (flags & (1LL << i)))
167 mlx4_dbg(dev, " %s\n", fname[i]);
168 }
169
170 int mlx4_MOD_STAT_CFG(struct mlx4_dev *dev, struct mlx4_mod_stat_cfg *cfg)
171 {
172 struct mlx4_cmd_mailbox *mailbox;
173 u32 *inbox;
174 int err = 0;
175
176 #define MOD_STAT_CFG_IN_SIZE 0x100
177
178 #define MOD_STAT_CFG_PG_SZ_M_OFFSET 0x002
179 #define MOD_STAT_CFG_PG_SZ_OFFSET 0x003
180
181 mailbox = mlx4_alloc_cmd_mailbox(dev);
182 if (IS_ERR(mailbox))
183 return PTR_ERR(mailbox);
184 inbox = mailbox->buf;
185
186 MLX4_PUT(inbox, cfg->log_pg_sz, MOD_STAT_CFG_PG_SZ_OFFSET);
187 MLX4_PUT(inbox, cfg->log_pg_sz_m, MOD_STAT_CFG_PG_SZ_M_OFFSET);
188
189 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_MOD_STAT_CFG,
190 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
191
192 mlx4_free_cmd_mailbox(dev, mailbox);
193 return err;
194 }
195
196 int mlx4_QUERY_FUNC(struct mlx4_dev *dev, struct mlx4_func *func, int slave)
197 {
198 struct mlx4_cmd_mailbox *mailbox;
199 u32 *outbox;
200 u8 in_modifier;
201 u8 field;
202 u16 field16;
203 int err;
204
205 #define QUERY_FUNC_BUS_OFFSET 0x00
206 #define QUERY_FUNC_DEVICE_OFFSET 0x01
207 #define QUERY_FUNC_FUNCTION_OFFSET 0x01
208 #define QUERY_FUNC_PHYSICAL_FUNCTION_OFFSET 0x03
209 #define QUERY_FUNC_RSVD_EQS_OFFSET 0x04
210 #define QUERY_FUNC_MAX_EQ_OFFSET 0x06
211 #define QUERY_FUNC_RSVD_UARS_OFFSET 0x0b
212
213 mailbox = mlx4_alloc_cmd_mailbox(dev);
214 if (IS_ERR(mailbox))
215 return PTR_ERR(mailbox);
216 outbox = mailbox->buf;
217
218 in_modifier = slave;
219
220 err = mlx4_cmd_box(dev, 0, mailbox->dma, in_modifier, 0,
221 MLX4_CMD_QUERY_FUNC,
222 MLX4_CMD_TIME_CLASS_A,
223 MLX4_CMD_NATIVE);
224 if (err)
225 goto out;
226
227 MLX4_GET(field, outbox, QUERY_FUNC_BUS_OFFSET);
228 func->bus = field & 0xf;
229 MLX4_GET(field, outbox, QUERY_FUNC_DEVICE_OFFSET);
230 func->device = field & 0xf1;
231 MLX4_GET(field, outbox, QUERY_FUNC_FUNCTION_OFFSET);
232 func->function = field & 0x7;
233 MLX4_GET(field, outbox, QUERY_FUNC_PHYSICAL_FUNCTION_OFFSET);
234 func->physical_function = field & 0xf;
235 MLX4_GET(field16, outbox, QUERY_FUNC_RSVD_EQS_OFFSET);
236 func->rsvd_eqs = field16 & 0xffff;
237 MLX4_GET(field16, outbox, QUERY_FUNC_MAX_EQ_OFFSET);
238 func->max_eq = field16 & 0xffff;
239 MLX4_GET(field, outbox, QUERY_FUNC_RSVD_UARS_OFFSET);
240 func->rsvd_uars = field & 0x0f;
241
242 mlx4_dbg(dev, "Bus: %d, Device: %d, Function: %d, Physical function: %d, Max EQs: %d, Reserved EQs: %d, Reserved UARs: %d\n",
243 func->bus, func->device, func->function, func->physical_function,
244 func->max_eq, func->rsvd_eqs, func->rsvd_uars);
245
246 out:
247 mlx4_free_cmd_mailbox(dev, mailbox);
248 return err;
249 }
250
251 int mlx4_QUERY_FUNC_CAP_wrapper(struct mlx4_dev *dev, int slave,
252 struct mlx4_vhcr *vhcr,
253 struct mlx4_cmd_mailbox *inbox,
254 struct mlx4_cmd_mailbox *outbox,
255 struct mlx4_cmd_info *cmd)
256 {
257 struct mlx4_priv *priv = mlx4_priv(dev);
258 u8 field, port;
259 u32 size, proxy_qp, qkey;
260 int err = 0;
261 struct mlx4_func func;
262
263 #define QUERY_FUNC_CAP_FLAGS_OFFSET 0x0
264 #define QUERY_FUNC_CAP_NUM_PORTS_OFFSET 0x1
265 #define QUERY_FUNC_CAP_PF_BHVR_OFFSET 0x4
266 #define QUERY_FUNC_CAP_FMR_OFFSET 0x8
267 #define QUERY_FUNC_CAP_QP_QUOTA_OFFSET_DEP 0x10
268 #define QUERY_FUNC_CAP_CQ_QUOTA_OFFSET_DEP 0x14
269 #define QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET_DEP 0x18
270 #define QUERY_FUNC_CAP_MPT_QUOTA_OFFSET_DEP 0x20
271 #define QUERY_FUNC_CAP_MTT_QUOTA_OFFSET_DEP 0x24
272 #define QUERY_FUNC_CAP_MCG_QUOTA_OFFSET_DEP 0x28
273 #define QUERY_FUNC_CAP_MAX_EQ_OFFSET 0x2c
274 #define QUERY_FUNC_CAP_RESERVED_EQ_OFFSET 0x30
275 #define QUERY_FUNC_CAP_QP_RESD_LKEY_OFFSET 0x48
276
277 #define QUERY_FUNC_CAP_QP_QUOTA_OFFSET 0x50
278 #define QUERY_FUNC_CAP_CQ_QUOTA_OFFSET 0x54
279 #define QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET 0x58
280 #define QUERY_FUNC_CAP_MPT_QUOTA_OFFSET 0x60
281 #define QUERY_FUNC_CAP_MTT_QUOTA_OFFSET 0x64
282 #define QUERY_FUNC_CAP_MCG_QUOTA_OFFSET 0x68
283
284 #define QUERY_FUNC_CAP_EXTRA_FLAGS_OFFSET 0x6c
285
286 #define QUERY_FUNC_CAP_FMR_FLAG 0x80
287 #define QUERY_FUNC_CAP_FLAG_RDMA 0x40
288 #define QUERY_FUNC_CAP_FLAG_ETH 0x80
289 #define QUERY_FUNC_CAP_FLAG_QUOTAS 0x10
290 #define QUERY_FUNC_CAP_FLAG_RESD_LKEY 0x08
291 #define QUERY_FUNC_CAP_FLAG_VALID_MAILBOX 0x04
292
293 #define QUERY_FUNC_CAP_EXTRA_FLAGS_BF_QP_ALLOC_FLAG (1UL << 31)
294 #define QUERY_FUNC_CAP_EXTRA_FLAGS_A0_QP_ALLOC_FLAG (1UL << 30)
295
296 /* when opcode modifier = 1 */
297 #define QUERY_FUNC_CAP_PHYS_PORT_OFFSET 0x3
298 #define QUERY_FUNC_CAP_PRIV_VF_QKEY_OFFSET 0x4
299 #define QUERY_FUNC_CAP_FLAGS0_OFFSET 0x8
300 #define QUERY_FUNC_CAP_FLAGS1_OFFSET 0xc
301
302 #define QUERY_FUNC_CAP_QP0_TUNNEL 0x10
303 #define QUERY_FUNC_CAP_QP0_PROXY 0x14
304 #define QUERY_FUNC_CAP_QP1_TUNNEL 0x18
305 #define QUERY_FUNC_CAP_QP1_PROXY 0x1c
306 #define QUERY_FUNC_CAP_PHYS_PORT_ID 0x28
307
308 #define QUERY_FUNC_CAP_FLAGS1_FORCE_MAC 0x40
309 #define QUERY_FUNC_CAP_FLAGS1_FORCE_VLAN 0x80
310 #define QUERY_FUNC_CAP_FLAGS1_NIC_INFO 0x10
311 #define QUERY_FUNC_CAP_VF_ENABLE_QP0 0x08
312
313 #define QUERY_FUNC_CAP_FLAGS0_FORCE_PHY_WQE_GID 0x80
314 #define QUERY_FUNC_CAP_SUPPORTS_NON_POWER_OF_2_NUM_EQS (1 << 31)
315 #define QUERY_FUNC_CAP_PHV_BIT 0x40
316
317 if (vhcr->op_modifier == 1) {
318 struct mlx4_active_ports actv_ports =
319 mlx4_get_active_ports(dev, slave);
320 int converted_port = mlx4_slave_convert_port(
321 dev, slave, vhcr->in_modifier);
322
323 if (converted_port < 0)
324 return -EINVAL;
325
326 vhcr->in_modifier = converted_port;
327 /* phys-port = logical-port */
328 field = vhcr->in_modifier -
329 find_first_bit(actv_ports.ports, dev->caps.num_ports);
330 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_PHYS_PORT_OFFSET);
331
332 port = vhcr->in_modifier;
333 proxy_qp = dev->phys_caps.base_proxy_sqpn + 8 * slave + port - 1;
334
335 /* Set nic_info bit to mark new fields support */
336 field = QUERY_FUNC_CAP_FLAGS1_NIC_INFO;
337
338 if (mlx4_vf_smi_enabled(dev, slave, port) &&
339 !mlx4_get_parav_qkey(dev, proxy_qp, &qkey)) {
340 field |= QUERY_FUNC_CAP_VF_ENABLE_QP0;
341 MLX4_PUT(outbox->buf, qkey,
342 QUERY_FUNC_CAP_PRIV_VF_QKEY_OFFSET);
343 }
344 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FLAGS1_OFFSET);
345
346 /* size is now the QP number */
347 size = dev->phys_caps.base_tunnel_sqpn + 8 * slave + port - 1;
348 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP0_TUNNEL);
349
350 size += 2;
351 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP1_TUNNEL);
352
353 MLX4_PUT(outbox->buf, proxy_qp, QUERY_FUNC_CAP_QP0_PROXY);
354 proxy_qp += 2;
355 MLX4_PUT(outbox->buf, proxy_qp, QUERY_FUNC_CAP_QP1_PROXY);
356
357 MLX4_PUT(outbox->buf, dev->caps.phys_port_id[vhcr->in_modifier],
358 QUERY_FUNC_CAP_PHYS_PORT_ID);
359
360 if (dev->caps.phv_bit[port]) {
361 field = QUERY_FUNC_CAP_PHV_BIT;
362 MLX4_PUT(outbox->buf, field,
363 QUERY_FUNC_CAP_FLAGS0_OFFSET);
364 }
365
366 } else if (vhcr->op_modifier == 0) {
367 struct mlx4_active_ports actv_ports =
368 mlx4_get_active_ports(dev, slave);
369 /* enable rdma and ethernet interfaces, new quota locations,
370 * and reserved lkey
371 */
372 field = (QUERY_FUNC_CAP_FLAG_ETH | QUERY_FUNC_CAP_FLAG_RDMA |
373 QUERY_FUNC_CAP_FLAG_QUOTAS | QUERY_FUNC_CAP_FLAG_VALID_MAILBOX |
374 QUERY_FUNC_CAP_FLAG_RESD_LKEY);
375 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FLAGS_OFFSET);
376
377 field = min(
378 bitmap_weight(actv_ports.ports, dev->caps.num_ports),
379 dev->caps.num_ports);
380 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_NUM_PORTS_OFFSET);
381
382 size = dev->caps.function_caps; /* set PF behaviours */
383 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_PF_BHVR_OFFSET);
384
385 field = 0; /* protected FMR support not available as yet */
386 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FMR_OFFSET);
387
388 size = priv->mfunc.master.res_tracker.res_alloc[RES_QP].quota[slave];
389 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP_QUOTA_OFFSET);
390 size = dev->caps.num_qps;
391 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP_QUOTA_OFFSET_DEP);
392
393 size = priv->mfunc.master.res_tracker.res_alloc[RES_SRQ].quota[slave];
394 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET);
395 size = dev->caps.num_srqs;
396 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET_DEP);
397
398 size = priv->mfunc.master.res_tracker.res_alloc[RES_CQ].quota[slave];
399 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET);
400 size = dev->caps.num_cqs;
401 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET_DEP);
402
403 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) ||
404 mlx4_QUERY_FUNC(dev, &func, slave)) {
405 size = vhcr->in_modifier &
406 QUERY_FUNC_CAP_SUPPORTS_NON_POWER_OF_2_NUM_EQS ?
407 dev->caps.num_eqs :
408 rounddown_pow_of_two(dev->caps.num_eqs);
409 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MAX_EQ_OFFSET);
410 size = dev->caps.reserved_eqs;
411 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET);
412 } else {
413 size = vhcr->in_modifier &
414 QUERY_FUNC_CAP_SUPPORTS_NON_POWER_OF_2_NUM_EQS ?
415 func.max_eq :
416 rounddown_pow_of_two(func.max_eq);
417 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MAX_EQ_OFFSET);
418 size = func.rsvd_eqs;
419 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET);
420 }
421
422 size = priv->mfunc.master.res_tracker.res_alloc[RES_MPT].quota[slave];
423 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET);
424 size = dev->caps.num_mpts;
425 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET_DEP);
426
427 size = priv->mfunc.master.res_tracker.res_alloc[RES_MTT].quota[slave];
428 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET);
429 size = dev->caps.num_mtts;
430 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET_DEP);
431
432 size = dev->caps.num_mgms + dev->caps.num_amgms;
433 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET);
434 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET_DEP);
435
436 size = QUERY_FUNC_CAP_EXTRA_FLAGS_BF_QP_ALLOC_FLAG |
437 QUERY_FUNC_CAP_EXTRA_FLAGS_A0_QP_ALLOC_FLAG;
438 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_EXTRA_FLAGS_OFFSET);
439
440 size = dev->caps.reserved_lkey + ((slave << 8) & 0xFF00);
441 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP_RESD_LKEY_OFFSET);
442 } else
443 err = -EINVAL;
444
445 return err;
446 }
447
448 int mlx4_QUERY_FUNC_CAP(struct mlx4_dev *dev, u8 gen_or_port,
449 struct mlx4_func_cap *func_cap)
450 {
451 struct mlx4_cmd_mailbox *mailbox;
452 u32 *outbox;
453 u8 field, op_modifier;
454 u32 size, qkey;
455 int err = 0, quotas = 0;
456 u32 in_modifier;
457
458 op_modifier = !!gen_or_port; /* 0 = general, 1 = logical port */
459 in_modifier = op_modifier ? gen_or_port :
460 QUERY_FUNC_CAP_SUPPORTS_NON_POWER_OF_2_NUM_EQS;
461
462 mailbox = mlx4_alloc_cmd_mailbox(dev);
463 if (IS_ERR(mailbox))
464 return PTR_ERR(mailbox);
465
466 err = mlx4_cmd_box(dev, 0, mailbox->dma, in_modifier, op_modifier,
467 MLX4_CMD_QUERY_FUNC_CAP,
468 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
469 if (err)
470 goto out;
471
472 outbox = mailbox->buf;
473
474 if (!op_modifier) {
475 MLX4_GET(field, outbox, QUERY_FUNC_CAP_FLAGS_OFFSET);
476 if (!(field & (QUERY_FUNC_CAP_FLAG_ETH | QUERY_FUNC_CAP_FLAG_RDMA))) {
477 mlx4_err(dev, "The host supports neither eth nor rdma interfaces\n");
478 err = -EPROTONOSUPPORT;
479 goto out;
480 }
481 func_cap->flags = field;
482 quotas = !!(func_cap->flags & QUERY_FUNC_CAP_FLAG_QUOTAS);
483
484 MLX4_GET(field, outbox, QUERY_FUNC_CAP_NUM_PORTS_OFFSET);
485 func_cap->num_ports = field;
486
487 MLX4_GET(size, outbox, QUERY_FUNC_CAP_PF_BHVR_OFFSET);
488 func_cap->pf_context_behaviour = size;
489
490 if (quotas) {
491 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP_QUOTA_OFFSET);
492 func_cap->qp_quota = size & 0xFFFFFF;
493
494 MLX4_GET(size, outbox, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET);
495 func_cap->srq_quota = size & 0xFFFFFF;
496
497 MLX4_GET(size, outbox, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET);
498 func_cap->cq_quota = size & 0xFFFFFF;
499
500 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET);
501 func_cap->mpt_quota = size & 0xFFFFFF;
502
503 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET);
504 func_cap->mtt_quota = size & 0xFFFFFF;
505
506 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET);
507 func_cap->mcg_quota = size & 0xFFFFFF;
508
509 } else {
510 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP_QUOTA_OFFSET_DEP);
511 func_cap->qp_quota = size & 0xFFFFFF;
512
513 MLX4_GET(size, outbox, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET_DEP);
514 func_cap->srq_quota = size & 0xFFFFFF;
515
516 MLX4_GET(size, outbox, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET_DEP);
517 func_cap->cq_quota = size & 0xFFFFFF;
518
519 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET_DEP);
520 func_cap->mpt_quota = size & 0xFFFFFF;
521
522 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET_DEP);
523 func_cap->mtt_quota = size & 0xFFFFFF;
524
525 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET_DEP);
526 func_cap->mcg_quota = size & 0xFFFFFF;
527 }
528 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MAX_EQ_OFFSET);
529 func_cap->max_eq = size & 0xFFFFFF;
530
531 MLX4_GET(size, outbox, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET);
532 func_cap->reserved_eq = size & 0xFFFFFF;
533
534 if (func_cap->flags & QUERY_FUNC_CAP_FLAG_RESD_LKEY) {
535 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP_RESD_LKEY_OFFSET);
536 func_cap->reserved_lkey = size;
537 } else {
538 func_cap->reserved_lkey = 0;
539 }
540
541 func_cap->extra_flags = 0;
542
543 /* Mailbox data from 0x6c and onward should only be treated if
544 * QUERY_FUNC_CAP_FLAG_VALID_MAILBOX is set in func_cap->flags
545 */
546 if (func_cap->flags & QUERY_FUNC_CAP_FLAG_VALID_MAILBOX) {
547 MLX4_GET(size, outbox, QUERY_FUNC_CAP_EXTRA_FLAGS_OFFSET);
548 if (size & QUERY_FUNC_CAP_EXTRA_FLAGS_BF_QP_ALLOC_FLAG)
549 func_cap->extra_flags |= MLX4_QUERY_FUNC_FLAGS_BF_RES_QP;
550 if (size & QUERY_FUNC_CAP_EXTRA_FLAGS_A0_QP_ALLOC_FLAG)
551 func_cap->extra_flags |= MLX4_QUERY_FUNC_FLAGS_A0_RES_QP;
552 }
553
554 goto out;
555 }
556
557 /* logical port query */
558 if (gen_or_port > dev->caps.num_ports) {
559 err = -EINVAL;
560 goto out;
561 }
562
563 MLX4_GET(func_cap->flags1, outbox, QUERY_FUNC_CAP_FLAGS1_OFFSET);
564 if (dev->caps.port_type[gen_or_port] == MLX4_PORT_TYPE_ETH) {
565 if (func_cap->flags1 & QUERY_FUNC_CAP_FLAGS1_FORCE_VLAN) {
566 mlx4_err(dev, "VLAN is enforced on this port\n");
567 err = -EPROTONOSUPPORT;
568 goto out;
569 }
570
571 if (func_cap->flags1 & QUERY_FUNC_CAP_FLAGS1_FORCE_MAC) {
572 mlx4_err(dev, "Force mac is enabled on this port\n");
573 err = -EPROTONOSUPPORT;
574 goto out;
575 }
576 } else if (dev->caps.port_type[gen_or_port] == MLX4_PORT_TYPE_IB) {
577 MLX4_GET(field, outbox, QUERY_FUNC_CAP_FLAGS0_OFFSET);
578 if (field & QUERY_FUNC_CAP_FLAGS0_FORCE_PHY_WQE_GID) {
579 mlx4_err(dev, "phy_wqe_gid is enforced on this ib port\n");
580 err = -EPROTONOSUPPORT;
581 goto out;
582 }
583 }
584
585 MLX4_GET(field, outbox, QUERY_FUNC_CAP_PHYS_PORT_OFFSET);
586 func_cap->physical_port = field;
587 if (func_cap->physical_port != gen_or_port) {
588 err = -ENOSYS;
589 goto out;
590 }
591
592 if (func_cap->flags1 & QUERY_FUNC_CAP_VF_ENABLE_QP0) {
593 MLX4_GET(qkey, outbox, QUERY_FUNC_CAP_PRIV_VF_QKEY_OFFSET);
594 func_cap->qp0_qkey = qkey;
595 } else {
596 func_cap->qp0_qkey = 0;
597 }
598
599 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP0_TUNNEL);
600 func_cap->qp0_tunnel_qpn = size & 0xFFFFFF;
601
602 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP0_PROXY);
603 func_cap->qp0_proxy_qpn = size & 0xFFFFFF;
604
605 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP1_TUNNEL);
606 func_cap->qp1_tunnel_qpn = size & 0xFFFFFF;
607
608 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP1_PROXY);
609 func_cap->qp1_proxy_qpn = size & 0xFFFFFF;
610
611 if (func_cap->flags1 & QUERY_FUNC_CAP_FLAGS1_NIC_INFO)
612 MLX4_GET(func_cap->phys_port_id, outbox,
613 QUERY_FUNC_CAP_PHYS_PORT_ID);
614
615 MLX4_GET(field, outbox, QUERY_FUNC_CAP_FLAGS0_OFFSET);
616 func_cap->flags |= (field & QUERY_FUNC_CAP_PHV_BIT);
617
618 /* All other resources are allocated by the master, but we still report
619 * 'num' and 'reserved' capabilities as follows:
620 * - num remains the maximum resource index
621 * - 'num - reserved' is the total available objects of a resource, but
622 * resource indices may be less than 'reserved'
623 * TODO: set per-resource quotas */
624
625 out:
626 mlx4_free_cmd_mailbox(dev, mailbox);
627
628 return err;
629 }
630
631 static void disable_unsupported_roce_caps(void *buf);
632
633 int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
634 {
635 struct mlx4_cmd_mailbox *mailbox;
636 u32 *outbox;
637 u8 field;
638 u32 field32, flags, ext_flags;
639 u16 size;
640 u16 stat_rate;
641 int err;
642 int i;
643
644 #define QUERY_DEV_CAP_OUT_SIZE 0x100
645 #define QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET 0x10
646 #define QUERY_DEV_CAP_MAX_QP_SZ_OFFSET 0x11
647 #define QUERY_DEV_CAP_RSVD_QP_OFFSET 0x12
648 #define QUERY_DEV_CAP_MAX_QP_OFFSET 0x13
649 #define QUERY_DEV_CAP_RSVD_SRQ_OFFSET 0x14
650 #define QUERY_DEV_CAP_MAX_SRQ_OFFSET 0x15
651 #define QUERY_DEV_CAP_RSVD_EEC_OFFSET 0x16
652 #define QUERY_DEV_CAP_MAX_EEC_OFFSET 0x17
653 #define QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET 0x19
654 #define QUERY_DEV_CAP_RSVD_CQ_OFFSET 0x1a
655 #define QUERY_DEV_CAP_MAX_CQ_OFFSET 0x1b
656 #define QUERY_DEV_CAP_MAX_MPT_OFFSET 0x1d
657 #define QUERY_DEV_CAP_RSVD_EQ_OFFSET 0x1e
658 #define QUERY_DEV_CAP_MAX_EQ_OFFSET 0x1f
659 #define QUERY_DEV_CAP_RSVD_MTT_OFFSET 0x20
660 #define QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET 0x21
661 #define QUERY_DEV_CAP_RSVD_MRW_OFFSET 0x22
662 #define QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET 0x23
663 #define QUERY_DEV_CAP_NUM_SYS_EQ_OFFSET 0x26
664 #define QUERY_DEV_CAP_MAX_AV_OFFSET 0x27
665 #define QUERY_DEV_CAP_MAX_REQ_QP_OFFSET 0x29
666 #define QUERY_DEV_CAP_MAX_RES_QP_OFFSET 0x2b
667 #define QUERY_DEV_CAP_MAX_GSO_OFFSET 0x2d
668 #define QUERY_DEV_CAP_RSS_OFFSET 0x2e
669 #define QUERY_DEV_CAP_MAX_RDMA_OFFSET 0x2f
670 #define QUERY_DEV_CAP_RSZ_SRQ_OFFSET 0x33
671 #define QUERY_DEV_CAP_PORT_BEACON_OFFSET 0x34
672 #define QUERY_DEV_CAP_ACK_DELAY_OFFSET 0x35
673 #define QUERY_DEV_CAP_MTU_WIDTH_OFFSET 0x36
674 #define QUERY_DEV_CAP_VL_PORT_OFFSET 0x37
675 #define QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET 0x38
676 #define QUERY_DEV_CAP_MAX_GID_OFFSET 0x3b
677 #define QUERY_DEV_CAP_RATE_SUPPORT_OFFSET 0x3c
678 #define QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET 0x3e
679 #define QUERY_DEV_CAP_MAX_PKEY_OFFSET 0x3f
680 #define QUERY_DEV_CAP_EXT_FLAGS_OFFSET 0x40
681 #define QUERY_DEV_CAP_FLAGS_OFFSET 0x44
682 #define QUERY_DEV_CAP_RSVD_UAR_OFFSET 0x48
683 #define QUERY_DEV_CAP_UAR_SZ_OFFSET 0x49
684 #define QUERY_DEV_CAP_PAGE_SZ_OFFSET 0x4b
685 #define QUERY_DEV_CAP_BF_OFFSET 0x4c
686 #define QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET 0x4d
687 #define QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET 0x4e
688 #define QUERY_DEV_CAP_LOG_MAX_BF_PAGES_OFFSET 0x4f
689 #define QUERY_DEV_CAP_MAX_SG_SQ_OFFSET 0x51
690 #define QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET 0x52
691 #define QUERY_DEV_CAP_MAX_SG_RQ_OFFSET 0x55
692 #define QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET 0x56
693 #define QUERY_DEV_CAP_MAX_QP_MCG_OFFSET 0x61
694 #define QUERY_DEV_CAP_RSVD_MCG_OFFSET 0x62
695 #define QUERY_DEV_CAP_MAX_MCG_OFFSET 0x63
696 #define QUERY_DEV_CAP_RSVD_PD_OFFSET 0x64
697 #define QUERY_DEV_CAP_MAX_PD_OFFSET 0x65
698 #define QUERY_DEV_CAP_RSVD_XRC_OFFSET 0x66
699 #define QUERY_DEV_CAP_MAX_XRC_OFFSET 0x67
700 #define QUERY_DEV_CAP_MAX_COUNTERS_OFFSET 0x68
701 #define QUERY_DEV_CAP_PORT_FLOWSTATS_COUNTERS_OFFSET 0x70
702 #define QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET 0x70
703 #define QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET 0x74
704 #define QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET 0x76
705 #define QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET 0x77
706 #define QUERY_DEV_CAP_CQ_EQ_CACHE_LINE_STRIDE 0x7a
707 #define QUERY_DEV_CAP_ECN_QCN_VER_OFFSET 0x7b
708 #define QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET 0x80
709 #define QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET 0x82
710 #define QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET 0x84
711 #define QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET 0x86
712 #define QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET 0x88
713 #define QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET 0x8a
714 #define QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET 0x8c
715 #define QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET 0x8e
716 #define QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET 0x90
717 #define QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET 0x92
718 #define QUERY_DEV_CAP_BMME_FLAGS_OFFSET 0x94
719 #define QUERY_DEV_CAP_CONFIG_DEV_OFFSET 0x94
720 #define QUERY_DEV_CAP_PHV_EN_OFFSET 0x96
721 #define QUERY_DEV_CAP_RSVD_LKEY_OFFSET 0x98
722 #define QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET 0xa0
723 #define QUERY_DEV_CAP_ETH_BACKPL_OFFSET 0x9c
724 #define QUERY_DEV_CAP_FW_REASSIGN_MAC 0x9d
725 #define QUERY_DEV_CAP_VXLAN 0x9e
726 #define QUERY_DEV_CAP_MAD_DEMUX_OFFSET 0xb0
727 #define QUERY_DEV_CAP_DMFS_HIGH_RATE_QPN_BASE_OFFSET 0xa8
728 #define QUERY_DEV_CAP_DMFS_HIGH_RATE_QPN_RANGE_OFFSET 0xac
729 #define QUERY_DEV_CAP_QP_RATE_LIMIT_NUM_OFFSET 0xcc
730 #define QUERY_DEV_CAP_QP_RATE_LIMIT_MAX_OFFSET 0xd0
731 #define QUERY_DEV_CAP_QP_RATE_LIMIT_MIN_OFFSET 0xd2
732
733
734 dev_cap->flags2 = 0;
735 mailbox = mlx4_alloc_cmd_mailbox(dev);
736 if (IS_ERR(mailbox))
737 return PTR_ERR(mailbox);
738 outbox = mailbox->buf;
739
740 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP,
741 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
742 if (err)
743 goto out;
744
745 if (mlx4_is_mfunc(dev))
746 disable_unsupported_roce_caps(outbox);
747 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_QP_OFFSET);
748 dev_cap->reserved_qps = 1 << (field & 0xf);
749 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_OFFSET);
750 dev_cap->max_qps = 1 << (field & 0x1f);
751 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_SRQ_OFFSET);
752 dev_cap->reserved_srqs = 1 << (field >> 4);
753 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_OFFSET);
754 dev_cap->max_srqs = 1 << (field & 0x1f);
755 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET);
756 dev_cap->max_cq_sz = 1 << field;
757 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_CQ_OFFSET);
758 dev_cap->reserved_cqs = 1 << (field & 0xf);
759 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_OFFSET);
760 dev_cap->max_cqs = 1 << (field & 0x1f);
761 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MPT_OFFSET);
762 dev_cap->max_mpts = 1 << (field & 0x3f);
763 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_EQ_OFFSET);
764 dev_cap->reserved_eqs = 1 << (field & 0xf);
765 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_EQ_OFFSET);
766 dev_cap->max_eqs = 1 << (field & 0xf);
767 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MTT_OFFSET);
768 dev_cap->reserved_mtts = 1 << (field >> 4);
769 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET);
770 dev_cap->max_mrw_sz = 1 << field;
771 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MRW_OFFSET);
772 dev_cap->reserved_mrws = 1 << (field & 0xf);
773 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET);
774 dev_cap->max_mtt_seg = 1 << (field & 0x3f);
775 MLX4_GET(size, outbox, QUERY_DEV_CAP_NUM_SYS_EQ_OFFSET);
776 dev_cap->num_sys_eqs = size & 0xfff;
777 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_REQ_QP_OFFSET);
778 dev_cap->max_requester_per_qp = 1 << (field & 0x3f);
779 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RES_QP_OFFSET);
780 dev_cap->max_responder_per_qp = 1 << (field & 0x3f);
781 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GSO_OFFSET);
782 field &= 0x1f;
783 if (!field)
784 dev_cap->max_gso_sz = 0;
785 else
786 dev_cap->max_gso_sz = 1 << field;
787
788 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSS_OFFSET);
789 if (field & 0x20)
790 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_XOR;
791 if (field & 0x10)
792 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_TOP;
793 field &= 0xf;
794 if (field) {
795 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS;
796 dev_cap->max_rss_tbl_sz = 1 << field;
797 } else
798 dev_cap->max_rss_tbl_sz = 0;
799 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RDMA_OFFSET);
800 dev_cap->max_rdma_global = 1 << (field & 0x3f);
801 MLX4_GET(field, outbox, QUERY_DEV_CAP_ACK_DELAY_OFFSET);
802 dev_cap->local_ca_ack_delay = field & 0x1f;
803 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET);
804 dev_cap->num_ports = field & 0xf;
805 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET);
806 dev_cap->max_msg_sz = 1 << (field & 0x1f);
807 MLX4_GET(field, outbox, QUERY_DEV_CAP_PORT_FLOWSTATS_COUNTERS_OFFSET);
808 if (field & 0x10)
809 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FLOWSTATS_EN;
810 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET);
811 if (field & 0x80)
812 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FS_EN;
813 dev_cap->fs_log_max_ucast_qp_range_size = field & 0x1f;
814 if (field & 0x20)
815 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_DMFS_UC_MC_SNIFFER;
816 MLX4_GET(field, outbox, QUERY_DEV_CAP_PORT_BEACON_OFFSET);
817 if (field & 0x80)
818 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_PORT_BEACON;
819 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET);
820 if (field & 0x80)
821 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_DMFS_IPOIB;
822 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET);
823 dev_cap->fs_max_num_qp_per_entry = field;
824 MLX4_GET(field, outbox, QUERY_DEV_CAP_ECN_QCN_VER_OFFSET);
825 if (field & 0x1)
826 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_QCN;
827 MLX4_GET(stat_rate, outbox, QUERY_DEV_CAP_RATE_SUPPORT_OFFSET);
828 dev_cap->stat_rate_support = stat_rate;
829 MLX4_GET(field, outbox, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET);
830 if (field & 0x80)
831 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_TS;
832 MLX4_GET(ext_flags, outbox, QUERY_DEV_CAP_EXT_FLAGS_OFFSET);
833 MLX4_GET(flags, outbox, QUERY_DEV_CAP_FLAGS_OFFSET);
834 dev_cap->flags = flags | (u64)ext_flags << 32;
835 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_UAR_OFFSET);
836 dev_cap->reserved_uars = field >> 4;
837 MLX4_GET(field, outbox, QUERY_DEV_CAP_UAR_SZ_OFFSET);
838 dev_cap->uar_size = 1 << ((field & 0x3f) + 20);
839 MLX4_GET(field, outbox, QUERY_DEV_CAP_PAGE_SZ_OFFSET);
840 dev_cap->min_page_sz = 1 << field;
841
842 MLX4_GET(field, outbox, QUERY_DEV_CAP_BF_OFFSET);
843 if (field & 0x80) {
844 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET);
845 dev_cap->bf_reg_size = 1 << (field & 0x1f);
846 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET);
847 if ((1 << (field & 0x3f)) > (PAGE_SIZE / dev_cap->bf_reg_size))
848 field = 3;
849 dev_cap->bf_regs_per_page = 1 << (field & 0x3f);
850 } else {
851 dev_cap->bf_reg_size = 0;
852 }
853
854 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_SQ_OFFSET);
855 dev_cap->max_sq_sg = field;
856 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET);
857 dev_cap->max_sq_desc_sz = size;
858
859 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_MCG_OFFSET);
860 dev_cap->max_qp_per_mcg = 1 << field;
861 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MCG_OFFSET);
862 dev_cap->reserved_mgms = field & 0xf;
863 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MCG_OFFSET);
864 dev_cap->max_mcgs = 1 << field;
865 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_PD_OFFSET);
866 dev_cap->reserved_pds = field >> 4;
867 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PD_OFFSET);
868 dev_cap->max_pds = 1 << (field & 0x3f);
869 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_XRC_OFFSET);
870 dev_cap->reserved_xrcds = field >> 4;
871 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_XRC_OFFSET);
872 dev_cap->max_xrcds = 1 << (field & 0x1f);
873
874 MLX4_GET(size, outbox, QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET);
875 dev_cap->rdmarc_entry_sz = size;
876 MLX4_GET(size, outbox, QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET);
877 dev_cap->qpc_entry_sz = size;
878 MLX4_GET(size, outbox, QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET);
879 dev_cap->aux_entry_sz = size;
880 MLX4_GET(size, outbox, QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET);
881 dev_cap->altc_entry_sz = size;
882 MLX4_GET(size, outbox, QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET);
883 dev_cap->eqc_entry_sz = size;
884 MLX4_GET(size, outbox, QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET);
885 dev_cap->cqc_entry_sz = size;
886 MLX4_GET(size, outbox, QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET);
887 dev_cap->srq_entry_sz = size;
888 MLX4_GET(size, outbox, QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET);
889 dev_cap->cmpt_entry_sz = size;
890 MLX4_GET(size, outbox, QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET);
891 dev_cap->mtt_entry_sz = size;
892 MLX4_GET(size, outbox, QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET);
893 dev_cap->dmpt_entry_sz = size;
894
895 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET);
896 dev_cap->max_srq_sz = 1 << field;
897 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_SZ_OFFSET);
898 dev_cap->max_qp_sz = 1 << field;
899 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSZ_SRQ_OFFSET);
900 dev_cap->resize_srq = field & 1;
901 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_RQ_OFFSET);
902 dev_cap->max_rq_sg = field;
903 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET);
904 dev_cap->max_rq_desc_sz = size;
905 MLX4_GET(field, outbox, QUERY_DEV_CAP_CQ_EQ_CACHE_LINE_STRIDE);
906 if (field & (1 << 4))
907 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_QOS_VPP;
908 if (field & (1 << 5))
909 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL;
910 if (field & (1 << 6))
911 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_CQE_STRIDE;
912 if (field & (1 << 7))
913 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_EQE_STRIDE;
914 MLX4_GET(dev_cap->bmme_flags, outbox,
915 QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
916 if (dev_cap->bmme_flags & MLX4_FLAG_ROCE_V1_V2)
917 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_ROCE_V1_V2;
918 if (dev_cap->bmme_flags & MLX4_FLAG_PORT_REMAP)
919 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_PORT_REMAP;
920 MLX4_GET(field, outbox, QUERY_DEV_CAP_CONFIG_DEV_OFFSET);
921 if (field & 0x20)
922 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_CONFIG_DEV;
923 if (field & (1 << 2))
924 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_IGNORE_FCS;
925 MLX4_GET(field, outbox, QUERY_DEV_CAP_PHV_EN_OFFSET);
926 if (field & 0x80)
927 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_PHV_EN;
928 if (field & 0x40)
929 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_SKIP_OUTER_VLAN;
930
931 MLX4_GET(dev_cap->reserved_lkey, outbox,
932 QUERY_DEV_CAP_RSVD_LKEY_OFFSET);
933 MLX4_GET(field32, outbox, QUERY_DEV_CAP_ETH_BACKPL_OFFSET);
934 if (field32 & (1 << 0))
935 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_ETH_BACKPL_AN_REP;
936 if (field32 & (1 << 7))
937 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RECOVERABLE_ERROR_EVENT;
938 MLX4_GET(field, outbox, QUERY_DEV_CAP_FW_REASSIGN_MAC);
939 if (field & 1<<6)
940 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN;
941 MLX4_GET(field, outbox, QUERY_DEV_CAP_VXLAN);
942 if (field & 1<<3)
943 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS;
944 if (field & (1 << 5))
945 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_ETS_CFG;
946 MLX4_GET(dev_cap->max_icm_sz, outbox,
947 QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET);
948 if (dev_cap->flags & MLX4_DEV_CAP_FLAG_COUNTERS)
949 MLX4_GET(dev_cap->max_counters, outbox,
950 QUERY_DEV_CAP_MAX_COUNTERS_OFFSET);
951
952 MLX4_GET(field32, outbox,
953 QUERY_DEV_CAP_MAD_DEMUX_OFFSET);
954 if (field32 & (1 << 0))
955 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_MAD_DEMUX;
956
957 MLX4_GET(dev_cap->dmfs_high_rate_qpn_base, outbox,
958 QUERY_DEV_CAP_DMFS_HIGH_RATE_QPN_BASE_OFFSET);
959 dev_cap->dmfs_high_rate_qpn_base &= MGM_QPN_MASK;
960 MLX4_GET(dev_cap->dmfs_high_rate_qpn_range, outbox,
961 QUERY_DEV_CAP_DMFS_HIGH_RATE_QPN_RANGE_OFFSET);
962 dev_cap->dmfs_high_rate_qpn_range &= MGM_QPN_MASK;
963
964 MLX4_GET(size, outbox, QUERY_DEV_CAP_QP_RATE_LIMIT_NUM_OFFSET);
965 dev_cap->rl_caps.num_rates = size;
966 if (dev_cap->rl_caps.num_rates) {
967 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_QP_RATE_LIMIT;
968 MLX4_GET(size, outbox, QUERY_DEV_CAP_QP_RATE_LIMIT_MAX_OFFSET);
969 dev_cap->rl_caps.max_val = size & 0xfff;
970 dev_cap->rl_caps.max_unit = size >> 14;
971 MLX4_GET(size, outbox, QUERY_DEV_CAP_QP_RATE_LIMIT_MIN_OFFSET);
972 dev_cap->rl_caps.min_val = size & 0xfff;
973 dev_cap->rl_caps.min_unit = size >> 14;
974 }
975
976 MLX4_GET(field32, outbox, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET);
977 if (field32 & (1 << 16))
978 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_UPDATE_QP;
979 if (field32 & (1 << 18))
980 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_UPDATE_QP_SRC_CHECK_LB;
981 if (field32 & (1 << 19))
982 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_LB_SRC_CHK;
983 if (field32 & (1 << 26))
984 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_VLAN_CONTROL;
985 if (field32 & (1 << 20))
986 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FSM;
987 if (field32 & (1 << 21))
988 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_80_VFS;
989
990 for (i = 1; i <= dev_cap->num_ports; i++) {
991 err = mlx4_QUERY_PORT(dev, i, dev_cap->port_cap + i);
992 if (err)
993 goto out;
994 }
995
996 /*
997 * Each UAR has 4 EQ doorbells; so if a UAR is reserved, then
998 * we can't use any EQs whose doorbell falls on that page,
999 * even if the EQ itself isn't reserved.
1000 */
1001 if (dev_cap->num_sys_eqs == 0)
1002 dev_cap->reserved_eqs = max(dev_cap->reserved_uars * 4,
1003 dev_cap->reserved_eqs);
1004 else
1005 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_SYS_EQS;
1006
1007 out:
1008 mlx4_free_cmd_mailbox(dev, mailbox);
1009 return err;
1010 }
1011
1012 void mlx4_dev_cap_dump(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
1013 {
1014 if (dev_cap->bf_reg_size > 0)
1015 mlx4_dbg(dev, "BlueFlame available (reg size %d, regs/page %d)\n",
1016 dev_cap->bf_reg_size, dev_cap->bf_regs_per_page);
1017 else
1018 mlx4_dbg(dev, "BlueFlame not available\n");
1019
1020 mlx4_dbg(dev, "Base MM extensions: flags %08x, rsvd L_Key %08x\n",
1021 dev_cap->bmme_flags, dev_cap->reserved_lkey);
1022 mlx4_dbg(dev, "Max ICM size %lld MB\n",
1023 (unsigned long long) dev_cap->max_icm_sz >> 20);
1024 mlx4_dbg(dev, "Max QPs: %d, reserved QPs: %d, entry size: %d\n",
1025 dev_cap->max_qps, dev_cap->reserved_qps, dev_cap->qpc_entry_sz);
1026 mlx4_dbg(dev, "Max SRQs: %d, reserved SRQs: %d, entry size: %d\n",
1027 dev_cap->max_srqs, dev_cap->reserved_srqs, dev_cap->srq_entry_sz);
1028 mlx4_dbg(dev, "Max CQs: %d, reserved CQs: %d, entry size: %d\n",
1029 dev_cap->max_cqs, dev_cap->reserved_cqs, dev_cap->cqc_entry_sz);
1030 mlx4_dbg(dev, "Num sys EQs: %d, max EQs: %d, reserved EQs: %d, entry size: %d\n",
1031 dev_cap->num_sys_eqs, dev_cap->max_eqs, dev_cap->reserved_eqs,
1032 dev_cap->eqc_entry_sz);
1033 mlx4_dbg(dev, "reserved MPTs: %d, reserved MTTs: %d\n",
1034 dev_cap->reserved_mrws, dev_cap->reserved_mtts);
1035 mlx4_dbg(dev, "Max PDs: %d, reserved PDs: %d, reserved UARs: %d\n",
1036 dev_cap->max_pds, dev_cap->reserved_pds, dev_cap->reserved_uars);
1037 mlx4_dbg(dev, "Max QP/MCG: %d, reserved MGMs: %d\n",
1038 dev_cap->max_pds, dev_cap->reserved_mgms);
1039 mlx4_dbg(dev, "Max CQEs: %d, max WQEs: %d, max SRQ WQEs: %d\n",
1040 dev_cap->max_cq_sz, dev_cap->max_qp_sz, dev_cap->max_srq_sz);
1041 mlx4_dbg(dev, "Local CA ACK delay: %d, max MTU: %d, port width cap: %d\n",
1042 dev_cap->local_ca_ack_delay, 128 << dev_cap->port_cap[1].ib_mtu,
1043 dev_cap->port_cap[1].max_port_width);
1044 mlx4_dbg(dev, "Max SQ desc size: %d, max SQ S/G: %d\n",
1045 dev_cap->max_sq_desc_sz, dev_cap->max_sq_sg);
1046 mlx4_dbg(dev, "Max RQ desc size: %d, max RQ S/G: %d\n",
1047 dev_cap->max_rq_desc_sz, dev_cap->max_rq_sg);
1048 mlx4_dbg(dev, "Max GSO size: %d\n", dev_cap->max_gso_sz);
1049 mlx4_dbg(dev, "Max counters: %d\n", dev_cap->max_counters);
1050 mlx4_dbg(dev, "Max RSS Table size: %d\n", dev_cap->max_rss_tbl_sz);
1051 mlx4_dbg(dev, "DMFS high rate steer QPn base: %d\n",
1052 dev_cap->dmfs_high_rate_qpn_base);
1053 mlx4_dbg(dev, "DMFS high rate steer QPn range: %d\n",
1054 dev_cap->dmfs_high_rate_qpn_range);
1055
1056 if (dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_QP_RATE_LIMIT) {
1057 struct mlx4_rate_limit_caps *rl_caps = &dev_cap->rl_caps;
1058
1059 mlx4_dbg(dev, "QP Rate-Limit: #rates %d, unit/val max %d/%d, min %d/%d\n",
1060 rl_caps->num_rates, rl_caps->max_unit, rl_caps->max_val,
1061 rl_caps->min_unit, rl_caps->min_val);
1062 }
1063
1064 dump_dev_cap_flags(dev, dev_cap->flags);
1065 dump_dev_cap_flags2(dev, dev_cap->flags2);
1066 }
1067
1068 int mlx4_QUERY_PORT(struct mlx4_dev *dev, int port, struct mlx4_port_cap *port_cap)
1069 {
1070 struct mlx4_cmd_mailbox *mailbox;
1071 u32 *outbox;
1072 u8 field;
1073 u32 field32;
1074 int err;
1075
1076 mailbox = mlx4_alloc_cmd_mailbox(dev);
1077 if (IS_ERR(mailbox))
1078 return PTR_ERR(mailbox);
1079 outbox = mailbox->buf;
1080
1081 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
1082 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP,
1083 MLX4_CMD_TIME_CLASS_A,
1084 MLX4_CMD_NATIVE);
1085
1086 if (err)
1087 goto out;
1088
1089 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET);
1090 port_cap->max_vl = field >> 4;
1091 MLX4_GET(field, outbox, QUERY_DEV_CAP_MTU_WIDTH_OFFSET);
1092 port_cap->ib_mtu = field >> 4;
1093 port_cap->max_port_width = field & 0xf;
1094 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GID_OFFSET);
1095 port_cap->max_gids = 1 << (field & 0xf);
1096 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PKEY_OFFSET);
1097 port_cap->max_pkeys = 1 << (field & 0xf);
1098 } else {
1099 #define QUERY_PORT_SUPPORTED_TYPE_OFFSET 0x00
1100 #define QUERY_PORT_MTU_OFFSET 0x01
1101 #define QUERY_PORT_ETH_MTU_OFFSET 0x02
1102 #define QUERY_PORT_WIDTH_OFFSET 0x06
1103 #define QUERY_PORT_MAX_GID_PKEY_OFFSET 0x07
1104 #define QUERY_PORT_MAX_MACVLAN_OFFSET 0x0a
1105 #define QUERY_PORT_MAX_VL_OFFSET 0x0b
1106 #define QUERY_PORT_MAC_OFFSET 0x10
1107 #define QUERY_PORT_TRANS_VENDOR_OFFSET 0x18
1108 #define QUERY_PORT_WAVELENGTH_OFFSET 0x1c
1109 #define QUERY_PORT_TRANS_CODE_OFFSET 0x20
1110
1111 err = mlx4_cmd_box(dev, 0, mailbox->dma, port, 0, MLX4_CMD_QUERY_PORT,
1112 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
1113 if (err)
1114 goto out;
1115
1116 MLX4_GET(field, outbox, QUERY_PORT_SUPPORTED_TYPE_OFFSET);
1117 port_cap->link_state = (field & 0x80) >> 7;
1118 port_cap->supported_port_types = field & 3;
1119 port_cap->suggested_type = (field >> 3) & 1;
1120 port_cap->default_sense = (field >> 4) & 1;
1121 port_cap->dmfs_optimized_state = (field >> 5) & 1;
1122 MLX4_GET(field, outbox, QUERY_PORT_MTU_OFFSET);
1123 port_cap->ib_mtu = field & 0xf;
1124 MLX4_GET(field, outbox, QUERY_PORT_WIDTH_OFFSET);
1125 port_cap->max_port_width = field & 0xf;
1126 MLX4_GET(field, outbox, QUERY_PORT_MAX_GID_PKEY_OFFSET);
1127 port_cap->max_gids = 1 << (field >> 4);
1128 port_cap->max_pkeys = 1 << (field & 0xf);
1129 MLX4_GET(field, outbox, QUERY_PORT_MAX_VL_OFFSET);
1130 port_cap->max_vl = field & 0xf;
1131 port_cap->max_tc_eth = field >> 4;
1132 MLX4_GET(field, outbox, QUERY_PORT_MAX_MACVLAN_OFFSET);
1133 port_cap->log_max_macs = field & 0xf;
1134 port_cap->log_max_vlans = field >> 4;
1135 MLX4_GET(port_cap->eth_mtu, outbox, QUERY_PORT_ETH_MTU_OFFSET);
1136 MLX4_GET(port_cap->def_mac, outbox, QUERY_PORT_MAC_OFFSET);
1137 MLX4_GET(field32, outbox, QUERY_PORT_TRANS_VENDOR_OFFSET);
1138 port_cap->trans_type = field32 >> 24;
1139 port_cap->vendor_oui = field32 & 0xffffff;
1140 MLX4_GET(port_cap->wavelength, outbox, QUERY_PORT_WAVELENGTH_OFFSET);
1141 MLX4_GET(port_cap->trans_code, outbox, QUERY_PORT_TRANS_CODE_OFFSET);
1142 }
1143
1144 out:
1145 mlx4_free_cmd_mailbox(dev, mailbox);
1146 return err;
1147 }
1148
1149 #define DEV_CAP_EXT_2_FLAG_PFC_COUNTERS (1 << 28)
1150 #define DEV_CAP_EXT_2_FLAG_VLAN_CONTROL (1 << 26)
1151 #define DEV_CAP_EXT_2_FLAG_80_VFS (1 << 21)
1152 #define DEV_CAP_EXT_2_FLAG_FSM (1 << 20)
1153
1154 int mlx4_QUERY_DEV_CAP_wrapper(struct mlx4_dev *dev, int slave,
1155 struct mlx4_vhcr *vhcr,
1156 struct mlx4_cmd_mailbox *inbox,
1157 struct mlx4_cmd_mailbox *outbox,
1158 struct mlx4_cmd_info *cmd)
1159 {
1160 u64 flags;
1161 int err = 0;
1162 u8 field;
1163 u16 field16;
1164 u32 bmme_flags, field32;
1165 int real_port;
1166 int slave_port;
1167 int first_port;
1168 struct mlx4_active_ports actv_ports;
1169
1170 err = mlx4_cmd_box(dev, 0, outbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP,
1171 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1172 if (err)
1173 return err;
1174
1175 disable_unsupported_roce_caps(outbox->buf);
1176 /* add port mng change event capability and disable mw type 1
1177 * unconditionally to slaves
1178 */
1179 MLX4_GET(flags, outbox->buf, QUERY_DEV_CAP_EXT_FLAGS_OFFSET);
1180 flags |= MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV;
1181 flags &= ~MLX4_DEV_CAP_FLAG_MEM_WINDOW;
1182 actv_ports = mlx4_get_active_ports(dev, slave);
1183 first_port = find_first_bit(actv_ports.ports, dev->caps.num_ports);
1184 for (slave_port = 0, real_port = first_port;
1185 real_port < first_port +
1186 bitmap_weight(actv_ports.ports, dev->caps.num_ports);
1187 ++real_port, ++slave_port) {
1188 if (flags & (MLX4_DEV_CAP_FLAG_WOL_PORT1 << real_port))
1189 flags |= MLX4_DEV_CAP_FLAG_WOL_PORT1 << slave_port;
1190 else
1191 flags &= ~(MLX4_DEV_CAP_FLAG_WOL_PORT1 << slave_port);
1192 }
1193 for (; slave_port < dev->caps.num_ports; ++slave_port)
1194 flags &= ~(MLX4_DEV_CAP_FLAG_WOL_PORT1 << slave_port);
1195
1196 /* Not exposing RSS IP fragments to guests */
1197 flags &= ~MLX4_DEV_CAP_FLAG_RSS_IP_FRAG;
1198 MLX4_PUT(outbox->buf, flags, QUERY_DEV_CAP_EXT_FLAGS_OFFSET);
1199
1200 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_VL_PORT_OFFSET);
1201 field &= ~0x0F;
1202 field |= bitmap_weight(actv_ports.ports, dev->caps.num_ports) & 0x0F;
1203 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_VL_PORT_OFFSET);
1204
1205 /* For guests, disable timestamp */
1206 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET);
1207 field &= 0x7f;
1208 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET);
1209
1210 /* For guests, disable vxlan tunneling and QoS support */
1211 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_VXLAN);
1212 field &= 0xd7;
1213 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_VXLAN);
1214
1215 /* For guests, disable port BEACON */
1216 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_PORT_BEACON_OFFSET);
1217 field &= 0x7f;
1218 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_PORT_BEACON_OFFSET);
1219
1220 /* For guests, report Blueflame disabled */
1221 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_BF_OFFSET);
1222 field &= 0x7f;
1223 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_BF_OFFSET);
1224
1225 /* For guests, disable mw type 2 and port remap*/
1226 MLX4_GET(bmme_flags, outbox->buf, QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
1227 bmme_flags &= ~MLX4_BMME_FLAG_TYPE_2_WIN;
1228 bmme_flags &= ~MLX4_FLAG_PORT_REMAP;
1229 MLX4_PUT(outbox->buf, bmme_flags, QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
1230
1231 /* turn off device-managed steering capability if not enabled */
1232 if (dev->caps.steering_mode != MLX4_STEERING_MODE_DEVICE_MANAGED) {
1233 MLX4_GET(field, outbox->buf,
1234 QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET);
1235 field &= 0x7f;
1236 MLX4_PUT(outbox->buf, field,
1237 QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET);
1238 }
1239
1240 /* turn off ipoib managed steering for guests */
1241 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET);
1242 field &= ~0x80;
1243 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET);
1244
1245 /* turn off host side virt features (VST, FSM, etc) for guests */
1246 MLX4_GET(field32, outbox->buf, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET);
1247 field32 &= ~(DEV_CAP_EXT_2_FLAG_VLAN_CONTROL | DEV_CAP_EXT_2_FLAG_80_VFS |
1248 DEV_CAP_EXT_2_FLAG_FSM | DEV_CAP_EXT_2_FLAG_PFC_COUNTERS);
1249 MLX4_PUT(outbox->buf, field32, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET);
1250
1251 /* turn off QCN for guests */
1252 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_ECN_QCN_VER_OFFSET);
1253 field &= 0xfe;
1254 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_ECN_QCN_VER_OFFSET);
1255
1256 /* turn off QP max-rate limiting for guests */
1257 field16 = 0;
1258 MLX4_PUT(outbox->buf, field16, QUERY_DEV_CAP_QP_RATE_LIMIT_NUM_OFFSET);
1259
1260 /* turn off QoS per VF support for guests */
1261 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_CQ_EQ_CACHE_LINE_STRIDE);
1262 field &= 0xef;
1263 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_CQ_EQ_CACHE_LINE_STRIDE);
1264
1265 /* turn off ignore FCS feature for guests */
1266 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_CONFIG_DEV_OFFSET);
1267 field &= 0xfb;
1268 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_CONFIG_DEV_OFFSET);
1269
1270 return 0;
1271 }
1272
1273 static void disable_unsupported_roce_caps(void *buf)
1274 {
1275 u32 flags;
1276
1277 MLX4_GET(flags, buf, QUERY_DEV_CAP_EXT_FLAGS_OFFSET);
1278 flags &= ~(1UL << 31);
1279 MLX4_PUT(buf, flags, QUERY_DEV_CAP_EXT_FLAGS_OFFSET);
1280 MLX4_GET(flags, buf, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET);
1281 flags &= ~(1UL << 24);
1282 MLX4_PUT(buf, flags, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET);
1283 MLX4_GET(flags, buf, QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
1284 flags &= ~(MLX4_FLAG_ROCE_V1_V2);
1285 MLX4_PUT(buf, flags, QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
1286 }
1287
1288 int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave,
1289 struct mlx4_vhcr *vhcr,
1290 struct mlx4_cmd_mailbox *inbox,
1291 struct mlx4_cmd_mailbox *outbox,
1292 struct mlx4_cmd_info *cmd)
1293 {
1294 struct mlx4_priv *priv = mlx4_priv(dev);
1295 u64 def_mac;
1296 u8 port_type;
1297 u16 short_field;
1298 int err;
1299 int admin_link_state;
1300 int port = mlx4_slave_convert_port(dev, slave,
1301 vhcr->in_modifier & 0xFF);
1302
1303 #define MLX4_VF_PORT_NO_LINK_SENSE_MASK 0xE0
1304 #define MLX4_PORT_LINK_UP_MASK 0x80
1305 #define QUERY_PORT_CUR_MAX_PKEY_OFFSET 0x0c
1306 #define QUERY_PORT_CUR_MAX_GID_OFFSET 0x0e
1307
1308 if (port < 0)
1309 return -EINVAL;
1310
1311 /* Protect against untrusted guests: enforce that this is the
1312 * QUERY_PORT general query.
1313 */
1314 if (vhcr->op_modifier || vhcr->in_modifier & ~0xFF)
1315 return -EINVAL;
1316
1317 vhcr->in_modifier = port;
1318
1319 err = mlx4_cmd_box(dev, 0, outbox->dma, vhcr->in_modifier, 0,
1320 MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B,
1321 MLX4_CMD_NATIVE);
1322
1323 if (!err && dev->caps.function != slave) {
1324 def_mac = priv->mfunc.master.vf_oper[slave].vport[vhcr->in_modifier].state.mac;
1325 MLX4_PUT(outbox->buf, def_mac, QUERY_PORT_MAC_OFFSET);
1326
1327 /* get port type - currently only eth is enabled */
1328 MLX4_GET(port_type, outbox->buf,
1329 QUERY_PORT_SUPPORTED_TYPE_OFFSET);
1330
1331 /* No link sensing allowed */
1332 port_type &= MLX4_VF_PORT_NO_LINK_SENSE_MASK;
1333 /* set port type to currently operating port type */
1334 port_type |= (dev->caps.port_type[vhcr->in_modifier] & 0x3);
1335
1336 admin_link_state = priv->mfunc.master.vf_oper[slave].vport[vhcr->in_modifier].state.link_state;
1337 if (IFLA_VF_LINK_STATE_ENABLE == admin_link_state)
1338 port_type |= MLX4_PORT_LINK_UP_MASK;
1339 else if (IFLA_VF_LINK_STATE_DISABLE == admin_link_state)
1340 port_type &= ~MLX4_PORT_LINK_UP_MASK;
1341 else if (IFLA_VF_LINK_STATE_AUTO == admin_link_state && mlx4_is_bonded(dev)) {
1342 int other_port = (port == 1) ? 2 : 1;
1343 struct mlx4_port_cap port_cap;
1344
1345 err = mlx4_QUERY_PORT(dev, other_port, &port_cap);
1346 if (err)
1347 goto out;
1348 port_type |= (port_cap.link_state << 7);
1349 }
1350
1351 MLX4_PUT(outbox->buf, port_type,
1352 QUERY_PORT_SUPPORTED_TYPE_OFFSET);
1353
1354 if (dev->caps.port_type[vhcr->in_modifier] == MLX4_PORT_TYPE_ETH)
1355 short_field = mlx4_get_slave_num_gids(dev, slave, port);
1356 else
1357 short_field = 1; /* slave max gids */
1358 MLX4_PUT(outbox->buf, short_field,
1359 QUERY_PORT_CUR_MAX_GID_OFFSET);
1360
1361 short_field = dev->caps.pkey_table_len[vhcr->in_modifier];
1362 MLX4_PUT(outbox->buf, short_field,
1363 QUERY_PORT_CUR_MAX_PKEY_OFFSET);
1364 }
1365 out:
1366 return err;
1367 }
1368
1369 int mlx4_get_slave_pkey_gid_tbl_len(struct mlx4_dev *dev, u8 port,
1370 int *gid_tbl_len, int *pkey_tbl_len)
1371 {
1372 struct mlx4_cmd_mailbox *mailbox;
1373 u32 *outbox;
1374 u16 field;
1375 int err;
1376
1377 mailbox = mlx4_alloc_cmd_mailbox(dev);
1378 if (IS_ERR(mailbox))
1379 return PTR_ERR(mailbox);
1380
1381 err = mlx4_cmd_box(dev, 0, mailbox->dma, port, 0,
1382 MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B,
1383 MLX4_CMD_WRAPPED);
1384 if (err)
1385 goto out;
1386
1387 outbox = mailbox->buf;
1388
1389 MLX4_GET(field, outbox, QUERY_PORT_CUR_MAX_GID_OFFSET);
1390 *gid_tbl_len = field;
1391
1392 MLX4_GET(field, outbox, QUERY_PORT_CUR_MAX_PKEY_OFFSET);
1393 *pkey_tbl_len = field;
1394
1395 out:
1396 mlx4_free_cmd_mailbox(dev, mailbox);
1397 return err;
1398 }
1399 EXPORT_SYMBOL(mlx4_get_slave_pkey_gid_tbl_len);
1400
1401 int mlx4_map_cmd(struct mlx4_dev *dev, u16 op, struct mlx4_icm *icm, u64 virt)
1402 {
1403 struct mlx4_cmd_mailbox *mailbox;
1404 struct mlx4_icm_iter iter;
1405 __be64 *pages;
1406 int lg;
1407 int nent = 0;
1408 int i;
1409 int err = 0;
1410 int ts = 0, tc = 0;
1411
1412 mailbox = mlx4_alloc_cmd_mailbox(dev);
1413 if (IS_ERR(mailbox))
1414 return PTR_ERR(mailbox);
1415 pages = mailbox->buf;
1416
1417 for (mlx4_icm_first(icm, &iter);
1418 !mlx4_icm_last(&iter);
1419 mlx4_icm_next(&iter)) {
1420 /*
1421 * We have to pass pages that are aligned to their
1422 * size, so find the least significant 1 in the
1423 * address or size and use that as our log2 size.
1424 */
1425 lg = ffs(mlx4_icm_addr(&iter) | mlx4_icm_size(&iter)) - 1;
1426 if (lg < MLX4_ICM_PAGE_SHIFT) {
1427 mlx4_warn(dev, "Got FW area not aligned to %d (%llx/%lx)\n",
1428 MLX4_ICM_PAGE_SIZE,
1429 (unsigned long long) mlx4_icm_addr(&iter),
1430 mlx4_icm_size(&iter));
1431 err = -EINVAL;
1432 goto out;
1433 }
1434
1435 for (i = 0; i < mlx4_icm_size(&iter) >> lg; ++i) {
1436 if (virt != -1) {
1437 pages[nent * 2] = cpu_to_be64(virt);
1438 virt += 1 << lg;
1439 }
1440
1441 pages[nent * 2 + 1] =
1442 cpu_to_be64((mlx4_icm_addr(&iter) + (i << lg)) |
1443 (lg - MLX4_ICM_PAGE_SHIFT));
1444 ts += 1 << (lg - 10);
1445 ++tc;
1446
1447 if (++nent == MLX4_MAILBOX_SIZE / 16) {
1448 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op,
1449 MLX4_CMD_TIME_CLASS_B,
1450 MLX4_CMD_NATIVE);
1451 if (err)
1452 goto out;
1453 nent = 0;
1454 }
1455 }
1456 }
1457
1458 if (nent)
1459 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op,
1460 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
1461 if (err)
1462 goto out;
1463
1464 switch (op) {
1465 case MLX4_CMD_MAP_FA:
1466 mlx4_dbg(dev, "Mapped %d chunks/%d KB for FW\n", tc, ts);
1467 break;
1468 case MLX4_CMD_MAP_ICM_AUX:
1469 mlx4_dbg(dev, "Mapped %d chunks/%d KB for ICM aux\n", tc, ts);
1470 break;
1471 case MLX4_CMD_MAP_ICM:
1472 mlx4_dbg(dev, "Mapped %d chunks/%d KB at %llx for ICM\n",
1473 tc, ts, (unsigned long long) virt - (ts << 10));
1474 break;
1475 }
1476
1477 out:
1478 mlx4_free_cmd_mailbox(dev, mailbox);
1479 return err;
1480 }
1481
1482 int mlx4_MAP_FA(struct mlx4_dev *dev, struct mlx4_icm *icm)
1483 {
1484 return mlx4_map_cmd(dev, MLX4_CMD_MAP_FA, icm, -1);
1485 }
1486
1487 int mlx4_UNMAP_FA(struct mlx4_dev *dev)
1488 {
1489 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_UNMAP_FA,
1490 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
1491 }
1492
1493
1494 int mlx4_RUN_FW(struct mlx4_dev *dev)
1495 {
1496 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_RUN_FW,
1497 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1498 }
1499
1500 int mlx4_QUERY_FW(struct mlx4_dev *dev)
1501 {
1502 struct mlx4_fw *fw = &mlx4_priv(dev)->fw;
1503 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
1504 struct mlx4_cmd_mailbox *mailbox;
1505 u32 *outbox;
1506 int err = 0;
1507 u64 fw_ver;
1508 u16 cmd_if_rev;
1509 u8 lg;
1510
1511 #define QUERY_FW_OUT_SIZE 0x100
1512 #define QUERY_FW_VER_OFFSET 0x00
1513 #define QUERY_FW_PPF_ID 0x09
1514 #define QUERY_FW_CMD_IF_REV_OFFSET 0x0a
1515 #define QUERY_FW_MAX_CMD_OFFSET 0x0f
1516 #define QUERY_FW_ERR_START_OFFSET 0x30
1517 #define QUERY_FW_ERR_SIZE_OFFSET 0x38
1518 #define QUERY_FW_ERR_BAR_OFFSET 0x3c
1519
1520 #define QUERY_FW_SIZE_OFFSET 0x00
1521 #define QUERY_FW_CLR_INT_BASE_OFFSET 0x20
1522 #define QUERY_FW_CLR_INT_BAR_OFFSET 0x28
1523
1524 #define QUERY_FW_COMM_BASE_OFFSET 0x40
1525 #define QUERY_FW_COMM_BAR_OFFSET 0x48
1526
1527 #define QUERY_FW_CLOCK_OFFSET 0x50
1528 #define QUERY_FW_CLOCK_BAR 0x58
1529
1530 mailbox = mlx4_alloc_cmd_mailbox(dev);
1531 if (IS_ERR(mailbox))
1532 return PTR_ERR(mailbox);
1533 outbox = mailbox->buf;
1534
1535 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_FW,
1536 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1537 if (err)
1538 goto out;
1539
1540 MLX4_GET(fw_ver, outbox, QUERY_FW_VER_OFFSET);
1541 /*
1542 * FW subminor version is at more significant bits than minor
1543 * version, so swap here.
1544 */
1545 dev->caps.fw_ver = (fw_ver & 0xffff00000000ull) |
1546 ((fw_ver & 0xffff0000ull) >> 16) |
1547 ((fw_ver & 0x0000ffffull) << 16);
1548
1549 MLX4_GET(lg, outbox, QUERY_FW_PPF_ID);
1550 dev->caps.function = lg;
1551
1552 if (mlx4_is_slave(dev))
1553 goto out;
1554
1555
1556 MLX4_GET(cmd_if_rev, outbox, QUERY_FW_CMD_IF_REV_OFFSET);
1557 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_MIN_REV ||
1558 cmd_if_rev > MLX4_COMMAND_INTERFACE_MAX_REV) {
1559 mlx4_err(dev, "Installed FW has unsupported command interface revision %d\n",
1560 cmd_if_rev);
1561 mlx4_err(dev, "(Installed FW version is %d.%d.%03d)\n",
1562 (int) (dev->caps.fw_ver >> 32),
1563 (int) (dev->caps.fw_ver >> 16) & 0xffff,
1564 (int) dev->caps.fw_ver & 0xffff);
1565 mlx4_err(dev, "This driver version supports only revisions %d to %d\n",
1566 MLX4_COMMAND_INTERFACE_MIN_REV, MLX4_COMMAND_INTERFACE_MAX_REV);
1567 err = -ENODEV;
1568 goto out;
1569 }
1570
1571 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS)
1572 dev->flags |= MLX4_FLAG_OLD_PORT_CMDS;
1573
1574 MLX4_GET(lg, outbox, QUERY_FW_MAX_CMD_OFFSET);
1575 cmd->max_cmds = 1 << lg;
1576
1577 mlx4_dbg(dev, "FW version %d.%d.%03d (cmd intf rev %d), max commands %d\n",
1578 (int) (dev->caps.fw_ver >> 32),
1579 (int) (dev->caps.fw_ver >> 16) & 0xffff,
1580 (int) dev->caps.fw_ver & 0xffff,
1581 cmd_if_rev, cmd->max_cmds);
1582
1583 MLX4_GET(fw->catas_offset, outbox, QUERY_FW_ERR_START_OFFSET);
1584 MLX4_GET(fw->catas_size, outbox, QUERY_FW_ERR_SIZE_OFFSET);
1585 MLX4_GET(fw->catas_bar, outbox, QUERY_FW_ERR_BAR_OFFSET);
1586 fw->catas_bar = (fw->catas_bar >> 6) * 2;
1587
1588 mlx4_dbg(dev, "Catastrophic error buffer at 0x%llx, size 0x%x, BAR %d\n",
1589 (unsigned long long) fw->catas_offset, fw->catas_size, fw->catas_bar);
1590
1591 MLX4_GET(fw->fw_pages, outbox, QUERY_FW_SIZE_OFFSET);
1592 MLX4_GET(fw->clr_int_base, outbox, QUERY_FW_CLR_INT_BASE_OFFSET);
1593 MLX4_GET(fw->clr_int_bar, outbox, QUERY_FW_CLR_INT_BAR_OFFSET);
1594 fw->clr_int_bar = (fw->clr_int_bar >> 6) * 2;
1595
1596 MLX4_GET(fw->comm_base, outbox, QUERY_FW_COMM_BASE_OFFSET);
1597 MLX4_GET(fw->comm_bar, outbox, QUERY_FW_COMM_BAR_OFFSET);
1598 fw->comm_bar = (fw->comm_bar >> 6) * 2;
1599 mlx4_dbg(dev, "Communication vector bar:%d offset:0x%llx\n",
1600 fw->comm_bar, fw->comm_base);
1601 mlx4_dbg(dev, "FW size %d KB\n", fw->fw_pages >> 2);
1602
1603 MLX4_GET(fw->clock_offset, outbox, QUERY_FW_CLOCK_OFFSET);
1604 MLX4_GET(fw->clock_bar, outbox, QUERY_FW_CLOCK_BAR);
1605 fw->clock_bar = (fw->clock_bar >> 6) * 2;
1606 mlx4_dbg(dev, "Internal clock bar:%d offset:0x%llx\n",
1607 fw->clock_bar, fw->clock_offset);
1608
1609 /*
1610 * Round up number of system pages needed in case
1611 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE.
1612 */
1613 fw->fw_pages =
1614 ALIGN(fw->fw_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >>
1615 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT);
1616
1617 mlx4_dbg(dev, "Clear int @ %llx, BAR %d\n",
1618 (unsigned long long) fw->clr_int_base, fw->clr_int_bar);
1619
1620 out:
1621 mlx4_free_cmd_mailbox(dev, mailbox);
1622 return err;
1623 }
1624
1625 int mlx4_QUERY_FW_wrapper(struct mlx4_dev *dev, int slave,
1626 struct mlx4_vhcr *vhcr,
1627 struct mlx4_cmd_mailbox *inbox,
1628 struct mlx4_cmd_mailbox *outbox,
1629 struct mlx4_cmd_info *cmd)
1630 {
1631 u8 *outbuf;
1632 int err;
1633
1634 outbuf = outbox->buf;
1635 err = mlx4_cmd_box(dev, 0, outbox->dma, 0, 0, MLX4_CMD_QUERY_FW,
1636 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1637 if (err)
1638 return err;
1639
1640 /* for slaves, set pci PPF ID to invalid and zero out everything
1641 * else except FW version */
1642 outbuf[0] = outbuf[1] = 0;
1643 memset(&outbuf[8], 0, QUERY_FW_OUT_SIZE - 8);
1644 outbuf[QUERY_FW_PPF_ID] = MLX4_INVALID_SLAVE_ID;
1645
1646 return 0;
1647 }
1648
1649 static void get_board_id(void *vsd, char *board_id)
1650 {
1651 int i;
1652
1653 #define VSD_OFFSET_SIG1 0x00
1654 #define VSD_OFFSET_SIG2 0xde
1655 #define VSD_OFFSET_MLX_BOARD_ID 0xd0
1656 #define VSD_OFFSET_TS_BOARD_ID 0x20
1657
1658 #define VSD_SIGNATURE_TOPSPIN 0x5ad
1659
1660 memset(board_id, 0, MLX4_BOARD_ID_LEN);
1661
1662 if (be16_to_cpup(vsd + VSD_OFFSET_SIG1) == VSD_SIGNATURE_TOPSPIN &&
1663 be16_to_cpup(vsd + VSD_OFFSET_SIG2) == VSD_SIGNATURE_TOPSPIN) {
1664 strlcpy(board_id, vsd + VSD_OFFSET_TS_BOARD_ID, MLX4_BOARD_ID_LEN);
1665 } else {
1666 /*
1667 * The board ID is a string but the firmware byte
1668 * swaps each 4-byte word before passing it back to
1669 * us. Therefore we need to swab it before printing.
1670 */
1671 u32 *bid_u32 = (u32 *)board_id;
1672
1673 for (i = 0; i < 4; ++i) {
1674 u32 *addr;
1675 u32 val;
1676
1677 addr = (u32 *) (vsd + VSD_OFFSET_MLX_BOARD_ID + i * 4);
1678 val = get_unaligned(addr);
1679 val = swab32(val);
1680 put_unaligned(val, &bid_u32[i]);
1681 }
1682 }
1683 }
1684
1685 int mlx4_QUERY_ADAPTER(struct mlx4_dev *dev, struct mlx4_adapter *adapter)
1686 {
1687 struct mlx4_cmd_mailbox *mailbox;
1688 u32 *outbox;
1689 int err;
1690
1691 #define QUERY_ADAPTER_OUT_SIZE 0x100
1692 #define QUERY_ADAPTER_INTA_PIN_OFFSET 0x10
1693 #define QUERY_ADAPTER_VSD_OFFSET 0x20
1694
1695 mailbox = mlx4_alloc_cmd_mailbox(dev);
1696 if (IS_ERR(mailbox))
1697 return PTR_ERR(mailbox);
1698 outbox = mailbox->buf;
1699
1700 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_ADAPTER,
1701 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1702 if (err)
1703 goto out;
1704
1705 MLX4_GET(adapter->inta_pin, outbox, QUERY_ADAPTER_INTA_PIN_OFFSET);
1706
1707 get_board_id(outbox + QUERY_ADAPTER_VSD_OFFSET / 4,
1708 adapter->board_id);
1709
1710 out:
1711 mlx4_free_cmd_mailbox(dev, mailbox);
1712 return err;
1713 }
1714
1715 int mlx4_INIT_HCA(struct mlx4_dev *dev, struct mlx4_init_hca_param *param)
1716 {
1717 struct mlx4_cmd_mailbox *mailbox;
1718 __be32 *inbox;
1719 int err;
1720 static const u8 a0_dmfs_hw_steering[] = {
1721 [MLX4_STEERING_DMFS_A0_DEFAULT] = 0,
1722 [MLX4_STEERING_DMFS_A0_DYNAMIC] = 1,
1723 [MLX4_STEERING_DMFS_A0_STATIC] = 2,
1724 [MLX4_STEERING_DMFS_A0_DISABLE] = 3
1725 };
1726
1727 #define INIT_HCA_IN_SIZE 0x200
1728 #define INIT_HCA_VERSION_OFFSET 0x000
1729 #define INIT_HCA_VERSION 2
1730 #define INIT_HCA_VXLAN_OFFSET 0x0c
1731 #define INIT_HCA_CACHELINE_SZ_OFFSET 0x0e
1732 #define INIT_HCA_FLAGS_OFFSET 0x014
1733 #define INIT_HCA_RECOVERABLE_ERROR_EVENT_OFFSET 0x018
1734 #define INIT_HCA_QPC_OFFSET 0x020
1735 #define INIT_HCA_QPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x10)
1736 #define INIT_HCA_LOG_QP_OFFSET (INIT_HCA_QPC_OFFSET + 0x17)
1737 #define INIT_HCA_SRQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x28)
1738 #define INIT_HCA_LOG_SRQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x2f)
1739 #define INIT_HCA_CQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x30)
1740 #define INIT_HCA_LOG_CQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x37)
1741 #define INIT_HCA_EQE_CQE_OFFSETS (INIT_HCA_QPC_OFFSET + 0x38)
1742 #define INIT_HCA_EQE_CQE_STRIDE_OFFSET (INIT_HCA_QPC_OFFSET + 0x3b)
1743 #define INIT_HCA_ALTC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x40)
1744 #define INIT_HCA_AUXC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x50)
1745 #define INIT_HCA_EQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x60)
1746 #define INIT_HCA_LOG_EQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x67)
1747 #define INIT_HCA_NUM_SYS_EQS_OFFSET (INIT_HCA_QPC_OFFSET + 0x6a)
1748 #define INIT_HCA_RDMARC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x70)
1749 #define INIT_HCA_LOG_RD_OFFSET (INIT_HCA_QPC_OFFSET + 0x77)
1750 #define INIT_HCA_MCAST_OFFSET 0x0c0
1751 #define INIT_HCA_MC_BASE_OFFSET (INIT_HCA_MCAST_OFFSET + 0x00)
1752 #define INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x12)
1753 #define INIT_HCA_LOG_MC_HASH_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x16)
1754 #define INIT_HCA_UC_STEERING_OFFSET (INIT_HCA_MCAST_OFFSET + 0x18)
1755 #define INIT_HCA_LOG_MC_TABLE_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x1b)
1756 #define INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN 0x6
1757 #define INIT_HCA_FS_PARAM_OFFSET 0x1d0
1758 #define INIT_HCA_FS_BASE_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x00)
1759 #define INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x12)
1760 #define INIT_HCA_FS_A0_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x18)
1761 #define INIT_HCA_FS_LOG_TABLE_SZ_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x1b)
1762 #define INIT_HCA_FS_ETH_BITS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x21)
1763 #define INIT_HCA_FS_ETH_NUM_ADDRS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x22)
1764 #define INIT_HCA_FS_IB_BITS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x25)
1765 #define INIT_HCA_FS_IB_NUM_ADDRS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x26)
1766 #define INIT_HCA_TPT_OFFSET 0x0f0
1767 #define INIT_HCA_DMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x00)
1768 #define INIT_HCA_TPT_MW_OFFSET (INIT_HCA_TPT_OFFSET + 0x08)
1769 #define INIT_HCA_LOG_MPT_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x0b)
1770 #define INIT_HCA_MTT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x10)
1771 #define INIT_HCA_CMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x18)
1772 #define INIT_HCA_UAR_OFFSET 0x120
1773 #define INIT_HCA_LOG_UAR_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0a)
1774 #define INIT_HCA_UAR_PAGE_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0b)
1775
1776 mailbox = mlx4_alloc_cmd_mailbox(dev);
1777 if (IS_ERR(mailbox))
1778 return PTR_ERR(mailbox);
1779 inbox = mailbox->buf;
1780
1781 *((u8 *) mailbox->buf + INIT_HCA_VERSION_OFFSET) = INIT_HCA_VERSION;
1782
1783 *((u8 *) mailbox->buf + INIT_HCA_CACHELINE_SZ_OFFSET) =
1784 (ilog2(cache_line_size()) - 4) << 5;
1785
1786 #if defined(__LITTLE_ENDIAN)
1787 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) &= ~cpu_to_be32(1 << 1);
1788 #elif defined(__BIG_ENDIAN)
1789 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 1);
1790 #else
1791 #error Host endianness not defined
1792 #endif
1793 /* Check port for UD address vector: */
1794 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1);
1795
1796 /* Enable IPoIB checksumming if we can: */
1797 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_IPOIB_CSUM)
1798 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 3);
1799
1800 /* Enable QoS support if module parameter set */
1801 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ETS_CFG && enable_qos)
1802 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 2);
1803
1804 /* enable counters */
1805 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS)
1806 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 4);
1807
1808 /* Enable RSS spread to fragmented IP packets when supported */
1809 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_RSS_IP_FRAG)
1810 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 13);
1811
1812 /* CX3 is capable of extending CQEs/EQEs from 32 to 64 bytes */
1813 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_64B_EQE) {
1814 *(inbox + INIT_HCA_EQE_CQE_OFFSETS / 4) |= cpu_to_be32(1 << 29);
1815 dev->caps.eqe_size = 64;
1816 dev->caps.eqe_factor = 1;
1817 } else {
1818 dev->caps.eqe_size = 32;
1819 dev->caps.eqe_factor = 0;
1820 }
1821
1822 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_64B_CQE) {
1823 *(inbox + INIT_HCA_EQE_CQE_OFFSETS / 4) |= cpu_to_be32(1 << 30);
1824 dev->caps.cqe_size = 64;
1825 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE;
1826 } else {
1827 dev->caps.cqe_size = 32;
1828 }
1829
1830 /* CX3 is capable of extending CQEs\EQEs to strides larger than 64B */
1831 if ((dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_EQE_STRIDE) &&
1832 (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_CQE_STRIDE)) {
1833 dev->caps.eqe_size = cache_line_size();
1834 dev->caps.cqe_size = cache_line_size();
1835 dev->caps.eqe_factor = 0;
1836 MLX4_PUT(inbox, (u8)((ilog2(dev->caps.eqe_size) - 5) << 4 |
1837 (ilog2(dev->caps.eqe_size) - 5)),
1838 INIT_HCA_EQE_CQE_STRIDE_OFFSET);
1839
1840 /* User still need to know to support CQE > 32B */
1841 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE;
1842 }
1843
1844 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RECOVERABLE_ERROR_EVENT)
1845 *(inbox + INIT_HCA_RECOVERABLE_ERROR_EVENT_OFFSET / 4) |= cpu_to_be32(1 << 31);
1846
1847 /* QPC/EEC/CQC/EQC/RDMARC attributes */
1848
1849 MLX4_PUT(inbox, param->qpc_base, INIT_HCA_QPC_BASE_OFFSET);
1850 MLX4_PUT(inbox, param->log_num_qps, INIT_HCA_LOG_QP_OFFSET);
1851 MLX4_PUT(inbox, param->srqc_base, INIT_HCA_SRQC_BASE_OFFSET);
1852 MLX4_PUT(inbox, param->log_num_srqs, INIT_HCA_LOG_SRQ_OFFSET);
1853 MLX4_PUT(inbox, param->cqc_base, INIT_HCA_CQC_BASE_OFFSET);
1854 MLX4_PUT(inbox, param->log_num_cqs, INIT_HCA_LOG_CQ_OFFSET);
1855 MLX4_PUT(inbox, param->altc_base, INIT_HCA_ALTC_BASE_OFFSET);
1856 MLX4_PUT(inbox, param->auxc_base, INIT_HCA_AUXC_BASE_OFFSET);
1857 MLX4_PUT(inbox, param->eqc_base, INIT_HCA_EQC_BASE_OFFSET);
1858 MLX4_PUT(inbox, param->log_num_eqs, INIT_HCA_LOG_EQ_OFFSET);
1859 MLX4_PUT(inbox, param->num_sys_eqs, INIT_HCA_NUM_SYS_EQS_OFFSET);
1860 MLX4_PUT(inbox, param->rdmarc_base, INIT_HCA_RDMARC_BASE_OFFSET);
1861 MLX4_PUT(inbox, param->log_rd_per_qp, INIT_HCA_LOG_RD_OFFSET);
1862
1863 /* steering attributes */
1864 if (dev->caps.steering_mode ==
1865 MLX4_STEERING_MODE_DEVICE_MANAGED) {
1866 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |=
1867 cpu_to_be32(1 <<
1868 INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN);
1869
1870 MLX4_PUT(inbox, param->mc_base, INIT_HCA_FS_BASE_OFFSET);
1871 MLX4_PUT(inbox, param->log_mc_entry_sz,
1872 INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET);
1873 MLX4_PUT(inbox, param->log_mc_table_sz,
1874 INIT_HCA_FS_LOG_TABLE_SZ_OFFSET);
1875 /* Enable Ethernet flow steering
1876 * with udp unicast and tcp unicast
1877 */
1878 if (dev->caps.dmfs_high_steer_mode !=
1879 MLX4_STEERING_DMFS_A0_STATIC)
1880 MLX4_PUT(inbox,
1881 (u8)(MLX4_FS_UDP_UC_EN | MLX4_FS_TCP_UC_EN),
1882 INIT_HCA_FS_ETH_BITS_OFFSET);
1883 MLX4_PUT(inbox, (u16) MLX4_FS_NUM_OF_L2_ADDR,
1884 INIT_HCA_FS_ETH_NUM_ADDRS_OFFSET);
1885 /* Enable IPoIB flow steering
1886 * with udp unicast and tcp unicast
1887 */
1888 MLX4_PUT(inbox, (u8) (MLX4_FS_UDP_UC_EN | MLX4_FS_TCP_UC_EN),
1889 INIT_HCA_FS_IB_BITS_OFFSET);
1890 MLX4_PUT(inbox, (u16) MLX4_FS_NUM_OF_L2_ADDR,
1891 INIT_HCA_FS_IB_NUM_ADDRS_OFFSET);
1892
1893 if (dev->caps.dmfs_high_steer_mode !=
1894 MLX4_STEERING_DMFS_A0_NOT_SUPPORTED)
1895 MLX4_PUT(inbox,
1896 ((u8)(a0_dmfs_hw_steering[dev->caps.dmfs_high_steer_mode]
1897 << 6)),
1898 INIT_HCA_FS_A0_OFFSET);
1899 } else {
1900 MLX4_PUT(inbox, param->mc_base, INIT_HCA_MC_BASE_OFFSET);
1901 MLX4_PUT(inbox, param->log_mc_entry_sz,
1902 INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET);
1903 MLX4_PUT(inbox, param->log_mc_hash_sz,
1904 INIT_HCA_LOG_MC_HASH_SZ_OFFSET);
1905 MLX4_PUT(inbox, param->log_mc_table_sz,
1906 INIT_HCA_LOG_MC_TABLE_SZ_OFFSET);
1907 if (dev->caps.steering_mode == MLX4_STEERING_MODE_B0)
1908 MLX4_PUT(inbox, (u8) (1 << 3),
1909 INIT_HCA_UC_STEERING_OFFSET);
1910 }
1911
1912 /* TPT attributes */
1913
1914 MLX4_PUT(inbox, param->dmpt_base, INIT_HCA_DMPT_BASE_OFFSET);
1915 MLX4_PUT(inbox, param->mw_enabled, INIT_HCA_TPT_MW_OFFSET);
1916 MLX4_PUT(inbox, param->log_mpt_sz, INIT_HCA_LOG_MPT_SZ_OFFSET);
1917 MLX4_PUT(inbox, param->mtt_base, INIT_HCA_MTT_BASE_OFFSET);
1918 MLX4_PUT(inbox, param->cmpt_base, INIT_HCA_CMPT_BASE_OFFSET);
1919
1920 /* UAR attributes */
1921
1922 MLX4_PUT(inbox, param->uar_page_sz, INIT_HCA_UAR_PAGE_SZ_OFFSET);
1923 MLX4_PUT(inbox, param->log_uar_sz, INIT_HCA_LOG_UAR_SZ_OFFSET);
1924
1925 /* set parser VXLAN attributes */
1926 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS) {
1927 u8 parser_params = 0;
1928 MLX4_PUT(inbox, parser_params, INIT_HCA_VXLAN_OFFSET);
1929 }
1930
1931 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_INIT_HCA,
1932 MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
1933
1934 if (err)
1935 mlx4_err(dev, "INIT_HCA returns %d\n", err);
1936
1937 mlx4_free_cmd_mailbox(dev, mailbox);
1938 return err;
1939 }
1940
1941 int mlx4_QUERY_HCA(struct mlx4_dev *dev,
1942 struct mlx4_init_hca_param *param)
1943 {
1944 struct mlx4_cmd_mailbox *mailbox;
1945 __be32 *outbox;
1946 u32 dword_field;
1947 int err;
1948 u8 byte_field;
1949 static const u8 a0_dmfs_query_hw_steering[] = {
1950 [0] = MLX4_STEERING_DMFS_A0_DEFAULT,
1951 [1] = MLX4_STEERING_DMFS_A0_DYNAMIC,
1952 [2] = MLX4_STEERING_DMFS_A0_STATIC,
1953 [3] = MLX4_STEERING_DMFS_A0_DISABLE
1954 };
1955
1956 #define QUERY_HCA_GLOBAL_CAPS_OFFSET 0x04
1957 #define QUERY_HCA_CORE_CLOCK_OFFSET 0x0c
1958
1959 mailbox = mlx4_alloc_cmd_mailbox(dev);
1960 if (IS_ERR(mailbox))
1961 return PTR_ERR(mailbox);
1962 outbox = mailbox->buf;
1963
1964 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0,
1965 MLX4_CMD_QUERY_HCA,
1966 MLX4_CMD_TIME_CLASS_B,
1967 !mlx4_is_slave(dev));
1968 if (err)
1969 goto out;
1970
1971 MLX4_GET(param->global_caps, outbox, QUERY_HCA_GLOBAL_CAPS_OFFSET);
1972 MLX4_GET(param->hca_core_clock, outbox, QUERY_HCA_CORE_CLOCK_OFFSET);
1973
1974 /* QPC/EEC/CQC/EQC/RDMARC attributes */
1975
1976 MLX4_GET(param->qpc_base, outbox, INIT_HCA_QPC_BASE_OFFSET);
1977 MLX4_GET(param->log_num_qps, outbox, INIT_HCA_LOG_QP_OFFSET);
1978 MLX4_GET(param->srqc_base, outbox, INIT_HCA_SRQC_BASE_OFFSET);
1979 MLX4_GET(param->log_num_srqs, outbox, INIT_HCA_LOG_SRQ_OFFSET);
1980 MLX4_GET(param->cqc_base, outbox, INIT_HCA_CQC_BASE_OFFSET);
1981 MLX4_GET(param->log_num_cqs, outbox, INIT_HCA_LOG_CQ_OFFSET);
1982 MLX4_GET(param->altc_base, outbox, INIT_HCA_ALTC_BASE_OFFSET);
1983 MLX4_GET(param->auxc_base, outbox, INIT_HCA_AUXC_BASE_OFFSET);
1984 MLX4_GET(param->eqc_base, outbox, INIT_HCA_EQC_BASE_OFFSET);
1985 MLX4_GET(param->log_num_eqs, outbox, INIT_HCA_LOG_EQ_OFFSET);
1986 MLX4_GET(param->num_sys_eqs, outbox, INIT_HCA_NUM_SYS_EQS_OFFSET);
1987 MLX4_GET(param->rdmarc_base, outbox, INIT_HCA_RDMARC_BASE_OFFSET);
1988 MLX4_GET(param->log_rd_per_qp, outbox, INIT_HCA_LOG_RD_OFFSET);
1989
1990 MLX4_GET(dword_field, outbox, INIT_HCA_FLAGS_OFFSET);
1991 if (dword_field & (1 << INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN)) {
1992 param->steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED;
1993 } else {
1994 MLX4_GET(byte_field, outbox, INIT_HCA_UC_STEERING_OFFSET);
1995 if (byte_field & 0x8)
1996 param->steering_mode = MLX4_STEERING_MODE_B0;
1997 else
1998 param->steering_mode = MLX4_STEERING_MODE_A0;
1999 }
2000
2001 if (dword_field & (1 << 13))
2002 param->rss_ip_frags = 1;
2003
2004 /* steering attributes */
2005 if (param->steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) {
2006 MLX4_GET(param->mc_base, outbox, INIT_HCA_FS_BASE_OFFSET);
2007 MLX4_GET(param->log_mc_entry_sz, outbox,
2008 INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET);
2009 MLX4_GET(param->log_mc_table_sz, outbox,
2010 INIT_HCA_FS_LOG_TABLE_SZ_OFFSET);
2011 MLX4_GET(byte_field, outbox,
2012 INIT_HCA_FS_A0_OFFSET);
2013 param->dmfs_high_steer_mode =
2014 a0_dmfs_query_hw_steering[(byte_field >> 6) & 3];
2015 } else {
2016 MLX4_GET(param->mc_base, outbox, INIT_HCA_MC_BASE_OFFSET);
2017 MLX4_GET(param->log_mc_entry_sz, outbox,
2018 INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET);
2019 MLX4_GET(param->log_mc_hash_sz, outbox,
2020 INIT_HCA_LOG_MC_HASH_SZ_OFFSET);
2021 MLX4_GET(param->log_mc_table_sz, outbox,
2022 INIT_HCA_LOG_MC_TABLE_SZ_OFFSET);
2023 }
2024
2025 /* CX3 is capable of extending CQEs/EQEs from 32 to 64 bytes */
2026 MLX4_GET(byte_field, outbox, INIT_HCA_EQE_CQE_OFFSETS);
2027 if (byte_field & 0x20) /* 64-bytes eqe enabled */
2028 param->dev_cap_enabled |= MLX4_DEV_CAP_64B_EQE_ENABLED;
2029 if (byte_field & 0x40) /* 64-bytes cqe enabled */
2030 param->dev_cap_enabled |= MLX4_DEV_CAP_64B_CQE_ENABLED;
2031
2032 /* CX3 is capable of extending CQEs\EQEs to strides larger than 64B */
2033 MLX4_GET(byte_field, outbox, INIT_HCA_EQE_CQE_STRIDE_OFFSET);
2034 if (byte_field) {
2035 param->dev_cap_enabled |= MLX4_DEV_CAP_EQE_STRIDE_ENABLED;
2036 param->dev_cap_enabled |= MLX4_DEV_CAP_CQE_STRIDE_ENABLED;
2037 param->cqe_size = 1 << ((byte_field &
2038 MLX4_CQE_SIZE_MASK_STRIDE) + 5);
2039 param->eqe_size = 1 << (((byte_field &
2040 MLX4_EQE_SIZE_MASK_STRIDE) >> 4) + 5);
2041 }
2042
2043 /* TPT attributes */
2044
2045 MLX4_GET(param->dmpt_base, outbox, INIT_HCA_DMPT_BASE_OFFSET);
2046 MLX4_GET(param->mw_enabled, outbox, INIT_HCA_TPT_MW_OFFSET);
2047 MLX4_GET(param->log_mpt_sz, outbox, INIT_HCA_LOG_MPT_SZ_OFFSET);
2048 MLX4_GET(param->mtt_base, outbox, INIT_HCA_MTT_BASE_OFFSET);
2049 MLX4_GET(param->cmpt_base, outbox, INIT_HCA_CMPT_BASE_OFFSET);
2050
2051 /* UAR attributes */
2052
2053 MLX4_GET(param->uar_page_sz, outbox, INIT_HCA_UAR_PAGE_SZ_OFFSET);
2054 MLX4_GET(param->log_uar_sz, outbox, INIT_HCA_LOG_UAR_SZ_OFFSET);
2055
2056 /* phv_check enable */
2057 MLX4_GET(byte_field, outbox, INIT_HCA_CACHELINE_SZ_OFFSET);
2058 if (byte_field & 0x2)
2059 param->phv_check_en = 1;
2060 out:
2061 mlx4_free_cmd_mailbox(dev, mailbox);
2062
2063 return err;
2064 }
2065
2066 static int mlx4_hca_core_clock_update(struct mlx4_dev *dev)
2067 {
2068 struct mlx4_cmd_mailbox *mailbox;
2069 __be32 *outbox;
2070 int err;
2071
2072 mailbox = mlx4_alloc_cmd_mailbox(dev);
2073 if (IS_ERR(mailbox)) {
2074 mlx4_warn(dev, "hca_core_clock mailbox allocation failed\n");
2075 return PTR_ERR(mailbox);
2076 }
2077 outbox = mailbox->buf;
2078
2079 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0,
2080 MLX4_CMD_QUERY_HCA,
2081 MLX4_CMD_TIME_CLASS_B,
2082 !mlx4_is_slave(dev));
2083 if (err) {
2084 mlx4_warn(dev, "hca_core_clock update failed\n");
2085 goto out;
2086 }
2087
2088 MLX4_GET(dev->caps.hca_core_clock, outbox, QUERY_HCA_CORE_CLOCK_OFFSET);
2089
2090 out:
2091 mlx4_free_cmd_mailbox(dev, mailbox);
2092
2093 return err;
2094 }
2095
2096 /* for IB-type ports only in SRIOV mode. Checks that both proxy QP0
2097 * and real QP0 are active, so that the paravirtualized QP0 is ready
2098 * to operate */
2099 static int check_qp0_state(struct mlx4_dev *dev, int function, int port)
2100 {
2101 struct mlx4_priv *priv = mlx4_priv(dev);
2102 /* irrelevant if not infiniband */
2103 if (priv->mfunc.master.qp0_state[port].proxy_qp0_active &&
2104 priv->mfunc.master.qp0_state[port].qp0_active)
2105 return 1;
2106 return 0;
2107 }
2108
2109 int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave,
2110 struct mlx4_vhcr *vhcr,
2111 struct mlx4_cmd_mailbox *inbox,
2112 struct mlx4_cmd_mailbox *outbox,
2113 struct mlx4_cmd_info *cmd)
2114 {
2115 struct mlx4_priv *priv = mlx4_priv(dev);
2116 int port = mlx4_slave_convert_port(dev, slave, vhcr->in_modifier);
2117 int err;
2118
2119 if (port < 0)
2120 return -EINVAL;
2121
2122 if (priv->mfunc.master.slave_state[slave].init_port_mask & (1 << port))
2123 return 0;
2124
2125 if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB) {
2126 /* Enable port only if it was previously disabled */
2127 if (!priv->mfunc.master.init_port_ref[port]) {
2128 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
2129 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
2130 if (err)
2131 return err;
2132 }
2133 priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port);
2134 } else {
2135 if (slave == mlx4_master_func_num(dev)) {
2136 if (check_qp0_state(dev, slave, port) &&
2137 !priv->mfunc.master.qp0_state[port].port_active) {
2138 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
2139 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
2140 if (err)
2141 return err;
2142 priv->mfunc.master.qp0_state[port].port_active = 1;
2143 priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port);
2144 }
2145 } else
2146 priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port);
2147 }
2148 ++priv->mfunc.master.init_port_ref[port];
2149 return 0;
2150 }
2151
2152 int mlx4_INIT_PORT(struct mlx4_dev *dev, int port)
2153 {
2154 struct mlx4_cmd_mailbox *mailbox;
2155 u32 *inbox;
2156 int err;
2157 u32 flags;
2158 u16 field;
2159
2160 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
2161 #define INIT_PORT_IN_SIZE 256
2162 #define INIT_PORT_FLAGS_OFFSET 0x00
2163 #define INIT_PORT_FLAG_SIG (1 << 18)
2164 #define INIT_PORT_FLAG_NG (1 << 17)
2165 #define INIT_PORT_FLAG_G0 (1 << 16)
2166 #define INIT_PORT_VL_SHIFT 4
2167 #define INIT_PORT_PORT_WIDTH_SHIFT 8
2168 #define INIT_PORT_MTU_OFFSET 0x04
2169 #define INIT_PORT_MAX_GID_OFFSET 0x06
2170 #define INIT_PORT_MAX_PKEY_OFFSET 0x0a
2171 #define INIT_PORT_GUID0_OFFSET 0x10
2172 #define INIT_PORT_NODE_GUID_OFFSET 0x18
2173 #define INIT_PORT_SI_GUID_OFFSET 0x20
2174
2175 mailbox = mlx4_alloc_cmd_mailbox(dev);
2176 if (IS_ERR(mailbox))
2177 return PTR_ERR(mailbox);
2178 inbox = mailbox->buf;
2179
2180 flags = 0;
2181 flags |= (dev->caps.vl_cap[port] & 0xf) << INIT_PORT_VL_SHIFT;
2182 flags |= (dev->caps.port_width_cap[port] & 0xf) << INIT_PORT_PORT_WIDTH_SHIFT;
2183 MLX4_PUT(inbox, flags, INIT_PORT_FLAGS_OFFSET);
2184
2185 field = 128 << dev->caps.ib_mtu_cap[port];
2186 MLX4_PUT(inbox, field, INIT_PORT_MTU_OFFSET);
2187 field = dev->caps.gid_table_len[port];
2188 MLX4_PUT(inbox, field, INIT_PORT_MAX_GID_OFFSET);
2189 field = dev->caps.pkey_table_len[port];
2190 MLX4_PUT(inbox, field, INIT_PORT_MAX_PKEY_OFFSET);
2191
2192 err = mlx4_cmd(dev, mailbox->dma, port, 0, MLX4_CMD_INIT_PORT,
2193 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
2194
2195 mlx4_free_cmd_mailbox(dev, mailbox);
2196 } else
2197 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
2198 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
2199
2200 if (!err)
2201 mlx4_hca_core_clock_update(dev);
2202
2203 return err;
2204 }
2205 EXPORT_SYMBOL_GPL(mlx4_INIT_PORT);
2206
2207 int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave,
2208 struct mlx4_vhcr *vhcr,
2209 struct mlx4_cmd_mailbox *inbox,
2210 struct mlx4_cmd_mailbox *outbox,
2211 struct mlx4_cmd_info *cmd)
2212 {
2213 struct mlx4_priv *priv = mlx4_priv(dev);
2214 int port = mlx4_slave_convert_port(dev, slave, vhcr->in_modifier);
2215 int err;
2216
2217 if (port < 0)
2218 return -EINVAL;
2219
2220 if (!(priv->mfunc.master.slave_state[slave].init_port_mask &
2221 (1 << port)))
2222 return 0;
2223
2224 if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB) {
2225 if (priv->mfunc.master.init_port_ref[port] == 1) {
2226 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT,
2227 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
2228 if (err)
2229 return err;
2230 }
2231 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port);
2232 } else {
2233 /* infiniband port */
2234 if (slave == mlx4_master_func_num(dev)) {
2235 if (!priv->mfunc.master.qp0_state[port].qp0_active &&
2236 priv->mfunc.master.qp0_state[port].port_active) {
2237 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT,
2238 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
2239 if (err)
2240 return err;
2241 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port);
2242 priv->mfunc.master.qp0_state[port].port_active = 0;
2243 }
2244 } else
2245 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port);
2246 }
2247 --priv->mfunc.master.init_port_ref[port];
2248 return 0;
2249 }
2250
2251 int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port)
2252 {
2253 return mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT,
2254 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
2255 }
2256 EXPORT_SYMBOL_GPL(mlx4_CLOSE_PORT);
2257
2258 int mlx4_CLOSE_HCA(struct mlx4_dev *dev, int panic)
2259 {
2260 return mlx4_cmd(dev, 0, 0, panic, MLX4_CMD_CLOSE_HCA,
2261 MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
2262 }
2263
2264 struct mlx4_config_dev {
2265 __be32 update_flags;
2266 __be32 rsvd1[3];
2267 __be16 vxlan_udp_dport;
2268 __be16 rsvd2;
2269 __be16 roce_v2_entropy;
2270 __be16 roce_v2_udp_dport;
2271 __be32 roce_flags;
2272 __be32 rsvd4[25];
2273 __be16 rsvd5;
2274 u8 rsvd6;
2275 u8 rx_checksum_val;
2276 };
2277
2278 #define MLX4_VXLAN_UDP_DPORT (1 << 0)
2279 #define MLX4_ROCE_V2_UDP_DPORT BIT(3)
2280 #define MLX4_DISABLE_RX_PORT BIT(18)
2281
2282 static int mlx4_CONFIG_DEV_set(struct mlx4_dev *dev, struct mlx4_config_dev *config_dev)
2283 {
2284 int err;
2285 struct mlx4_cmd_mailbox *mailbox;
2286
2287 mailbox = mlx4_alloc_cmd_mailbox(dev);
2288 if (IS_ERR(mailbox))
2289 return PTR_ERR(mailbox);
2290
2291 memcpy(mailbox->buf, config_dev, sizeof(*config_dev));
2292
2293 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_CONFIG_DEV,
2294 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
2295
2296 mlx4_free_cmd_mailbox(dev, mailbox);
2297 return err;
2298 }
2299
2300 static int mlx4_CONFIG_DEV_get(struct mlx4_dev *dev, struct mlx4_config_dev *config_dev)
2301 {
2302 int err;
2303 struct mlx4_cmd_mailbox *mailbox;
2304
2305 mailbox = mlx4_alloc_cmd_mailbox(dev);
2306 if (IS_ERR(mailbox))
2307 return PTR_ERR(mailbox);
2308
2309 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 1, MLX4_CMD_CONFIG_DEV,
2310 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
2311
2312 if (!err)
2313 memcpy(config_dev, mailbox->buf, sizeof(*config_dev));
2314
2315 mlx4_free_cmd_mailbox(dev, mailbox);
2316 return err;
2317 }
2318
2319 /* Conversion between the HW values and the actual functionality.
2320 * The value represented by the array index,
2321 * and the functionality determined by the flags.
2322 */
2323 static const u8 config_dev_csum_flags[] = {
2324 [0] = 0,
2325 [1] = MLX4_RX_CSUM_MODE_VAL_NON_TCP_UDP,
2326 [2] = MLX4_RX_CSUM_MODE_VAL_NON_TCP_UDP |
2327 MLX4_RX_CSUM_MODE_L4,
2328 [3] = MLX4_RX_CSUM_MODE_L4 |
2329 MLX4_RX_CSUM_MODE_IP_OK_IP_NON_TCP_UDP |
2330 MLX4_RX_CSUM_MODE_MULTI_VLAN
2331 };
2332
2333 int mlx4_config_dev_retrieval(struct mlx4_dev *dev,
2334 struct mlx4_config_dev_params *params)
2335 {
2336 struct mlx4_config_dev config_dev = {0};
2337 int err;
2338 u8 csum_mask;
2339
2340 #define CONFIG_DEV_RX_CSUM_MODE_MASK 0x7
2341 #define CONFIG_DEV_RX_CSUM_MODE_PORT1_BIT_OFFSET 0
2342 #define CONFIG_DEV_RX_CSUM_MODE_PORT2_BIT_OFFSET 4
2343
2344 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_CONFIG_DEV))
2345 return -ENOTSUPP;
2346
2347 err = mlx4_CONFIG_DEV_get(dev, &config_dev);
2348 if (err)
2349 return err;
2350
2351 csum_mask = (config_dev.rx_checksum_val >> CONFIG_DEV_RX_CSUM_MODE_PORT1_BIT_OFFSET) &
2352 CONFIG_DEV_RX_CSUM_MODE_MASK;
2353
2354 if (csum_mask >= sizeof(config_dev_csum_flags)/sizeof(config_dev_csum_flags[0]))
2355 return -EINVAL;
2356 params->rx_csum_flags_port_1 = config_dev_csum_flags[csum_mask];
2357
2358 csum_mask = (config_dev.rx_checksum_val >> CONFIG_DEV_RX_CSUM_MODE_PORT2_BIT_OFFSET) &
2359 CONFIG_DEV_RX_CSUM_MODE_MASK;
2360
2361 if (csum_mask >= sizeof(config_dev_csum_flags)/sizeof(config_dev_csum_flags[0]))
2362 return -EINVAL;
2363 params->rx_csum_flags_port_2 = config_dev_csum_flags[csum_mask];
2364
2365 params->vxlan_udp_dport = be16_to_cpu(config_dev.vxlan_udp_dport);
2366
2367 return 0;
2368 }
2369 EXPORT_SYMBOL_GPL(mlx4_config_dev_retrieval);
2370
2371 int mlx4_config_vxlan_port(struct mlx4_dev *dev, __be16 udp_port)
2372 {
2373 struct mlx4_config_dev config_dev;
2374
2375 memset(&config_dev, 0, sizeof(config_dev));
2376 config_dev.update_flags = cpu_to_be32(MLX4_VXLAN_UDP_DPORT);
2377 config_dev.vxlan_udp_dport = udp_port;
2378
2379 return mlx4_CONFIG_DEV_set(dev, &config_dev);
2380 }
2381 EXPORT_SYMBOL_GPL(mlx4_config_vxlan_port);
2382
2383 #define CONFIG_DISABLE_RX_PORT BIT(15)
2384 int mlx4_disable_rx_port_check(struct mlx4_dev *dev, bool dis)
2385 {
2386 struct mlx4_config_dev config_dev;
2387
2388 memset(&config_dev, 0, sizeof(config_dev));
2389 config_dev.update_flags = cpu_to_be32(MLX4_DISABLE_RX_PORT);
2390 if (dis)
2391 config_dev.roce_flags =
2392 cpu_to_be32(CONFIG_DISABLE_RX_PORT);
2393
2394 return mlx4_CONFIG_DEV_set(dev, &config_dev);
2395 }
2396
2397 int mlx4_config_roce_v2_port(struct mlx4_dev *dev, u16 udp_port)
2398 {
2399 struct mlx4_config_dev config_dev;
2400
2401 memset(&config_dev, 0, sizeof(config_dev));
2402 config_dev.update_flags = cpu_to_be32(MLX4_ROCE_V2_UDP_DPORT);
2403 config_dev.roce_v2_udp_dport = cpu_to_be16(udp_port);
2404
2405 return mlx4_CONFIG_DEV_set(dev, &config_dev);
2406 }
2407 EXPORT_SYMBOL_GPL(mlx4_config_roce_v2_port);
2408
2409 int mlx4_virt2phy_port_map(struct mlx4_dev *dev, u32 port1, u32 port2)
2410 {
2411 struct mlx4_cmd_mailbox *mailbox;
2412 struct {
2413 __be32 v_port1;
2414 __be32 v_port2;
2415 } *v2p;
2416 int err;
2417
2418 mailbox = mlx4_alloc_cmd_mailbox(dev);
2419 if (IS_ERR(mailbox))
2420 return -ENOMEM;
2421
2422 v2p = mailbox->buf;
2423 v2p->v_port1 = cpu_to_be32(port1);
2424 v2p->v_port2 = cpu_to_be32(port2);
2425
2426 err = mlx4_cmd(dev, mailbox->dma, 0,
2427 MLX4_SET_PORT_VIRT2PHY, MLX4_CMD_VIRT_PORT_MAP,
2428 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
2429
2430 mlx4_free_cmd_mailbox(dev, mailbox);
2431 return err;
2432 }
2433
2434
2435 int mlx4_SET_ICM_SIZE(struct mlx4_dev *dev, u64 icm_size, u64 *aux_pages)
2436 {
2437 int ret = mlx4_cmd_imm(dev, icm_size, aux_pages, 0, 0,
2438 MLX4_CMD_SET_ICM_SIZE,
2439 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
2440 if (ret)
2441 return ret;
2442
2443 /*
2444 * Round up number of system pages needed in case
2445 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE.
2446 */
2447 *aux_pages = ALIGN(*aux_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >>
2448 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT);
2449
2450 return 0;
2451 }
2452
2453 int mlx4_NOP(struct mlx4_dev *dev)
2454 {
2455 /* Input modifier of 0x1f means "finish as soon as possible." */
2456 return mlx4_cmd(dev, 0, 0x1f, 0, MLX4_CMD_NOP, MLX4_CMD_TIME_CLASS_A,
2457 MLX4_CMD_NATIVE);
2458 }
2459
2460 int mlx4_get_phys_port_id(struct mlx4_dev *dev)
2461 {
2462 u8 port;
2463 u32 *outbox;
2464 struct mlx4_cmd_mailbox *mailbox;
2465 u32 in_mod;
2466 u32 guid_hi, guid_lo;
2467 int err, ret = 0;
2468 #define MOD_STAT_CFG_PORT_OFFSET 8
2469 #define MOD_STAT_CFG_GUID_H 0X14
2470 #define MOD_STAT_CFG_GUID_L 0X1c
2471
2472 mailbox = mlx4_alloc_cmd_mailbox(dev);
2473 if (IS_ERR(mailbox))
2474 return PTR_ERR(mailbox);
2475 outbox = mailbox->buf;
2476
2477 for (port = 1; port <= dev->caps.num_ports; port++) {
2478 in_mod = port << MOD_STAT_CFG_PORT_OFFSET;
2479 err = mlx4_cmd_box(dev, 0, mailbox->dma, in_mod, 0x2,
2480 MLX4_CMD_MOD_STAT_CFG, MLX4_CMD_TIME_CLASS_A,
2481 MLX4_CMD_NATIVE);
2482 if (err) {
2483 mlx4_err(dev, "Fail to get port %d uplink guid\n",
2484 port);
2485 ret = err;
2486 } else {
2487 MLX4_GET(guid_hi, outbox, MOD_STAT_CFG_GUID_H);
2488 MLX4_GET(guid_lo, outbox, MOD_STAT_CFG_GUID_L);
2489 dev->caps.phys_port_id[port] = (u64)guid_lo |
2490 (u64)guid_hi << 32;
2491 }
2492 }
2493 mlx4_free_cmd_mailbox(dev, mailbox);
2494 return ret;
2495 }
2496
2497 #define MLX4_WOL_SETUP_MODE (5 << 28)
2498 int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port)
2499 {
2500 u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8;
2501
2502 return mlx4_cmd_imm(dev, 0, config, in_mod, 0x3,
2503 MLX4_CMD_MOD_STAT_CFG, MLX4_CMD_TIME_CLASS_A,
2504 MLX4_CMD_NATIVE);
2505 }
2506 EXPORT_SYMBOL_GPL(mlx4_wol_read);
2507
2508 int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port)
2509 {
2510 u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8;
2511
2512 return mlx4_cmd(dev, config, in_mod, 0x1, MLX4_CMD_MOD_STAT_CFG,
2513 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
2514 }
2515 EXPORT_SYMBOL_GPL(mlx4_wol_write);
2516
2517 enum {
2518 ADD_TO_MCG = 0x26,
2519 };
2520
2521
2522 void mlx4_opreq_action(struct work_struct *work)
2523 {
2524 struct mlx4_priv *priv = container_of(work, struct mlx4_priv,
2525 opreq_task);
2526 struct mlx4_dev *dev = &priv->dev;
2527 int num_tasks = atomic_read(&priv->opreq_count);
2528 struct mlx4_cmd_mailbox *mailbox;
2529 struct mlx4_mgm *mgm;
2530 u32 *outbox;
2531 u32 modifier;
2532 u16 token;
2533 u16 type;
2534 int err;
2535 u32 num_qps;
2536 struct mlx4_qp qp;
2537 int i;
2538 u8 rem_mcg;
2539 u8 prot;
2540
2541 #define GET_OP_REQ_MODIFIER_OFFSET 0x08
2542 #define GET_OP_REQ_TOKEN_OFFSET 0x14
2543 #define GET_OP_REQ_TYPE_OFFSET 0x1a
2544 #define GET_OP_REQ_DATA_OFFSET 0x20
2545
2546 mailbox = mlx4_alloc_cmd_mailbox(dev);
2547 if (IS_ERR(mailbox)) {
2548 mlx4_err(dev, "Failed to allocate mailbox for GET_OP_REQ\n");
2549 return;
2550 }
2551 outbox = mailbox->buf;
2552
2553 while (num_tasks) {
2554 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0,
2555 MLX4_CMD_GET_OP_REQ, MLX4_CMD_TIME_CLASS_A,
2556 MLX4_CMD_NATIVE);
2557 if (err) {
2558 mlx4_err(dev, "Failed to retrieve required operation: %d\n",
2559 err);
2560 return;
2561 }
2562 MLX4_GET(modifier, outbox, GET_OP_REQ_MODIFIER_OFFSET);
2563 MLX4_GET(token, outbox, GET_OP_REQ_TOKEN_OFFSET);
2564 MLX4_GET(type, outbox, GET_OP_REQ_TYPE_OFFSET);
2565 type &= 0xfff;
2566
2567 switch (type) {
2568 case ADD_TO_MCG:
2569 if (dev->caps.steering_mode ==
2570 MLX4_STEERING_MODE_DEVICE_MANAGED) {
2571 mlx4_warn(dev, "ADD MCG operation is not supported in DEVICE_MANAGED steering mode\n");
2572 err = EPERM;
2573 break;
2574 }
2575 mgm = (struct mlx4_mgm *)((u8 *)(outbox) +
2576 GET_OP_REQ_DATA_OFFSET);
2577 num_qps = be32_to_cpu(mgm->members_count) &
2578 MGM_QPN_MASK;
2579 rem_mcg = ((u8 *)(&mgm->members_count))[0] & 1;
2580 prot = ((u8 *)(&mgm->members_count))[0] >> 6;
2581
2582 for (i = 0; i < num_qps; i++) {
2583 qp.qpn = be32_to_cpu(mgm->qp[i]);
2584 if (rem_mcg)
2585 err = mlx4_multicast_detach(dev, &qp,
2586 mgm->gid,
2587 prot, 0);
2588 else
2589 err = mlx4_multicast_attach(dev, &qp,
2590 mgm->gid,
2591 mgm->gid[5]
2592 , 0, prot,
2593 NULL);
2594 if (err)
2595 break;
2596 }
2597 break;
2598 default:
2599 mlx4_warn(dev, "Bad type for required operation\n");
2600 err = EINVAL;
2601 break;
2602 }
2603 err = mlx4_cmd(dev, 0, ((u32) err |
2604 (__force u32)cpu_to_be32(token) << 16),
2605 1, MLX4_CMD_GET_OP_REQ, MLX4_CMD_TIME_CLASS_A,
2606 MLX4_CMD_NATIVE);
2607 if (err) {
2608 mlx4_err(dev, "Failed to acknowledge required request: %d\n",
2609 err);
2610 goto out;
2611 }
2612 memset(outbox, 0, 0xffc);
2613 num_tasks = atomic_dec_return(&priv->opreq_count);
2614 }
2615
2616 out:
2617 mlx4_free_cmd_mailbox(dev, mailbox);
2618 }
2619
2620 static int mlx4_check_smp_firewall_active(struct mlx4_dev *dev,
2621 struct mlx4_cmd_mailbox *mailbox)
2622 {
2623 #define MLX4_CMD_MAD_DEMUX_SET_ATTR_OFFSET 0x10
2624 #define MLX4_CMD_MAD_DEMUX_GETRESP_ATTR_OFFSET 0x20
2625 #define MLX4_CMD_MAD_DEMUX_TRAP_ATTR_OFFSET 0x40
2626 #define MLX4_CMD_MAD_DEMUX_TRAP_REPRESS_ATTR_OFFSET 0x70
2627
2628 u32 set_attr_mask, getresp_attr_mask;
2629 u32 trap_attr_mask, traprepress_attr_mask;
2630
2631 MLX4_GET(set_attr_mask, mailbox->buf,
2632 MLX4_CMD_MAD_DEMUX_SET_ATTR_OFFSET);
2633 mlx4_dbg(dev, "SMP firewall set_attribute_mask = 0x%x\n",
2634 set_attr_mask);
2635
2636 MLX4_GET(getresp_attr_mask, mailbox->buf,
2637 MLX4_CMD_MAD_DEMUX_GETRESP_ATTR_OFFSET);
2638 mlx4_dbg(dev, "SMP firewall getresp_attribute_mask = 0x%x\n",
2639 getresp_attr_mask);
2640
2641 MLX4_GET(trap_attr_mask, mailbox->buf,
2642 MLX4_CMD_MAD_DEMUX_TRAP_ATTR_OFFSET);
2643 mlx4_dbg(dev, "SMP firewall trap_attribute_mask = 0x%x\n",
2644 trap_attr_mask);
2645
2646 MLX4_GET(traprepress_attr_mask, mailbox->buf,
2647 MLX4_CMD_MAD_DEMUX_TRAP_REPRESS_ATTR_OFFSET);
2648 mlx4_dbg(dev, "SMP firewall traprepress_attribute_mask = 0x%x\n",
2649 traprepress_attr_mask);
2650
2651 if (set_attr_mask && getresp_attr_mask && trap_attr_mask &&
2652 traprepress_attr_mask)
2653 return 1;
2654
2655 return 0;
2656 }
2657
2658 int mlx4_config_mad_demux(struct mlx4_dev *dev)
2659 {
2660 struct mlx4_cmd_mailbox *mailbox;
2661 int secure_host_active;
2662 int err;
2663
2664 /* Check if mad_demux is supported */
2665 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_MAD_DEMUX))
2666 return 0;
2667
2668 mailbox = mlx4_alloc_cmd_mailbox(dev);
2669 if (IS_ERR(mailbox)) {
2670 mlx4_warn(dev, "Failed to allocate mailbox for cmd MAD_DEMUX");
2671 return -ENOMEM;
2672 }
2673
2674 /* Query mad_demux to find out which MADs are handled by internal sma */
2675 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0x01 /* subn mgmt class */,
2676 MLX4_CMD_MAD_DEMUX_QUERY_RESTR, MLX4_CMD_MAD_DEMUX,
2677 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
2678 if (err) {
2679 mlx4_warn(dev, "MLX4_CMD_MAD_DEMUX: query restrictions failed (%d)\n",
2680 err);
2681 goto out;
2682 }
2683
2684 secure_host_active = mlx4_check_smp_firewall_active(dev, mailbox);
2685
2686 /* Config mad_demux to handle all MADs returned by the query above */
2687 err = mlx4_cmd(dev, mailbox->dma, 0x01 /* subn mgmt class */,
2688 MLX4_CMD_MAD_DEMUX_CONFIG, MLX4_CMD_MAD_DEMUX,
2689 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
2690 if (err) {
2691 mlx4_warn(dev, "MLX4_CMD_MAD_DEMUX: configure failed (%d)\n", err);
2692 goto out;
2693 }
2694
2695 if (secure_host_active)
2696 mlx4_warn(dev, "HCA operating in secure-host mode. SMP firewall activated.\n");
2697 out:
2698 mlx4_free_cmd_mailbox(dev, mailbox);
2699 return err;
2700 }
2701
2702 /* Access Reg commands */
2703 enum mlx4_access_reg_masks {
2704 MLX4_ACCESS_REG_STATUS_MASK = 0x7f,
2705 MLX4_ACCESS_REG_METHOD_MASK = 0x7f,
2706 MLX4_ACCESS_REG_LEN_MASK = 0x7ff
2707 };
2708
2709 struct mlx4_access_reg {
2710 __be16 constant1;
2711 u8 status;
2712 u8 resrvd1;
2713 __be16 reg_id;
2714 u8 method;
2715 u8 constant2;
2716 __be32 resrvd2[2];
2717 __be16 len_const;
2718 __be16 resrvd3;
2719 #define MLX4_ACCESS_REG_HEADER_SIZE (20)
2720 u8 reg_data[MLX4_MAILBOX_SIZE-MLX4_ACCESS_REG_HEADER_SIZE];
2721 } __attribute__((__packed__));
2722
2723 /**
2724 * mlx4_ACCESS_REG - Generic access reg command.
2725 * @dev: mlx4_dev.
2726 * @reg_id: register ID to access.
2727 * @method: Access method Read/Write.
2728 * @reg_len: register length to Read/Write in bytes.
2729 * @reg_data: reg_data pointer to Read/Write From/To.
2730 *
2731 * Access ConnectX registers FW command.
2732 * Returns 0 on success and copies outbox mlx4_access_reg data
2733 * field into reg_data or a negative error code.
2734 */
2735 static int mlx4_ACCESS_REG(struct mlx4_dev *dev, u16 reg_id,
2736 enum mlx4_access_reg_method method,
2737 u16 reg_len, void *reg_data)
2738 {
2739 struct mlx4_cmd_mailbox *inbox, *outbox;
2740 struct mlx4_access_reg *inbuf, *outbuf;
2741 int err;
2742
2743 inbox = mlx4_alloc_cmd_mailbox(dev);
2744 if (IS_ERR(inbox))
2745 return PTR_ERR(inbox);
2746
2747 outbox = mlx4_alloc_cmd_mailbox(dev);
2748 if (IS_ERR(outbox)) {
2749 mlx4_free_cmd_mailbox(dev, inbox);
2750 return PTR_ERR(outbox);
2751 }
2752
2753 inbuf = inbox->buf;
2754 outbuf = outbox->buf;
2755
2756 inbuf->constant1 = cpu_to_be16(0x1<<11 | 0x4);
2757 inbuf->constant2 = 0x1;
2758 inbuf->reg_id = cpu_to_be16(reg_id);
2759 inbuf->method = method & MLX4_ACCESS_REG_METHOD_MASK;
2760
2761 reg_len = min(reg_len, (u16)(sizeof(inbuf->reg_data)));
2762 inbuf->len_const =
2763 cpu_to_be16(((reg_len/4 + 1) & MLX4_ACCESS_REG_LEN_MASK) |
2764 ((0x3) << 12));
2765
2766 memcpy(inbuf->reg_data, reg_data, reg_len);
2767 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma, 0, 0,
2768 MLX4_CMD_ACCESS_REG, MLX4_CMD_TIME_CLASS_C,
2769 MLX4_CMD_WRAPPED);
2770 if (err)
2771 goto out;
2772
2773 if (outbuf->status & MLX4_ACCESS_REG_STATUS_MASK) {
2774 err = outbuf->status & MLX4_ACCESS_REG_STATUS_MASK;
2775 mlx4_err(dev,
2776 "MLX4_CMD_ACCESS_REG(%x) returned REG status (%x)\n",
2777 reg_id, err);
2778 goto out;
2779 }
2780
2781 memcpy(reg_data, outbuf->reg_data, reg_len);
2782 out:
2783 mlx4_free_cmd_mailbox(dev, inbox);
2784 mlx4_free_cmd_mailbox(dev, outbox);
2785 return err;
2786 }
2787
2788 /* ConnectX registers IDs */
2789 enum mlx4_reg_id {
2790 MLX4_REG_ID_PTYS = 0x5004,
2791 };
2792
2793 /**
2794 * mlx4_ACCESS_PTYS_REG - Access PTYs (Port Type and Speed)
2795 * register
2796 * @dev: mlx4_dev.
2797 * @method: Access method Read/Write.
2798 * @ptys_reg: PTYS register data pointer.
2799 *
2800 * Access ConnectX PTYS register, to Read/Write Port Type/Speed
2801 * configuration
2802 * Returns 0 on success or a negative error code.
2803 */
2804 int mlx4_ACCESS_PTYS_REG(struct mlx4_dev *dev,
2805 enum mlx4_access_reg_method method,
2806 struct mlx4_ptys_reg *ptys_reg)
2807 {
2808 return mlx4_ACCESS_REG(dev, MLX4_REG_ID_PTYS,
2809 method, sizeof(*ptys_reg), ptys_reg);
2810 }
2811 EXPORT_SYMBOL_GPL(mlx4_ACCESS_PTYS_REG);
2812
2813 int mlx4_ACCESS_REG_wrapper(struct mlx4_dev *dev, int slave,
2814 struct mlx4_vhcr *vhcr,
2815 struct mlx4_cmd_mailbox *inbox,
2816 struct mlx4_cmd_mailbox *outbox,
2817 struct mlx4_cmd_info *cmd)
2818 {
2819 struct mlx4_access_reg *inbuf = inbox->buf;
2820 u8 method = inbuf->method & MLX4_ACCESS_REG_METHOD_MASK;
2821 u16 reg_id = be16_to_cpu(inbuf->reg_id);
2822
2823 if (slave != mlx4_master_func_num(dev) &&
2824 method == MLX4_ACCESS_REG_WRITE)
2825 return -EPERM;
2826
2827 if (reg_id == MLX4_REG_ID_PTYS) {
2828 struct mlx4_ptys_reg *ptys_reg =
2829 (struct mlx4_ptys_reg *)inbuf->reg_data;
2830
2831 ptys_reg->local_port =
2832 mlx4_slave_convert_port(dev, slave,
2833 ptys_reg->local_port);
2834 }
2835
2836 return mlx4_cmd_box(dev, inbox->dma, outbox->dma, vhcr->in_modifier,
2837 0, MLX4_CMD_ACCESS_REG, MLX4_CMD_TIME_CLASS_C,
2838 MLX4_CMD_NATIVE);
2839 }
2840
2841 static int mlx4_SET_PORT_phv_bit(struct mlx4_dev *dev, u8 port, u8 phv_bit)
2842 {
2843 #define SET_PORT_GEN_PHV_VALID 0x10
2844 #define SET_PORT_GEN_PHV_EN 0x80
2845
2846 struct mlx4_cmd_mailbox *mailbox;
2847 struct mlx4_set_port_general_context *context;
2848 u32 in_mod;
2849 int err;
2850
2851 mailbox = mlx4_alloc_cmd_mailbox(dev);
2852 if (IS_ERR(mailbox))
2853 return PTR_ERR(mailbox);
2854 context = mailbox->buf;
2855
2856 context->v_ignore_fcs |= SET_PORT_GEN_PHV_VALID;
2857 if (phv_bit)
2858 context->phv_en |= SET_PORT_GEN_PHV_EN;
2859
2860 in_mod = MLX4_SET_PORT_GENERAL << 8 | port;
2861 err = mlx4_cmd(dev, mailbox->dma, in_mod, MLX4_SET_PORT_ETH_OPCODE,
2862 MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B,
2863 MLX4_CMD_NATIVE);
2864
2865 mlx4_free_cmd_mailbox(dev, mailbox);
2866 return err;
2867 }
2868
2869 int get_phv_bit(struct mlx4_dev *dev, u8 port, int *phv)
2870 {
2871 int err;
2872 struct mlx4_func_cap func_cap;
2873
2874 memset(&func_cap, 0, sizeof(func_cap));
2875 err = mlx4_QUERY_FUNC_CAP(dev, port, &func_cap);
2876 if (!err)
2877 *phv = func_cap.flags & QUERY_FUNC_CAP_PHV_BIT;
2878 return err;
2879 }
2880 EXPORT_SYMBOL(get_phv_bit);
2881
2882 int set_phv_bit(struct mlx4_dev *dev, u8 port, int new_val)
2883 {
2884 int ret;
2885
2886 if (mlx4_is_slave(dev))
2887 return -EPERM;
2888
2889 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_PHV_EN &&
2890 !(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SKIP_OUTER_VLAN)) {
2891 ret = mlx4_SET_PORT_phv_bit(dev, port, new_val);
2892 if (!ret)
2893 dev->caps.phv_bit[port] = new_val;
2894 return ret;
2895 }
2896
2897 return -EOPNOTSUPP;
2898 }
2899 EXPORT_SYMBOL(set_phv_bit);
2900
2901 void mlx4_replace_zero_macs(struct mlx4_dev *dev)
2902 {
2903 int i;
2904 u8 mac_addr[ETH_ALEN];
2905
2906 dev->port_random_macs = 0;
2907 for (i = 1; i <= dev->caps.num_ports; ++i)
2908 if (!dev->caps.def_mac[i] &&
2909 dev->caps.port_type[i] == MLX4_PORT_TYPE_ETH) {
2910 eth_random_addr(mac_addr);
2911 dev->port_random_macs |= 1 << i;
2912 dev->caps.def_mac[i] = mlx4_mac_to_u64(mac_addr);
2913 }
2914 }
2915 EXPORT_SYMBOL_GPL(mlx4_replace_zero_macs);
Linux kernel - Deliverables
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