drivers/net/ethernet/mellanox/mlx4/fw.h

   1 /*
   2  * Copyright (c) 2004, 2005 Topspin Communications.  All rights reserved.
   3  * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
   4  * Copyright (c) 2006, 2007 Cisco Systems.  All rights reserved.
   5  *
   6  * This software is available to you under a choice of one of two
   7  * licenses.  You may choose to be licensed under the terms of the GNU
   8  * General Public License (GPL) Version 2, available from the file
   9  * COPYING in the main directory of this source tree, or the
  10  * OpenIB.org BSD license below:
  11  *
  12  *     Redistribution and use in source and binary forms, with or
  13  *     without modification, are permitted provided that the following
  14  *     conditions are met:
  15  *
  16  *      - Redistributions of source code must retain the above
  17  *        copyright notice, this list of conditions and the following
  18  *        disclaimer.
  19  *
  20  *      - Redistributions in binary form must reproduce the above
  21  *        copyright notice, this list of conditions and the following
  22  *        disclaimer in the documentation and/or other materials
  23  *        provided with the distribution.
  24  *
  25  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  26  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  27  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  28  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  29  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  30  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  31  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  32  * SOFTWARE.
  33  */
  34
  35 #ifndef MLX4_FW_H
  36 #define MLX4_FW_H
  37
  38 #include "mlx4.h"
  39 #include "icm.h"
  40
  41 struct mlx4_mod_stat_cfg {
  42         u8 log_pg_sz;
  43         u8 log_pg_sz_m;
  44 };
  45
  46 struct mlx4_dev_cap {
  47         int max_srq_sz;
  48         int max_qp_sz;
  49         int reserved_qps;
  50         int max_qps;
  51         int reserved_srqs;
  52         int max_srqs;
  53         int max_cq_sz;
  54         int reserved_cqs;
  55         int max_cqs;
  56         int max_mpts;
  57         int reserved_eqs;
  58         int max_eqs;
  59         int reserved_mtts;
  60         int max_mrw_sz;
  61         int reserved_mrws;
  62         int max_mtt_seg;
  63         int max_requester_per_qp;
  64         int max_responder_per_qp;
  65         int max_rdma_global;
  66         int local_ca_ack_delay;
  67         int num_ports;
  68         u32 max_msg_sz;
  69         int ib_mtu[MLX4_MAX_PORTS + 1];
  70         int max_port_width[MLX4_MAX_PORTS + 1];
  71         int max_vl[MLX4_MAX_PORTS + 1];
  72         int max_gids[MLX4_MAX_PORTS + 1];
  73         int max_pkeys[MLX4_MAX_PORTS + 1];
  74         u64 def_mac[MLX4_MAX_PORTS + 1];
  75         u16 eth_mtu[MLX4_MAX_PORTS + 1];
  76         int trans_type[MLX4_MAX_PORTS + 1];
  77         int vendor_oui[MLX4_MAX_PORTS + 1];
  78         u16 wavelength[MLX4_MAX_PORTS + 1];
  79         u64 trans_code[MLX4_MAX_PORTS + 1];
  80         u16 stat_rate_support;
  81         int fs_log_max_ucast_qp_range_size;
  82         int fs_max_num_qp_per_entry;
  83         u64 flags;
  84         u64 flags2;
  85         int reserved_uars;
  86         int uar_size;
  87         int min_page_sz;
  88         int bf_reg_size;
  89         int bf_regs_per_page;
  90         int max_sq_sg;
  91         int max_sq_desc_sz;
  92         int max_rq_sg;
  93         int max_rq_desc_sz;
  94         int max_qp_per_mcg;
  95         int reserved_mgms;
  96         int max_mcgs;
  97         int reserved_pds;
  98         int max_pds;
  99         int reserved_xrcds;
 100         int max_xrcds;
 101         int qpc_entry_sz;
 102         int rdmarc_entry_sz;
 103         int altc_entry_sz;
 104         int aux_entry_sz;
 105         int srq_entry_sz;
 106         int cqc_entry_sz;
 107         int eqc_entry_sz;
 108         int dmpt_entry_sz;
 109         int cmpt_entry_sz;
 110         int mtt_entry_sz;
 111         int resize_srq;
 112         u32 bmme_flags;
 113         u32 reserved_lkey;
 114         u64 max_icm_sz;
 115         int max_gso_sz;
 116         int max_rss_tbl_sz;
 117         u8  supported_port_types[MLX4_MAX_PORTS + 1];
 118         u8  suggested_type[MLX4_MAX_PORTS + 1];
 119         u8  default_sense[MLX4_MAX_PORTS + 1];
 120         u8  log_max_macs[MLX4_MAX_PORTS + 1];
 121         u8  log_max_vlans[MLX4_MAX_PORTS + 1];
 122         u32 max_counters;
 123 };
 124
 125 struct mlx4_func_cap {
 126         u8      num_ports;
 127         u8      flags;
 128         u32     pf_context_behaviour;
 129         int     qp_quota;
 130         int     cq_quota;
 131         int     srq_quota;
 132         int     mpt_quota;
 133         int     mtt_quota;
 134         int     max_eq;
 135         int     reserved_eq;
 136         int     mcg_quota;
 137         u32     qp0_qkey;
 138         u32     qp0_tunnel_qpn;
 139         u32     qp0_proxy_qpn;
 140         u32     qp1_tunnel_qpn;
 141         u32     qp1_proxy_qpn;
 142         u8      physical_port;
 143         u8      port_flags;
 144         u8      flags1;
 145         u64     phys_port_id;
 146 };
 147
 148 struct mlx4_adapter {
 149         char board_id[MLX4_BOARD_ID_LEN];
 150         u8   inta_pin;
 151 };
 152
 153 struct mlx4_init_hca_param {
 154         u64 qpc_base;
 155         u64 rdmarc_base;
 156         u64 auxc_base;
 157         u64 altc_base;
 158         u64 srqc_base;
 159         u64 cqc_base;
 160         u64 eqc_base;
 161         u64 mc_base;
 162         u64 dmpt_base;
 163         u64 cmpt_base;
 164         u64 mtt_base;
 165         u64 global_caps;
 166         u16 log_mc_entry_sz;
 167         u16 log_mc_hash_sz;
 168         u16 hca_core_clock; /* Internal Clock Frequency (in MHz) */
 169         u8  log_num_qps;
 170         u8  log_num_srqs;
 171         u8  log_num_cqs;
 172         u8  log_num_eqs;
 173         u8  log_rd_per_qp;
 174         u8  log_mc_table_sz;
 175         u8  log_mpt_sz;
 176         u8  log_uar_sz;
 177         u8  mw_enabled;  /* Enable memory windows */
 178         u8  uar_page_sz; /* log pg sz in 4k chunks */
 179         u8  steering_mode; /* for QUERY_HCA */
 180         u64 dev_cap_enabled;
 181         u16 cqe_size; /* For use only when CQE stride feature enabled */
 182         u16 eqe_size; /* For use only when EQE stride feature enabled */
 183 };
 184
 185 struct mlx4_init_ib_param {
 186         int port_width;
 187         int vl_cap;
 188         int mtu_cap;
 189         u16 gid_cap;
 190         u16 pkey_cap;
 191         int set_guid0;
 192         u64 guid0;
 193         int set_node_guid;
 194         u64 node_guid;
 195         int set_si_guid;
 196         u64 si_guid;
 197 };
 198
 199 struct mlx4_set_ib_param {
 200         int set_si_guid;
 201         int reset_qkey_viol;
 202         u64 si_guid;
 203         u32 cap_mask;
 204 };
 205
 206 int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap);
 207 int mlx4_QUERY_FUNC_CAP(struct mlx4_dev *dev, u32 gen_or_port,
 208                         struct mlx4_func_cap *func_cap);
 209 int mlx4_QUERY_FUNC_CAP_wrapper(struct mlx4_dev *dev, int slave,
 210                                 struct mlx4_vhcr *vhcr,
 211                                 struct mlx4_cmd_mailbox *inbox,
 212                                 struct mlx4_cmd_mailbox *outbox,
 213                                 struct mlx4_cmd_info *cmd);
 214 int mlx4_MAP_FA(struct mlx4_dev *dev, struct mlx4_icm *icm);
 215 int mlx4_UNMAP_FA(struct mlx4_dev *dev);
 216 int mlx4_RUN_FW(struct mlx4_dev *dev);
 217 int mlx4_QUERY_FW(struct mlx4_dev *dev);
 218 int mlx4_QUERY_ADAPTER(struct mlx4_dev *dev, struct mlx4_adapter *adapter);
 219 int mlx4_INIT_HCA(struct mlx4_dev *dev, struct mlx4_init_hca_param *param);
 220 int mlx4_QUERY_HCA(struct mlx4_dev *dev, struct mlx4_init_hca_param *param);
 221 int mlx4_CLOSE_HCA(struct mlx4_dev *dev, int panic);
 222 int mlx4_map_cmd(struct mlx4_dev *dev, u16 op, struct mlx4_icm *icm, u64 virt);
 223 int mlx4_SET_ICM_SIZE(struct mlx4_dev *dev, u64 icm_size, u64 *aux_pages);
 224 int mlx4_MAP_ICM_AUX(struct mlx4_dev *dev, struct mlx4_icm *icm);
 225 int mlx4_UNMAP_ICM_AUX(struct mlx4_dev *dev);
 226 int mlx4_NOP(struct mlx4_dev *dev);
 227 int mlx4_MOD_STAT_CFG(struct mlx4_dev *dev, struct mlx4_mod_stat_cfg *cfg);
 228 void mlx4_opreq_action(struct work_struct *work);
 229
 230 #endif /* MLX4_FW_H */