2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
5 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * OpenIB.org BSD license below:
13 * Redistribution and use in source and binary forms, with or
14 * without modification, are permitted provided that the following
17 * - Redistributions of source code must retain the above
18 * copyright notice, this list of conditions and the following
21 * - Redistributions in binary form must reproduce the above
22 * copyright notice, this list of conditions and the following
23 * disclaimer in the documentation and/or other materials
24 * provided with the distribution.
26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/module.h>
37 #include <linux/init.h>
38 #include <linux/errno.h>
39 #include <linux/pci.h>
40 #include <linux/dma-mapping.h>
41 #include <linux/slab.h>
42 #include <linux/io-mapping.h>
43 #include <linux/delay.h>
44 #include <linux/kmod.h>
46 #include <linux/mlx4/device.h>
47 #include <linux/mlx4/doorbell.h>
53 MODULE_AUTHOR("Roland Dreier");
54 MODULE_DESCRIPTION("Mellanox ConnectX HCA low-level driver");
55 MODULE_LICENSE("Dual BSD/GPL");
56 MODULE_VERSION(DRV_VERSION
);
58 struct workqueue_struct
*mlx4_wq
;
60 #ifdef CONFIG_MLX4_DEBUG
62 int mlx4_debug_level
= 0;
63 module_param_named(debug_level
, mlx4_debug_level
, int, 0644);
64 MODULE_PARM_DESC(debug_level
, "Enable debug tracing if > 0");
66 #endif /* CONFIG_MLX4_DEBUG */
71 module_param(msi_x
, int, 0444);
72 MODULE_PARM_DESC(msi_x
, "attempt to use MSI-X if nonzero");
74 #else /* CONFIG_PCI_MSI */
78 #endif /* CONFIG_PCI_MSI */
80 static uint8_t num_vfs
[3] = {0, 0, 0};
81 static int num_vfs_argc
= 3;
82 module_param_array(num_vfs
, byte
, &num_vfs_argc
, 0444);
83 MODULE_PARM_DESC(num_vfs
, "enable #num_vfs functions if num_vfs > 0\n"
84 "num_vfs=port1,port2,port1+2");
86 static uint8_t probe_vf
[3] = {0, 0, 0};
87 static int probe_vfs_argc
= 3;
88 module_param_array(probe_vf
, byte
, &probe_vfs_argc
, 0444);
89 MODULE_PARM_DESC(probe_vf
, "number of vfs to probe by pf driver (num_vfs > 0)\n"
90 "probe_vf=port1,port2,port1+2");
92 int mlx4_log_num_mgm_entry_size
= MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE
;
93 module_param_named(log_num_mgm_entry_size
,
94 mlx4_log_num_mgm_entry_size
, int, 0444);
95 MODULE_PARM_DESC(log_num_mgm_entry_size
, "log mgm size, that defines the num"
96 " of qp per mcg, for example:"
97 " 10 gives 248.range: 7 <="
98 " log_num_mgm_entry_size <= 12."
99 " To activate device managed"
100 " flow steering when available, set to -1");
102 static bool enable_64b_cqe_eqe
= true;
103 module_param(enable_64b_cqe_eqe
, bool, 0444);
104 MODULE_PARM_DESC(enable_64b_cqe_eqe
,
105 "Enable 64 byte CQEs/EQEs when the FW supports this (default: True)");
107 #define PF_CONTEXT_BEHAVIOUR_MASK MLX4_FUNC_CAP_64B_EQE_CQE
109 static char mlx4_version
[] =
110 DRV_NAME
": Mellanox ConnectX core driver v"
111 DRV_VERSION
" (" DRV_RELDATE
")\n";
113 static struct mlx4_profile default_profile
= {
116 .rdmarc_per_qp
= 1 << 4,
120 .num_mtt
= 1 << 20, /* It is really num mtt segements */
123 static int log_num_mac
= 7;
124 module_param_named(log_num_mac
, log_num_mac
, int, 0444);
125 MODULE_PARM_DESC(log_num_mac
, "Log2 max number of MACs per ETH port (1-7)");
127 static int log_num_vlan
;
128 module_param_named(log_num_vlan
, log_num_vlan
, int, 0444);
129 MODULE_PARM_DESC(log_num_vlan
, "Log2 max number of VLANs per ETH port (0-7)");
130 /* Log2 max number of VLANs per ETH port (0-7) */
131 #define MLX4_LOG_NUM_VLANS 7
133 static bool use_prio
;
134 module_param_named(use_prio
, use_prio
, bool, 0444);
135 MODULE_PARM_DESC(use_prio
, "Enable steering by VLAN priority on ETH ports (deprecated)");
137 int log_mtts_per_seg
= ilog2(MLX4_MTT_ENTRY_PER_SEG
);
138 module_param_named(log_mtts_per_seg
, log_mtts_per_seg
, int, 0444);
139 MODULE_PARM_DESC(log_mtts_per_seg
, "Log2 number of MTT entries per segment (1-7)");
141 static int port_type_array
[2] = {MLX4_PORT_TYPE_NONE
, MLX4_PORT_TYPE_NONE
};
142 static int arr_argc
= 2;
143 module_param_array(port_type_array
, int, &arr_argc
, 0444);
144 MODULE_PARM_DESC(port_type_array
, "Array of port types: HW_DEFAULT (0) is default "
145 "1 for IB, 2 for Ethernet");
147 struct mlx4_port_config
{
148 struct list_head list
;
149 enum mlx4_port_type port_type
[MLX4_MAX_PORTS
+ 1];
150 struct pci_dev
*pdev
;
153 static atomic_t pf_loading
= ATOMIC_INIT(0);
155 int mlx4_check_port_params(struct mlx4_dev
*dev
,
156 enum mlx4_port_type
*port_type
)
160 for (i
= 0; i
< dev
->caps
.num_ports
- 1; i
++) {
161 if (port_type
[i
] != port_type
[i
+ 1]) {
162 if (!(dev
->caps
.flags
& MLX4_DEV_CAP_FLAG_DPDP
)) {
163 mlx4_err(dev
, "Only same port types supported on this HCA, aborting\n");
169 for (i
= 0; i
< dev
->caps
.num_ports
; i
++) {
170 if (!(port_type
[i
] & dev
->caps
.supported_type
[i
+1])) {
171 mlx4_err(dev
, "Requested port type for port %d is not supported on this HCA\n",
179 static void mlx4_set_port_mask(struct mlx4_dev
*dev
)
183 for (i
= 1; i
<= dev
->caps
.num_ports
; ++i
)
184 dev
->caps
.port_mask
[i
] = dev
->caps
.port_type
[i
];
187 static int mlx4_dev_cap(struct mlx4_dev
*dev
, struct mlx4_dev_cap
*dev_cap
)
192 err
= mlx4_QUERY_DEV_CAP(dev
, dev_cap
);
194 mlx4_err(dev
, "QUERY_DEV_CAP command failed, aborting\n");
198 if (dev_cap
->min_page_sz
> PAGE_SIZE
) {
199 mlx4_err(dev
, "HCA minimum page size of %d bigger than kernel PAGE_SIZE of %ld, aborting\n",
200 dev_cap
->min_page_sz
, PAGE_SIZE
);
203 if (dev_cap
->num_ports
> MLX4_MAX_PORTS
) {
204 mlx4_err(dev
, "HCA has %d ports, but we only support %d, aborting\n",
205 dev_cap
->num_ports
, MLX4_MAX_PORTS
);
209 if (dev_cap
->uar_size
> pci_resource_len(dev
->pdev
, 2)) {
210 mlx4_err(dev
, "HCA reported UAR size of 0x%x bigger than PCI resource 2 size of 0x%llx, aborting\n",
212 (unsigned long long) pci_resource_len(dev
->pdev
, 2));
216 dev
->caps
.num_ports
= dev_cap
->num_ports
;
217 dev
->phys_caps
.num_phys_eqs
= MLX4_MAX_EQ_NUM
;
218 for (i
= 1; i
<= dev
->caps
.num_ports
; ++i
) {
219 dev
->caps
.vl_cap
[i
] = dev_cap
->max_vl
[i
];
220 dev
->caps
.ib_mtu_cap
[i
] = dev_cap
->ib_mtu
[i
];
221 dev
->phys_caps
.gid_phys_table_len
[i
] = dev_cap
->max_gids
[i
];
222 dev
->phys_caps
.pkey_phys_table_len
[i
] = dev_cap
->max_pkeys
[i
];
223 /* set gid and pkey table operating lengths by default
224 * to non-sriov values */
225 dev
->caps
.gid_table_len
[i
] = dev_cap
->max_gids
[i
];
226 dev
->caps
.pkey_table_len
[i
] = dev_cap
->max_pkeys
[i
];
227 dev
->caps
.port_width_cap
[i
] = dev_cap
->max_port_width
[i
];
228 dev
->caps
.eth_mtu_cap
[i
] = dev_cap
->eth_mtu
[i
];
229 dev
->caps
.def_mac
[i
] = dev_cap
->def_mac
[i
];
230 dev
->caps
.supported_type
[i
] = dev_cap
->supported_port_types
[i
];
231 dev
->caps
.suggested_type
[i
] = dev_cap
->suggested_type
[i
];
232 dev
->caps
.default_sense
[i
] = dev_cap
->default_sense
[i
];
233 dev
->caps
.trans_type
[i
] = dev_cap
->trans_type
[i
];
234 dev
->caps
.vendor_oui
[i
] = dev_cap
->vendor_oui
[i
];
235 dev
->caps
.wavelength
[i
] = dev_cap
->wavelength
[i
];
236 dev
->caps
.trans_code
[i
] = dev_cap
->trans_code
[i
];
239 dev
->caps
.uar_page_size
= PAGE_SIZE
;
240 dev
->caps
.num_uars
= dev_cap
->uar_size
/ PAGE_SIZE
;
241 dev
->caps
.local_ca_ack_delay
= dev_cap
->local_ca_ack_delay
;
242 dev
->caps
.bf_reg_size
= dev_cap
->bf_reg_size
;
243 dev
->caps
.bf_regs_per_page
= dev_cap
->bf_regs_per_page
;
244 dev
->caps
.max_sq_sg
= dev_cap
->max_sq_sg
;
245 dev
->caps
.max_rq_sg
= dev_cap
->max_rq_sg
;
246 dev
->caps
.max_wqes
= dev_cap
->max_qp_sz
;
247 dev
->caps
.max_qp_init_rdma
= dev_cap
->max_requester_per_qp
;
248 dev
->caps
.max_srq_wqes
= dev_cap
->max_srq_sz
;
249 dev
->caps
.max_srq_sge
= dev_cap
->max_rq_sg
- 1;
250 dev
->caps
.reserved_srqs
= dev_cap
->reserved_srqs
;
251 dev
->caps
.max_sq_desc_sz
= dev_cap
->max_sq_desc_sz
;
252 dev
->caps
.max_rq_desc_sz
= dev_cap
->max_rq_desc_sz
;
254 * Subtract 1 from the limit because we need to allocate a
255 * spare CQE so the HCA HW can tell the difference between an
256 * empty CQ and a full CQ.
258 dev
->caps
.max_cqes
= dev_cap
->max_cq_sz
- 1;
259 dev
->caps
.reserved_cqs
= dev_cap
->reserved_cqs
;
260 dev
->caps
.reserved_eqs
= dev_cap
->reserved_eqs
;
261 dev
->caps
.reserved_mtts
= dev_cap
->reserved_mtts
;
262 dev
->caps
.reserved_mrws
= dev_cap
->reserved_mrws
;
264 /* The first 128 UARs are used for EQ doorbells */
265 dev
->caps
.reserved_uars
= max_t(int, 128, dev_cap
->reserved_uars
);
266 dev
->caps
.reserved_pds
= dev_cap
->reserved_pds
;
267 dev
->caps
.reserved_xrcds
= (dev
->caps
.flags
& MLX4_DEV_CAP_FLAG_XRC
) ?
268 dev_cap
->reserved_xrcds
: 0;
269 dev
->caps
.max_xrcds
= (dev
->caps
.flags
& MLX4_DEV_CAP_FLAG_XRC
) ?
270 dev_cap
->max_xrcds
: 0;
271 dev
->caps
.mtt_entry_sz
= dev_cap
->mtt_entry_sz
;
273 dev
->caps
.max_msg_sz
= dev_cap
->max_msg_sz
;
274 dev
->caps
.page_size_cap
= ~(u32
) (dev_cap
->min_page_sz
- 1);
275 dev
->caps
.flags
= dev_cap
->flags
;
276 dev
->caps
.flags2
= dev_cap
->flags2
;
277 dev
->caps
.bmme_flags
= dev_cap
->bmme_flags
;
278 dev
->caps
.reserved_lkey
= dev_cap
->reserved_lkey
;
279 dev
->caps
.stat_rate_support
= dev_cap
->stat_rate_support
;
280 dev
->caps
.max_gso_sz
= dev_cap
->max_gso_sz
;
281 dev
->caps
.max_rss_tbl_sz
= dev_cap
->max_rss_tbl_sz
;
283 /* Sense port always allowed on supported devices for ConnectX-1 and -2 */
284 if (mlx4_priv(dev
)->pci_dev_data
& MLX4_PCI_DEV_FORCE_SENSE_PORT
)
285 dev
->caps
.flags
|= MLX4_DEV_CAP_FLAG_SENSE_SUPPORT
;
286 /* Don't do sense port on multifunction devices (for now at least) */
287 if (mlx4_is_mfunc(dev
))
288 dev
->caps
.flags
&= ~MLX4_DEV_CAP_FLAG_SENSE_SUPPORT
;
290 dev
->caps
.log_num_macs
= log_num_mac
;
291 dev
->caps
.log_num_vlans
= MLX4_LOG_NUM_VLANS
;
293 for (i
= 1; i
<= dev
->caps
.num_ports
; ++i
) {
294 dev
->caps
.port_type
[i
] = MLX4_PORT_TYPE_NONE
;
295 if (dev
->caps
.supported_type
[i
]) {
296 /* if only ETH is supported - assign ETH */
297 if (dev
->caps
.supported_type
[i
] == MLX4_PORT_TYPE_ETH
)
298 dev
->caps
.port_type
[i
] = MLX4_PORT_TYPE_ETH
;
299 /* if only IB is supported, assign IB */
300 else if (dev
->caps
.supported_type
[i
] ==
302 dev
->caps
.port_type
[i
] = MLX4_PORT_TYPE_IB
;
304 /* if IB and ETH are supported, we set the port
305 * type according to user selection of port type;
306 * if user selected none, take the FW hint */
307 if (port_type_array
[i
- 1] == MLX4_PORT_TYPE_NONE
)
308 dev
->caps
.port_type
[i
] = dev
->caps
.suggested_type
[i
] ?
309 MLX4_PORT_TYPE_ETH
: MLX4_PORT_TYPE_IB
;
311 dev
->caps
.port_type
[i
] = port_type_array
[i
- 1];
315 * Link sensing is allowed on the port if 3 conditions are true:
316 * 1. Both protocols are supported on the port.
317 * 2. Different types are supported on the port
318 * 3. FW declared that it supports link sensing
320 mlx4_priv(dev
)->sense
.sense_allowed
[i
] =
321 ((dev
->caps
.supported_type
[i
] == MLX4_PORT_TYPE_AUTO
) &&
322 (dev
->caps
.flags
& MLX4_DEV_CAP_FLAG_DPDP
) &&
323 (dev
->caps
.flags
& MLX4_DEV_CAP_FLAG_SENSE_SUPPORT
));
326 * If "default_sense" bit is set, we move the port to "AUTO" mode
327 * and perform sense_port FW command to try and set the correct
328 * port type from beginning
330 if (mlx4_priv(dev
)->sense
.sense_allowed
[i
] && dev
->caps
.default_sense
[i
]) {
331 enum mlx4_port_type sensed_port
= MLX4_PORT_TYPE_NONE
;
332 dev
->caps
.possible_type
[i
] = MLX4_PORT_TYPE_AUTO
;
333 mlx4_SENSE_PORT(dev
, i
, &sensed_port
);
334 if (sensed_port
!= MLX4_PORT_TYPE_NONE
)
335 dev
->caps
.port_type
[i
] = sensed_port
;
337 dev
->caps
.possible_type
[i
] = dev
->caps
.port_type
[i
];
340 if (dev
->caps
.log_num_macs
> dev_cap
->log_max_macs
[i
]) {
341 dev
->caps
.log_num_macs
= dev_cap
->log_max_macs
[i
];
342 mlx4_warn(dev
, "Requested number of MACs is too much for port %d, reducing to %d\n",
343 i
, 1 << dev
->caps
.log_num_macs
);
345 if (dev
->caps
.log_num_vlans
> dev_cap
->log_max_vlans
[i
]) {
346 dev
->caps
.log_num_vlans
= dev_cap
->log_max_vlans
[i
];
347 mlx4_warn(dev
, "Requested number of VLANs is too much for port %d, reducing to %d\n",
348 i
, 1 << dev
->caps
.log_num_vlans
);
352 dev
->caps
.max_counters
= 1 << ilog2(dev_cap
->max_counters
);
354 dev
->caps
.reserved_qps_cnt
[MLX4_QP_REGION_FW
] = dev_cap
->reserved_qps
;
355 dev
->caps
.reserved_qps_cnt
[MLX4_QP_REGION_ETH_ADDR
] =
356 dev
->caps
.reserved_qps_cnt
[MLX4_QP_REGION_FC_ADDR
] =
357 (1 << dev
->caps
.log_num_macs
) *
358 (1 << dev
->caps
.log_num_vlans
) *
360 dev
->caps
.reserved_qps_cnt
[MLX4_QP_REGION_FC_EXCH
] = MLX4_NUM_FEXCH
;
362 dev
->caps
.reserved_qps
= dev
->caps
.reserved_qps_cnt
[MLX4_QP_REGION_FW
] +
363 dev
->caps
.reserved_qps_cnt
[MLX4_QP_REGION_ETH_ADDR
] +
364 dev
->caps
.reserved_qps_cnt
[MLX4_QP_REGION_FC_ADDR
] +
365 dev
->caps
.reserved_qps_cnt
[MLX4_QP_REGION_FC_EXCH
];
367 dev
->caps
.sqp_demux
= (mlx4_is_master(dev
)) ? MLX4_MAX_NUM_SLAVES
: 0;
369 if (!enable_64b_cqe_eqe
&& !mlx4_is_slave(dev
)) {
371 (MLX4_DEV_CAP_FLAG_64B_CQE
| MLX4_DEV_CAP_FLAG_64B_EQE
)) {
372 mlx4_warn(dev
, "64B EQEs/CQEs supported by the device but not enabled\n");
373 dev
->caps
.flags
&= ~MLX4_DEV_CAP_FLAG_64B_CQE
;
374 dev
->caps
.flags
&= ~MLX4_DEV_CAP_FLAG_64B_EQE
;
378 if ((dev
->caps
.flags
&
379 (MLX4_DEV_CAP_FLAG_64B_CQE
| MLX4_DEV_CAP_FLAG_64B_EQE
)) &&
381 dev
->caps
.function_caps
|= MLX4_FUNC_CAP_64B_EQE_CQE
;
386 static int mlx4_get_pcie_dev_link_caps(struct mlx4_dev
*dev
,
387 enum pci_bus_speed
*speed
,
388 enum pcie_link_width
*width
)
390 u32 lnkcap1
, lnkcap2
;
393 #define PCIE_MLW_CAP_SHIFT 4 /* start of MLW mask in link capabilities */
395 *speed
= PCI_SPEED_UNKNOWN
;
396 *width
= PCIE_LNK_WIDTH_UNKNOWN
;
398 err1
= pcie_capability_read_dword(dev
->pdev
, PCI_EXP_LNKCAP
, &lnkcap1
);
399 err2
= pcie_capability_read_dword(dev
->pdev
, PCI_EXP_LNKCAP2
, &lnkcap2
);
400 if (!err2
&& lnkcap2
) { /* PCIe r3.0-compliant */
401 if (lnkcap2
& PCI_EXP_LNKCAP2_SLS_8_0GB
)
402 *speed
= PCIE_SPEED_8_0GT
;
403 else if (lnkcap2
& PCI_EXP_LNKCAP2_SLS_5_0GB
)
404 *speed
= PCIE_SPEED_5_0GT
;
405 else if (lnkcap2
& PCI_EXP_LNKCAP2_SLS_2_5GB
)
406 *speed
= PCIE_SPEED_2_5GT
;
409 *width
= (lnkcap1
& PCI_EXP_LNKCAP_MLW
) >> PCIE_MLW_CAP_SHIFT
;
410 if (!lnkcap2
) { /* pre-r3.0 */
411 if (lnkcap1
& PCI_EXP_LNKCAP_SLS_5_0GB
)
412 *speed
= PCIE_SPEED_5_0GT
;
413 else if (lnkcap1
& PCI_EXP_LNKCAP_SLS_2_5GB
)
414 *speed
= PCIE_SPEED_2_5GT
;
418 if (*speed
== PCI_SPEED_UNKNOWN
|| *width
== PCIE_LNK_WIDTH_UNKNOWN
) {
420 err2
? err2
: -EINVAL
;
425 static void mlx4_check_pcie_caps(struct mlx4_dev
*dev
)
427 enum pcie_link_width width
, width_cap
;
428 enum pci_bus_speed speed
, speed_cap
;
431 #define PCIE_SPEED_STR(speed) \
432 (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" : \
433 speed == PCIE_SPEED_5_0GT ? "5.0GT/s" : \
434 speed == PCIE_SPEED_2_5GT ? "2.5GT/s" : \
437 err
= mlx4_get_pcie_dev_link_caps(dev
, &speed_cap
, &width_cap
);
440 "Unable to determine PCIe device BW capabilities\n");
444 err
= pcie_get_minimum_link(dev
->pdev
, &speed
, &width
);
445 if (err
|| speed
== PCI_SPEED_UNKNOWN
||
446 width
== PCIE_LNK_WIDTH_UNKNOWN
) {
448 "Unable to determine PCI device chain minimum BW\n");
452 if (width
!= width_cap
|| speed
!= speed_cap
)
454 "PCIe BW is different than device's capability\n");
456 mlx4_info(dev
, "PCIe link speed is %s, device supports %s\n",
457 PCIE_SPEED_STR(speed
), PCIE_SPEED_STR(speed_cap
));
458 mlx4_info(dev
, "PCIe link width is x%d, device supports x%d\n",
463 /*The function checks if there are live vf, return the num of them*/
464 static int mlx4_how_many_lives_vf(struct mlx4_dev
*dev
)
466 struct mlx4_priv
*priv
= mlx4_priv(dev
);
467 struct mlx4_slave_state
*s_state
;
471 for (i
= 1/*the ppf is 0*/; i
< dev
->num_slaves
; ++i
) {
472 s_state
= &priv
->mfunc
.master
.slave_state
[i
];
473 if (s_state
->active
&& s_state
->last_cmd
!=
474 MLX4_COMM_CMD_RESET
) {
475 mlx4_warn(dev
, "%s: slave: %d is still active\n",
483 int mlx4_get_parav_qkey(struct mlx4_dev
*dev
, u32 qpn
, u32
*qkey
)
485 u32 qk
= MLX4_RESERVED_QKEY_BASE
;
487 if (qpn
>= dev
->phys_caps
.base_tunnel_sqpn
+ 8 * MLX4_MFUNC_MAX
||
488 qpn
< dev
->phys_caps
.base_proxy_sqpn
)
491 if (qpn
>= dev
->phys_caps
.base_tunnel_sqpn
)
493 qk
+= qpn
- dev
->phys_caps
.base_tunnel_sqpn
;
495 qk
+= qpn
- dev
->phys_caps
.base_proxy_sqpn
;
499 EXPORT_SYMBOL(mlx4_get_parav_qkey
);
501 void mlx4_sync_pkey_table(struct mlx4_dev
*dev
, int slave
, int port
, int i
, int val
)
503 struct mlx4_priv
*priv
= container_of(dev
, struct mlx4_priv
, dev
);
505 if (!mlx4_is_master(dev
))
508 priv
->virt2phys_pkey
[slave
][port
- 1][i
] = val
;
510 EXPORT_SYMBOL(mlx4_sync_pkey_table
);
512 void mlx4_put_slave_node_guid(struct mlx4_dev
*dev
, int slave
, __be64 guid
)
514 struct mlx4_priv
*priv
= container_of(dev
, struct mlx4_priv
, dev
);
516 if (!mlx4_is_master(dev
))
519 priv
->slave_node_guids
[slave
] = guid
;
521 EXPORT_SYMBOL(mlx4_put_slave_node_guid
);
523 __be64
mlx4_get_slave_node_guid(struct mlx4_dev
*dev
, int slave
)
525 struct mlx4_priv
*priv
= container_of(dev
, struct mlx4_priv
, dev
);
527 if (!mlx4_is_master(dev
))
530 return priv
->slave_node_guids
[slave
];
532 EXPORT_SYMBOL(mlx4_get_slave_node_guid
);
534 int mlx4_is_slave_active(struct mlx4_dev
*dev
, int slave
)
536 struct mlx4_priv
*priv
= mlx4_priv(dev
);
537 struct mlx4_slave_state
*s_slave
;
539 if (!mlx4_is_master(dev
))
542 s_slave
= &priv
->mfunc
.master
.slave_state
[slave
];
543 return !!s_slave
->active
;
545 EXPORT_SYMBOL(mlx4_is_slave_active
);
547 static void slave_adjust_steering_mode(struct mlx4_dev
*dev
,
548 struct mlx4_dev_cap
*dev_cap
,
549 struct mlx4_init_hca_param
*hca_param
)
551 dev
->caps
.steering_mode
= hca_param
->steering_mode
;
552 if (dev
->caps
.steering_mode
== MLX4_STEERING_MODE_DEVICE_MANAGED
) {
553 dev
->caps
.num_qp_per_mgm
= dev_cap
->fs_max_num_qp_per_entry
;
554 dev
->caps
.fs_log_max_ucast_qp_range_size
=
555 dev_cap
->fs_log_max_ucast_qp_range_size
;
557 dev
->caps
.num_qp_per_mgm
=
558 4 * ((1 << hca_param
->log_mc_entry_sz
)/16 - 2);
560 mlx4_dbg(dev
, "Steering mode is: %s\n",
561 mlx4_steering_mode_str(dev
->caps
.steering_mode
));
564 static int mlx4_slave_cap(struct mlx4_dev
*dev
)
568 struct mlx4_dev_cap dev_cap
;
569 struct mlx4_func_cap func_cap
;
570 struct mlx4_init_hca_param hca_param
;
573 memset(&hca_param
, 0, sizeof(hca_param
));
574 err
= mlx4_QUERY_HCA(dev
, &hca_param
);
576 mlx4_err(dev
, "QUERY_HCA command failed, aborting\n");
580 /* fail if the hca has an unknown global capability
581 * at this time global_caps should be always zeroed
583 if (hca_param
.global_caps
) {
584 mlx4_err(dev
, "Unknown hca global capabilities\n");
588 mlx4_log_num_mgm_entry_size
= hca_param
.log_mc_entry_sz
;
590 dev
->caps
.hca_core_clock
= hca_param
.hca_core_clock
;
592 memset(&dev_cap
, 0, sizeof(dev_cap
));
593 dev
->caps
.max_qp_dest_rdma
= 1 << hca_param
.log_rd_per_qp
;
594 err
= mlx4_dev_cap(dev
, &dev_cap
);
596 mlx4_err(dev
, "QUERY_DEV_CAP command failed, aborting\n");
600 err
= mlx4_QUERY_FW(dev
);
602 mlx4_err(dev
, "QUERY_FW command failed: could not get FW version\n");
604 page_size
= ~dev
->caps
.page_size_cap
+ 1;
605 mlx4_warn(dev
, "HCA minimum page size:%d\n", page_size
);
606 if (page_size
> PAGE_SIZE
) {
607 mlx4_err(dev
, "HCA minimum page size of %d bigger than kernel PAGE_SIZE of %ld, aborting\n",
608 page_size
, PAGE_SIZE
);
612 /* slave gets uar page size from QUERY_HCA fw command */
613 dev
->caps
.uar_page_size
= 1 << (hca_param
.uar_page_sz
+ 12);
615 /* TODO: relax this assumption */
616 if (dev
->caps
.uar_page_size
!= PAGE_SIZE
) {
617 mlx4_err(dev
, "UAR size:%d != kernel PAGE_SIZE of %ld\n",
618 dev
->caps
.uar_page_size
, PAGE_SIZE
);
622 memset(&func_cap
, 0, sizeof(func_cap
));
623 err
= mlx4_QUERY_FUNC_CAP(dev
, 0, &func_cap
);
625 mlx4_err(dev
, "QUERY_FUNC_CAP general command failed, aborting (%d)\n",
630 if ((func_cap
.pf_context_behaviour
| PF_CONTEXT_BEHAVIOUR_MASK
) !=
631 PF_CONTEXT_BEHAVIOUR_MASK
) {
632 mlx4_err(dev
, "Unknown pf context behaviour\n");
636 dev
->caps
.num_ports
= func_cap
.num_ports
;
637 dev
->quotas
.qp
= func_cap
.qp_quota
;
638 dev
->quotas
.srq
= func_cap
.srq_quota
;
639 dev
->quotas
.cq
= func_cap
.cq_quota
;
640 dev
->quotas
.mpt
= func_cap
.mpt_quota
;
641 dev
->quotas
.mtt
= func_cap
.mtt_quota
;
642 dev
->caps
.num_qps
= 1 << hca_param
.log_num_qps
;
643 dev
->caps
.num_srqs
= 1 << hca_param
.log_num_srqs
;
644 dev
->caps
.num_cqs
= 1 << hca_param
.log_num_cqs
;
645 dev
->caps
.num_mpts
= 1 << hca_param
.log_mpt_sz
;
646 dev
->caps
.num_eqs
= func_cap
.max_eq
;
647 dev
->caps
.reserved_eqs
= func_cap
.reserved_eq
;
648 dev
->caps
.num_pds
= MLX4_NUM_PDS
;
649 dev
->caps
.num_mgms
= 0;
650 dev
->caps
.num_amgms
= 0;
652 if (dev
->caps
.num_ports
> MLX4_MAX_PORTS
) {
653 mlx4_err(dev
, "HCA has %d ports, but we only support %d, aborting\n",
654 dev
->caps
.num_ports
, MLX4_MAX_PORTS
);
658 dev
->caps
.qp0_tunnel
= kcalloc(dev
->caps
.num_ports
, sizeof (u32
), GFP_KERNEL
);
659 dev
->caps
.qp0_proxy
= kcalloc(dev
->caps
.num_ports
, sizeof (u32
), GFP_KERNEL
);
660 dev
->caps
.qp1_tunnel
= kcalloc(dev
->caps
.num_ports
, sizeof (u32
), GFP_KERNEL
);
661 dev
->caps
.qp1_proxy
= kcalloc(dev
->caps
.num_ports
, sizeof (u32
), GFP_KERNEL
);
663 if (!dev
->caps
.qp0_tunnel
|| !dev
->caps
.qp0_proxy
||
664 !dev
->caps
.qp1_tunnel
|| !dev
->caps
.qp1_proxy
) {
669 for (i
= 1; i
<= dev
->caps
.num_ports
; ++i
) {
670 err
= mlx4_QUERY_FUNC_CAP(dev
, (u32
) i
, &func_cap
);
672 mlx4_err(dev
, "QUERY_FUNC_CAP port command failed for port %d, aborting (%d)\n",
676 dev
->caps
.qp0_tunnel
[i
- 1] = func_cap
.qp0_tunnel_qpn
;
677 dev
->caps
.qp0_proxy
[i
- 1] = func_cap
.qp0_proxy_qpn
;
678 dev
->caps
.qp1_tunnel
[i
- 1] = func_cap
.qp1_tunnel_qpn
;
679 dev
->caps
.qp1_proxy
[i
- 1] = func_cap
.qp1_proxy_qpn
;
680 dev
->caps
.port_mask
[i
] = dev
->caps
.port_type
[i
];
681 dev
->caps
.phys_port_id
[i
] = func_cap
.phys_port_id
;
682 if (mlx4_get_slave_pkey_gid_tbl_len(dev
, i
,
683 &dev
->caps
.gid_table_len
[i
],
684 &dev
->caps
.pkey_table_len
[i
]))
688 if (dev
->caps
.uar_page_size
* (dev
->caps
.num_uars
-
689 dev
->caps
.reserved_uars
) >
690 pci_resource_len(dev
->pdev
, 2)) {
691 mlx4_err(dev
, "HCA reported UAR region size of 0x%x bigger than PCI resource 2 size of 0x%llx, aborting\n",
692 dev
->caps
.uar_page_size
* dev
->caps
.num_uars
,
693 (unsigned long long) pci_resource_len(dev
->pdev
, 2));
697 if (hca_param
.dev_cap_enabled
& MLX4_DEV_CAP_64B_EQE_ENABLED
) {
698 dev
->caps
.eqe_size
= 64;
699 dev
->caps
.eqe_factor
= 1;
701 dev
->caps
.eqe_size
= 32;
702 dev
->caps
.eqe_factor
= 0;
705 if (hca_param
.dev_cap_enabled
& MLX4_DEV_CAP_64B_CQE_ENABLED
) {
706 dev
->caps
.cqe_size
= 64;
707 dev
->caps
.userspace_caps
|= MLX4_USER_DEV_CAP_64B_CQE
;
709 dev
->caps
.cqe_size
= 32;
712 dev
->caps
.flags2
&= ~MLX4_DEV_CAP_FLAG2_TS
;
713 mlx4_warn(dev
, "Timestamping is not supported in slave mode\n");
715 slave_adjust_steering_mode(dev
, &dev_cap
, &hca_param
);
720 kfree(dev
->caps
.qp0_tunnel
);
721 kfree(dev
->caps
.qp0_proxy
);
722 kfree(dev
->caps
.qp1_tunnel
);
723 kfree(dev
->caps
.qp1_proxy
);
724 dev
->caps
.qp0_tunnel
= dev
->caps
.qp0_proxy
=
725 dev
->caps
.qp1_tunnel
= dev
->caps
.qp1_proxy
= NULL
;
730 static void mlx4_request_modules(struct mlx4_dev
*dev
)
733 int has_ib_port
= false;
734 int has_eth_port
= false;
735 #define EN_DRV_NAME "mlx4_en"
736 #define IB_DRV_NAME "mlx4_ib"
738 for (port
= 1; port
<= dev
->caps
.num_ports
; port
++) {
739 if (dev
->caps
.port_type
[port
] == MLX4_PORT_TYPE_IB
)
741 else if (dev
->caps
.port_type
[port
] == MLX4_PORT_TYPE_ETH
)
746 request_module_nowait(EN_DRV_NAME
);
747 if (has_ib_port
|| (dev
->caps
.flags
& MLX4_DEV_CAP_FLAG_IBOE
))
748 request_module_nowait(IB_DRV_NAME
);
752 * Change the port configuration of the device.
753 * Every user of this function must hold the port mutex.
755 int mlx4_change_port_types(struct mlx4_dev
*dev
,
756 enum mlx4_port_type
*port_types
)
762 for (port
= 0; port
< dev
->caps
.num_ports
; port
++) {
763 /* Change the port type only if the new type is different
764 * from the current, and not set to Auto */
765 if (port_types
[port
] != dev
->caps
.port_type
[port
+ 1])
769 mlx4_unregister_device(dev
);
770 for (port
= 1; port
<= dev
->caps
.num_ports
; port
++) {
771 mlx4_CLOSE_PORT(dev
, port
);
772 dev
->caps
.port_type
[port
] = port_types
[port
- 1];
773 err
= mlx4_SET_PORT(dev
, port
, -1);
775 mlx4_err(dev
, "Failed to set port %d, aborting\n",
780 mlx4_set_port_mask(dev
);
781 err
= mlx4_register_device(dev
);
783 mlx4_err(dev
, "Failed to register device\n");
786 mlx4_request_modules(dev
);
793 static ssize_t
show_port_type(struct device
*dev
,
794 struct device_attribute
*attr
,
797 struct mlx4_port_info
*info
= container_of(attr
, struct mlx4_port_info
,
799 struct mlx4_dev
*mdev
= info
->dev
;
803 (mdev
->caps
.port_type
[info
->port
] == MLX4_PORT_TYPE_IB
) ?
805 if (mdev
->caps
.possible_type
[info
->port
] == MLX4_PORT_TYPE_AUTO
)
806 sprintf(buf
, "auto (%s)\n", type
);
808 sprintf(buf
, "%s\n", type
);
813 static ssize_t
set_port_type(struct device
*dev
,
814 struct device_attribute
*attr
,
815 const char *buf
, size_t count
)
817 struct mlx4_port_info
*info
= container_of(attr
, struct mlx4_port_info
,
819 struct mlx4_dev
*mdev
= info
->dev
;
820 struct mlx4_priv
*priv
= mlx4_priv(mdev
);
821 enum mlx4_port_type types
[MLX4_MAX_PORTS
];
822 enum mlx4_port_type new_types
[MLX4_MAX_PORTS
];
826 if (!strcmp(buf
, "ib\n"))
827 info
->tmp_type
= MLX4_PORT_TYPE_IB
;
828 else if (!strcmp(buf
, "eth\n"))
829 info
->tmp_type
= MLX4_PORT_TYPE_ETH
;
830 else if (!strcmp(buf
, "auto\n"))
831 info
->tmp_type
= MLX4_PORT_TYPE_AUTO
;
833 mlx4_err(mdev
, "%s is not supported port type\n", buf
);
837 mlx4_stop_sense(mdev
);
838 mutex_lock(&priv
->port_mutex
);
839 /* Possible type is always the one that was delivered */
840 mdev
->caps
.possible_type
[info
->port
] = info
->tmp_type
;
842 for (i
= 0; i
< mdev
->caps
.num_ports
; i
++) {
843 types
[i
] = priv
->port
[i
+1].tmp_type
? priv
->port
[i
+1].tmp_type
:
844 mdev
->caps
.possible_type
[i
+1];
845 if (types
[i
] == MLX4_PORT_TYPE_AUTO
)
846 types
[i
] = mdev
->caps
.port_type
[i
+1];
849 if (!(mdev
->caps
.flags
& MLX4_DEV_CAP_FLAG_DPDP
) &&
850 !(mdev
->caps
.flags
& MLX4_DEV_CAP_FLAG_SENSE_SUPPORT
)) {
851 for (i
= 1; i
<= mdev
->caps
.num_ports
; i
++) {
852 if (mdev
->caps
.possible_type
[i
] == MLX4_PORT_TYPE_AUTO
) {
853 mdev
->caps
.possible_type
[i
] = mdev
->caps
.port_type
[i
];
859 mlx4_err(mdev
, "Auto sensing is not supported on this HCA. Set only 'eth' or 'ib' for both ports (should be the same)\n");
863 mlx4_do_sense_ports(mdev
, new_types
, types
);
865 err
= mlx4_check_port_params(mdev
, new_types
);
869 /* We are about to apply the changes after the configuration
870 * was verified, no need to remember the temporary types
872 for (i
= 0; i
< mdev
->caps
.num_ports
; i
++)
873 priv
->port
[i
+ 1].tmp_type
= 0;
875 err
= mlx4_change_port_types(mdev
, new_types
);
878 mlx4_start_sense(mdev
);
879 mutex_unlock(&priv
->port_mutex
);
880 return err
? err
: count
;
891 static inline int int_to_ibta_mtu(int mtu
)
894 case 256: return IB_MTU_256
;
895 case 512: return IB_MTU_512
;
896 case 1024: return IB_MTU_1024
;
897 case 2048: return IB_MTU_2048
;
898 case 4096: return IB_MTU_4096
;
903 static inline int ibta_mtu_to_int(enum ibta_mtu mtu
)
906 case IB_MTU_256
: return 256;
907 case IB_MTU_512
: return 512;
908 case IB_MTU_1024
: return 1024;
909 case IB_MTU_2048
: return 2048;
910 case IB_MTU_4096
: return 4096;
915 static ssize_t
show_port_ib_mtu(struct device
*dev
,
916 struct device_attribute
*attr
,
919 struct mlx4_port_info
*info
= container_of(attr
, struct mlx4_port_info
,
921 struct mlx4_dev
*mdev
= info
->dev
;
923 if (mdev
->caps
.port_type
[info
->port
] == MLX4_PORT_TYPE_ETH
)
924 mlx4_warn(mdev
, "port level mtu is only used for IB ports\n");
927 ibta_mtu_to_int(mdev
->caps
.port_ib_mtu
[info
->port
]));
931 static ssize_t
set_port_ib_mtu(struct device
*dev
,
932 struct device_attribute
*attr
,
933 const char *buf
, size_t count
)
935 struct mlx4_port_info
*info
= container_of(attr
, struct mlx4_port_info
,
937 struct mlx4_dev
*mdev
= info
->dev
;
938 struct mlx4_priv
*priv
= mlx4_priv(mdev
);
939 int err
, port
, mtu
, ibta_mtu
= -1;
941 if (mdev
->caps
.port_type
[info
->port
] == MLX4_PORT_TYPE_ETH
) {
942 mlx4_warn(mdev
, "port level mtu is only used for IB ports\n");
946 err
= kstrtoint(buf
, 0, &mtu
);
948 ibta_mtu
= int_to_ibta_mtu(mtu
);
950 if (err
|| ibta_mtu
< 0) {
951 mlx4_err(mdev
, "%s is invalid IBTA mtu\n", buf
);
955 mdev
->caps
.port_ib_mtu
[info
->port
] = ibta_mtu
;
957 mlx4_stop_sense(mdev
);
958 mutex_lock(&priv
->port_mutex
);
959 mlx4_unregister_device(mdev
);
960 for (port
= 1; port
<= mdev
->caps
.num_ports
; port
++) {
961 mlx4_CLOSE_PORT(mdev
, port
);
962 err
= mlx4_SET_PORT(mdev
, port
, -1);
964 mlx4_err(mdev
, "Failed to set port %d, aborting\n",
969 err
= mlx4_register_device(mdev
);
971 mutex_unlock(&priv
->port_mutex
);
972 mlx4_start_sense(mdev
);
973 return err
? err
: count
;
976 static int mlx4_load_fw(struct mlx4_dev
*dev
)
978 struct mlx4_priv
*priv
= mlx4_priv(dev
);
981 priv
->fw
.fw_icm
= mlx4_alloc_icm(dev
, priv
->fw
.fw_pages
,
982 GFP_HIGHUSER
| __GFP_NOWARN
, 0);
983 if (!priv
->fw
.fw_icm
) {
984 mlx4_err(dev
, "Couldn't allocate FW area, aborting\n");
988 err
= mlx4_MAP_FA(dev
, priv
->fw
.fw_icm
);
990 mlx4_err(dev
, "MAP_FA command failed, aborting\n");
994 err
= mlx4_RUN_FW(dev
);
996 mlx4_err(dev
, "RUN_FW command failed, aborting\n");
1006 mlx4_free_icm(dev
, priv
->fw
.fw_icm
, 0);
1010 static int mlx4_init_cmpt_table(struct mlx4_dev
*dev
, u64 cmpt_base
,
1013 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1017 err
= mlx4_init_icm_table(dev
, &priv
->qp_table
.cmpt_table
,
1019 ((u64
) (MLX4_CMPT_TYPE_QP
*
1020 cmpt_entry_sz
) << MLX4_CMPT_SHIFT
),
1021 cmpt_entry_sz
, dev
->caps
.num_qps
,
1022 dev
->caps
.reserved_qps_cnt
[MLX4_QP_REGION_FW
],
1027 err
= mlx4_init_icm_table(dev
, &priv
->srq_table
.cmpt_table
,
1029 ((u64
) (MLX4_CMPT_TYPE_SRQ
*
1030 cmpt_entry_sz
) << MLX4_CMPT_SHIFT
),
1031 cmpt_entry_sz
, dev
->caps
.num_srqs
,
1032 dev
->caps
.reserved_srqs
, 0, 0);
1036 err
= mlx4_init_icm_table(dev
, &priv
->cq_table
.cmpt_table
,
1038 ((u64
) (MLX4_CMPT_TYPE_CQ
*
1039 cmpt_entry_sz
) << MLX4_CMPT_SHIFT
),
1040 cmpt_entry_sz
, dev
->caps
.num_cqs
,
1041 dev
->caps
.reserved_cqs
, 0, 0);
1045 num_eqs
= (mlx4_is_master(dev
)) ? dev
->phys_caps
.num_phys_eqs
:
1047 err
= mlx4_init_icm_table(dev
, &priv
->eq_table
.cmpt_table
,
1049 ((u64
) (MLX4_CMPT_TYPE_EQ
*
1050 cmpt_entry_sz
) << MLX4_CMPT_SHIFT
),
1051 cmpt_entry_sz
, num_eqs
, num_eqs
, 0, 0);
1058 mlx4_cleanup_icm_table(dev
, &priv
->cq_table
.cmpt_table
);
1061 mlx4_cleanup_icm_table(dev
, &priv
->srq_table
.cmpt_table
);
1064 mlx4_cleanup_icm_table(dev
, &priv
->qp_table
.cmpt_table
);
1070 static int mlx4_init_icm(struct mlx4_dev
*dev
, struct mlx4_dev_cap
*dev_cap
,
1071 struct mlx4_init_hca_param
*init_hca
, u64 icm_size
)
1073 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1078 err
= mlx4_SET_ICM_SIZE(dev
, icm_size
, &aux_pages
);
1080 mlx4_err(dev
, "SET_ICM_SIZE command failed, aborting\n");
1084 mlx4_dbg(dev
, "%lld KB of HCA context requires %lld KB aux memory\n",
1085 (unsigned long long) icm_size
>> 10,
1086 (unsigned long long) aux_pages
<< 2);
1088 priv
->fw
.aux_icm
= mlx4_alloc_icm(dev
, aux_pages
,
1089 GFP_HIGHUSER
| __GFP_NOWARN
, 0);
1090 if (!priv
->fw
.aux_icm
) {
1091 mlx4_err(dev
, "Couldn't allocate aux memory, aborting\n");
1095 err
= mlx4_MAP_ICM_AUX(dev
, priv
->fw
.aux_icm
);
1097 mlx4_err(dev
, "MAP_ICM_AUX command failed, aborting\n");
1101 err
= mlx4_init_cmpt_table(dev
, init_hca
->cmpt_base
, dev_cap
->cmpt_entry_sz
);
1103 mlx4_err(dev
, "Failed to map cMPT context memory, aborting\n");
1108 num_eqs
= (mlx4_is_master(dev
)) ? dev
->phys_caps
.num_phys_eqs
:
1110 err
= mlx4_init_icm_table(dev
, &priv
->eq_table
.table
,
1111 init_hca
->eqc_base
, dev_cap
->eqc_entry_sz
,
1112 num_eqs
, num_eqs
, 0, 0);
1114 mlx4_err(dev
, "Failed to map EQ context memory, aborting\n");
1115 goto err_unmap_cmpt
;
1119 * Reserved MTT entries must be aligned up to a cacheline
1120 * boundary, since the FW will write to them, while the driver
1121 * writes to all other MTT entries. (The variable
1122 * dev->caps.mtt_entry_sz below is really the MTT segment
1123 * size, not the raw entry size)
1125 dev
->caps
.reserved_mtts
=
1126 ALIGN(dev
->caps
.reserved_mtts
* dev
->caps
.mtt_entry_sz
,
1127 dma_get_cache_alignment()) / dev
->caps
.mtt_entry_sz
;
1129 err
= mlx4_init_icm_table(dev
, &priv
->mr_table
.mtt_table
,
1131 dev
->caps
.mtt_entry_sz
,
1133 dev
->caps
.reserved_mtts
, 1, 0);
1135 mlx4_err(dev
, "Failed to map MTT context memory, aborting\n");
1139 err
= mlx4_init_icm_table(dev
, &priv
->mr_table
.dmpt_table
,
1140 init_hca
->dmpt_base
,
1141 dev_cap
->dmpt_entry_sz
,
1143 dev
->caps
.reserved_mrws
, 1, 1);
1145 mlx4_err(dev
, "Failed to map dMPT context memory, aborting\n");
1149 err
= mlx4_init_icm_table(dev
, &priv
->qp_table
.qp_table
,
1151 dev_cap
->qpc_entry_sz
,
1153 dev
->caps
.reserved_qps_cnt
[MLX4_QP_REGION_FW
],
1156 mlx4_err(dev
, "Failed to map QP context memory, aborting\n");
1157 goto err_unmap_dmpt
;
1160 err
= mlx4_init_icm_table(dev
, &priv
->qp_table
.auxc_table
,
1161 init_hca
->auxc_base
,
1162 dev_cap
->aux_entry_sz
,
1164 dev
->caps
.reserved_qps_cnt
[MLX4_QP_REGION_FW
],
1167 mlx4_err(dev
, "Failed to map AUXC context memory, aborting\n");
1171 err
= mlx4_init_icm_table(dev
, &priv
->qp_table
.altc_table
,
1172 init_hca
->altc_base
,
1173 dev_cap
->altc_entry_sz
,
1175 dev
->caps
.reserved_qps_cnt
[MLX4_QP_REGION_FW
],
1178 mlx4_err(dev
, "Failed to map ALTC context memory, aborting\n");
1179 goto err_unmap_auxc
;
1182 err
= mlx4_init_icm_table(dev
, &priv
->qp_table
.rdmarc_table
,
1183 init_hca
->rdmarc_base
,
1184 dev_cap
->rdmarc_entry_sz
<< priv
->qp_table
.rdmarc_shift
,
1186 dev
->caps
.reserved_qps_cnt
[MLX4_QP_REGION_FW
],
1189 mlx4_err(dev
, "Failed to map RDMARC context memory, aborting\n");
1190 goto err_unmap_altc
;
1193 err
= mlx4_init_icm_table(dev
, &priv
->cq_table
.table
,
1195 dev_cap
->cqc_entry_sz
,
1197 dev
->caps
.reserved_cqs
, 0, 0);
1199 mlx4_err(dev
, "Failed to map CQ context memory, aborting\n");
1200 goto err_unmap_rdmarc
;
1203 err
= mlx4_init_icm_table(dev
, &priv
->srq_table
.table
,
1204 init_hca
->srqc_base
,
1205 dev_cap
->srq_entry_sz
,
1207 dev
->caps
.reserved_srqs
, 0, 0);
1209 mlx4_err(dev
, "Failed to map SRQ context memory, aborting\n");
1214 * For flow steering device managed mode it is required to use
1215 * mlx4_init_icm_table. For B0 steering mode it's not strictly
1216 * required, but for simplicity just map the whole multicast
1217 * group table now. The table isn't very big and it's a lot
1218 * easier than trying to track ref counts.
1220 err
= mlx4_init_icm_table(dev
, &priv
->mcg_table
.table
,
1222 mlx4_get_mgm_entry_size(dev
),
1223 dev
->caps
.num_mgms
+ dev
->caps
.num_amgms
,
1224 dev
->caps
.num_mgms
+ dev
->caps
.num_amgms
,
1227 mlx4_err(dev
, "Failed to map MCG context memory, aborting\n");
1234 mlx4_cleanup_icm_table(dev
, &priv
->srq_table
.table
);
1237 mlx4_cleanup_icm_table(dev
, &priv
->cq_table
.table
);
1240 mlx4_cleanup_icm_table(dev
, &priv
->qp_table
.rdmarc_table
);
1243 mlx4_cleanup_icm_table(dev
, &priv
->qp_table
.altc_table
);
1246 mlx4_cleanup_icm_table(dev
, &priv
->qp_table
.auxc_table
);
1249 mlx4_cleanup_icm_table(dev
, &priv
->qp_table
.qp_table
);
1252 mlx4_cleanup_icm_table(dev
, &priv
->mr_table
.dmpt_table
);
1255 mlx4_cleanup_icm_table(dev
, &priv
->mr_table
.mtt_table
);
1258 mlx4_cleanup_icm_table(dev
, &priv
->eq_table
.table
);
1261 mlx4_cleanup_icm_table(dev
, &priv
->eq_table
.cmpt_table
);
1262 mlx4_cleanup_icm_table(dev
, &priv
->cq_table
.cmpt_table
);
1263 mlx4_cleanup_icm_table(dev
, &priv
->srq_table
.cmpt_table
);
1264 mlx4_cleanup_icm_table(dev
, &priv
->qp_table
.cmpt_table
);
1267 mlx4_UNMAP_ICM_AUX(dev
);
1270 mlx4_free_icm(dev
, priv
->fw
.aux_icm
, 0);
1275 static void mlx4_free_icms(struct mlx4_dev
*dev
)
1277 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1279 mlx4_cleanup_icm_table(dev
, &priv
->mcg_table
.table
);
1280 mlx4_cleanup_icm_table(dev
, &priv
->srq_table
.table
);
1281 mlx4_cleanup_icm_table(dev
, &priv
->cq_table
.table
);
1282 mlx4_cleanup_icm_table(dev
, &priv
->qp_table
.rdmarc_table
);
1283 mlx4_cleanup_icm_table(dev
, &priv
->qp_table
.altc_table
);
1284 mlx4_cleanup_icm_table(dev
, &priv
->qp_table
.auxc_table
);
1285 mlx4_cleanup_icm_table(dev
, &priv
->qp_table
.qp_table
);
1286 mlx4_cleanup_icm_table(dev
, &priv
->mr_table
.dmpt_table
);
1287 mlx4_cleanup_icm_table(dev
, &priv
->mr_table
.mtt_table
);
1288 mlx4_cleanup_icm_table(dev
, &priv
->eq_table
.table
);
1289 mlx4_cleanup_icm_table(dev
, &priv
->eq_table
.cmpt_table
);
1290 mlx4_cleanup_icm_table(dev
, &priv
->cq_table
.cmpt_table
);
1291 mlx4_cleanup_icm_table(dev
, &priv
->srq_table
.cmpt_table
);
1292 mlx4_cleanup_icm_table(dev
, &priv
->qp_table
.cmpt_table
);
1294 mlx4_UNMAP_ICM_AUX(dev
);
1295 mlx4_free_icm(dev
, priv
->fw
.aux_icm
, 0);
1298 static void mlx4_slave_exit(struct mlx4_dev
*dev
)
1300 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1302 mutex_lock(&priv
->cmd
.slave_cmd_mutex
);
1303 if (mlx4_comm_cmd(dev
, MLX4_COMM_CMD_RESET
, 0, MLX4_COMM_TIME
))
1304 mlx4_warn(dev
, "Failed to close slave function\n");
1305 mutex_unlock(&priv
->cmd
.slave_cmd_mutex
);
1308 static int map_bf_area(struct mlx4_dev
*dev
)
1310 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1311 resource_size_t bf_start
;
1312 resource_size_t bf_len
;
1315 if (!dev
->caps
.bf_reg_size
)
1318 bf_start
= pci_resource_start(dev
->pdev
, 2) +
1319 (dev
->caps
.num_uars
<< PAGE_SHIFT
);
1320 bf_len
= pci_resource_len(dev
->pdev
, 2) -
1321 (dev
->caps
.num_uars
<< PAGE_SHIFT
);
1322 priv
->bf_mapping
= io_mapping_create_wc(bf_start
, bf_len
);
1323 if (!priv
->bf_mapping
)
1329 static void unmap_bf_area(struct mlx4_dev
*dev
)
1331 if (mlx4_priv(dev
)->bf_mapping
)
1332 io_mapping_free(mlx4_priv(dev
)->bf_mapping
);
1335 cycle_t
mlx4_read_clock(struct mlx4_dev
*dev
)
1337 u32 clockhi
, clocklo
, clockhi1
;
1340 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1342 for (i
= 0; i
< 10; i
++) {
1343 clockhi
= swab32(readl(priv
->clock_mapping
));
1344 clocklo
= swab32(readl(priv
->clock_mapping
+ 4));
1345 clockhi1
= swab32(readl(priv
->clock_mapping
));
1346 if (clockhi
== clockhi1
)
1350 cycles
= (u64
) clockhi
<< 32 | (u64
) clocklo
;
1354 EXPORT_SYMBOL_GPL(mlx4_read_clock
);
1357 static int map_internal_clock(struct mlx4_dev
*dev
)
1359 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1361 priv
->clock_mapping
=
1362 ioremap(pci_resource_start(dev
->pdev
, priv
->fw
.clock_bar
) +
1363 priv
->fw
.clock_offset
, MLX4_CLOCK_SIZE
);
1365 if (!priv
->clock_mapping
)
1371 static void unmap_internal_clock(struct mlx4_dev
*dev
)
1373 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1375 if (priv
->clock_mapping
)
1376 iounmap(priv
->clock_mapping
);
1379 static void mlx4_close_hca(struct mlx4_dev
*dev
)
1381 unmap_internal_clock(dev
);
1383 if (mlx4_is_slave(dev
))
1384 mlx4_slave_exit(dev
);
1386 mlx4_CLOSE_HCA(dev
, 0);
1387 mlx4_free_icms(dev
);
1389 mlx4_free_icm(dev
, mlx4_priv(dev
)->fw
.fw_icm
, 0);
1393 static int mlx4_init_slave(struct mlx4_dev
*dev
)
1395 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1396 u64 dma
= (u64
) priv
->mfunc
.vhcr_dma
;
1397 int ret_from_reset
= 0;
1399 u32 cmd_channel_ver
;
1401 if (atomic_read(&pf_loading
)) {
1402 mlx4_warn(dev
, "PF is not ready - Deferring probe\n");
1403 return -EPROBE_DEFER
;
1406 mutex_lock(&priv
->cmd
.slave_cmd_mutex
);
1407 priv
->cmd
.max_cmds
= 1;
1408 mlx4_warn(dev
, "Sending reset\n");
1409 ret_from_reset
= mlx4_comm_cmd(dev
, MLX4_COMM_CMD_RESET
, 0,
1411 /* if we are in the middle of flr the slave will try
1412 * NUM_OF_RESET_RETRIES times before leaving.*/
1413 if (ret_from_reset
) {
1414 if (MLX4_DELAY_RESET_SLAVE
== ret_from_reset
) {
1415 mlx4_warn(dev
, "slave is currently in the middle of FLR - Deferring probe\n");
1416 mutex_unlock(&priv
->cmd
.slave_cmd_mutex
);
1417 return -EPROBE_DEFER
;
1422 /* check the driver version - the slave I/F revision
1423 * must match the master's */
1424 slave_read
= swab32(readl(&priv
->mfunc
.comm
->slave_read
));
1425 cmd_channel_ver
= mlx4_comm_get_version();
1427 if (MLX4_COMM_GET_IF_REV(cmd_channel_ver
) !=
1428 MLX4_COMM_GET_IF_REV(slave_read
)) {
1429 mlx4_err(dev
, "slave driver version is not supported by the master\n");
1433 mlx4_warn(dev
, "Sending vhcr0\n");
1434 if (mlx4_comm_cmd(dev
, MLX4_COMM_CMD_VHCR0
, dma
>> 48,
1437 if (mlx4_comm_cmd(dev
, MLX4_COMM_CMD_VHCR1
, dma
>> 32,
1440 if (mlx4_comm_cmd(dev
, MLX4_COMM_CMD_VHCR2
, dma
>> 16,
1443 if (mlx4_comm_cmd(dev
, MLX4_COMM_CMD_VHCR_EN
, dma
, MLX4_COMM_TIME
))
1446 mutex_unlock(&priv
->cmd
.slave_cmd_mutex
);
1450 mlx4_comm_cmd(dev
, MLX4_COMM_CMD_RESET
, 0, 0);
1451 mutex_unlock(&priv
->cmd
.slave_cmd_mutex
);
1455 static void mlx4_parav_master_pf_caps(struct mlx4_dev
*dev
)
1459 for (i
= 1; i
<= dev
->caps
.num_ports
; i
++) {
1460 if (dev
->caps
.port_type
[i
] == MLX4_PORT_TYPE_ETH
)
1461 dev
->caps
.gid_table_len
[i
] =
1462 mlx4_get_slave_num_gids(dev
, 0, i
);
1464 dev
->caps
.gid_table_len
[i
] = 1;
1465 dev
->caps
.pkey_table_len
[i
] =
1466 dev
->phys_caps
.pkey_phys_table_len
[i
] - 1;
1470 static int choose_log_fs_mgm_entry_size(int qp_per_entry
)
1472 int i
= MLX4_MIN_MGM_LOG_ENTRY_SIZE
;
1474 for (i
= MLX4_MIN_MGM_LOG_ENTRY_SIZE
; i
<= MLX4_MAX_MGM_LOG_ENTRY_SIZE
;
1476 if (qp_per_entry
<= 4 * ((1 << i
) / 16 - 2))
1480 return (i
<= MLX4_MAX_MGM_LOG_ENTRY_SIZE
) ? i
: -1;
1483 static void choose_steering_mode(struct mlx4_dev
*dev
,
1484 struct mlx4_dev_cap
*dev_cap
)
1486 if (mlx4_log_num_mgm_entry_size
== -1 &&
1487 dev_cap
->flags2
& MLX4_DEV_CAP_FLAG2_FS_EN
&&
1488 (!mlx4_is_mfunc(dev
) ||
1489 (dev_cap
->fs_max_num_qp_per_entry
>= (dev
->num_vfs
+ 1))) &&
1490 choose_log_fs_mgm_entry_size(dev_cap
->fs_max_num_qp_per_entry
) >=
1491 MLX4_MIN_MGM_LOG_ENTRY_SIZE
) {
1492 dev
->oper_log_mgm_entry_size
=
1493 choose_log_fs_mgm_entry_size(dev_cap
->fs_max_num_qp_per_entry
);
1494 dev
->caps
.steering_mode
= MLX4_STEERING_MODE_DEVICE_MANAGED
;
1495 dev
->caps
.num_qp_per_mgm
= dev_cap
->fs_max_num_qp_per_entry
;
1496 dev
->caps
.fs_log_max_ucast_qp_range_size
=
1497 dev_cap
->fs_log_max_ucast_qp_range_size
;
1499 if (dev
->caps
.flags
& MLX4_DEV_CAP_FLAG_VEP_UC_STEER
&&
1500 dev
->caps
.flags
& MLX4_DEV_CAP_FLAG_VEP_MC_STEER
)
1501 dev
->caps
.steering_mode
= MLX4_STEERING_MODE_B0
;
1503 dev
->caps
.steering_mode
= MLX4_STEERING_MODE_A0
;
1505 if (dev
->caps
.flags
& MLX4_DEV_CAP_FLAG_VEP_UC_STEER
||
1506 dev
->caps
.flags
& MLX4_DEV_CAP_FLAG_VEP_MC_STEER
)
1507 mlx4_warn(dev
, "Must have both UC_STEER and MC_STEER flags set to use B0 steering - falling back to A0 steering mode\n");
1509 dev
->oper_log_mgm_entry_size
=
1510 mlx4_log_num_mgm_entry_size
> 0 ?
1511 mlx4_log_num_mgm_entry_size
:
1512 MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE
;
1513 dev
->caps
.num_qp_per_mgm
= mlx4_get_qp_per_mgm(dev
);
1515 mlx4_dbg(dev
, "Steering mode is: %s, oper_log_mgm_entry_size = %d, modparam log_num_mgm_entry_size = %d\n",
1516 mlx4_steering_mode_str(dev
->caps
.steering_mode
),
1517 dev
->oper_log_mgm_entry_size
,
1518 mlx4_log_num_mgm_entry_size
);
1521 static void choose_tunnel_offload_mode(struct mlx4_dev
*dev
,
1522 struct mlx4_dev_cap
*dev_cap
)
1524 if (dev
->caps
.steering_mode
== MLX4_STEERING_MODE_DEVICE_MANAGED
&&
1525 dev_cap
->flags2
& MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS
)
1526 dev
->caps
.tunnel_offload_mode
= MLX4_TUNNEL_OFFLOAD_MODE_VXLAN
;
1528 dev
->caps
.tunnel_offload_mode
= MLX4_TUNNEL_OFFLOAD_MODE_NONE
;
1530 mlx4_dbg(dev
, "Tunneling offload mode is: %s\n", (dev
->caps
.tunnel_offload_mode
1531 == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN
) ? "vxlan" : "none");
1534 static int mlx4_init_hca(struct mlx4_dev
*dev
)
1536 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1537 struct mlx4_adapter adapter
;
1538 struct mlx4_dev_cap dev_cap
;
1539 struct mlx4_mod_stat_cfg mlx4_cfg
;
1540 struct mlx4_profile profile
;
1541 struct mlx4_init_hca_param init_hca
;
1545 if (!mlx4_is_slave(dev
)) {
1546 err
= mlx4_QUERY_FW(dev
);
1549 mlx4_info(dev
, "non-primary physical function, skipping\n");
1551 mlx4_err(dev
, "QUERY_FW command failed, aborting\n");
1555 err
= mlx4_load_fw(dev
);
1557 mlx4_err(dev
, "Failed to start FW, aborting\n");
1561 mlx4_cfg
.log_pg_sz_m
= 1;
1562 mlx4_cfg
.log_pg_sz
= 0;
1563 err
= mlx4_MOD_STAT_CFG(dev
, &mlx4_cfg
);
1565 mlx4_warn(dev
, "Failed to override log_pg_sz parameter\n");
1567 err
= mlx4_dev_cap(dev
, &dev_cap
);
1569 mlx4_err(dev
, "QUERY_DEV_CAP command failed, aborting\n");
1573 choose_steering_mode(dev
, &dev_cap
);
1574 choose_tunnel_offload_mode(dev
, &dev_cap
);
1576 err
= mlx4_get_phys_port_id(dev
);
1578 mlx4_err(dev
, "Fail to get physical port id\n");
1580 if (mlx4_is_master(dev
))
1581 mlx4_parav_master_pf_caps(dev
);
1583 profile
= default_profile
;
1584 if (dev
->caps
.steering_mode
==
1585 MLX4_STEERING_MODE_DEVICE_MANAGED
)
1586 profile
.num_mcg
= MLX4_FS_NUM_MCG
;
1588 icm_size
= mlx4_make_profile(dev
, &profile
, &dev_cap
,
1590 if ((long long) icm_size
< 0) {
1595 dev
->caps
.max_fmr_maps
= (1 << (32 - ilog2(dev
->caps
.num_mpts
))) - 1;
1597 init_hca
.log_uar_sz
= ilog2(dev
->caps
.num_uars
);
1598 init_hca
.uar_page_sz
= PAGE_SHIFT
- 12;
1599 init_hca
.mw_enabled
= 0;
1600 if (dev
->caps
.flags
& MLX4_DEV_CAP_FLAG_MEM_WINDOW
||
1601 dev
->caps
.bmme_flags
& MLX4_BMME_FLAG_TYPE_2_WIN
)
1602 init_hca
.mw_enabled
= INIT_HCA_TPT_MW_ENABLE
;
1604 err
= mlx4_init_icm(dev
, &dev_cap
, &init_hca
, icm_size
);
1608 err
= mlx4_INIT_HCA(dev
, &init_hca
);
1610 mlx4_err(dev
, "INIT_HCA command failed, aborting\n");
1614 * If TS is supported by FW
1615 * read HCA frequency by QUERY_HCA command
1617 if (dev
->caps
.flags2
& MLX4_DEV_CAP_FLAG2_TS
) {
1618 memset(&init_hca
, 0, sizeof(init_hca
));
1619 err
= mlx4_QUERY_HCA(dev
, &init_hca
);
1621 mlx4_err(dev
, "QUERY_HCA command failed, disable timestamp\n");
1622 dev
->caps
.flags2
&= ~MLX4_DEV_CAP_FLAG2_TS
;
1624 dev
->caps
.hca_core_clock
=
1625 init_hca
.hca_core_clock
;
1628 /* In case we got HCA frequency 0 - disable timestamping
1629 * to avoid dividing by zero
1631 if (!dev
->caps
.hca_core_clock
) {
1632 dev
->caps
.flags2
&= ~MLX4_DEV_CAP_FLAG2_TS
;
1634 "HCA frequency is 0 - timestamping is not supported\n");
1635 } else if (map_internal_clock(dev
)) {
1637 * Map internal clock,
1638 * in case of failure disable timestamping
1640 dev
->caps
.flags2
&= ~MLX4_DEV_CAP_FLAG2_TS
;
1641 mlx4_err(dev
, "Failed to map internal clock. Timestamping is not supported\n");
1645 err
= mlx4_init_slave(dev
);
1647 if (err
!= -EPROBE_DEFER
)
1648 mlx4_err(dev
, "Failed to initialize slave\n");
1652 err
= mlx4_slave_cap(dev
);
1654 mlx4_err(dev
, "Failed to obtain slave caps\n");
1659 if (map_bf_area(dev
))
1660 mlx4_dbg(dev
, "Failed to map blue flame area\n");
1662 /*Only the master set the ports, all the rest got it from it.*/
1663 if (!mlx4_is_slave(dev
))
1664 mlx4_set_port_mask(dev
);
1666 err
= mlx4_QUERY_ADAPTER(dev
, &adapter
);
1668 mlx4_err(dev
, "QUERY_ADAPTER command failed, aborting\n");
1672 priv
->eq_table
.inta_pin
= adapter
.inta_pin
;
1673 memcpy(dev
->board_id
, adapter
.board_id
, sizeof dev
->board_id
);
1678 unmap_internal_clock(dev
);
1682 if (mlx4_is_slave(dev
))
1683 mlx4_slave_exit(dev
);
1685 mlx4_CLOSE_HCA(dev
, 0);
1688 if (!mlx4_is_slave(dev
))
1689 mlx4_free_icms(dev
);
1692 if (!mlx4_is_slave(dev
)) {
1694 mlx4_free_icm(dev
, priv
->fw
.fw_icm
, 0);
1699 static int mlx4_init_counters_table(struct mlx4_dev
*dev
)
1701 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1704 if (!(dev
->caps
.flags
& MLX4_DEV_CAP_FLAG_COUNTERS
))
1707 nent
= dev
->caps
.max_counters
;
1708 return mlx4_bitmap_init(&priv
->counters_bitmap
, nent
, nent
- 1, 0, 0);
1711 static void mlx4_cleanup_counters_table(struct mlx4_dev
*dev
)
1713 mlx4_bitmap_cleanup(&mlx4_priv(dev
)->counters_bitmap
);
1716 int __mlx4_counter_alloc(struct mlx4_dev
*dev
, u32
*idx
)
1718 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1720 if (!(dev
->caps
.flags
& MLX4_DEV_CAP_FLAG_COUNTERS
))
1723 *idx
= mlx4_bitmap_alloc(&priv
->counters_bitmap
);
1730 int mlx4_counter_alloc(struct mlx4_dev
*dev
, u32
*idx
)
1735 if (mlx4_is_mfunc(dev
)) {
1736 err
= mlx4_cmd_imm(dev
, 0, &out_param
, RES_COUNTER
,
1737 RES_OP_RESERVE
, MLX4_CMD_ALLOC_RES
,
1738 MLX4_CMD_TIME_CLASS_A
, MLX4_CMD_WRAPPED
);
1740 *idx
= get_param_l(&out_param
);
1744 return __mlx4_counter_alloc(dev
, idx
);
1746 EXPORT_SYMBOL_GPL(mlx4_counter_alloc
);
1748 void __mlx4_counter_free(struct mlx4_dev
*dev
, u32 idx
)
1750 mlx4_bitmap_free(&mlx4_priv(dev
)->counters_bitmap
, idx
, MLX4_USE_RR
);
1754 void mlx4_counter_free(struct mlx4_dev
*dev
, u32 idx
)
1758 if (mlx4_is_mfunc(dev
)) {
1759 set_param_l(&in_param
, idx
);
1760 mlx4_cmd(dev
, in_param
, RES_COUNTER
, RES_OP_RESERVE
,
1761 MLX4_CMD_FREE_RES
, MLX4_CMD_TIME_CLASS_A
,
1765 __mlx4_counter_free(dev
, idx
);
1767 EXPORT_SYMBOL_GPL(mlx4_counter_free
);
1769 static int mlx4_setup_hca(struct mlx4_dev
*dev
)
1771 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1774 __be32 ib_port_default_caps
;
1776 err
= mlx4_init_uar_table(dev
);
1778 mlx4_err(dev
, "Failed to initialize user access region table, aborting\n");
1782 err
= mlx4_uar_alloc(dev
, &priv
->driver_uar
);
1784 mlx4_err(dev
, "Failed to allocate driver access region, aborting\n");
1785 goto err_uar_table_free
;
1788 priv
->kar
= ioremap((phys_addr_t
) priv
->driver_uar
.pfn
<< PAGE_SHIFT
, PAGE_SIZE
);
1790 mlx4_err(dev
, "Couldn't map kernel access region, aborting\n");
1795 err
= mlx4_init_pd_table(dev
);
1797 mlx4_err(dev
, "Failed to initialize protection domain table, aborting\n");
1801 err
= mlx4_init_xrcd_table(dev
);
1803 mlx4_err(dev
, "Failed to initialize reliable connection domain table, aborting\n");
1804 goto err_pd_table_free
;
1807 err
= mlx4_init_mr_table(dev
);
1809 mlx4_err(dev
, "Failed to initialize memory region table, aborting\n");
1810 goto err_xrcd_table_free
;
1813 if (!mlx4_is_slave(dev
)) {
1814 err
= mlx4_init_mcg_table(dev
);
1816 mlx4_err(dev
, "Failed to initialize multicast group table, aborting\n");
1817 goto err_mr_table_free
;
1821 err
= mlx4_init_eq_table(dev
);
1823 mlx4_err(dev
, "Failed to initialize event queue table, aborting\n");
1824 goto err_mcg_table_free
;
1827 err
= mlx4_cmd_use_events(dev
);
1829 mlx4_err(dev
, "Failed to switch to event-driven firmware commands, aborting\n");
1830 goto err_eq_table_free
;
1833 err
= mlx4_NOP(dev
);
1835 if (dev
->flags
& MLX4_FLAG_MSI_X
) {
1836 mlx4_warn(dev
, "NOP command failed to generate MSI-X interrupt IRQ %d)\n",
1837 priv
->eq_table
.eq
[dev
->caps
.num_comp_vectors
].irq
);
1838 mlx4_warn(dev
, "Trying again without MSI-X\n");
1840 mlx4_err(dev
, "NOP command failed to generate interrupt (IRQ %d), aborting\n",
1841 priv
->eq_table
.eq
[dev
->caps
.num_comp_vectors
].irq
);
1842 mlx4_err(dev
, "BIOS or ACPI interrupt routing problem?\n");
1848 mlx4_dbg(dev
, "NOP command IRQ test passed\n");
1850 err
= mlx4_init_cq_table(dev
);
1852 mlx4_err(dev
, "Failed to initialize completion queue table, aborting\n");
1856 err
= mlx4_init_srq_table(dev
);
1858 mlx4_err(dev
, "Failed to initialize shared receive queue table, aborting\n");
1859 goto err_cq_table_free
;
1862 err
= mlx4_init_qp_table(dev
);
1864 mlx4_err(dev
, "Failed to initialize queue pair table, aborting\n");
1865 goto err_srq_table_free
;
1868 err
= mlx4_init_counters_table(dev
);
1869 if (err
&& err
!= -ENOENT
) {
1870 mlx4_err(dev
, "Failed to initialize counters table, aborting\n");
1871 goto err_qp_table_free
;
1874 if (!mlx4_is_slave(dev
)) {
1875 for (port
= 1; port
<= dev
->caps
.num_ports
; port
++) {
1876 ib_port_default_caps
= 0;
1877 err
= mlx4_get_port_ib_caps(dev
, port
,
1878 &ib_port_default_caps
);
1880 mlx4_warn(dev
, "failed to get port %d default ib capabilities (%d). Continuing with caps = 0\n",
1882 dev
->caps
.ib_port_def_cap
[port
] = ib_port_default_caps
;
1884 /* initialize per-slave default ib port capabilities */
1885 if (mlx4_is_master(dev
)) {
1887 for (i
= 0; i
< dev
->num_slaves
; i
++) {
1888 if (i
== mlx4_master_func_num(dev
))
1890 priv
->mfunc
.master
.slave_state
[i
].ib_cap_mask
[port
] =
1891 ib_port_default_caps
;
1895 if (mlx4_is_mfunc(dev
))
1896 dev
->caps
.port_ib_mtu
[port
] = IB_MTU_2048
;
1898 dev
->caps
.port_ib_mtu
[port
] = IB_MTU_4096
;
1900 err
= mlx4_SET_PORT(dev
, port
, mlx4_is_master(dev
) ?
1901 dev
->caps
.pkey_table_len
[port
] : -1);
1903 mlx4_err(dev
, "Failed to set port %d, aborting\n",
1905 goto err_counters_table_free
;
1912 err_counters_table_free
:
1913 mlx4_cleanup_counters_table(dev
);
1916 mlx4_cleanup_qp_table(dev
);
1919 mlx4_cleanup_srq_table(dev
);
1922 mlx4_cleanup_cq_table(dev
);
1925 mlx4_cmd_use_polling(dev
);
1928 mlx4_cleanup_eq_table(dev
);
1931 if (!mlx4_is_slave(dev
))
1932 mlx4_cleanup_mcg_table(dev
);
1935 mlx4_cleanup_mr_table(dev
);
1937 err_xrcd_table_free
:
1938 mlx4_cleanup_xrcd_table(dev
);
1941 mlx4_cleanup_pd_table(dev
);
1947 mlx4_uar_free(dev
, &priv
->driver_uar
);
1950 mlx4_cleanup_uar_table(dev
);
1954 static void mlx4_enable_msi_x(struct mlx4_dev
*dev
)
1956 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1957 struct msix_entry
*entries
;
1958 int nreq
= min_t(int, dev
->caps
.num_ports
*
1959 min_t(int, num_online_cpus() + 1,
1960 MAX_MSIX_P_PORT
) + MSIX_LEGACY_SZ
, MAX_MSIX
);
1964 nreq
= min_t(int, dev
->caps
.num_eqs
- dev
->caps
.reserved_eqs
,
1967 entries
= kcalloc(nreq
, sizeof *entries
, GFP_KERNEL
);
1971 for (i
= 0; i
< nreq
; ++i
)
1972 entries
[i
].entry
= i
;
1974 nreq
= pci_enable_msix_range(dev
->pdev
, entries
, 2, nreq
);
1979 } else if (nreq
< MSIX_LEGACY_SZ
+
1980 dev
->caps
.num_ports
* MIN_MSIX_P_PORT
) {
1981 /*Working in legacy mode , all EQ's shared*/
1982 dev
->caps
.comp_pool
= 0;
1983 dev
->caps
.num_comp_vectors
= nreq
- 1;
1985 dev
->caps
.comp_pool
= nreq
- MSIX_LEGACY_SZ
;
1986 dev
->caps
.num_comp_vectors
= MSIX_LEGACY_SZ
- 1;
1988 for (i
= 0; i
< nreq
; ++i
)
1989 priv
->eq_table
.eq
[i
].irq
= entries
[i
].vector
;
1991 dev
->flags
|= MLX4_FLAG_MSI_X
;
1998 dev
->caps
.num_comp_vectors
= 1;
1999 dev
->caps
.comp_pool
= 0;
2001 for (i
= 0; i
< 2; ++i
)
2002 priv
->eq_table
.eq
[i
].irq
= dev
->pdev
->irq
;
2005 static int mlx4_init_port_info(struct mlx4_dev
*dev
, int port
)
2007 struct mlx4_port_info
*info
= &mlx4_priv(dev
)->port
[port
];
2012 if (!mlx4_is_slave(dev
)) {
2013 mlx4_init_mac_table(dev
, &info
->mac_table
);
2014 mlx4_init_vlan_table(dev
, &info
->vlan_table
);
2015 info
->base_qpn
= mlx4_get_base_qpn(dev
, port
);
2018 sprintf(info
->dev_name
, "mlx4_port%d", port
);
2019 info
->port_attr
.attr
.name
= info
->dev_name
;
2020 if (mlx4_is_mfunc(dev
))
2021 info
->port_attr
.attr
.mode
= S_IRUGO
;
2023 info
->port_attr
.attr
.mode
= S_IRUGO
| S_IWUSR
;
2024 info
->port_attr
.store
= set_port_type
;
2026 info
->port_attr
.show
= show_port_type
;
2027 sysfs_attr_init(&info
->port_attr
.attr
);
2029 err
= device_create_file(&dev
->pdev
->dev
, &info
->port_attr
);
2031 mlx4_err(dev
, "Failed to create file for port %d\n", port
);
2035 sprintf(info
->dev_mtu_name
, "mlx4_port%d_mtu", port
);
2036 info
->port_mtu_attr
.attr
.name
= info
->dev_mtu_name
;
2037 if (mlx4_is_mfunc(dev
))
2038 info
->port_mtu_attr
.attr
.mode
= S_IRUGO
;
2040 info
->port_mtu_attr
.attr
.mode
= S_IRUGO
| S_IWUSR
;
2041 info
->port_mtu_attr
.store
= set_port_ib_mtu
;
2043 info
->port_mtu_attr
.show
= show_port_ib_mtu
;
2044 sysfs_attr_init(&info
->port_mtu_attr
.attr
);
2046 err
= device_create_file(&dev
->pdev
->dev
, &info
->port_mtu_attr
);
2048 mlx4_err(dev
, "Failed to create mtu file for port %d\n", port
);
2049 device_remove_file(&info
->dev
->pdev
->dev
, &info
->port_attr
);
2056 static void mlx4_cleanup_port_info(struct mlx4_port_info
*info
)
2061 device_remove_file(&info
->dev
->pdev
->dev
, &info
->port_attr
);
2062 device_remove_file(&info
->dev
->pdev
->dev
, &info
->port_mtu_attr
);
2065 static int mlx4_init_steering(struct mlx4_dev
*dev
)
2067 struct mlx4_priv
*priv
= mlx4_priv(dev
);
2068 int num_entries
= dev
->caps
.num_ports
;
2071 priv
->steer
= kzalloc(sizeof(struct mlx4_steer
) * num_entries
, GFP_KERNEL
);
2075 for (i
= 0; i
< num_entries
; i
++)
2076 for (j
= 0; j
< MLX4_NUM_STEERS
; j
++) {
2077 INIT_LIST_HEAD(&priv
->steer
[i
].promisc_qps
[j
]);
2078 INIT_LIST_HEAD(&priv
->steer
[i
].steer_entries
[j
]);
2083 static void mlx4_clear_steering(struct mlx4_dev
*dev
)
2085 struct mlx4_priv
*priv
= mlx4_priv(dev
);
2086 struct mlx4_steer_index
*entry
, *tmp_entry
;
2087 struct mlx4_promisc_qp
*pqp
, *tmp_pqp
;
2088 int num_entries
= dev
->caps
.num_ports
;
2091 for (i
= 0; i
< num_entries
; i
++) {
2092 for (j
= 0; j
< MLX4_NUM_STEERS
; j
++) {
2093 list_for_each_entry_safe(pqp
, tmp_pqp
,
2094 &priv
->steer
[i
].promisc_qps
[j
],
2096 list_del(&pqp
->list
);
2099 list_for_each_entry_safe(entry
, tmp_entry
,
2100 &priv
->steer
[i
].steer_entries
[j
],
2102 list_del(&entry
->list
);
2103 list_for_each_entry_safe(pqp
, tmp_pqp
,
2106 list_del(&pqp
->list
);
2116 static int extended_func_num(struct pci_dev
*pdev
)
2118 return PCI_SLOT(pdev
->devfn
) * 8 + PCI_FUNC(pdev
->devfn
);
2121 #define MLX4_OWNER_BASE 0x8069c
2122 #define MLX4_OWNER_SIZE 4
2124 static int mlx4_get_ownership(struct mlx4_dev
*dev
)
2126 void __iomem
*owner
;
2129 if (pci_channel_offline(dev
->pdev
))
2132 owner
= ioremap(pci_resource_start(dev
->pdev
, 0) + MLX4_OWNER_BASE
,
2135 mlx4_err(dev
, "Failed to obtain ownership bit\n");
2144 static void mlx4_free_ownership(struct mlx4_dev
*dev
)
2146 void __iomem
*owner
;
2148 if (pci_channel_offline(dev
->pdev
))
2151 owner
= ioremap(pci_resource_start(dev
->pdev
, 0) + MLX4_OWNER_BASE
,
2154 mlx4_err(dev
, "Failed to obtain ownership bit\n");
2162 static int __mlx4_init_one(struct pci_dev
*pdev
, int pci_dev_data
)
2164 struct mlx4_priv
*priv
;
2165 struct mlx4_dev
*dev
;
2168 int nvfs
[MLX4_MAX_PORTS
+ 1] = {0, 0, 0};
2169 int prb_vf
[MLX4_MAX_PORTS
+ 1] = {0, 0, 0};
2170 const int param_map
[MLX4_MAX_PORTS
+ 1][MLX4_MAX_PORTS
+ 1] = {
2171 {2, 0, 0}, {0, 1, 2}, {0, 1, 2} };
2172 unsigned total_vfs
= 0;
2173 int sriov_initialized
= 0;
2176 pr_info(DRV_NAME
": Initializing %s\n", pci_name(pdev
));
2178 err
= pci_enable_device(pdev
);
2180 dev_err(&pdev
->dev
, "Cannot enable PCI device, aborting\n");
2184 /* Due to requirement that all VFs and the PF are *guaranteed* 2 MACS
2185 * per port, we must limit the number of VFs to 63 (since their are
2188 for (i
= 0; i
< sizeof(nvfs
)/sizeof(nvfs
[0]) && i
< num_vfs_argc
;
2189 total_vfs
+= nvfs
[param_map
[num_vfs_argc
- 1][i
]], i
++) {
2190 nvfs
[param_map
[num_vfs_argc
- 1][i
]] = num_vfs
[i
];
2192 dev_err(&pdev
->dev
, "num_vfs module parameter cannot be negative\n");
2196 for (i
= 0; i
< sizeof(prb_vf
)/sizeof(prb_vf
[0]) && i
< probe_vfs_argc
;
2198 prb_vf
[param_map
[probe_vfs_argc
- 1][i
]] = probe_vf
[i
];
2199 if (prb_vf
[i
] < 0 || prb_vf
[i
] > nvfs
[i
]) {
2200 dev_err(&pdev
->dev
, "probe_vf module parameter cannot be negative or greater than num_vfs\n");
2204 if (total_vfs
>= MLX4_MAX_NUM_VF
) {
2206 "Requested more VF's (%d) than allowed (%d)\n",
2207 total_vfs
, MLX4_MAX_NUM_VF
- 1);
2211 for (i
= 0; i
< MLX4_MAX_PORTS
; i
++) {
2212 if (nvfs
[i
] + nvfs
[2] >= MLX4_MAX_NUM_VF_P_PORT
) {
2214 "Requested more VF's (%d) for port (%d) than allowed (%d)\n",
2215 nvfs
[i
] + nvfs
[2], i
+ 1,
2216 MLX4_MAX_NUM_VF_P_PORT
- 1);
2225 if (!(pci_dev_data
& MLX4_PCI_DEV_IS_VF
) &&
2226 !(pci_resource_flags(pdev
, 0) & IORESOURCE_MEM
)) {
2227 dev_err(&pdev
->dev
, "Missing DCS, aborting (driver_data: 0x%x, pci_resource_flags(pdev, 0):0x%lx)\n",
2228 pci_dev_data
, pci_resource_flags(pdev
, 0));
2230 goto err_disable_pdev
;
2232 if (!(pci_resource_flags(pdev
, 2) & IORESOURCE_MEM
)) {
2233 dev_err(&pdev
->dev
, "Missing UAR, aborting\n");
2235 goto err_disable_pdev
;
2238 err
= pci_request_regions(pdev
, DRV_NAME
);
2240 dev_err(&pdev
->dev
, "Couldn't get PCI resources, aborting\n");
2241 goto err_disable_pdev
;
2244 pci_set_master(pdev
);
2246 err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(64));
2248 dev_warn(&pdev
->dev
, "Warning: couldn't set 64-bit PCI DMA mask\n");
2249 err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
2251 dev_err(&pdev
->dev
, "Can't set PCI DMA mask, aborting\n");
2252 goto err_release_regions
;
2255 err
= pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(64));
2257 dev_warn(&pdev
->dev
, "Warning: couldn't set 64-bit consistent PCI DMA mask\n");
2258 err
= pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(32));
2260 dev_err(&pdev
->dev
, "Can't set consistent PCI DMA mask, aborting\n");
2261 goto err_release_regions
;
2265 /* Allow large DMA segments, up to the firmware limit of 1 GB */
2266 dma_set_max_seg_size(&pdev
->dev
, 1024 * 1024 * 1024);
2268 dev
= pci_get_drvdata(pdev
);
2269 priv
= mlx4_priv(dev
);
2271 INIT_LIST_HEAD(&priv
->ctx_list
);
2272 spin_lock_init(&priv
->ctx_lock
);
2274 mutex_init(&priv
->port_mutex
);
2276 INIT_LIST_HEAD(&priv
->pgdir_list
);
2277 mutex_init(&priv
->pgdir_mutex
);
2279 INIT_LIST_HEAD(&priv
->bf_list
);
2280 mutex_init(&priv
->bf_mutex
);
2282 dev
->rev_id
= pdev
->revision
;
2283 dev
->numa_node
= dev_to_node(&pdev
->dev
);
2284 /* Detect if this device is a virtual function */
2285 if (pci_dev_data
& MLX4_PCI_DEV_IS_VF
) {
2286 /* When acting as pf, we normally skip vfs unless explicitly
2287 * requested to probe them. */
2289 unsigned vfs_offset
= 0;
2290 for (i
= 0; i
< sizeof(nvfs
)/sizeof(nvfs
[0]) &&
2291 vfs_offset
+ nvfs
[i
] < extended_func_num(pdev
);
2292 vfs_offset
+= nvfs
[i
], i
++)
2294 if (i
== sizeof(nvfs
)/sizeof(nvfs
[0])) {
2298 if ((extended_func_num(pdev
) - vfs_offset
)
2300 mlx4_warn(dev
, "Skipping virtual function:%d\n",
2301 extended_func_num(pdev
));
2306 mlx4_warn(dev
, "Detected virtual function - running in slave mode\n");
2307 dev
->flags
|= MLX4_FLAG_SLAVE
;
2309 /* We reset the device and enable SRIOV only for physical
2310 * devices. Try to claim ownership on the device;
2311 * if already taken, skip -- do not allow multiple PFs */
2312 err
= mlx4_get_ownership(dev
);
2317 mlx4_warn(dev
, "Multiple PFs not yet supported - Skipping PF\n");
2324 mlx4_warn(dev
, "Enabling SR-IOV with %d VFs\n",
2326 dev
->dev_vfs
= kzalloc(
2327 total_vfs
* sizeof(*dev
->dev_vfs
),
2329 if (NULL
== dev
->dev_vfs
) {
2330 mlx4_err(dev
, "Failed to allocate memory for VFs\n");
2333 atomic_inc(&pf_loading
);
2334 err
= pci_enable_sriov(pdev
, total_vfs
);
2336 mlx4_err(dev
, "Failed to enable SR-IOV, continuing without SR-IOV (err = %d)\n",
2338 atomic_dec(&pf_loading
);
2341 mlx4_warn(dev
, "Running in master mode\n");
2342 dev
->flags
|= MLX4_FLAG_SRIOV
|
2344 dev
->num_vfs
= total_vfs
;
2345 sriov_initialized
= 1;
2350 atomic_set(&priv
->opreq_count
, 0);
2351 INIT_WORK(&priv
->opreq_task
, mlx4_opreq_action
);
2354 * Now reset the HCA before we touch the PCI capabilities or
2355 * attempt a firmware command, since a boot ROM may have left
2356 * the HCA in an undefined state.
2358 err
= mlx4_reset(dev
);
2360 mlx4_err(dev
, "Failed to reset HCA, aborting\n");
2366 err
= mlx4_cmd_init(dev
);
2368 mlx4_err(dev
, "Failed to init command interface, aborting\n");
2372 /* In slave functions, the communication channel must be initialized
2373 * before posting commands. Also, init num_slaves before calling
2375 if (mlx4_is_mfunc(dev
)) {
2376 if (mlx4_is_master(dev
))
2377 dev
->num_slaves
= MLX4_MAX_NUM_SLAVES
;
2379 dev
->num_slaves
= 0;
2380 err
= mlx4_multi_func_init(dev
);
2382 mlx4_err(dev
, "Failed to init slave mfunc interface, aborting\n");
2388 err
= mlx4_init_hca(dev
);
2390 if (err
== -EACCES
) {
2391 /* Not primary Physical function
2392 * Running in slave mode */
2393 mlx4_cmd_cleanup(dev
);
2394 dev
->flags
|= MLX4_FLAG_SLAVE
;
2395 dev
->flags
&= ~MLX4_FLAG_MASTER
;
2401 /* check if the device is functioning at its maximum possible speed.
2402 * No return code for this call, just warn the user in case of PCI
2403 * express device capabilities are under-satisfied by the bus.
2405 if (!mlx4_is_slave(dev
))
2406 mlx4_check_pcie_caps(dev
);
2408 /* In master functions, the communication channel must be initialized
2409 * after obtaining its address from fw */
2410 if (mlx4_is_master(dev
)) {
2412 err
= mlx4_multi_func_init(dev
);
2414 mlx4_err(dev
, "Failed to init master mfunc interface, aborting\n");
2417 if (sriov_initialized
) {
2419 mlx4_foreach_port(i
, dev
, MLX4_PORT_TYPE_IB
)
2423 (num_vfs_argc
> 1 || probe_vfs_argc
> 1)) {
2425 "Invalid syntax of num_vfs/probe_vfs with IB port - single port VFs syntax is only supported when all ports are configured as ethernet\n");
2428 for (i
= 0; i
< sizeof(nvfs
)/sizeof(nvfs
[0]); i
++) {
2430 for (j
= 0; j
< nvfs
[i
]; ++sum
, ++j
) {
2431 dev
->dev_vfs
[sum
].min_port
=
2433 dev
->dev_vfs
[sum
].n_ports
= i
< 2 ? 1 :
2434 dev
->caps
.num_ports
;
2440 err
= mlx4_alloc_eq_table(dev
);
2442 goto err_master_mfunc
;
2444 priv
->msix_ctl
.pool_bm
= 0;
2445 mutex_init(&priv
->msix_ctl
.pool_lock
);
2447 mlx4_enable_msi_x(dev
);
2448 if ((mlx4_is_mfunc(dev
)) &&
2449 !(dev
->flags
& MLX4_FLAG_MSI_X
)) {
2451 mlx4_err(dev
, "INTx is not supported in multi-function mode, aborting\n");
2455 if (!mlx4_is_slave(dev
)) {
2456 err
= mlx4_init_steering(dev
);
2461 err
= mlx4_setup_hca(dev
);
2462 if (err
== -EBUSY
&& (dev
->flags
& MLX4_FLAG_MSI_X
) &&
2463 !mlx4_is_mfunc(dev
)) {
2464 dev
->flags
&= ~MLX4_FLAG_MSI_X
;
2465 dev
->caps
.num_comp_vectors
= 1;
2466 dev
->caps
.comp_pool
= 0;
2467 pci_disable_msix(pdev
);
2468 err
= mlx4_setup_hca(dev
);
2474 mlx4_init_quotas(dev
);
2476 for (port
= 1; port
<= dev
->caps
.num_ports
; port
++) {
2477 err
= mlx4_init_port_info(dev
, port
);
2482 err
= mlx4_register_device(dev
);
2486 mlx4_request_modules(dev
);
2488 mlx4_sense_init(dev
);
2489 mlx4_start_sense(dev
);
2493 if (mlx4_is_master(dev
) && dev
->num_vfs
)
2494 atomic_dec(&pf_loading
);
2499 for (--port
; port
>= 1; --port
)
2500 mlx4_cleanup_port_info(&priv
->port
[port
]);
2502 mlx4_cleanup_counters_table(dev
);
2503 mlx4_cleanup_qp_table(dev
);
2504 mlx4_cleanup_srq_table(dev
);
2505 mlx4_cleanup_cq_table(dev
);
2506 mlx4_cmd_use_polling(dev
);
2507 mlx4_cleanup_eq_table(dev
);
2508 mlx4_cleanup_mcg_table(dev
);
2509 mlx4_cleanup_mr_table(dev
);
2510 mlx4_cleanup_xrcd_table(dev
);
2511 mlx4_cleanup_pd_table(dev
);
2512 mlx4_cleanup_uar_table(dev
);
2515 if (!mlx4_is_slave(dev
))
2516 mlx4_clear_steering(dev
);
2519 mlx4_free_eq_table(dev
);
2522 if (mlx4_is_master(dev
))
2523 mlx4_multi_func_cleanup(dev
);
2526 if (dev
->flags
& MLX4_FLAG_MSI_X
)
2527 pci_disable_msix(pdev
);
2529 mlx4_close_hca(dev
);
2532 if (mlx4_is_slave(dev
))
2533 mlx4_multi_func_cleanup(dev
);
2536 mlx4_cmd_cleanup(dev
);
2539 if (dev
->flags
& MLX4_FLAG_SRIOV
)
2540 pci_disable_sriov(pdev
);
2543 if (!mlx4_is_slave(dev
))
2544 mlx4_free_ownership(dev
);
2546 if (mlx4_is_master(dev
) && dev
->num_vfs
)
2547 atomic_dec(&pf_loading
);
2549 kfree(priv
->dev
.dev_vfs
);
2554 err_release_regions
:
2555 pci_release_regions(pdev
);
2558 pci_disable_device(pdev
);
2559 pci_set_drvdata(pdev
, NULL
);
2563 static int mlx4_init_one(struct pci_dev
*pdev
, const struct pci_device_id
*id
)
2565 struct mlx4_priv
*priv
;
2566 struct mlx4_dev
*dev
;
2568 printk_once(KERN_INFO
"%s", mlx4_version
);
2570 priv
= kzalloc(sizeof(*priv
), GFP_KERNEL
);
2575 pci_set_drvdata(pdev
, dev
);
2576 priv
->pci_dev_data
= id
->driver_data
;
2578 return __mlx4_init_one(pdev
, id
->driver_data
);
2581 static void __mlx4_remove_one(struct pci_dev
*pdev
)
2583 struct mlx4_dev
*dev
= pci_get_drvdata(pdev
);
2584 struct mlx4_priv
*priv
= mlx4_priv(dev
);
2591 pci_dev_data
= priv
->pci_dev_data
;
2593 /* in SRIOV it is not allowed to unload the pf's
2594 * driver while there are alive vf's */
2595 if (mlx4_is_master(dev
) && mlx4_how_many_lives_vf(dev
))
2596 printk(KERN_ERR
"Removing PF when there are assigned VF's !!!\n");
2597 mlx4_stop_sense(dev
);
2598 mlx4_unregister_device(dev
);
2600 for (p
= 1; p
<= dev
->caps
.num_ports
; p
++) {
2601 mlx4_cleanup_port_info(&priv
->port
[p
]);
2602 mlx4_CLOSE_PORT(dev
, p
);
2605 if (mlx4_is_master(dev
))
2606 mlx4_free_resource_tracker(dev
,
2607 RES_TR_FREE_SLAVES_ONLY
);
2609 mlx4_cleanup_counters_table(dev
);
2610 mlx4_cleanup_qp_table(dev
);
2611 mlx4_cleanup_srq_table(dev
);
2612 mlx4_cleanup_cq_table(dev
);
2613 mlx4_cmd_use_polling(dev
);
2614 mlx4_cleanup_eq_table(dev
);
2615 mlx4_cleanup_mcg_table(dev
);
2616 mlx4_cleanup_mr_table(dev
);
2617 mlx4_cleanup_xrcd_table(dev
);
2618 mlx4_cleanup_pd_table(dev
);
2620 if (mlx4_is_master(dev
))
2621 mlx4_free_resource_tracker(dev
,
2622 RES_TR_FREE_STRUCTS_ONLY
);
2625 mlx4_uar_free(dev
, &priv
->driver_uar
);
2626 mlx4_cleanup_uar_table(dev
);
2627 if (!mlx4_is_slave(dev
))
2628 mlx4_clear_steering(dev
);
2629 mlx4_free_eq_table(dev
);
2630 if (mlx4_is_master(dev
))
2631 mlx4_multi_func_cleanup(dev
);
2632 mlx4_close_hca(dev
);
2633 if (mlx4_is_slave(dev
))
2634 mlx4_multi_func_cleanup(dev
);
2635 mlx4_cmd_cleanup(dev
);
2637 if (dev
->flags
& MLX4_FLAG_MSI_X
)
2638 pci_disable_msix(pdev
);
2639 if (dev
->flags
& MLX4_FLAG_SRIOV
) {
2640 mlx4_warn(dev
, "Disabling SR-IOV\n");
2641 pci_disable_sriov(pdev
);
2645 if (!mlx4_is_slave(dev
))
2646 mlx4_free_ownership(dev
);
2648 kfree(dev
->caps
.qp0_tunnel
);
2649 kfree(dev
->caps
.qp0_proxy
);
2650 kfree(dev
->caps
.qp1_tunnel
);
2651 kfree(dev
->caps
.qp1_proxy
);
2652 kfree(dev
->dev_vfs
);
2654 pci_release_regions(pdev
);
2655 pci_disable_device(pdev
);
2656 memset(priv
, 0, sizeof(*priv
));
2657 priv
->pci_dev_data
= pci_dev_data
;
2661 static void mlx4_remove_one(struct pci_dev
*pdev
)
2663 struct mlx4_dev
*dev
= pci_get_drvdata(pdev
);
2664 struct mlx4_priv
*priv
= mlx4_priv(dev
);
2666 __mlx4_remove_one(pdev
);
2668 pci_set_drvdata(pdev
, NULL
);
2671 int mlx4_restart_one(struct pci_dev
*pdev
)
2673 struct mlx4_dev
*dev
= pci_get_drvdata(pdev
);
2674 struct mlx4_priv
*priv
= mlx4_priv(dev
);
2677 pci_dev_data
= priv
->pci_dev_data
;
2678 __mlx4_remove_one(pdev
);
2679 return __mlx4_init_one(pdev
, pci_dev_data
);
2682 static DEFINE_PCI_DEVICE_TABLE(mlx4_pci_table
) = {
2683 /* MT25408 "Hermon" SDR */
2684 { PCI_VDEVICE(MELLANOX
, 0x6340), MLX4_PCI_DEV_FORCE_SENSE_PORT
},
2685 /* MT25408 "Hermon" DDR */
2686 { PCI_VDEVICE(MELLANOX
, 0x634a), MLX4_PCI_DEV_FORCE_SENSE_PORT
},
2687 /* MT25408 "Hermon" QDR */
2688 { PCI_VDEVICE(MELLANOX
, 0x6354), MLX4_PCI_DEV_FORCE_SENSE_PORT
},
2689 /* MT25408 "Hermon" DDR PCIe gen2 */
2690 { PCI_VDEVICE(MELLANOX
, 0x6732), MLX4_PCI_DEV_FORCE_SENSE_PORT
},
2691 /* MT25408 "Hermon" QDR PCIe gen2 */
2692 { PCI_VDEVICE(MELLANOX
, 0x673c), MLX4_PCI_DEV_FORCE_SENSE_PORT
},
2693 /* MT25408 "Hermon" EN 10GigE */
2694 { PCI_VDEVICE(MELLANOX
, 0x6368), MLX4_PCI_DEV_FORCE_SENSE_PORT
},
2695 /* MT25408 "Hermon" EN 10GigE PCIe gen2 */
2696 { PCI_VDEVICE(MELLANOX
, 0x6750), MLX4_PCI_DEV_FORCE_SENSE_PORT
},
2697 /* MT25458 ConnectX EN 10GBASE-T 10GigE */
2698 { PCI_VDEVICE(MELLANOX
, 0x6372), MLX4_PCI_DEV_FORCE_SENSE_PORT
},
2699 /* MT25458 ConnectX EN 10GBASE-T+Gen2 10GigE */
2700 { PCI_VDEVICE(MELLANOX
, 0x675a), MLX4_PCI_DEV_FORCE_SENSE_PORT
},
2701 /* MT26468 ConnectX EN 10GigE PCIe gen2*/
2702 { PCI_VDEVICE(MELLANOX
, 0x6764), MLX4_PCI_DEV_FORCE_SENSE_PORT
},
2703 /* MT26438 ConnectX EN 40GigE PCIe gen2 5GT/s */
2704 { PCI_VDEVICE(MELLANOX
, 0x6746), MLX4_PCI_DEV_FORCE_SENSE_PORT
},
2705 /* MT26478 ConnectX2 40GigE PCIe gen2 */
2706 { PCI_VDEVICE(MELLANOX
, 0x676e), MLX4_PCI_DEV_FORCE_SENSE_PORT
},
2707 /* MT25400 Family [ConnectX-2 Virtual Function] */
2708 { PCI_VDEVICE(MELLANOX
, 0x1002), MLX4_PCI_DEV_IS_VF
},
2709 /* MT27500 Family [ConnectX-3] */
2710 { PCI_VDEVICE(MELLANOX
, 0x1003), 0 },
2711 /* MT27500 Family [ConnectX-3 Virtual Function] */
2712 { PCI_VDEVICE(MELLANOX
, 0x1004), MLX4_PCI_DEV_IS_VF
},
2713 { PCI_VDEVICE(MELLANOX
, 0x1005), 0 }, /* MT27510 Family */
2714 { PCI_VDEVICE(MELLANOX
, 0x1006), 0 }, /* MT27511 Family */
2715 { PCI_VDEVICE(MELLANOX
, 0x1007), 0 }, /* MT27520 Family */
2716 { PCI_VDEVICE(MELLANOX
, 0x1008), 0 }, /* MT27521 Family */
2717 { PCI_VDEVICE(MELLANOX
, 0x1009), 0 }, /* MT27530 Family */
2718 { PCI_VDEVICE(MELLANOX
, 0x100a), 0 }, /* MT27531 Family */
2719 { PCI_VDEVICE(MELLANOX
, 0x100b), 0 }, /* MT27540 Family */
2720 { PCI_VDEVICE(MELLANOX
, 0x100c), 0 }, /* MT27541 Family */
2721 { PCI_VDEVICE(MELLANOX
, 0x100d), 0 }, /* MT27550 Family */
2722 { PCI_VDEVICE(MELLANOX
, 0x100e), 0 }, /* MT27551 Family */
2723 { PCI_VDEVICE(MELLANOX
, 0x100f), 0 }, /* MT27560 Family */
2724 { PCI_VDEVICE(MELLANOX
, 0x1010), 0 }, /* MT27561 Family */
2728 MODULE_DEVICE_TABLE(pci
, mlx4_pci_table
);
2730 static pci_ers_result_t
mlx4_pci_err_detected(struct pci_dev
*pdev
,
2731 pci_channel_state_t state
)
2733 __mlx4_remove_one(pdev
);
2735 return state
== pci_channel_io_perm_failure
?
2736 PCI_ERS_RESULT_DISCONNECT
: PCI_ERS_RESULT_NEED_RESET
;
2739 static pci_ers_result_t
mlx4_pci_slot_reset(struct pci_dev
*pdev
)
2741 struct mlx4_dev
*dev
= pci_get_drvdata(pdev
);
2742 struct mlx4_priv
*priv
= mlx4_priv(dev
);
2745 ret
= __mlx4_init_one(pdev
, priv
->pci_dev_data
);
2747 return ret
? PCI_ERS_RESULT_DISCONNECT
: PCI_ERS_RESULT_RECOVERED
;
2750 static const struct pci_error_handlers mlx4_err_handler
= {
2751 .error_detected
= mlx4_pci_err_detected
,
2752 .slot_reset
= mlx4_pci_slot_reset
,
2755 static struct pci_driver mlx4_driver
= {
2757 .id_table
= mlx4_pci_table
,
2758 .probe
= mlx4_init_one
,
2759 .shutdown
= mlx4_remove_one
,
2760 .remove
= mlx4_remove_one
,
2761 .err_handler
= &mlx4_err_handler
,
2764 static int __init
mlx4_verify_params(void)
2766 if ((log_num_mac
< 0) || (log_num_mac
> 7)) {
2767 pr_warning("mlx4_core: bad num_mac: %d\n", log_num_mac
);
2771 if (log_num_vlan
!= 0)
2772 pr_warning("mlx4_core: log_num_vlan - obsolete module param, using %d\n",
2773 MLX4_LOG_NUM_VLANS
);
2776 pr_warn("mlx4_core: use_prio - obsolete module param, ignored\n");
2778 if ((log_mtts_per_seg
< 1) || (log_mtts_per_seg
> 7)) {
2779 pr_warning("mlx4_core: bad log_mtts_per_seg: %d\n", log_mtts_per_seg
);
2783 /* Check if module param for ports type has legal combination */
2784 if (port_type_array
[0] == false && port_type_array
[1] == true) {
2785 printk(KERN_WARNING
"Module parameter configuration ETH/IB is not supported. Switching to default configuration IB/IB\n");
2786 port_type_array
[0] = true;
2789 if (mlx4_log_num_mgm_entry_size
!= -1 &&
2790 (mlx4_log_num_mgm_entry_size
< MLX4_MIN_MGM_LOG_ENTRY_SIZE
||
2791 mlx4_log_num_mgm_entry_size
> MLX4_MAX_MGM_LOG_ENTRY_SIZE
)) {
2792 pr_warn("mlx4_core: mlx4_log_num_mgm_entry_size (%d) not in legal range (-1 or %d..%d)\n",
2793 mlx4_log_num_mgm_entry_size
,
2794 MLX4_MIN_MGM_LOG_ENTRY_SIZE
,
2795 MLX4_MAX_MGM_LOG_ENTRY_SIZE
);
2802 static int __init
mlx4_init(void)
2806 if (mlx4_verify_params())
2811 mlx4_wq
= create_singlethread_workqueue("mlx4");
2815 ret
= pci_register_driver(&mlx4_driver
);
2817 destroy_workqueue(mlx4_wq
);
2818 return ret
< 0 ? ret
: 0;
2821 static void __exit
mlx4_cleanup(void)
2823 pci_unregister_driver(&mlx4_driver
);
2824 destroy_workqueue(mlx4_wq
);
2827 module_init(mlx4_init
);
2828 module_exit(mlx4_cleanup
);