2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
5 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * OpenIB.org BSD license below:
13 * Redistribution and use in source and binary forms, with or
14 * without modification, are permitted provided that the following
17 * - Redistributions of source code must retain the above
18 * copyright notice, this list of conditions and the following
21 * - Redistributions in binary form must reproduce the above
22 * copyright notice, this list of conditions and the following
23 * disclaimer in the documentation and/or other materials
24 * provided with the distribution.
26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/module.h>
37 #include <linux/init.h>
38 #include <linux/errno.h>
39 #include <linux/pci.h>
40 #include <linux/dma-mapping.h>
41 #include <linux/slab.h>
42 #include <linux/io-mapping.h>
43 #include <linux/delay.h>
44 #include <linux/kmod.h>
46 #include <linux/mlx4/device.h>
47 #include <linux/mlx4/doorbell.h>
53 MODULE_AUTHOR("Roland Dreier");
54 MODULE_DESCRIPTION("Mellanox ConnectX HCA low-level driver");
55 MODULE_LICENSE("Dual BSD/GPL");
56 MODULE_VERSION(DRV_VERSION
);
58 struct workqueue_struct
*mlx4_wq
;
60 #ifdef CONFIG_MLX4_DEBUG
62 int mlx4_debug_level
= 0;
63 module_param_named(debug_level
, mlx4_debug_level
, int, 0644);
64 MODULE_PARM_DESC(debug_level
, "Enable debug tracing if > 0");
66 #endif /* CONFIG_MLX4_DEBUG */
71 module_param(msi_x
, int, 0444);
72 MODULE_PARM_DESC(msi_x
, "attempt to use MSI-X if nonzero");
74 #else /* CONFIG_PCI_MSI */
78 #endif /* CONFIG_PCI_MSI */
80 static uint8_t num_vfs
[3] = {0, 0, 0};
81 static int num_vfs_argc
;
82 module_param_array(num_vfs
, byte
, &num_vfs_argc
, 0444);
83 MODULE_PARM_DESC(num_vfs
, "enable #num_vfs functions if num_vfs > 0\n"
84 "num_vfs=port1,port2,port1+2");
86 static uint8_t probe_vf
[3] = {0, 0, 0};
87 static int probe_vfs_argc
;
88 module_param_array(probe_vf
, byte
, &probe_vfs_argc
, 0444);
89 MODULE_PARM_DESC(probe_vf
, "number of vfs to probe by pf driver (num_vfs > 0)\n"
90 "probe_vf=port1,port2,port1+2");
92 int mlx4_log_num_mgm_entry_size
= MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE
;
93 module_param_named(log_num_mgm_entry_size
,
94 mlx4_log_num_mgm_entry_size
, int, 0444);
95 MODULE_PARM_DESC(log_num_mgm_entry_size
, "log mgm size, that defines the num"
96 " of qp per mcg, for example:"
97 " 10 gives 248.range: 7 <="
98 " log_num_mgm_entry_size <= 12."
99 " To activate device managed"
100 " flow steering when available, set to -1");
102 static bool enable_64b_cqe_eqe
= true;
103 module_param(enable_64b_cqe_eqe
, bool, 0444);
104 MODULE_PARM_DESC(enable_64b_cqe_eqe
,
105 "Enable 64 byte CQEs/EQEs when the FW supports this (default: True)");
107 #define PF_CONTEXT_BEHAVIOUR_MASK (MLX4_FUNC_CAP_64B_EQE_CQE | \
108 MLX4_FUNC_CAP_EQE_CQE_STRIDE)
110 static char mlx4_version
[] =
111 DRV_NAME
": Mellanox ConnectX core driver v"
112 DRV_VERSION
" (" DRV_RELDATE
")\n";
114 static struct mlx4_profile default_profile
= {
117 .rdmarc_per_qp
= 1 << 4,
121 .num_mtt
= 1 << 20, /* It is really num mtt segements */
124 static struct mlx4_profile low_mem_profile
= {
127 .rdmarc_per_qp
= 1 << 4,
134 static int log_num_mac
= 7;
135 module_param_named(log_num_mac
, log_num_mac
, int, 0444);
136 MODULE_PARM_DESC(log_num_mac
, "Log2 max number of MACs per ETH port (1-7)");
138 static int log_num_vlan
;
139 module_param_named(log_num_vlan
, log_num_vlan
, int, 0444);
140 MODULE_PARM_DESC(log_num_vlan
, "Log2 max number of VLANs per ETH port (0-7)");
141 /* Log2 max number of VLANs per ETH port (0-7) */
142 #define MLX4_LOG_NUM_VLANS 7
143 #define MLX4_MIN_LOG_NUM_VLANS 0
144 #define MLX4_MIN_LOG_NUM_MAC 1
146 static bool use_prio
;
147 module_param_named(use_prio
, use_prio
, bool, 0444);
148 MODULE_PARM_DESC(use_prio
, "Enable steering by VLAN priority on ETH ports (deprecated)");
150 int log_mtts_per_seg
= ilog2(MLX4_MTT_ENTRY_PER_SEG
);
151 module_param_named(log_mtts_per_seg
, log_mtts_per_seg
, int, 0444);
152 MODULE_PARM_DESC(log_mtts_per_seg
, "Log2 number of MTT entries per segment (1-7)");
154 static int port_type_array
[2] = {MLX4_PORT_TYPE_NONE
, MLX4_PORT_TYPE_NONE
};
155 static int arr_argc
= 2;
156 module_param_array(port_type_array
, int, &arr_argc
, 0444);
157 MODULE_PARM_DESC(port_type_array
, "Array of port types: HW_DEFAULT (0) is default "
158 "1 for IB, 2 for Ethernet");
160 struct mlx4_port_config
{
161 struct list_head list
;
162 enum mlx4_port_type port_type
[MLX4_MAX_PORTS
+ 1];
163 struct pci_dev
*pdev
;
166 static atomic_t pf_loading
= ATOMIC_INIT(0);
168 int mlx4_check_port_params(struct mlx4_dev
*dev
,
169 enum mlx4_port_type
*port_type
)
173 for (i
= 0; i
< dev
->caps
.num_ports
- 1; i
++) {
174 if (port_type
[i
] != port_type
[i
+ 1]) {
175 if (!(dev
->caps
.flags
& MLX4_DEV_CAP_FLAG_DPDP
)) {
176 mlx4_err(dev
, "Only same port types supported on this HCA, aborting\n");
182 for (i
= 0; i
< dev
->caps
.num_ports
; i
++) {
183 if (!(port_type
[i
] & dev
->caps
.supported_type
[i
+1])) {
184 mlx4_err(dev
, "Requested port type for port %d is not supported on this HCA\n",
192 static void mlx4_set_port_mask(struct mlx4_dev
*dev
)
196 for (i
= 1; i
<= dev
->caps
.num_ports
; ++i
)
197 dev
->caps
.port_mask
[i
] = dev
->caps
.port_type
[i
];
201 MLX4_QUERY_FUNC_NUM_SYS_EQS
= 1 << 0,
204 static int mlx4_query_func(struct mlx4_dev
*dev
, struct mlx4_dev_cap
*dev_cap
)
207 struct mlx4_func func
;
209 if (dev
->caps
.flags2
& MLX4_DEV_CAP_FLAG2_SYS_EQS
) {
210 err
= mlx4_QUERY_FUNC(dev
, &func
, 0);
212 mlx4_err(dev
, "QUERY_DEV_CAP command failed, aborting.\n");
215 dev_cap
->max_eqs
= func
.max_eq
;
216 dev_cap
->reserved_eqs
= func
.rsvd_eqs
;
217 dev_cap
->reserved_uars
= func
.rsvd_uars
;
218 err
|= MLX4_QUERY_FUNC_NUM_SYS_EQS
;
223 static void mlx4_enable_cqe_eqe_stride(struct mlx4_dev
*dev
)
225 struct mlx4_caps
*dev_cap
= &dev
->caps
;
227 /* FW not supporting or cancelled by user */
228 if (!(dev_cap
->flags2
& MLX4_DEV_CAP_FLAG2_EQE_STRIDE
) ||
229 !(dev_cap
->flags2
& MLX4_DEV_CAP_FLAG2_CQE_STRIDE
))
232 /* Must have 64B CQE_EQE enabled by FW to use bigger stride
233 * When FW has NCSI it may decide not to report 64B CQE/EQEs
235 if (!(dev_cap
->flags
& MLX4_DEV_CAP_FLAG_64B_EQE
) ||
236 !(dev_cap
->flags
& MLX4_DEV_CAP_FLAG_64B_CQE
)) {
237 dev_cap
->flags2
&= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE
;
238 dev_cap
->flags2
&= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE
;
242 if (cache_line_size() == 128 || cache_line_size() == 256) {
243 mlx4_dbg(dev
, "Enabling CQE stride cacheLine supported\n");
244 /* Changing the real data inside CQE size to 32B */
245 dev_cap
->flags
&= ~MLX4_DEV_CAP_FLAG_64B_CQE
;
246 dev_cap
->flags
&= ~MLX4_DEV_CAP_FLAG_64B_EQE
;
248 if (mlx4_is_master(dev
))
249 dev_cap
->function_caps
|= MLX4_FUNC_CAP_EQE_CQE_STRIDE
;
251 mlx4_dbg(dev
, "Disabling CQE stride cacheLine unsupported\n");
252 dev_cap
->flags2
&= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE
;
253 dev_cap
->flags2
&= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE
;
257 static int mlx4_dev_cap(struct mlx4_dev
*dev
, struct mlx4_dev_cap
*dev_cap
)
262 err
= mlx4_QUERY_DEV_CAP(dev
, dev_cap
);
264 mlx4_err(dev
, "QUERY_DEV_CAP command failed, aborting\n");
268 if (dev_cap
->min_page_sz
> PAGE_SIZE
) {
269 mlx4_err(dev
, "HCA minimum page size of %d bigger than kernel PAGE_SIZE of %ld, aborting\n",
270 dev_cap
->min_page_sz
, PAGE_SIZE
);
273 if (dev_cap
->num_ports
> MLX4_MAX_PORTS
) {
274 mlx4_err(dev
, "HCA has %d ports, but we only support %d, aborting\n",
275 dev_cap
->num_ports
, MLX4_MAX_PORTS
);
279 if (dev_cap
->uar_size
> pci_resource_len(dev
->pdev
, 2)) {
280 mlx4_err(dev
, "HCA reported UAR size of 0x%x bigger than PCI resource 2 size of 0x%llx, aborting\n",
282 (unsigned long long) pci_resource_len(dev
->pdev
, 2));
286 dev
->caps
.num_ports
= dev_cap
->num_ports
;
287 dev
->caps
.num_sys_eqs
= dev_cap
->num_sys_eqs
;
288 dev
->phys_caps
.num_phys_eqs
= dev_cap
->flags2
& MLX4_DEV_CAP_FLAG2_SYS_EQS
?
289 dev
->caps
.num_sys_eqs
:
291 for (i
= 1; i
<= dev
->caps
.num_ports
; ++i
) {
292 dev
->caps
.vl_cap
[i
] = dev_cap
->max_vl
[i
];
293 dev
->caps
.ib_mtu_cap
[i
] = dev_cap
->ib_mtu
[i
];
294 dev
->phys_caps
.gid_phys_table_len
[i
] = dev_cap
->max_gids
[i
];
295 dev
->phys_caps
.pkey_phys_table_len
[i
] = dev_cap
->max_pkeys
[i
];
296 /* set gid and pkey table operating lengths by default
297 * to non-sriov values */
298 dev
->caps
.gid_table_len
[i
] = dev_cap
->max_gids
[i
];
299 dev
->caps
.pkey_table_len
[i
] = dev_cap
->max_pkeys
[i
];
300 dev
->caps
.port_width_cap
[i
] = dev_cap
->max_port_width
[i
];
301 dev
->caps
.eth_mtu_cap
[i
] = dev_cap
->eth_mtu
[i
];
302 dev
->caps
.def_mac
[i
] = dev_cap
->def_mac
[i
];
303 dev
->caps
.supported_type
[i
] = dev_cap
->supported_port_types
[i
];
304 dev
->caps
.suggested_type
[i
] = dev_cap
->suggested_type
[i
];
305 dev
->caps
.default_sense
[i
] = dev_cap
->default_sense
[i
];
306 dev
->caps
.trans_type
[i
] = dev_cap
->trans_type
[i
];
307 dev
->caps
.vendor_oui
[i
] = dev_cap
->vendor_oui
[i
];
308 dev
->caps
.wavelength
[i
] = dev_cap
->wavelength
[i
];
309 dev
->caps
.trans_code
[i
] = dev_cap
->trans_code
[i
];
312 dev
->caps
.uar_page_size
= PAGE_SIZE
;
313 dev
->caps
.num_uars
= dev_cap
->uar_size
/ PAGE_SIZE
;
314 dev
->caps
.local_ca_ack_delay
= dev_cap
->local_ca_ack_delay
;
315 dev
->caps
.bf_reg_size
= dev_cap
->bf_reg_size
;
316 dev
->caps
.bf_regs_per_page
= dev_cap
->bf_regs_per_page
;
317 dev
->caps
.max_sq_sg
= dev_cap
->max_sq_sg
;
318 dev
->caps
.max_rq_sg
= dev_cap
->max_rq_sg
;
319 dev
->caps
.max_wqes
= dev_cap
->max_qp_sz
;
320 dev
->caps
.max_qp_init_rdma
= dev_cap
->max_requester_per_qp
;
321 dev
->caps
.max_srq_wqes
= dev_cap
->max_srq_sz
;
322 dev
->caps
.max_srq_sge
= dev_cap
->max_rq_sg
- 1;
323 dev
->caps
.reserved_srqs
= dev_cap
->reserved_srqs
;
324 dev
->caps
.max_sq_desc_sz
= dev_cap
->max_sq_desc_sz
;
325 dev
->caps
.max_rq_desc_sz
= dev_cap
->max_rq_desc_sz
;
327 * Subtract 1 from the limit because we need to allocate a
328 * spare CQE so the HCA HW can tell the difference between an
329 * empty CQ and a full CQ.
331 dev
->caps
.max_cqes
= dev_cap
->max_cq_sz
- 1;
332 dev
->caps
.reserved_cqs
= dev_cap
->reserved_cqs
;
333 dev
->caps
.reserved_eqs
= dev_cap
->reserved_eqs
;
334 dev
->caps
.reserved_mtts
= dev_cap
->reserved_mtts
;
335 dev
->caps
.reserved_mrws
= dev_cap
->reserved_mrws
;
337 /* The first 128 UARs are used for EQ doorbells */
338 dev
->caps
.reserved_uars
= max_t(int, 128, dev_cap
->reserved_uars
);
339 dev
->caps
.reserved_pds
= dev_cap
->reserved_pds
;
340 dev
->caps
.reserved_xrcds
= (dev
->caps
.flags
& MLX4_DEV_CAP_FLAG_XRC
) ?
341 dev_cap
->reserved_xrcds
: 0;
342 dev
->caps
.max_xrcds
= (dev
->caps
.flags
& MLX4_DEV_CAP_FLAG_XRC
) ?
343 dev_cap
->max_xrcds
: 0;
344 dev
->caps
.mtt_entry_sz
= dev_cap
->mtt_entry_sz
;
346 dev
->caps
.max_msg_sz
= dev_cap
->max_msg_sz
;
347 dev
->caps
.page_size_cap
= ~(u32
) (dev_cap
->min_page_sz
- 1);
348 dev
->caps
.flags
= dev_cap
->flags
;
349 dev
->caps
.flags2
= dev_cap
->flags2
;
350 dev
->caps
.bmme_flags
= dev_cap
->bmme_flags
;
351 dev
->caps
.reserved_lkey
= dev_cap
->reserved_lkey
;
352 dev
->caps
.stat_rate_support
= dev_cap
->stat_rate_support
;
353 dev
->caps
.max_gso_sz
= dev_cap
->max_gso_sz
;
354 dev
->caps
.max_rss_tbl_sz
= dev_cap
->max_rss_tbl_sz
;
356 /* Sense port always allowed on supported devices for ConnectX-1 and -2 */
357 if (mlx4_priv(dev
)->pci_dev_data
& MLX4_PCI_DEV_FORCE_SENSE_PORT
)
358 dev
->caps
.flags
|= MLX4_DEV_CAP_FLAG_SENSE_SUPPORT
;
359 /* Don't do sense port on multifunction devices (for now at least) */
360 if (mlx4_is_mfunc(dev
))
361 dev
->caps
.flags
&= ~MLX4_DEV_CAP_FLAG_SENSE_SUPPORT
;
363 if (mlx4_low_memory_profile()) {
364 dev
->caps
.log_num_macs
= MLX4_MIN_LOG_NUM_MAC
;
365 dev
->caps
.log_num_vlans
= MLX4_MIN_LOG_NUM_VLANS
;
367 dev
->caps
.log_num_macs
= log_num_mac
;
368 dev
->caps
.log_num_vlans
= MLX4_LOG_NUM_VLANS
;
371 for (i
= 1; i
<= dev
->caps
.num_ports
; ++i
) {
372 dev
->caps
.port_type
[i
] = MLX4_PORT_TYPE_NONE
;
373 if (dev
->caps
.supported_type
[i
]) {
374 /* if only ETH is supported - assign ETH */
375 if (dev
->caps
.supported_type
[i
] == MLX4_PORT_TYPE_ETH
)
376 dev
->caps
.port_type
[i
] = MLX4_PORT_TYPE_ETH
;
377 /* if only IB is supported, assign IB */
378 else if (dev
->caps
.supported_type
[i
] ==
380 dev
->caps
.port_type
[i
] = MLX4_PORT_TYPE_IB
;
382 /* if IB and ETH are supported, we set the port
383 * type according to user selection of port type;
384 * if user selected none, take the FW hint */
385 if (port_type_array
[i
- 1] == MLX4_PORT_TYPE_NONE
)
386 dev
->caps
.port_type
[i
] = dev
->caps
.suggested_type
[i
] ?
387 MLX4_PORT_TYPE_ETH
: MLX4_PORT_TYPE_IB
;
389 dev
->caps
.port_type
[i
] = port_type_array
[i
- 1];
393 * Link sensing is allowed on the port if 3 conditions are true:
394 * 1. Both protocols are supported on the port.
395 * 2. Different types are supported on the port
396 * 3. FW declared that it supports link sensing
398 mlx4_priv(dev
)->sense
.sense_allowed
[i
] =
399 ((dev
->caps
.supported_type
[i
] == MLX4_PORT_TYPE_AUTO
) &&
400 (dev
->caps
.flags
& MLX4_DEV_CAP_FLAG_DPDP
) &&
401 (dev
->caps
.flags
& MLX4_DEV_CAP_FLAG_SENSE_SUPPORT
));
404 * If "default_sense" bit is set, we move the port to "AUTO" mode
405 * and perform sense_port FW command to try and set the correct
406 * port type from beginning
408 if (mlx4_priv(dev
)->sense
.sense_allowed
[i
] && dev
->caps
.default_sense
[i
]) {
409 enum mlx4_port_type sensed_port
= MLX4_PORT_TYPE_NONE
;
410 dev
->caps
.possible_type
[i
] = MLX4_PORT_TYPE_AUTO
;
411 mlx4_SENSE_PORT(dev
, i
, &sensed_port
);
412 if (sensed_port
!= MLX4_PORT_TYPE_NONE
)
413 dev
->caps
.port_type
[i
] = sensed_port
;
415 dev
->caps
.possible_type
[i
] = dev
->caps
.port_type
[i
];
418 if (dev
->caps
.log_num_macs
> dev_cap
->log_max_macs
[i
]) {
419 dev
->caps
.log_num_macs
= dev_cap
->log_max_macs
[i
];
420 mlx4_warn(dev
, "Requested number of MACs is too much for port %d, reducing to %d\n",
421 i
, 1 << dev
->caps
.log_num_macs
);
423 if (dev
->caps
.log_num_vlans
> dev_cap
->log_max_vlans
[i
]) {
424 dev
->caps
.log_num_vlans
= dev_cap
->log_max_vlans
[i
];
425 mlx4_warn(dev
, "Requested number of VLANs is too much for port %d, reducing to %d\n",
426 i
, 1 << dev
->caps
.log_num_vlans
);
430 dev
->caps
.max_counters
= 1 << ilog2(dev_cap
->max_counters
);
432 dev
->caps
.reserved_qps_cnt
[MLX4_QP_REGION_FW
] = dev_cap
->reserved_qps
;
433 dev
->caps
.reserved_qps_cnt
[MLX4_QP_REGION_ETH_ADDR
] =
434 dev
->caps
.reserved_qps_cnt
[MLX4_QP_REGION_FC_ADDR
] =
435 (1 << dev
->caps
.log_num_macs
) *
436 (1 << dev
->caps
.log_num_vlans
) *
438 dev
->caps
.reserved_qps_cnt
[MLX4_QP_REGION_FC_EXCH
] = MLX4_NUM_FEXCH
;
440 dev
->caps
.reserved_qps
= dev
->caps
.reserved_qps_cnt
[MLX4_QP_REGION_FW
] +
441 dev
->caps
.reserved_qps_cnt
[MLX4_QP_REGION_ETH_ADDR
] +
442 dev
->caps
.reserved_qps_cnt
[MLX4_QP_REGION_FC_ADDR
] +
443 dev
->caps
.reserved_qps_cnt
[MLX4_QP_REGION_FC_EXCH
];
445 dev
->caps
.sqp_demux
= (mlx4_is_master(dev
)) ? MLX4_MAX_NUM_SLAVES
: 0;
447 if (!enable_64b_cqe_eqe
&& !mlx4_is_slave(dev
)) {
449 (MLX4_DEV_CAP_FLAG_64B_CQE
| MLX4_DEV_CAP_FLAG_64B_EQE
)) {
450 mlx4_warn(dev
, "64B EQEs/CQEs supported by the device but not enabled\n");
451 dev
->caps
.flags
&= ~MLX4_DEV_CAP_FLAG_64B_CQE
;
452 dev
->caps
.flags
&= ~MLX4_DEV_CAP_FLAG_64B_EQE
;
455 if (dev_cap
->flags2
&
456 (MLX4_DEV_CAP_FLAG2_CQE_STRIDE
|
457 MLX4_DEV_CAP_FLAG2_EQE_STRIDE
)) {
458 mlx4_warn(dev
, "Disabling EQE/CQE stride per user request\n");
459 dev_cap
->flags2
&= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE
;
460 dev_cap
->flags2
&= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE
;
464 if ((dev
->caps
.flags
&
465 (MLX4_DEV_CAP_FLAG_64B_CQE
| MLX4_DEV_CAP_FLAG_64B_EQE
)) &&
467 dev
->caps
.function_caps
|= MLX4_FUNC_CAP_64B_EQE_CQE
;
469 if (!mlx4_is_slave(dev
)) {
470 mlx4_enable_cqe_eqe_stride(dev
);
471 dev
->caps
.alloc_res_qp_mask
=
472 (dev
->caps
.bf_reg_size
? MLX4_RESERVE_ETH_BF_QP
: 0);
474 dev
->caps
.alloc_res_qp_mask
= 0;
480 static int mlx4_get_pcie_dev_link_caps(struct mlx4_dev
*dev
,
481 enum pci_bus_speed
*speed
,
482 enum pcie_link_width
*width
)
484 u32 lnkcap1
, lnkcap2
;
487 #define PCIE_MLW_CAP_SHIFT 4 /* start of MLW mask in link capabilities */
489 *speed
= PCI_SPEED_UNKNOWN
;
490 *width
= PCIE_LNK_WIDTH_UNKNOWN
;
492 err1
= pcie_capability_read_dword(dev
->pdev
, PCI_EXP_LNKCAP
, &lnkcap1
);
493 err2
= pcie_capability_read_dword(dev
->pdev
, PCI_EXP_LNKCAP2
, &lnkcap2
);
494 if (!err2
&& lnkcap2
) { /* PCIe r3.0-compliant */
495 if (lnkcap2
& PCI_EXP_LNKCAP2_SLS_8_0GB
)
496 *speed
= PCIE_SPEED_8_0GT
;
497 else if (lnkcap2
& PCI_EXP_LNKCAP2_SLS_5_0GB
)
498 *speed
= PCIE_SPEED_5_0GT
;
499 else if (lnkcap2
& PCI_EXP_LNKCAP2_SLS_2_5GB
)
500 *speed
= PCIE_SPEED_2_5GT
;
503 *width
= (lnkcap1
& PCI_EXP_LNKCAP_MLW
) >> PCIE_MLW_CAP_SHIFT
;
504 if (!lnkcap2
) { /* pre-r3.0 */
505 if (lnkcap1
& PCI_EXP_LNKCAP_SLS_5_0GB
)
506 *speed
= PCIE_SPEED_5_0GT
;
507 else if (lnkcap1
& PCI_EXP_LNKCAP_SLS_2_5GB
)
508 *speed
= PCIE_SPEED_2_5GT
;
512 if (*speed
== PCI_SPEED_UNKNOWN
|| *width
== PCIE_LNK_WIDTH_UNKNOWN
) {
514 err2
? err2
: -EINVAL
;
519 static void mlx4_check_pcie_caps(struct mlx4_dev
*dev
)
521 enum pcie_link_width width
, width_cap
;
522 enum pci_bus_speed speed
, speed_cap
;
525 #define PCIE_SPEED_STR(speed) \
526 (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" : \
527 speed == PCIE_SPEED_5_0GT ? "5.0GT/s" : \
528 speed == PCIE_SPEED_2_5GT ? "2.5GT/s" : \
531 err
= mlx4_get_pcie_dev_link_caps(dev
, &speed_cap
, &width_cap
);
534 "Unable to determine PCIe device BW capabilities\n");
538 err
= pcie_get_minimum_link(dev
->pdev
, &speed
, &width
);
539 if (err
|| speed
== PCI_SPEED_UNKNOWN
||
540 width
== PCIE_LNK_WIDTH_UNKNOWN
) {
542 "Unable to determine PCI device chain minimum BW\n");
546 if (width
!= width_cap
|| speed
!= speed_cap
)
548 "PCIe BW is different than device's capability\n");
550 mlx4_info(dev
, "PCIe link speed is %s, device supports %s\n",
551 PCIE_SPEED_STR(speed
), PCIE_SPEED_STR(speed_cap
));
552 mlx4_info(dev
, "PCIe link width is x%d, device supports x%d\n",
557 /*The function checks if there are live vf, return the num of them*/
558 static int mlx4_how_many_lives_vf(struct mlx4_dev
*dev
)
560 struct mlx4_priv
*priv
= mlx4_priv(dev
);
561 struct mlx4_slave_state
*s_state
;
565 for (i
= 1/*the ppf is 0*/; i
< dev
->num_slaves
; ++i
) {
566 s_state
= &priv
->mfunc
.master
.slave_state
[i
];
567 if (s_state
->active
&& s_state
->last_cmd
!=
568 MLX4_COMM_CMD_RESET
) {
569 mlx4_warn(dev
, "%s: slave: %d is still active\n",
577 int mlx4_get_parav_qkey(struct mlx4_dev
*dev
, u32 qpn
, u32
*qkey
)
579 u32 qk
= MLX4_RESERVED_QKEY_BASE
;
581 if (qpn
>= dev
->phys_caps
.base_tunnel_sqpn
+ 8 * MLX4_MFUNC_MAX
||
582 qpn
< dev
->phys_caps
.base_proxy_sqpn
)
585 if (qpn
>= dev
->phys_caps
.base_tunnel_sqpn
)
587 qk
+= qpn
- dev
->phys_caps
.base_tunnel_sqpn
;
589 qk
+= qpn
- dev
->phys_caps
.base_proxy_sqpn
;
593 EXPORT_SYMBOL(mlx4_get_parav_qkey
);
595 void mlx4_sync_pkey_table(struct mlx4_dev
*dev
, int slave
, int port
, int i
, int val
)
597 struct mlx4_priv
*priv
= container_of(dev
, struct mlx4_priv
, dev
);
599 if (!mlx4_is_master(dev
))
602 priv
->virt2phys_pkey
[slave
][port
- 1][i
] = val
;
604 EXPORT_SYMBOL(mlx4_sync_pkey_table
);
606 void mlx4_put_slave_node_guid(struct mlx4_dev
*dev
, int slave
, __be64 guid
)
608 struct mlx4_priv
*priv
= container_of(dev
, struct mlx4_priv
, dev
);
610 if (!mlx4_is_master(dev
))
613 priv
->slave_node_guids
[slave
] = guid
;
615 EXPORT_SYMBOL(mlx4_put_slave_node_guid
);
617 __be64
mlx4_get_slave_node_guid(struct mlx4_dev
*dev
, int slave
)
619 struct mlx4_priv
*priv
= container_of(dev
, struct mlx4_priv
, dev
);
621 if (!mlx4_is_master(dev
))
624 return priv
->slave_node_guids
[slave
];
626 EXPORT_SYMBOL(mlx4_get_slave_node_guid
);
628 int mlx4_is_slave_active(struct mlx4_dev
*dev
, int slave
)
630 struct mlx4_priv
*priv
= mlx4_priv(dev
);
631 struct mlx4_slave_state
*s_slave
;
633 if (!mlx4_is_master(dev
))
636 s_slave
= &priv
->mfunc
.master
.slave_state
[slave
];
637 return !!s_slave
->active
;
639 EXPORT_SYMBOL(mlx4_is_slave_active
);
641 static void slave_adjust_steering_mode(struct mlx4_dev
*dev
,
642 struct mlx4_dev_cap
*dev_cap
,
643 struct mlx4_init_hca_param
*hca_param
)
645 dev
->caps
.steering_mode
= hca_param
->steering_mode
;
646 if (dev
->caps
.steering_mode
== MLX4_STEERING_MODE_DEVICE_MANAGED
) {
647 dev
->caps
.num_qp_per_mgm
= dev_cap
->fs_max_num_qp_per_entry
;
648 dev
->caps
.fs_log_max_ucast_qp_range_size
=
649 dev_cap
->fs_log_max_ucast_qp_range_size
;
651 dev
->caps
.num_qp_per_mgm
=
652 4 * ((1 << hca_param
->log_mc_entry_sz
)/16 - 2);
654 mlx4_dbg(dev
, "Steering mode is: %s\n",
655 mlx4_steering_mode_str(dev
->caps
.steering_mode
));
658 static int mlx4_slave_cap(struct mlx4_dev
*dev
)
662 struct mlx4_dev_cap dev_cap
;
663 struct mlx4_func_cap func_cap
;
664 struct mlx4_init_hca_param hca_param
;
667 memset(&hca_param
, 0, sizeof(hca_param
));
668 err
= mlx4_QUERY_HCA(dev
, &hca_param
);
670 mlx4_err(dev
, "QUERY_HCA command failed, aborting\n");
674 /* fail if the hca has an unknown global capability
675 * at this time global_caps should be always zeroed
677 if (hca_param
.global_caps
) {
678 mlx4_err(dev
, "Unknown hca global capabilities\n");
682 mlx4_log_num_mgm_entry_size
= hca_param
.log_mc_entry_sz
;
684 dev
->caps
.hca_core_clock
= hca_param
.hca_core_clock
;
686 memset(&dev_cap
, 0, sizeof(dev_cap
));
687 dev
->caps
.max_qp_dest_rdma
= 1 << hca_param
.log_rd_per_qp
;
688 err
= mlx4_dev_cap(dev
, &dev_cap
);
690 mlx4_err(dev
, "QUERY_DEV_CAP command failed, aborting\n");
694 err
= mlx4_QUERY_FW(dev
);
696 mlx4_err(dev
, "QUERY_FW command failed: could not get FW version\n");
698 page_size
= ~dev
->caps
.page_size_cap
+ 1;
699 mlx4_warn(dev
, "HCA minimum page size:%d\n", page_size
);
700 if (page_size
> PAGE_SIZE
) {
701 mlx4_err(dev
, "HCA minimum page size of %d bigger than kernel PAGE_SIZE of %ld, aborting\n",
702 page_size
, PAGE_SIZE
);
706 /* slave gets uar page size from QUERY_HCA fw command */
707 dev
->caps
.uar_page_size
= 1 << (hca_param
.uar_page_sz
+ 12);
709 /* TODO: relax this assumption */
710 if (dev
->caps
.uar_page_size
!= PAGE_SIZE
) {
711 mlx4_err(dev
, "UAR size:%d != kernel PAGE_SIZE of %ld\n",
712 dev
->caps
.uar_page_size
, PAGE_SIZE
);
716 memset(&func_cap
, 0, sizeof(func_cap
));
717 err
= mlx4_QUERY_FUNC_CAP(dev
, 0, &func_cap
);
719 mlx4_err(dev
, "QUERY_FUNC_CAP general command failed, aborting (%d)\n",
724 if ((func_cap
.pf_context_behaviour
| PF_CONTEXT_BEHAVIOUR_MASK
) !=
725 PF_CONTEXT_BEHAVIOUR_MASK
) {
726 mlx4_err(dev
, "Unknown pf context behaviour\n");
730 dev
->caps
.num_ports
= func_cap
.num_ports
;
731 dev
->quotas
.qp
= func_cap
.qp_quota
;
732 dev
->quotas
.srq
= func_cap
.srq_quota
;
733 dev
->quotas
.cq
= func_cap
.cq_quota
;
734 dev
->quotas
.mpt
= func_cap
.mpt_quota
;
735 dev
->quotas
.mtt
= func_cap
.mtt_quota
;
736 dev
->caps
.num_qps
= 1 << hca_param
.log_num_qps
;
737 dev
->caps
.num_srqs
= 1 << hca_param
.log_num_srqs
;
738 dev
->caps
.num_cqs
= 1 << hca_param
.log_num_cqs
;
739 dev
->caps
.num_mpts
= 1 << hca_param
.log_mpt_sz
;
740 dev
->caps
.num_eqs
= func_cap
.max_eq
;
741 dev
->caps
.reserved_eqs
= func_cap
.reserved_eq
;
742 dev
->caps
.num_pds
= MLX4_NUM_PDS
;
743 dev
->caps
.num_mgms
= 0;
744 dev
->caps
.num_amgms
= 0;
746 if (dev
->caps
.num_ports
> MLX4_MAX_PORTS
) {
747 mlx4_err(dev
, "HCA has %d ports, but we only support %d, aborting\n",
748 dev
->caps
.num_ports
, MLX4_MAX_PORTS
);
752 dev
->caps
.qp0_qkey
= kcalloc(dev
->caps
.num_ports
, sizeof(u32
), GFP_KERNEL
);
753 dev
->caps
.qp0_tunnel
= kcalloc(dev
->caps
.num_ports
, sizeof (u32
), GFP_KERNEL
);
754 dev
->caps
.qp0_proxy
= kcalloc(dev
->caps
.num_ports
, sizeof (u32
), GFP_KERNEL
);
755 dev
->caps
.qp1_tunnel
= kcalloc(dev
->caps
.num_ports
, sizeof (u32
), GFP_KERNEL
);
756 dev
->caps
.qp1_proxy
= kcalloc(dev
->caps
.num_ports
, sizeof (u32
), GFP_KERNEL
);
758 if (!dev
->caps
.qp0_tunnel
|| !dev
->caps
.qp0_proxy
||
759 !dev
->caps
.qp1_tunnel
|| !dev
->caps
.qp1_proxy
||
760 !dev
->caps
.qp0_qkey
) {
765 for (i
= 1; i
<= dev
->caps
.num_ports
; ++i
) {
766 err
= mlx4_QUERY_FUNC_CAP(dev
, i
, &func_cap
);
768 mlx4_err(dev
, "QUERY_FUNC_CAP port command failed for port %d, aborting (%d)\n",
772 dev
->caps
.qp0_qkey
[i
- 1] = func_cap
.qp0_qkey
;
773 dev
->caps
.qp0_tunnel
[i
- 1] = func_cap
.qp0_tunnel_qpn
;
774 dev
->caps
.qp0_proxy
[i
- 1] = func_cap
.qp0_proxy_qpn
;
775 dev
->caps
.qp1_tunnel
[i
- 1] = func_cap
.qp1_tunnel_qpn
;
776 dev
->caps
.qp1_proxy
[i
- 1] = func_cap
.qp1_proxy_qpn
;
777 dev
->caps
.port_mask
[i
] = dev
->caps
.port_type
[i
];
778 dev
->caps
.phys_port_id
[i
] = func_cap
.phys_port_id
;
779 if (mlx4_get_slave_pkey_gid_tbl_len(dev
, i
,
780 &dev
->caps
.gid_table_len
[i
],
781 &dev
->caps
.pkey_table_len
[i
]))
785 if (dev
->caps
.uar_page_size
* (dev
->caps
.num_uars
-
786 dev
->caps
.reserved_uars
) >
787 pci_resource_len(dev
->pdev
, 2)) {
788 mlx4_err(dev
, "HCA reported UAR region size of 0x%x bigger than PCI resource 2 size of 0x%llx, aborting\n",
789 dev
->caps
.uar_page_size
* dev
->caps
.num_uars
,
790 (unsigned long long) pci_resource_len(dev
->pdev
, 2));
794 if (hca_param
.dev_cap_enabled
& MLX4_DEV_CAP_64B_EQE_ENABLED
) {
795 dev
->caps
.eqe_size
= 64;
796 dev
->caps
.eqe_factor
= 1;
798 dev
->caps
.eqe_size
= 32;
799 dev
->caps
.eqe_factor
= 0;
802 if (hca_param
.dev_cap_enabled
& MLX4_DEV_CAP_64B_CQE_ENABLED
) {
803 dev
->caps
.cqe_size
= 64;
804 dev
->caps
.userspace_caps
|= MLX4_USER_DEV_CAP_LARGE_CQE
;
806 dev
->caps
.cqe_size
= 32;
809 if (hca_param
.dev_cap_enabled
& MLX4_DEV_CAP_EQE_STRIDE_ENABLED
) {
810 dev
->caps
.eqe_size
= hca_param
.eqe_size
;
811 dev
->caps
.eqe_factor
= 0;
814 if (hca_param
.dev_cap_enabled
& MLX4_DEV_CAP_CQE_STRIDE_ENABLED
) {
815 dev
->caps
.cqe_size
= hca_param
.cqe_size
;
816 /* User still need to know when CQE > 32B */
817 dev
->caps
.userspace_caps
|= MLX4_USER_DEV_CAP_LARGE_CQE
;
820 dev
->caps
.flags2
&= ~MLX4_DEV_CAP_FLAG2_TS
;
821 mlx4_warn(dev
, "Timestamping is not supported in slave mode\n");
823 slave_adjust_steering_mode(dev
, &dev_cap
, &hca_param
);
825 if (func_cap
.extra_flags
& MLX4_QUERY_FUNC_FLAGS_BF_RES_QP
&&
826 dev
->caps
.bf_reg_size
)
827 dev
->caps
.alloc_res_qp_mask
|= MLX4_RESERVE_ETH_BF_QP
;
832 kfree(dev
->caps
.qp0_qkey
);
833 kfree(dev
->caps
.qp0_tunnel
);
834 kfree(dev
->caps
.qp0_proxy
);
835 kfree(dev
->caps
.qp1_tunnel
);
836 kfree(dev
->caps
.qp1_proxy
);
837 dev
->caps
.qp0_qkey
= NULL
;
838 dev
->caps
.qp0_tunnel
= NULL
;
839 dev
->caps
.qp0_proxy
= NULL
;
840 dev
->caps
.qp1_tunnel
= NULL
;
841 dev
->caps
.qp1_proxy
= NULL
;
846 static void mlx4_request_modules(struct mlx4_dev
*dev
)
849 int has_ib_port
= false;
850 int has_eth_port
= false;
851 #define EN_DRV_NAME "mlx4_en"
852 #define IB_DRV_NAME "mlx4_ib"
854 for (port
= 1; port
<= dev
->caps
.num_ports
; port
++) {
855 if (dev
->caps
.port_type
[port
] == MLX4_PORT_TYPE_IB
)
857 else if (dev
->caps
.port_type
[port
] == MLX4_PORT_TYPE_ETH
)
862 request_module_nowait(EN_DRV_NAME
);
863 if (has_ib_port
|| (dev
->caps
.flags
& MLX4_DEV_CAP_FLAG_IBOE
))
864 request_module_nowait(IB_DRV_NAME
);
868 * Change the port configuration of the device.
869 * Every user of this function must hold the port mutex.
871 int mlx4_change_port_types(struct mlx4_dev
*dev
,
872 enum mlx4_port_type
*port_types
)
878 for (port
= 0; port
< dev
->caps
.num_ports
; port
++) {
879 /* Change the port type only if the new type is different
880 * from the current, and not set to Auto */
881 if (port_types
[port
] != dev
->caps
.port_type
[port
+ 1])
885 mlx4_unregister_device(dev
);
886 for (port
= 1; port
<= dev
->caps
.num_ports
; port
++) {
887 mlx4_CLOSE_PORT(dev
, port
);
888 dev
->caps
.port_type
[port
] = port_types
[port
- 1];
889 err
= mlx4_SET_PORT(dev
, port
, -1);
891 mlx4_err(dev
, "Failed to set port %d, aborting\n",
896 mlx4_set_port_mask(dev
);
897 err
= mlx4_register_device(dev
);
899 mlx4_err(dev
, "Failed to register device\n");
902 mlx4_request_modules(dev
);
909 static ssize_t
show_port_type(struct device
*dev
,
910 struct device_attribute
*attr
,
913 struct mlx4_port_info
*info
= container_of(attr
, struct mlx4_port_info
,
915 struct mlx4_dev
*mdev
= info
->dev
;
919 (mdev
->caps
.port_type
[info
->port
] == MLX4_PORT_TYPE_IB
) ?
921 if (mdev
->caps
.possible_type
[info
->port
] == MLX4_PORT_TYPE_AUTO
)
922 sprintf(buf
, "auto (%s)\n", type
);
924 sprintf(buf
, "%s\n", type
);
929 static ssize_t
set_port_type(struct device
*dev
,
930 struct device_attribute
*attr
,
931 const char *buf
, size_t count
)
933 struct mlx4_port_info
*info
= container_of(attr
, struct mlx4_port_info
,
935 struct mlx4_dev
*mdev
= info
->dev
;
936 struct mlx4_priv
*priv
= mlx4_priv(mdev
);
937 enum mlx4_port_type types
[MLX4_MAX_PORTS
];
938 enum mlx4_port_type new_types
[MLX4_MAX_PORTS
];
939 static DEFINE_MUTEX(set_port_type_mutex
);
943 mutex_lock(&set_port_type_mutex
);
945 if (!strcmp(buf
, "ib\n"))
946 info
->tmp_type
= MLX4_PORT_TYPE_IB
;
947 else if (!strcmp(buf
, "eth\n"))
948 info
->tmp_type
= MLX4_PORT_TYPE_ETH
;
949 else if (!strcmp(buf
, "auto\n"))
950 info
->tmp_type
= MLX4_PORT_TYPE_AUTO
;
952 mlx4_err(mdev
, "%s is not supported port type\n", buf
);
957 mlx4_stop_sense(mdev
);
958 mutex_lock(&priv
->port_mutex
);
959 /* Possible type is always the one that was delivered */
960 mdev
->caps
.possible_type
[info
->port
] = info
->tmp_type
;
962 for (i
= 0; i
< mdev
->caps
.num_ports
; i
++) {
963 types
[i
] = priv
->port
[i
+1].tmp_type
? priv
->port
[i
+1].tmp_type
:
964 mdev
->caps
.possible_type
[i
+1];
965 if (types
[i
] == MLX4_PORT_TYPE_AUTO
)
966 types
[i
] = mdev
->caps
.port_type
[i
+1];
969 if (!(mdev
->caps
.flags
& MLX4_DEV_CAP_FLAG_DPDP
) &&
970 !(mdev
->caps
.flags
& MLX4_DEV_CAP_FLAG_SENSE_SUPPORT
)) {
971 for (i
= 1; i
<= mdev
->caps
.num_ports
; i
++) {
972 if (mdev
->caps
.possible_type
[i
] == MLX4_PORT_TYPE_AUTO
) {
973 mdev
->caps
.possible_type
[i
] = mdev
->caps
.port_type
[i
];
979 mlx4_err(mdev
, "Auto sensing is not supported on this HCA. Set only 'eth' or 'ib' for both ports (should be the same)\n");
983 mlx4_do_sense_ports(mdev
, new_types
, types
);
985 err
= mlx4_check_port_params(mdev
, new_types
);
989 /* We are about to apply the changes after the configuration
990 * was verified, no need to remember the temporary types
992 for (i
= 0; i
< mdev
->caps
.num_ports
; i
++)
993 priv
->port
[i
+ 1].tmp_type
= 0;
995 err
= mlx4_change_port_types(mdev
, new_types
);
998 mlx4_start_sense(mdev
);
999 mutex_unlock(&priv
->port_mutex
);
1001 mutex_unlock(&set_port_type_mutex
);
1003 return err
? err
: count
;
1014 static inline int int_to_ibta_mtu(int mtu
)
1017 case 256: return IB_MTU_256
;
1018 case 512: return IB_MTU_512
;
1019 case 1024: return IB_MTU_1024
;
1020 case 2048: return IB_MTU_2048
;
1021 case 4096: return IB_MTU_4096
;
1026 static inline int ibta_mtu_to_int(enum ibta_mtu mtu
)
1029 case IB_MTU_256
: return 256;
1030 case IB_MTU_512
: return 512;
1031 case IB_MTU_1024
: return 1024;
1032 case IB_MTU_2048
: return 2048;
1033 case IB_MTU_4096
: return 4096;
1038 static ssize_t
show_port_ib_mtu(struct device
*dev
,
1039 struct device_attribute
*attr
,
1042 struct mlx4_port_info
*info
= container_of(attr
, struct mlx4_port_info
,
1044 struct mlx4_dev
*mdev
= info
->dev
;
1046 if (mdev
->caps
.port_type
[info
->port
] == MLX4_PORT_TYPE_ETH
)
1047 mlx4_warn(mdev
, "port level mtu is only used for IB ports\n");
1049 sprintf(buf
, "%d\n",
1050 ibta_mtu_to_int(mdev
->caps
.port_ib_mtu
[info
->port
]));
1054 static ssize_t
set_port_ib_mtu(struct device
*dev
,
1055 struct device_attribute
*attr
,
1056 const char *buf
, size_t count
)
1058 struct mlx4_port_info
*info
= container_of(attr
, struct mlx4_port_info
,
1060 struct mlx4_dev
*mdev
= info
->dev
;
1061 struct mlx4_priv
*priv
= mlx4_priv(mdev
);
1062 int err
, port
, mtu
, ibta_mtu
= -1;
1064 if (mdev
->caps
.port_type
[info
->port
] == MLX4_PORT_TYPE_ETH
) {
1065 mlx4_warn(mdev
, "port level mtu is only used for IB ports\n");
1069 err
= kstrtoint(buf
, 0, &mtu
);
1071 ibta_mtu
= int_to_ibta_mtu(mtu
);
1073 if (err
|| ibta_mtu
< 0) {
1074 mlx4_err(mdev
, "%s is invalid IBTA mtu\n", buf
);
1078 mdev
->caps
.port_ib_mtu
[info
->port
] = ibta_mtu
;
1080 mlx4_stop_sense(mdev
);
1081 mutex_lock(&priv
->port_mutex
);
1082 mlx4_unregister_device(mdev
);
1083 for (port
= 1; port
<= mdev
->caps
.num_ports
; port
++) {
1084 mlx4_CLOSE_PORT(mdev
, port
);
1085 err
= mlx4_SET_PORT(mdev
, port
, -1);
1087 mlx4_err(mdev
, "Failed to set port %d, aborting\n",
1092 err
= mlx4_register_device(mdev
);
1094 mutex_unlock(&priv
->port_mutex
);
1095 mlx4_start_sense(mdev
);
1096 return err
? err
: count
;
1099 static int mlx4_load_fw(struct mlx4_dev
*dev
)
1101 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1104 priv
->fw
.fw_icm
= mlx4_alloc_icm(dev
, priv
->fw
.fw_pages
,
1105 GFP_HIGHUSER
| __GFP_NOWARN
, 0);
1106 if (!priv
->fw
.fw_icm
) {
1107 mlx4_err(dev
, "Couldn't allocate FW area, aborting\n");
1111 err
= mlx4_MAP_FA(dev
, priv
->fw
.fw_icm
);
1113 mlx4_err(dev
, "MAP_FA command failed, aborting\n");
1117 err
= mlx4_RUN_FW(dev
);
1119 mlx4_err(dev
, "RUN_FW command failed, aborting\n");
1129 mlx4_free_icm(dev
, priv
->fw
.fw_icm
, 0);
1133 static int mlx4_init_cmpt_table(struct mlx4_dev
*dev
, u64 cmpt_base
,
1136 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1140 err
= mlx4_init_icm_table(dev
, &priv
->qp_table
.cmpt_table
,
1142 ((u64
) (MLX4_CMPT_TYPE_QP
*
1143 cmpt_entry_sz
) << MLX4_CMPT_SHIFT
),
1144 cmpt_entry_sz
, dev
->caps
.num_qps
,
1145 dev
->caps
.reserved_qps_cnt
[MLX4_QP_REGION_FW
],
1150 err
= mlx4_init_icm_table(dev
, &priv
->srq_table
.cmpt_table
,
1152 ((u64
) (MLX4_CMPT_TYPE_SRQ
*
1153 cmpt_entry_sz
) << MLX4_CMPT_SHIFT
),
1154 cmpt_entry_sz
, dev
->caps
.num_srqs
,
1155 dev
->caps
.reserved_srqs
, 0, 0);
1159 err
= mlx4_init_icm_table(dev
, &priv
->cq_table
.cmpt_table
,
1161 ((u64
) (MLX4_CMPT_TYPE_CQ
*
1162 cmpt_entry_sz
) << MLX4_CMPT_SHIFT
),
1163 cmpt_entry_sz
, dev
->caps
.num_cqs
,
1164 dev
->caps
.reserved_cqs
, 0, 0);
1168 num_eqs
= dev
->phys_caps
.num_phys_eqs
;
1169 err
= mlx4_init_icm_table(dev
, &priv
->eq_table
.cmpt_table
,
1171 ((u64
) (MLX4_CMPT_TYPE_EQ
*
1172 cmpt_entry_sz
) << MLX4_CMPT_SHIFT
),
1173 cmpt_entry_sz
, num_eqs
, num_eqs
, 0, 0);
1180 mlx4_cleanup_icm_table(dev
, &priv
->cq_table
.cmpt_table
);
1183 mlx4_cleanup_icm_table(dev
, &priv
->srq_table
.cmpt_table
);
1186 mlx4_cleanup_icm_table(dev
, &priv
->qp_table
.cmpt_table
);
1192 static int mlx4_init_icm(struct mlx4_dev
*dev
, struct mlx4_dev_cap
*dev_cap
,
1193 struct mlx4_init_hca_param
*init_hca
, u64 icm_size
)
1195 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1200 err
= mlx4_SET_ICM_SIZE(dev
, icm_size
, &aux_pages
);
1202 mlx4_err(dev
, "SET_ICM_SIZE command failed, aborting\n");
1206 mlx4_dbg(dev
, "%lld KB of HCA context requires %lld KB aux memory\n",
1207 (unsigned long long) icm_size
>> 10,
1208 (unsigned long long) aux_pages
<< 2);
1210 priv
->fw
.aux_icm
= mlx4_alloc_icm(dev
, aux_pages
,
1211 GFP_HIGHUSER
| __GFP_NOWARN
, 0);
1212 if (!priv
->fw
.aux_icm
) {
1213 mlx4_err(dev
, "Couldn't allocate aux memory, aborting\n");
1217 err
= mlx4_MAP_ICM_AUX(dev
, priv
->fw
.aux_icm
);
1219 mlx4_err(dev
, "MAP_ICM_AUX command failed, aborting\n");
1223 err
= mlx4_init_cmpt_table(dev
, init_hca
->cmpt_base
, dev_cap
->cmpt_entry_sz
);
1225 mlx4_err(dev
, "Failed to map cMPT context memory, aborting\n");
1230 num_eqs
= dev
->phys_caps
.num_phys_eqs
;
1231 err
= mlx4_init_icm_table(dev
, &priv
->eq_table
.table
,
1232 init_hca
->eqc_base
, dev_cap
->eqc_entry_sz
,
1233 num_eqs
, num_eqs
, 0, 0);
1235 mlx4_err(dev
, "Failed to map EQ context memory, aborting\n");
1236 goto err_unmap_cmpt
;
1240 * Reserved MTT entries must be aligned up to a cacheline
1241 * boundary, since the FW will write to them, while the driver
1242 * writes to all other MTT entries. (The variable
1243 * dev->caps.mtt_entry_sz below is really the MTT segment
1244 * size, not the raw entry size)
1246 dev
->caps
.reserved_mtts
=
1247 ALIGN(dev
->caps
.reserved_mtts
* dev
->caps
.mtt_entry_sz
,
1248 dma_get_cache_alignment()) / dev
->caps
.mtt_entry_sz
;
1250 err
= mlx4_init_icm_table(dev
, &priv
->mr_table
.mtt_table
,
1252 dev
->caps
.mtt_entry_sz
,
1254 dev
->caps
.reserved_mtts
, 1, 0);
1256 mlx4_err(dev
, "Failed to map MTT context memory, aborting\n");
1260 err
= mlx4_init_icm_table(dev
, &priv
->mr_table
.dmpt_table
,
1261 init_hca
->dmpt_base
,
1262 dev_cap
->dmpt_entry_sz
,
1264 dev
->caps
.reserved_mrws
, 1, 1);
1266 mlx4_err(dev
, "Failed to map dMPT context memory, aborting\n");
1270 err
= mlx4_init_icm_table(dev
, &priv
->qp_table
.qp_table
,
1272 dev_cap
->qpc_entry_sz
,
1274 dev
->caps
.reserved_qps_cnt
[MLX4_QP_REGION_FW
],
1277 mlx4_err(dev
, "Failed to map QP context memory, aborting\n");
1278 goto err_unmap_dmpt
;
1281 err
= mlx4_init_icm_table(dev
, &priv
->qp_table
.auxc_table
,
1282 init_hca
->auxc_base
,
1283 dev_cap
->aux_entry_sz
,
1285 dev
->caps
.reserved_qps_cnt
[MLX4_QP_REGION_FW
],
1288 mlx4_err(dev
, "Failed to map AUXC context memory, aborting\n");
1292 err
= mlx4_init_icm_table(dev
, &priv
->qp_table
.altc_table
,
1293 init_hca
->altc_base
,
1294 dev_cap
->altc_entry_sz
,
1296 dev
->caps
.reserved_qps_cnt
[MLX4_QP_REGION_FW
],
1299 mlx4_err(dev
, "Failed to map ALTC context memory, aborting\n");
1300 goto err_unmap_auxc
;
1303 err
= mlx4_init_icm_table(dev
, &priv
->qp_table
.rdmarc_table
,
1304 init_hca
->rdmarc_base
,
1305 dev_cap
->rdmarc_entry_sz
<< priv
->qp_table
.rdmarc_shift
,
1307 dev
->caps
.reserved_qps_cnt
[MLX4_QP_REGION_FW
],
1310 mlx4_err(dev
, "Failed to map RDMARC context memory, aborting\n");
1311 goto err_unmap_altc
;
1314 err
= mlx4_init_icm_table(dev
, &priv
->cq_table
.table
,
1316 dev_cap
->cqc_entry_sz
,
1318 dev
->caps
.reserved_cqs
, 0, 0);
1320 mlx4_err(dev
, "Failed to map CQ context memory, aborting\n");
1321 goto err_unmap_rdmarc
;
1324 err
= mlx4_init_icm_table(dev
, &priv
->srq_table
.table
,
1325 init_hca
->srqc_base
,
1326 dev_cap
->srq_entry_sz
,
1328 dev
->caps
.reserved_srqs
, 0, 0);
1330 mlx4_err(dev
, "Failed to map SRQ context memory, aborting\n");
1335 * For flow steering device managed mode it is required to use
1336 * mlx4_init_icm_table. For B0 steering mode it's not strictly
1337 * required, but for simplicity just map the whole multicast
1338 * group table now. The table isn't very big and it's a lot
1339 * easier than trying to track ref counts.
1341 err
= mlx4_init_icm_table(dev
, &priv
->mcg_table
.table
,
1343 mlx4_get_mgm_entry_size(dev
),
1344 dev
->caps
.num_mgms
+ dev
->caps
.num_amgms
,
1345 dev
->caps
.num_mgms
+ dev
->caps
.num_amgms
,
1348 mlx4_err(dev
, "Failed to map MCG context memory, aborting\n");
1355 mlx4_cleanup_icm_table(dev
, &priv
->srq_table
.table
);
1358 mlx4_cleanup_icm_table(dev
, &priv
->cq_table
.table
);
1361 mlx4_cleanup_icm_table(dev
, &priv
->qp_table
.rdmarc_table
);
1364 mlx4_cleanup_icm_table(dev
, &priv
->qp_table
.altc_table
);
1367 mlx4_cleanup_icm_table(dev
, &priv
->qp_table
.auxc_table
);
1370 mlx4_cleanup_icm_table(dev
, &priv
->qp_table
.qp_table
);
1373 mlx4_cleanup_icm_table(dev
, &priv
->mr_table
.dmpt_table
);
1376 mlx4_cleanup_icm_table(dev
, &priv
->mr_table
.mtt_table
);
1379 mlx4_cleanup_icm_table(dev
, &priv
->eq_table
.table
);
1382 mlx4_cleanup_icm_table(dev
, &priv
->eq_table
.cmpt_table
);
1383 mlx4_cleanup_icm_table(dev
, &priv
->cq_table
.cmpt_table
);
1384 mlx4_cleanup_icm_table(dev
, &priv
->srq_table
.cmpt_table
);
1385 mlx4_cleanup_icm_table(dev
, &priv
->qp_table
.cmpt_table
);
1388 mlx4_UNMAP_ICM_AUX(dev
);
1391 mlx4_free_icm(dev
, priv
->fw
.aux_icm
, 0);
1396 static void mlx4_free_icms(struct mlx4_dev
*dev
)
1398 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1400 mlx4_cleanup_icm_table(dev
, &priv
->mcg_table
.table
);
1401 mlx4_cleanup_icm_table(dev
, &priv
->srq_table
.table
);
1402 mlx4_cleanup_icm_table(dev
, &priv
->cq_table
.table
);
1403 mlx4_cleanup_icm_table(dev
, &priv
->qp_table
.rdmarc_table
);
1404 mlx4_cleanup_icm_table(dev
, &priv
->qp_table
.altc_table
);
1405 mlx4_cleanup_icm_table(dev
, &priv
->qp_table
.auxc_table
);
1406 mlx4_cleanup_icm_table(dev
, &priv
->qp_table
.qp_table
);
1407 mlx4_cleanup_icm_table(dev
, &priv
->mr_table
.dmpt_table
);
1408 mlx4_cleanup_icm_table(dev
, &priv
->mr_table
.mtt_table
);
1409 mlx4_cleanup_icm_table(dev
, &priv
->eq_table
.table
);
1410 mlx4_cleanup_icm_table(dev
, &priv
->eq_table
.cmpt_table
);
1411 mlx4_cleanup_icm_table(dev
, &priv
->cq_table
.cmpt_table
);
1412 mlx4_cleanup_icm_table(dev
, &priv
->srq_table
.cmpt_table
);
1413 mlx4_cleanup_icm_table(dev
, &priv
->qp_table
.cmpt_table
);
1415 mlx4_UNMAP_ICM_AUX(dev
);
1416 mlx4_free_icm(dev
, priv
->fw
.aux_icm
, 0);
1419 static void mlx4_slave_exit(struct mlx4_dev
*dev
)
1421 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1423 mutex_lock(&priv
->cmd
.slave_cmd_mutex
);
1424 if (mlx4_comm_cmd(dev
, MLX4_COMM_CMD_RESET
, 0, MLX4_COMM_TIME
))
1425 mlx4_warn(dev
, "Failed to close slave function\n");
1426 mutex_unlock(&priv
->cmd
.slave_cmd_mutex
);
1429 static int map_bf_area(struct mlx4_dev
*dev
)
1431 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1432 resource_size_t bf_start
;
1433 resource_size_t bf_len
;
1436 if (!dev
->caps
.bf_reg_size
)
1439 bf_start
= pci_resource_start(dev
->pdev
, 2) +
1440 (dev
->caps
.num_uars
<< PAGE_SHIFT
);
1441 bf_len
= pci_resource_len(dev
->pdev
, 2) -
1442 (dev
->caps
.num_uars
<< PAGE_SHIFT
);
1443 priv
->bf_mapping
= io_mapping_create_wc(bf_start
, bf_len
);
1444 if (!priv
->bf_mapping
)
1450 static void unmap_bf_area(struct mlx4_dev
*dev
)
1452 if (mlx4_priv(dev
)->bf_mapping
)
1453 io_mapping_free(mlx4_priv(dev
)->bf_mapping
);
1456 cycle_t
mlx4_read_clock(struct mlx4_dev
*dev
)
1458 u32 clockhi
, clocklo
, clockhi1
;
1461 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1463 for (i
= 0; i
< 10; i
++) {
1464 clockhi
= swab32(readl(priv
->clock_mapping
));
1465 clocklo
= swab32(readl(priv
->clock_mapping
+ 4));
1466 clockhi1
= swab32(readl(priv
->clock_mapping
));
1467 if (clockhi
== clockhi1
)
1471 cycles
= (u64
) clockhi
<< 32 | (u64
) clocklo
;
1475 EXPORT_SYMBOL_GPL(mlx4_read_clock
);
1478 static int map_internal_clock(struct mlx4_dev
*dev
)
1480 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1482 priv
->clock_mapping
=
1483 ioremap(pci_resource_start(dev
->pdev
, priv
->fw
.clock_bar
) +
1484 priv
->fw
.clock_offset
, MLX4_CLOCK_SIZE
);
1486 if (!priv
->clock_mapping
)
1492 static void unmap_internal_clock(struct mlx4_dev
*dev
)
1494 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1496 if (priv
->clock_mapping
)
1497 iounmap(priv
->clock_mapping
);
1500 static void mlx4_close_hca(struct mlx4_dev
*dev
)
1502 unmap_internal_clock(dev
);
1504 if (mlx4_is_slave(dev
))
1505 mlx4_slave_exit(dev
);
1507 mlx4_CLOSE_HCA(dev
, 0);
1508 mlx4_free_icms(dev
);
1512 static void mlx4_close_fw(struct mlx4_dev
*dev
)
1514 if (!mlx4_is_slave(dev
)) {
1516 mlx4_free_icm(dev
, mlx4_priv(dev
)->fw
.fw_icm
, 0);
1520 static int mlx4_init_slave(struct mlx4_dev
*dev
)
1522 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1523 u64 dma
= (u64
) priv
->mfunc
.vhcr_dma
;
1524 int ret_from_reset
= 0;
1526 u32 cmd_channel_ver
;
1528 if (atomic_read(&pf_loading
)) {
1529 mlx4_warn(dev
, "PF is not ready - Deferring probe\n");
1530 return -EPROBE_DEFER
;
1533 mutex_lock(&priv
->cmd
.slave_cmd_mutex
);
1534 priv
->cmd
.max_cmds
= 1;
1535 mlx4_warn(dev
, "Sending reset\n");
1536 ret_from_reset
= mlx4_comm_cmd(dev
, MLX4_COMM_CMD_RESET
, 0,
1538 /* if we are in the middle of flr the slave will try
1539 * NUM_OF_RESET_RETRIES times before leaving.*/
1540 if (ret_from_reset
) {
1541 if (MLX4_DELAY_RESET_SLAVE
== ret_from_reset
) {
1542 mlx4_warn(dev
, "slave is currently in the middle of FLR - Deferring probe\n");
1543 mutex_unlock(&priv
->cmd
.slave_cmd_mutex
);
1544 return -EPROBE_DEFER
;
1549 /* check the driver version - the slave I/F revision
1550 * must match the master's */
1551 slave_read
= swab32(readl(&priv
->mfunc
.comm
->slave_read
));
1552 cmd_channel_ver
= mlx4_comm_get_version();
1554 if (MLX4_COMM_GET_IF_REV(cmd_channel_ver
) !=
1555 MLX4_COMM_GET_IF_REV(slave_read
)) {
1556 mlx4_err(dev
, "slave driver version is not supported by the master\n");
1560 mlx4_warn(dev
, "Sending vhcr0\n");
1561 if (mlx4_comm_cmd(dev
, MLX4_COMM_CMD_VHCR0
, dma
>> 48,
1564 if (mlx4_comm_cmd(dev
, MLX4_COMM_CMD_VHCR1
, dma
>> 32,
1567 if (mlx4_comm_cmd(dev
, MLX4_COMM_CMD_VHCR2
, dma
>> 16,
1570 if (mlx4_comm_cmd(dev
, MLX4_COMM_CMD_VHCR_EN
, dma
, MLX4_COMM_TIME
))
1573 mutex_unlock(&priv
->cmd
.slave_cmd_mutex
);
1577 mlx4_comm_cmd(dev
, MLX4_COMM_CMD_RESET
, 0, 0);
1578 mutex_unlock(&priv
->cmd
.slave_cmd_mutex
);
1582 static void mlx4_parav_master_pf_caps(struct mlx4_dev
*dev
)
1586 for (i
= 1; i
<= dev
->caps
.num_ports
; i
++) {
1587 if (dev
->caps
.port_type
[i
] == MLX4_PORT_TYPE_ETH
)
1588 dev
->caps
.gid_table_len
[i
] =
1589 mlx4_get_slave_num_gids(dev
, 0, i
);
1591 dev
->caps
.gid_table_len
[i
] = 1;
1592 dev
->caps
.pkey_table_len
[i
] =
1593 dev
->phys_caps
.pkey_phys_table_len
[i
] - 1;
1597 static int choose_log_fs_mgm_entry_size(int qp_per_entry
)
1599 int i
= MLX4_MIN_MGM_LOG_ENTRY_SIZE
;
1601 for (i
= MLX4_MIN_MGM_LOG_ENTRY_SIZE
; i
<= MLX4_MAX_MGM_LOG_ENTRY_SIZE
;
1603 if (qp_per_entry
<= 4 * ((1 << i
) / 16 - 2))
1607 return (i
<= MLX4_MAX_MGM_LOG_ENTRY_SIZE
) ? i
: -1;
1610 static void choose_steering_mode(struct mlx4_dev
*dev
,
1611 struct mlx4_dev_cap
*dev_cap
)
1613 if (mlx4_log_num_mgm_entry_size
== -1 &&
1614 dev_cap
->flags2
& MLX4_DEV_CAP_FLAG2_FS_EN
&&
1615 (!mlx4_is_mfunc(dev
) ||
1616 (dev_cap
->fs_max_num_qp_per_entry
>= (dev
->num_vfs
+ 1))) &&
1617 choose_log_fs_mgm_entry_size(dev_cap
->fs_max_num_qp_per_entry
) >=
1618 MLX4_MIN_MGM_LOG_ENTRY_SIZE
) {
1619 dev
->oper_log_mgm_entry_size
=
1620 choose_log_fs_mgm_entry_size(dev_cap
->fs_max_num_qp_per_entry
);
1621 dev
->caps
.steering_mode
= MLX4_STEERING_MODE_DEVICE_MANAGED
;
1622 dev
->caps
.num_qp_per_mgm
= dev_cap
->fs_max_num_qp_per_entry
;
1623 dev
->caps
.fs_log_max_ucast_qp_range_size
=
1624 dev_cap
->fs_log_max_ucast_qp_range_size
;
1626 if (dev
->caps
.flags
& MLX4_DEV_CAP_FLAG_VEP_UC_STEER
&&
1627 dev
->caps
.flags
& MLX4_DEV_CAP_FLAG_VEP_MC_STEER
)
1628 dev
->caps
.steering_mode
= MLX4_STEERING_MODE_B0
;
1630 dev
->caps
.steering_mode
= MLX4_STEERING_MODE_A0
;
1632 if (dev
->caps
.flags
& MLX4_DEV_CAP_FLAG_VEP_UC_STEER
||
1633 dev
->caps
.flags
& MLX4_DEV_CAP_FLAG_VEP_MC_STEER
)
1634 mlx4_warn(dev
, "Must have both UC_STEER and MC_STEER flags set to use B0 steering - falling back to A0 steering mode\n");
1636 dev
->oper_log_mgm_entry_size
=
1637 mlx4_log_num_mgm_entry_size
> 0 ?
1638 mlx4_log_num_mgm_entry_size
:
1639 MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE
;
1640 dev
->caps
.num_qp_per_mgm
= mlx4_get_qp_per_mgm(dev
);
1642 mlx4_dbg(dev
, "Steering mode is: %s, oper_log_mgm_entry_size = %d, modparam log_num_mgm_entry_size = %d\n",
1643 mlx4_steering_mode_str(dev
->caps
.steering_mode
),
1644 dev
->oper_log_mgm_entry_size
,
1645 mlx4_log_num_mgm_entry_size
);
1648 static void choose_tunnel_offload_mode(struct mlx4_dev
*dev
,
1649 struct mlx4_dev_cap
*dev_cap
)
1651 if (dev
->caps
.steering_mode
== MLX4_STEERING_MODE_DEVICE_MANAGED
&&
1652 dev_cap
->flags2
& MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS
)
1653 dev
->caps
.tunnel_offload_mode
= MLX4_TUNNEL_OFFLOAD_MODE_VXLAN
;
1655 dev
->caps
.tunnel_offload_mode
= MLX4_TUNNEL_OFFLOAD_MODE_NONE
;
1657 mlx4_dbg(dev
, "Tunneling offload mode is: %s\n", (dev
->caps
.tunnel_offload_mode
1658 == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN
) ? "vxlan" : "none");
1661 static int mlx4_init_fw(struct mlx4_dev
*dev
)
1663 struct mlx4_mod_stat_cfg mlx4_cfg
;
1666 if (!mlx4_is_slave(dev
)) {
1667 err
= mlx4_QUERY_FW(dev
);
1670 mlx4_info(dev
, "non-primary physical function, skipping\n");
1672 mlx4_err(dev
, "QUERY_FW command failed, aborting\n");
1676 err
= mlx4_load_fw(dev
);
1678 mlx4_err(dev
, "Failed to start FW, aborting\n");
1682 mlx4_cfg
.log_pg_sz_m
= 1;
1683 mlx4_cfg
.log_pg_sz
= 0;
1684 err
= mlx4_MOD_STAT_CFG(dev
, &mlx4_cfg
);
1686 mlx4_warn(dev
, "Failed to override log_pg_sz parameter\n");
1692 static int mlx4_init_hca(struct mlx4_dev
*dev
)
1694 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1695 struct mlx4_adapter adapter
;
1696 struct mlx4_dev_cap dev_cap
;
1697 struct mlx4_profile profile
;
1698 struct mlx4_init_hca_param init_hca
;
1700 struct mlx4_config_dev_params params
;
1703 if (!mlx4_is_slave(dev
)) {
1704 err
= mlx4_dev_cap(dev
, &dev_cap
);
1706 mlx4_err(dev
, "QUERY_DEV_CAP command failed, aborting\n");
1710 choose_steering_mode(dev
, &dev_cap
);
1711 choose_tunnel_offload_mode(dev
, &dev_cap
);
1713 err
= mlx4_get_phys_port_id(dev
);
1715 mlx4_err(dev
, "Fail to get physical port id\n");
1717 if (mlx4_is_master(dev
))
1718 mlx4_parav_master_pf_caps(dev
);
1720 if (mlx4_low_memory_profile()) {
1721 mlx4_info(dev
, "Running from within kdump kernel. Using low memory profile\n");
1722 profile
= low_mem_profile
;
1724 profile
= default_profile
;
1726 if (dev
->caps
.steering_mode
==
1727 MLX4_STEERING_MODE_DEVICE_MANAGED
)
1728 profile
.num_mcg
= MLX4_FS_NUM_MCG
;
1730 icm_size
= mlx4_make_profile(dev
, &profile
, &dev_cap
,
1732 if ((long long) icm_size
< 0) {
1737 dev
->caps
.max_fmr_maps
= (1 << (32 - ilog2(dev
->caps
.num_mpts
))) - 1;
1739 init_hca
.log_uar_sz
= ilog2(dev
->caps
.num_uars
);
1740 init_hca
.uar_page_sz
= PAGE_SHIFT
- 12;
1741 init_hca
.mw_enabled
= 0;
1742 if (dev
->caps
.flags
& MLX4_DEV_CAP_FLAG_MEM_WINDOW
||
1743 dev
->caps
.bmme_flags
& MLX4_BMME_FLAG_TYPE_2_WIN
)
1744 init_hca
.mw_enabled
= INIT_HCA_TPT_MW_ENABLE
;
1746 err
= mlx4_init_icm(dev
, &dev_cap
, &init_hca
, icm_size
);
1750 err
= mlx4_INIT_HCA(dev
, &init_hca
);
1752 mlx4_err(dev
, "INIT_HCA command failed, aborting\n");
1756 if (dev_cap
.flags2
& MLX4_DEV_CAP_FLAG2_SYS_EQS
) {
1757 err
= mlx4_query_func(dev
, &dev_cap
);
1759 mlx4_err(dev
, "QUERY_FUNC command failed, aborting.\n");
1761 } else if (err
& MLX4_QUERY_FUNC_NUM_SYS_EQS
) {
1762 dev
->caps
.num_eqs
= dev_cap
.max_eqs
;
1763 dev
->caps
.reserved_eqs
= dev_cap
.reserved_eqs
;
1764 dev
->caps
.reserved_uars
= dev_cap
.reserved_uars
;
1769 * If TS is supported by FW
1770 * read HCA frequency by QUERY_HCA command
1772 if (dev
->caps
.flags2
& MLX4_DEV_CAP_FLAG2_TS
) {
1773 memset(&init_hca
, 0, sizeof(init_hca
));
1774 err
= mlx4_QUERY_HCA(dev
, &init_hca
);
1776 mlx4_err(dev
, "QUERY_HCA command failed, disable timestamp\n");
1777 dev
->caps
.flags2
&= ~MLX4_DEV_CAP_FLAG2_TS
;
1779 dev
->caps
.hca_core_clock
=
1780 init_hca
.hca_core_clock
;
1783 /* In case we got HCA frequency 0 - disable timestamping
1784 * to avoid dividing by zero
1786 if (!dev
->caps
.hca_core_clock
) {
1787 dev
->caps
.flags2
&= ~MLX4_DEV_CAP_FLAG2_TS
;
1789 "HCA frequency is 0 - timestamping is not supported\n");
1790 } else if (map_internal_clock(dev
)) {
1792 * Map internal clock,
1793 * in case of failure disable timestamping
1795 dev
->caps
.flags2
&= ~MLX4_DEV_CAP_FLAG2_TS
;
1796 mlx4_err(dev
, "Failed to map internal clock. Timestamping is not supported\n");
1800 err
= mlx4_init_slave(dev
);
1802 if (err
!= -EPROBE_DEFER
)
1803 mlx4_err(dev
, "Failed to initialize slave\n");
1807 err
= mlx4_slave_cap(dev
);
1809 mlx4_err(dev
, "Failed to obtain slave caps\n");
1814 if (map_bf_area(dev
))
1815 mlx4_dbg(dev
, "Failed to map blue flame area\n");
1817 /*Only the master set the ports, all the rest got it from it.*/
1818 if (!mlx4_is_slave(dev
))
1819 mlx4_set_port_mask(dev
);
1821 err
= mlx4_QUERY_ADAPTER(dev
, &adapter
);
1823 mlx4_err(dev
, "QUERY_ADAPTER command failed, aborting\n");
1827 /* Query CONFIG_DEV parameters */
1828 err
= mlx4_config_dev_retrieval(dev
, ¶ms
);
1829 if (err
&& err
!= -ENOTSUPP
) {
1830 mlx4_err(dev
, "Failed to query CONFIG_DEV parameters\n");
1832 dev
->caps
.rx_checksum_flags_port
[1] = params
.rx_csum_flags_port_1
;
1833 dev
->caps
.rx_checksum_flags_port
[2] = params
.rx_csum_flags_port_2
;
1835 priv
->eq_table
.inta_pin
= adapter
.inta_pin
;
1836 memcpy(dev
->board_id
, adapter
.board_id
, sizeof dev
->board_id
);
1841 unmap_internal_clock(dev
);
1844 if (mlx4_is_slave(dev
)) {
1845 kfree(dev
->caps
.qp0_qkey
);
1846 kfree(dev
->caps
.qp0_tunnel
);
1847 kfree(dev
->caps
.qp0_proxy
);
1848 kfree(dev
->caps
.qp1_tunnel
);
1849 kfree(dev
->caps
.qp1_proxy
);
1853 if (mlx4_is_slave(dev
))
1854 mlx4_slave_exit(dev
);
1856 mlx4_CLOSE_HCA(dev
, 0);
1859 if (!mlx4_is_slave(dev
))
1860 mlx4_free_icms(dev
);
1863 if (!mlx4_is_slave(dev
)) {
1865 mlx4_free_icm(dev
, priv
->fw
.fw_icm
, 0);
1870 static int mlx4_init_counters_table(struct mlx4_dev
*dev
)
1872 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1875 if (!(dev
->caps
.flags
& MLX4_DEV_CAP_FLAG_COUNTERS
))
1878 nent
= dev
->caps
.max_counters
;
1879 return mlx4_bitmap_init(&priv
->counters_bitmap
, nent
, nent
- 1, 0, 0);
1882 static void mlx4_cleanup_counters_table(struct mlx4_dev
*dev
)
1884 mlx4_bitmap_cleanup(&mlx4_priv(dev
)->counters_bitmap
);
1887 int __mlx4_counter_alloc(struct mlx4_dev
*dev
, u32
*idx
)
1889 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1891 if (!(dev
->caps
.flags
& MLX4_DEV_CAP_FLAG_COUNTERS
))
1894 *idx
= mlx4_bitmap_alloc(&priv
->counters_bitmap
);
1901 int mlx4_counter_alloc(struct mlx4_dev
*dev
, u32
*idx
)
1906 if (mlx4_is_mfunc(dev
)) {
1907 err
= mlx4_cmd_imm(dev
, 0, &out_param
, RES_COUNTER
,
1908 RES_OP_RESERVE
, MLX4_CMD_ALLOC_RES
,
1909 MLX4_CMD_TIME_CLASS_A
, MLX4_CMD_WRAPPED
);
1911 *idx
= get_param_l(&out_param
);
1915 return __mlx4_counter_alloc(dev
, idx
);
1917 EXPORT_SYMBOL_GPL(mlx4_counter_alloc
);
1919 void __mlx4_counter_free(struct mlx4_dev
*dev
, u32 idx
)
1921 mlx4_bitmap_free(&mlx4_priv(dev
)->counters_bitmap
, idx
, MLX4_USE_RR
);
1925 void mlx4_counter_free(struct mlx4_dev
*dev
, u32 idx
)
1929 if (mlx4_is_mfunc(dev
)) {
1930 set_param_l(&in_param
, idx
);
1931 mlx4_cmd(dev
, in_param
, RES_COUNTER
, RES_OP_RESERVE
,
1932 MLX4_CMD_FREE_RES
, MLX4_CMD_TIME_CLASS_A
,
1936 __mlx4_counter_free(dev
, idx
);
1938 EXPORT_SYMBOL_GPL(mlx4_counter_free
);
1940 static int mlx4_setup_hca(struct mlx4_dev
*dev
)
1942 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1945 __be32 ib_port_default_caps
;
1947 err
= mlx4_init_uar_table(dev
);
1949 mlx4_err(dev
, "Failed to initialize user access region table, aborting\n");
1953 err
= mlx4_uar_alloc(dev
, &priv
->driver_uar
);
1955 mlx4_err(dev
, "Failed to allocate driver access region, aborting\n");
1956 goto err_uar_table_free
;
1959 priv
->kar
= ioremap((phys_addr_t
) priv
->driver_uar
.pfn
<< PAGE_SHIFT
, PAGE_SIZE
);
1961 mlx4_err(dev
, "Couldn't map kernel access region, aborting\n");
1966 err
= mlx4_init_pd_table(dev
);
1968 mlx4_err(dev
, "Failed to initialize protection domain table, aborting\n");
1972 err
= mlx4_init_xrcd_table(dev
);
1974 mlx4_err(dev
, "Failed to initialize reliable connection domain table, aborting\n");
1975 goto err_pd_table_free
;
1978 err
= mlx4_init_mr_table(dev
);
1980 mlx4_err(dev
, "Failed to initialize memory region table, aborting\n");
1981 goto err_xrcd_table_free
;
1984 if (!mlx4_is_slave(dev
)) {
1985 err
= mlx4_init_mcg_table(dev
);
1987 mlx4_err(dev
, "Failed to initialize multicast group table, aborting\n");
1988 goto err_mr_table_free
;
1990 err
= mlx4_config_mad_demux(dev
);
1992 mlx4_err(dev
, "Failed in config_mad_demux, aborting\n");
1993 goto err_mcg_table_free
;
1997 err
= mlx4_init_eq_table(dev
);
1999 mlx4_err(dev
, "Failed to initialize event queue table, aborting\n");
2000 goto err_mcg_table_free
;
2003 err
= mlx4_cmd_use_events(dev
);
2005 mlx4_err(dev
, "Failed to switch to event-driven firmware commands, aborting\n");
2006 goto err_eq_table_free
;
2009 err
= mlx4_NOP(dev
);
2011 if (dev
->flags
& MLX4_FLAG_MSI_X
) {
2012 mlx4_warn(dev
, "NOP command failed to generate MSI-X interrupt IRQ %d)\n",
2013 priv
->eq_table
.eq
[dev
->caps
.num_comp_vectors
].irq
);
2014 mlx4_warn(dev
, "Trying again without MSI-X\n");
2016 mlx4_err(dev
, "NOP command failed to generate interrupt (IRQ %d), aborting\n",
2017 priv
->eq_table
.eq
[dev
->caps
.num_comp_vectors
].irq
);
2018 mlx4_err(dev
, "BIOS or ACPI interrupt routing problem?\n");
2024 mlx4_dbg(dev
, "NOP command IRQ test passed\n");
2026 err
= mlx4_init_cq_table(dev
);
2028 mlx4_err(dev
, "Failed to initialize completion queue table, aborting\n");
2032 err
= mlx4_init_srq_table(dev
);
2034 mlx4_err(dev
, "Failed to initialize shared receive queue table, aborting\n");
2035 goto err_cq_table_free
;
2038 err
= mlx4_init_qp_table(dev
);
2040 mlx4_err(dev
, "Failed to initialize queue pair table, aborting\n");
2041 goto err_srq_table_free
;
2044 err
= mlx4_init_counters_table(dev
);
2045 if (err
&& err
!= -ENOENT
) {
2046 mlx4_err(dev
, "Failed to initialize counters table, aborting\n");
2047 goto err_qp_table_free
;
2050 if (!mlx4_is_slave(dev
)) {
2051 for (port
= 1; port
<= dev
->caps
.num_ports
; port
++) {
2052 ib_port_default_caps
= 0;
2053 err
= mlx4_get_port_ib_caps(dev
, port
,
2054 &ib_port_default_caps
);
2056 mlx4_warn(dev
, "failed to get port %d default ib capabilities (%d). Continuing with caps = 0\n",
2058 dev
->caps
.ib_port_def_cap
[port
] = ib_port_default_caps
;
2060 /* initialize per-slave default ib port capabilities */
2061 if (mlx4_is_master(dev
)) {
2063 for (i
= 0; i
< dev
->num_slaves
; i
++) {
2064 if (i
== mlx4_master_func_num(dev
))
2066 priv
->mfunc
.master
.slave_state
[i
].ib_cap_mask
[port
] =
2067 ib_port_default_caps
;
2071 if (mlx4_is_mfunc(dev
))
2072 dev
->caps
.port_ib_mtu
[port
] = IB_MTU_2048
;
2074 dev
->caps
.port_ib_mtu
[port
] = IB_MTU_4096
;
2076 err
= mlx4_SET_PORT(dev
, port
, mlx4_is_master(dev
) ?
2077 dev
->caps
.pkey_table_len
[port
] : -1);
2079 mlx4_err(dev
, "Failed to set port %d, aborting\n",
2081 goto err_counters_table_free
;
2088 err_counters_table_free
:
2089 mlx4_cleanup_counters_table(dev
);
2092 mlx4_cleanup_qp_table(dev
);
2095 mlx4_cleanup_srq_table(dev
);
2098 mlx4_cleanup_cq_table(dev
);
2101 mlx4_cmd_use_polling(dev
);
2104 mlx4_cleanup_eq_table(dev
);
2107 if (!mlx4_is_slave(dev
))
2108 mlx4_cleanup_mcg_table(dev
);
2111 mlx4_cleanup_mr_table(dev
);
2113 err_xrcd_table_free
:
2114 mlx4_cleanup_xrcd_table(dev
);
2117 mlx4_cleanup_pd_table(dev
);
2123 mlx4_uar_free(dev
, &priv
->driver_uar
);
2126 mlx4_cleanup_uar_table(dev
);
2130 static void mlx4_enable_msi_x(struct mlx4_dev
*dev
)
2132 struct mlx4_priv
*priv
= mlx4_priv(dev
);
2133 struct msix_entry
*entries
;
2137 int nreq
= dev
->caps
.num_ports
* num_online_cpus() + MSIX_LEGACY_SZ
;
2139 nreq
= min_t(int, dev
->caps
.num_eqs
- dev
->caps
.reserved_eqs
,
2142 entries
= kcalloc(nreq
, sizeof *entries
, GFP_KERNEL
);
2146 for (i
= 0; i
< nreq
; ++i
)
2147 entries
[i
].entry
= i
;
2149 nreq
= pci_enable_msix_range(dev
->pdev
, entries
, 2, nreq
);
2154 } else if (nreq
< MSIX_LEGACY_SZ
+
2155 dev
->caps
.num_ports
* MIN_MSIX_P_PORT
) {
2156 /*Working in legacy mode , all EQ's shared*/
2157 dev
->caps
.comp_pool
= 0;
2158 dev
->caps
.num_comp_vectors
= nreq
- 1;
2160 dev
->caps
.comp_pool
= nreq
- MSIX_LEGACY_SZ
;
2161 dev
->caps
.num_comp_vectors
= MSIX_LEGACY_SZ
- 1;
2163 for (i
= 0; i
< nreq
; ++i
)
2164 priv
->eq_table
.eq
[i
].irq
= entries
[i
].vector
;
2166 dev
->flags
|= MLX4_FLAG_MSI_X
;
2173 dev
->caps
.num_comp_vectors
= 1;
2174 dev
->caps
.comp_pool
= 0;
2176 for (i
= 0; i
< 2; ++i
)
2177 priv
->eq_table
.eq
[i
].irq
= dev
->pdev
->irq
;
2180 static int mlx4_init_port_info(struct mlx4_dev
*dev
, int port
)
2182 struct mlx4_port_info
*info
= &mlx4_priv(dev
)->port
[port
];
2187 if (!mlx4_is_slave(dev
)) {
2188 mlx4_init_mac_table(dev
, &info
->mac_table
);
2189 mlx4_init_vlan_table(dev
, &info
->vlan_table
);
2190 mlx4_init_roce_gid_table(dev
, &info
->gid_table
);
2191 info
->base_qpn
= mlx4_get_base_qpn(dev
, port
);
2194 sprintf(info
->dev_name
, "mlx4_port%d", port
);
2195 info
->port_attr
.attr
.name
= info
->dev_name
;
2196 if (mlx4_is_mfunc(dev
))
2197 info
->port_attr
.attr
.mode
= S_IRUGO
;
2199 info
->port_attr
.attr
.mode
= S_IRUGO
| S_IWUSR
;
2200 info
->port_attr
.store
= set_port_type
;
2202 info
->port_attr
.show
= show_port_type
;
2203 sysfs_attr_init(&info
->port_attr
.attr
);
2205 err
= device_create_file(&dev
->pdev
->dev
, &info
->port_attr
);
2207 mlx4_err(dev
, "Failed to create file for port %d\n", port
);
2211 sprintf(info
->dev_mtu_name
, "mlx4_port%d_mtu", port
);
2212 info
->port_mtu_attr
.attr
.name
= info
->dev_mtu_name
;
2213 if (mlx4_is_mfunc(dev
))
2214 info
->port_mtu_attr
.attr
.mode
= S_IRUGO
;
2216 info
->port_mtu_attr
.attr
.mode
= S_IRUGO
| S_IWUSR
;
2217 info
->port_mtu_attr
.store
= set_port_ib_mtu
;
2219 info
->port_mtu_attr
.show
= show_port_ib_mtu
;
2220 sysfs_attr_init(&info
->port_mtu_attr
.attr
);
2222 err
= device_create_file(&dev
->pdev
->dev
, &info
->port_mtu_attr
);
2224 mlx4_err(dev
, "Failed to create mtu file for port %d\n", port
);
2225 device_remove_file(&info
->dev
->pdev
->dev
, &info
->port_attr
);
2232 static void mlx4_cleanup_port_info(struct mlx4_port_info
*info
)
2237 device_remove_file(&info
->dev
->pdev
->dev
, &info
->port_attr
);
2238 device_remove_file(&info
->dev
->pdev
->dev
, &info
->port_mtu_attr
);
2241 static int mlx4_init_steering(struct mlx4_dev
*dev
)
2243 struct mlx4_priv
*priv
= mlx4_priv(dev
);
2244 int num_entries
= dev
->caps
.num_ports
;
2247 priv
->steer
= kzalloc(sizeof(struct mlx4_steer
) * num_entries
, GFP_KERNEL
);
2251 for (i
= 0; i
< num_entries
; i
++)
2252 for (j
= 0; j
< MLX4_NUM_STEERS
; j
++) {
2253 INIT_LIST_HEAD(&priv
->steer
[i
].promisc_qps
[j
]);
2254 INIT_LIST_HEAD(&priv
->steer
[i
].steer_entries
[j
]);
2259 static void mlx4_clear_steering(struct mlx4_dev
*dev
)
2261 struct mlx4_priv
*priv
= mlx4_priv(dev
);
2262 struct mlx4_steer_index
*entry
, *tmp_entry
;
2263 struct mlx4_promisc_qp
*pqp
, *tmp_pqp
;
2264 int num_entries
= dev
->caps
.num_ports
;
2267 for (i
= 0; i
< num_entries
; i
++) {
2268 for (j
= 0; j
< MLX4_NUM_STEERS
; j
++) {
2269 list_for_each_entry_safe(pqp
, tmp_pqp
,
2270 &priv
->steer
[i
].promisc_qps
[j
],
2272 list_del(&pqp
->list
);
2275 list_for_each_entry_safe(entry
, tmp_entry
,
2276 &priv
->steer
[i
].steer_entries
[j
],
2278 list_del(&entry
->list
);
2279 list_for_each_entry_safe(pqp
, tmp_pqp
,
2282 list_del(&pqp
->list
);
2292 static int extended_func_num(struct pci_dev
*pdev
)
2294 return PCI_SLOT(pdev
->devfn
) * 8 + PCI_FUNC(pdev
->devfn
);
2297 #define MLX4_OWNER_BASE 0x8069c
2298 #define MLX4_OWNER_SIZE 4
2300 static int mlx4_get_ownership(struct mlx4_dev
*dev
)
2302 void __iomem
*owner
;
2305 if (pci_channel_offline(dev
->pdev
))
2308 owner
= ioremap(pci_resource_start(dev
->pdev
, 0) + MLX4_OWNER_BASE
,
2311 mlx4_err(dev
, "Failed to obtain ownership bit\n");
2320 static void mlx4_free_ownership(struct mlx4_dev
*dev
)
2322 void __iomem
*owner
;
2324 if (pci_channel_offline(dev
->pdev
))
2327 owner
= ioremap(pci_resource_start(dev
->pdev
, 0) + MLX4_OWNER_BASE
,
2330 mlx4_err(dev
, "Failed to obtain ownership bit\n");
2338 #define SRIOV_VALID_STATE(flags) (!!((flags) & MLX4_FLAG_SRIOV) ==\
2339 !!((flags) & MLX4_FLAG_MASTER))
2341 static u64
mlx4_enable_sriov(struct mlx4_dev
*dev
, struct pci_dev
*pdev
,
2342 u8 total_vfs
, int existing_vfs
)
2344 u64 dev_flags
= dev
->flags
;
2346 dev
->dev_vfs
= kzalloc(
2347 total_vfs
* sizeof(*dev
->dev_vfs
),
2349 if (NULL
== dev
->dev_vfs
) {
2350 mlx4_err(dev
, "Failed to allocate memory for VFs\n");
2352 } else if (!(dev
->flags
& MLX4_FLAG_SRIOV
)) {
2355 atomic_inc(&pf_loading
);
2357 if (existing_vfs
!= total_vfs
)
2358 mlx4_err(dev
, "SR-IOV was already enabled, but with num_vfs (%d) different than requested (%d)\n",
2359 existing_vfs
, total_vfs
);
2361 mlx4_warn(dev
, "Enabling SR-IOV with %d VFs\n", total_vfs
);
2362 err
= pci_enable_sriov(pdev
, total_vfs
);
2365 mlx4_err(dev
, "Failed to enable SR-IOV, continuing without SR-IOV (err = %d)\n",
2367 atomic_dec(&pf_loading
);
2370 mlx4_warn(dev
, "Running in master mode\n");
2371 dev_flags
|= MLX4_FLAG_SRIOV
|
2373 dev_flags
&= ~MLX4_FLAG_SLAVE
;
2374 dev
->num_vfs
= total_vfs
;
2381 kfree(dev
->dev_vfs
);
2382 return dev_flags
& ~MLX4_FLAG_MASTER
;
2386 MLX4_DEV_CAP_CHECK_NUM_VFS_ABOVE_64
= -1,
2389 static int mlx4_check_dev_cap(struct mlx4_dev
*dev
, struct mlx4_dev_cap
*dev_cap
,
2392 int requested_vfs
= nvfs
[0] + nvfs
[1] + nvfs
[2];
2393 /* Checking for 64 VFs as a limitation of CX2 */
2394 if (!(dev_cap
->flags2
& MLX4_DEV_CAP_FLAG2_80_VFS
) &&
2395 requested_vfs
>= 64) {
2396 mlx4_err(dev
, "Requested %d VFs, but FW does not support more than 64\n",
2398 return MLX4_DEV_CAP_CHECK_NUM_VFS_ABOVE_64
;
2403 static int mlx4_load_one(struct pci_dev
*pdev
, int pci_dev_data
,
2404 int total_vfs
, int *nvfs
, struct mlx4_priv
*priv
)
2406 struct mlx4_dev
*dev
;
2411 struct mlx4_dev_cap
*dev_cap
= NULL
;
2412 int existing_vfs
= 0;
2416 INIT_LIST_HEAD(&priv
->ctx_list
);
2417 spin_lock_init(&priv
->ctx_lock
);
2419 mutex_init(&priv
->port_mutex
);
2421 INIT_LIST_HEAD(&priv
->pgdir_list
);
2422 mutex_init(&priv
->pgdir_mutex
);
2424 INIT_LIST_HEAD(&priv
->bf_list
);
2425 mutex_init(&priv
->bf_mutex
);
2427 dev
->rev_id
= pdev
->revision
;
2428 dev
->numa_node
= dev_to_node(&pdev
->dev
);
2430 /* Detect if this device is a virtual function */
2431 if (pci_dev_data
& MLX4_PCI_DEV_IS_VF
) {
2432 mlx4_warn(dev
, "Detected virtual function - running in slave mode\n");
2433 dev
->flags
|= MLX4_FLAG_SLAVE
;
2435 /* We reset the device and enable SRIOV only for physical
2436 * devices. Try to claim ownership on the device;
2437 * if already taken, skip -- do not allow multiple PFs */
2438 err
= mlx4_get_ownership(dev
);
2443 mlx4_warn(dev
, "Multiple PFs not yet supported - Skipping PF\n");
2448 atomic_set(&priv
->opreq_count
, 0);
2449 INIT_WORK(&priv
->opreq_task
, mlx4_opreq_action
);
2452 * Now reset the HCA before we touch the PCI capabilities or
2453 * attempt a firmware command, since a boot ROM may have left
2454 * the HCA in an undefined state.
2456 err
= mlx4_reset(dev
);
2458 mlx4_err(dev
, "Failed to reset HCA, aborting\n");
2463 existing_vfs
= pci_num_vf(pdev
);
2464 dev
->flags
= MLX4_FLAG_MASTER
;
2465 dev
->num_vfs
= total_vfs
;
2470 err
= mlx4_cmd_init(dev
);
2472 mlx4_err(dev
, "Failed to init command interface, aborting\n");
2476 /* In slave functions, the communication channel must be initialized
2477 * before posting commands. Also, init num_slaves before calling
2479 if (mlx4_is_mfunc(dev
)) {
2480 if (mlx4_is_master(dev
)) {
2481 dev
->num_slaves
= MLX4_MAX_NUM_SLAVES
;
2484 dev
->num_slaves
= 0;
2485 err
= mlx4_multi_func_init(dev
);
2487 mlx4_err(dev
, "Failed to init slave mfunc interface, aborting\n");
2493 err
= mlx4_init_fw(dev
);
2495 mlx4_err(dev
, "Failed to init fw, aborting.\n");
2499 if (mlx4_is_master(dev
)) {
2501 dev_cap
= kzalloc(sizeof(*dev_cap
), GFP_KERNEL
);
2508 err
= mlx4_QUERY_DEV_CAP(dev
, dev_cap
);
2510 mlx4_err(dev
, "QUERY_DEV_CAP command failed, aborting.\n");
2514 if (mlx4_check_dev_cap(dev
, dev_cap
, nvfs
))
2517 if (!(dev_cap
->flags2
& MLX4_DEV_CAP_FLAG2_SYS_EQS
)) {
2518 u64 dev_flags
= mlx4_enable_sriov(dev
, pdev
, total_vfs
,
2521 mlx4_cmd_cleanup(dev
, MLX4_CMD_CLEANUP_ALL
);
2522 dev
->flags
= dev_flags
;
2523 if (!SRIOV_VALID_STATE(dev
->flags
)) {
2524 mlx4_err(dev
, "Invalid SRIOV state\n");
2527 err
= mlx4_reset(dev
);
2529 mlx4_err(dev
, "Failed to reset HCA, aborting.\n");
2535 /* Legacy mode FW requires SRIOV to be enabled before
2536 * doing QUERY_DEV_CAP, since max_eq's value is different if
2539 memset(dev_cap
, 0, sizeof(*dev_cap
));
2540 err
= mlx4_QUERY_DEV_CAP(dev
, dev_cap
);
2542 mlx4_err(dev
, "QUERY_DEV_CAP command failed, aborting.\n");
2546 if (mlx4_check_dev_cap(dev
, dev_cap
, nvfs
))
2551 err
= mlx4_init_hca(dev
);
2553 if (err
== -EACCES
) {
2554 /* Not primary Physical function
2555 * Running in slave mode */
2556 mlx4_cmd_cleanup(dev
, MLX4_CMD_CLEANUP_ALL
);
2557 /* We're not a PF */
2558 if (dev
->flags
& MLX4_FLAG_SRIOV
) {
2560 pci_disable_sriov(pdev
);
2561 if (mlx4_is_master(dev
))
2562 atomic_dec(&pf_loading
);
2563 dev
->flags
&= ~MLX4_FLAG_SRIOV
;
2565 if (!mlx4_is_slave(dev
))
2566 mlx4_free_ownership(dev
);
2567 dev
->flags
|= MLX4_FLAG_SLAVE
;
2568 dev
->flags
&= ~MLX4_FLAG_MASTER
;
2574 if (mlx4_is_master(dev
) && (dev_cap
->flags2
& MLX4_DEV_CAP_FLAG2_SYS_EQS
)) {
2575 u64 dev_flags
= mlx4_enable_sriov(dev
, pdev
, total_vfs
, existing_vfs
);
2577 if ((dev
->flags
^ dev_flags
) & (MLX4_FLAG_MASTER
| MLX4_FLAG_SLAVE
)) {
2578 mlx4_cmd_cleanup(dev
, MLX4_CMD_CLEANUP_VHCR
);
2579 dev
->flags
= dev_flags
;
2580 err
= mlx4_cmd_init(dev
);
2582 /* Only VHCR is cleaned up, so could still
2585 mlx4_err(dev
, "Failed to init VHCR command interface, aborting\n");
2589 dev
->flags
= dev_flags
;
2592 if (!SRIOV_VALID_STATE(dev
->flags
)) {
2593 mlx4_err(dev
, "Invalid SRIOV state\n");
2598 /* check if the device is functioning at its maximum possible speed.
2599 * No return code for this call, just warn the user in case of PCI
2600 * express device capabilities are under-satisfied by the bus.
2602 if (!mlx4_is_slave(dev
))
2603 mlx4_check_pcie_caps(dev
);
2605 /* In master functions, the communication channel must be initialized
2606 * after obtaining its address from fw */
2607 if (mlx4_is_master(dev
)) {
2610 mlx4_foreach_port(i
, dev
, MLX4_PORT_TYPE_IB
)
2614 (num_vfs_argc
> 1 || probe_vfs_argc
> 1)) {
2616 "Invalid syntax of num_vfs/probe_vfs with IB port - single port VFs syntax is only supported when all ports are configured as ethernet\n");
2620 if (dev
->caps
.num_ports
< 2 &&
2624 "Error: Trying to configure VFs on port 2, but HCA has only %d physical ports\n",
2625 dev
->caps
.num_ports
);
2628 memcpy(dev
->nvfs
, nvfs
, sizeof(dev
->nvfs
));
2630 for (i
= 0; i
< sizeof(dev
->nvfs
)/sizeof(dev
->nvfs
[0]); i
++) {
2633 for (j
= 0; j
< dev
->nvfs
[i
]; ++sum
, ++j
) {
2634 dev
->dev_vfs
[sum
].min_port
= i
< 2 ? i
+ 1 : 1;
2635 dev
->dev_vfs
[sum
].n_ports
= i
< 2 ? 1 :
2636 dev
->caps
.num_ports
;
2640 /* In master functions, the communication channel
2641 * must be initialized after obtaining its address from fw
2643 err
= mlx4_multi_func_init(dev
);
2645 mlx4_err(dev
, "Failed to init master mfunc interface, aborting.\n");
2650 err
= mlx4_alloc_eq_table(dev
);
2652 goto err_master_mfunc
;
2654 priv
->msix_ctl
.pool_bm
= 0;
2655 mutex_init(&priv
->msix_ctl
.pool_lock
);
2657 mlx4_enable_msi_x(dev
);
2658 if ((mlx4_is_mfunc(dev
)) &&
2659 !(dev
->flags
& MLX4_FLAG_MSI_X
)) {
2661 mlx4_err(dev
, "INTx is not supported in multi-function mode, aborting\n");
2665 if (!mlx4_is_slave(dev
)) {
2666 err
= mlx4_init_steering(dev
);
2668 goto err_disable_msix
;
2671 err
= mlx4_setup_hca(dev
);
2672 if (err
== -EBUSY
&& (dev
->flags
& MLX4_FLAG_MSI_X
) &&
2673 !mlx4_is_mfunc(dev
)) {
2674 dev
->flags
&= ~MLX4_FLAG_MSI_X
;
2675 dev
->caps
.num_comp_vectors
= 1;
2676 dev
->caps
.comp_pool
= 0;
2677 pci_disable_msix(pdev
);
2678 err
= mlx4_setup_hca(dev
);
2684 mlx4_init_quotas(dev
);
2686 for (port
= 1; port
<= dev
->caps
.num_ports
; port
++) {
2687 err
= mlx4_init_port_info(dev
, port
);
2692 err
= mlx4_register_device(dev
);
2696 mlx4_request_modules(dev
);
2698 mlx4_sense_init(dev
);
2699 mlx4_start_sense(dev
);
2703 if (mlx4_is_master(dev
) && dev
->num_vfs
)
2704 atomic_dec(&pf_loading
);
2709 for (--port
; port
>= 1; --port
)
2710 mlx4_cleanup_port_info(&priv
->port
[port
]);
2712 mlx4_cleanup_counters_table(dev
);
2713 mlx4_cleanup_qp_table(dev
);
2714 mlx4_cleanup_srq_table(dev
);
2715 mlx4_cleanup_cq_table(dev
);
2716 mlx4_cmd_use_polling(dev
);
2717 mlx4_cleanup_eq_table(dev
);
2718 mlx4_cleanup_mcg_table(dev
);
2719 mlx4_cleanup_mr_table(dev
);
2720 mlx4_cleanup_xrcd_table(dev
);
2721 mlx4_cleanup_pd_table(dev
);
2722 mlx4_cleanup_uar_table(dev
);
2725 if (!mlx4_is_slave(dev
))
2726 mlx4_clear_steering(dev
);
2729 if (dev
->flags
& MLX4_FLAG_MSI_X
)
2730 pci_disable_msix(pdev
);
2733 mlx4_free_eq_table(dev
);
2736 if (mlx4_is_master(dev
))
2737 mlx4_multi_func_cleanup(dev
);
2739 if (mlx4_is_slave(dev
)) {
2740 kfree(dev
->caps
.qp0_qkey
);
2741 kfree(dev
->caps
.qp0_tunnel
);
2742 kfree(dev
->caps
.qp0_proxy
);
2743 kfree(dev
->caps
.qp1_tunnel
);
2744 kfree(dev
->caps
.qp1_proxy
);
2748 mlx4_close_hca(dev
);
2754 if (mlx4_is_slave(dev
))
2755 mlx4_multi_func_cleanup(dev
);
2758 mlx4_cmd_cleanup(dev
, MLX4_CMD_CLEANUP_ALL
);
2761 if (dev
->flags
& MLX4_FLAG_SRIOV
&& !existing_vfs
)
2762 pci_disable_sriov(pdev
);
2764 if (mlx4_is_master(dev
) && dev
->num_vfs
)
2765 atomic_dec(&pf_loading
);
2767 kfree(priv
->dev
.dev_vfs
);
2769 if (!mlx4_is_slave(dev
))
2770 mlx4_free_ownership(dev
);
2776 static int __mlx4_init_one(struct pci_dev
*pdev
, int pci_dev_data
,
2777 struct mlx4_priv
*priv
)
2780 int nvfs
[MLX4_MAX_PORTS
+ 1] = {0, 0, 0};
2781 int prb_vf
[MLX4_MAX_PORTS
+ 1] = {0, 0, 0};
2782 const int param_map
[MLX4_MAX_PORTS
+ 1][MLX4_MAX_PORTS
+ 1] = {
2783 {2, 0, 0}, {0, 1, 2}, {0, 1, 2} };
2784 unsigned total_vfs
= 0;
2787 pr_info(DRV_NAME
": Initializing %s\n", pci_name(pdev
));
2789 err
= pci_enable_device(pdev
);
2791 dev_err(&pdev
->dev
, "Cannot enable PCI device, aborting\n");
2795 /* Due to requirement that all VFs and the PF are *guaranteed* 2 MACS
2796 * per port, we must limit the number of VFs to 63 (since their are
2799 for (i
= 0; i
< sizeof(nvfs
)/sizeof(nvfs
[0]) && i
< num_vfs_argc
;
2800 total_vfs
+= nvfs
[param_map
[num_vfs_argc
- 1][i
]], i
++) {
2801 nvfs
[param_map
[num_vfs_argc
- 1][i
]] = num_vfs
[i
];
2803 dev_err(&pdev
->dev
, "num_vfs module parameter cannot be negative\n");
2805 goto err_disable_pdev
;
2808 for (i
= 0; i
< sizeof(prb_vf
)/sizeof(prb_vf
[0]) && i
< probe_vfs_argc
;
2810 prb_vf
[param_map
[probe_vfs_argc
- 1][i
]] = probe_vf
[i
];
2811 if (prb_vf
[i
] < 0 || prb_vf
[i
] > nvfs
[i
]) {
2812 dev_err(&pdev
->dev
, "probe_vf module parameter cannot be negative or greater than num_vfs\n");
2814 goto err_disable_pdev
;
2817 if (total_vfs
>= MLX4_MAX_NUM_VF
) {
2819 "Requested more VF's (%d) than allowed (%d)\n",
2820 total_vfs
, MLX4_MAX_NUM_VF
- 1);
2822 goto err_disable_pdev
;
2825 for (i
= 0; i
< MLX4_MAX_PORTS
; i
++) {
2826 if (nvfs
[i
] + nvfs
[2] >= MLX4_MAX_NUM_VF_P_PORT
) {
2828 "Requested more VF's (%d) for port (%d) than allowed (%d)\n",
2829 nvfs
[i
] + nvfs
[2], i
+ 1,
2830 MLX4_MAX_NUM_VF_P_PORT
- 1);
2832 goto err_disable_pdev
;
2836 /* Check for BARs. */
2837 if (!(pci_dev_data
& MLX4_PCI_DEV_IS_VF
) &&
2838 !(pci_resource_flags(pdev
, 0) & IORESOURCE_MEM
)) {
2839 dev_err(&pdev
->dev
, "Missing DCS, aborting (driver_data: 0x%x, pci_resource_flags(pdev, 0):0x%lx)\n",
2840 pci_dev_data
, pci_resource_flags(pdev
, 0));
2842 goto err_disable_pdev
;
2844 if (!(pci_resource_flags(pdev
, 2) & IORESOURCE_MEM
)) {
2845 dev_err(&pdev
->dev
, "Missing UAR, aborting\n");
2847 goto err_disable_pdev
;
2850 err
= pci_request_regions(pdev
, DRV_NAME
);
2852 dev_err(&pdev
->dev
, "Couldn't get PCI resources, aborting\n");
2853 goto err_disable_pdev
;
2856 pci_set_master(pdev
);
2858 err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(64));
2860 dev_warn(&pdev
->dev
, "Warning: couldn't set 64-bit PCI DMA mask\n");
2861 err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
2863 dev_err(&pdev
->dev
, "Can't set PCI DMA mask, aborting\n");
2864 goto err_release_regions
;
2867 err
= pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(64));
2869 dev_warn(&pdev
->dev
, "Warning: couldn't set 64-bit consistent PCI DMA mask\n");
2870 err
= pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(32));
2872 dev_err(&pdev
->dev
, "Can't set consistent PCI DMA mask, aborting\n");
2873 goto err_release_regions
;
2877 /* Allow large DMA segments, up to the firmware limit of 1 GB */
2878 dma_set_max_seg_size(&pdev
->dev
, 1024 * 1024 * 1024);
2879 /* Detect if this device is a virtual function */
2880 if (pci_dev_data
& MLX4_PCI_DEV_IS_VF
) {
2881 /* When acting as pf, we normally skip vfs unless explicitly
2882 * requested to probe them.
2885 unsigned vfs_offset
= 0;
2887 for (i
= 0; i
< sizeof(nvfs
)/sizeof(nvfs
[0]) &&
2888 vfs_offset
+ nvfs
[i
] < extended_func_num(pdev
);
2889 vfs_offset
+= nvfs
[i
], i
++)
2891 if (i
== sizeof(nvfs
)/sizeof(nvfs
[0])) {
2893 goto err_release_regions
;
2895 if ((extended_func_num(pdev
) - vfs_offset
)
2897 dev_warn(&pdev
->dev
, "Skipping virtual function:%d\n",
2898 extended_func_num(pdev
));
2900 goto err_release_regions
;
2905 err
= mlx4_load_one(pdev
, pci_dev_data
, total_vfs
, nvfs
, priv
);
2907 goto err_release_regions
;
2910 err_release_regions
:
2911 pci_release_regions(pdev
);
2914 pci_disable_device(pdev
);
2915 pci_set_drvdata(pdev
, NULL
);
2919 static int mlx4_init_one(struct pci_dev
*pdev
, const struct pci_device_id
*id
)
2921 struct mlx4_priv
*priv
;
2922 struct mlx4_dev
*dev
;
2925 printk_once(KERN_INFO
"%s", mlx4_version
);
2927 priv
= kzalloc(sizeof(*priv
), GFP_KERNEL
);
2933 pci_set_drvdata(pdev
, dev
);
2934 priv
->pci_dev_data
= id
->driver_data
;
2936 ret
= __mlx4_init_one(pdev
, id
->driver_data
, priv
);
2943 static void mlx4_unload_one(struct pci_dev
*pdev
)
2945 struct mlx4_dev
*dev
= pci_get_drvdata(pdev
);
2946 struct mlx4_priv
*priv
= mlx4_priv(dev
);
2954 pci_dev_data
= priv
->pci_dev_data
;
2956 /* Disabling SR-IOV is not allowed while there are active vf's */
2957 if (mlx4_is_master(dev
)) {
2958 active_vfs
= mlx4_how_many_lives_vf(dev
);
2960 pr_warn("Removing PF when there are active VF's !!\n");
2961 pr_warn("Will not disable SR-IOV.\n");
2964 mlx4_stop_sense(dev
);
2965 mlx4_unregister_device(dev
);
2967 for (p
= 1; p
<= dev
->caps
.num_ports
; p
++) {
2968 mlx4_cleanup_port_info(&priv
->port
[p
]);
2969 mlx4_CLOSE_PORT(dev
, p
);
2972 if (mlx4_is_master(dev
))
2973 mlx4_free_resource_tracker(dev
,
2974 RES_TR_FREE_SLAVES_ONLY
);
2976 mlx4_cleanup_counters_table(dev
);
2977 mlx4_cleanup_qp_table(dev
);
2978 mlx4_cleanup_srq_table(dev
);
2979 mlx4_cleanup_cq_table(dev
);
2980 mlx4_cmd_use_polling(dev
);
2981 mlx4_cleanup_eq_table(dev
);
2982 mlx4_cleanup_mcg_table(dev
);
2983 mlx4_cleanup_mr_table(dev
);
2984 mlx4_cleanup_xrcd_table(dev
);
2985 mlx4_cleanup_pd_table(dev
);
2987 if (mlx4_is_master(dev
))
2988 mlx4_free_resource_tracker(dev
,
2989 RES_TR_FREE_STRUCTS_ONLY
);
2992 mlx4_uar_free(dev
, &priv
->driver_uar
);
2993 mlx4_cleanup_uar_table(dev
);
2994 if (!mlx4_is_slave(dev
))
2995 mlx4_clear_steering(dev
);
2996 mlx4_free_eq_table(dev
);
2997 if (mlx4_is_master(dev
))
2998 mlx4_multi_func_cleanup(dev
);
2999 mlx4_close_hca(dev
);
3001 if (mlx4_is_slave(dev
))
3002 mlx4_multi_func_cleanup(dev
);
3003 mlx4_cmd_cleanup(dev
, MLX4_CMD_CLEANUP_ALL
);
3005 if (dev
->flags
& MLX4_FLAG_MSI_X
)
3006 pci_disable_msix(pdev
);
3007 if (dev
->flags
& MLX4_FLAG_SRIOV
&& !active_vfs
) {
3008 mlx4_warn(dev
, "Disabling SR-IOV\n");
3009 pci_disable_sriov(pdev
);
3010 dev
->flags
&= ~MLX4_FLAG_SRIOV
;
3014 if (!mlx4_is_slave(dev
))
3015 mlx4_free_ownership(dev
);
3017 kfree(dev
->caps
.qp0_qkey
);
3018 kfree(dev
->caps
.qp0_tunnel
);
3019 kfree(dev
->caps
.qp0_proxy
);
3020 kfree(dev
->caps
.qp1_tunnel
);
3021 kfree(dev
->caps
.qp1_proxy
);
3022 kfree(dev
->dev_vfs
);
3024 memset(priv
, 0, sizeof(*priv
));
3025 priv
->pci_dev_data
= pci_dev_data
;
3029 static void mlx4_remove_one(struct pci_dev
*pdev
)
3031 struct mlx4_dev
*dev
= pci_get_drvdata(pdev
);
3032 struct mlx4_priv
*priv
= mlx4_priv(dev
);
3034 mlx4_unload_one(pdev
);
3035 pci_release_regions(pdev
);
3036 pci_disable_device(pdev
);
3038 pci_set_drvdata(pdev
, NULL
);
3041 int mlx4_restart_one(struct pci_dev
*pdev
)
3043 struct mlx4_dev
*dev
= pci_get_drvdata(pdev
);
3044 struct mlx4_priv
*priv
= mlx4_priv(dev
);
3045 int nvfs
[MLX4_MAX_PORTS
+ 1] = {0, 0, 0};
3046 int pci_dev_data
, err
, total_vfs
;
3048 pci_dev_data
= priv
->pci_dev_data
;
3049 total_vfs
= dev
->num_vfs
;
3050 memcpy(nvfs
, dev
->nvfs
, sizeof(dev
->nvfs
));
3052 mlx4_unload_one(pdev
);
3053 err
= mlx4_load_one(pdev
, pci_dev_data
, total_vfs
, nvfs
, priv
);
3055 mlx4_err(dev
, "%s: ERROR: mlx4_load_one failed, pci_name=%s, err=%d\n",
3056 __func__
, pci_name(pdev
), err
);
3063 static const struct pci_device_id mlx4_pci_table
[] = {
3064 /* MT25408 "Hermon" SDR */
3065 { PCI_VDEVICE(MELLANOX
, 0x6340), MLX4_PCI_DEV_FORCE_SENSE_PORT
},
3066 /* MT25408 "Hermon" DDR */
3067 { PCI_VDEVICE(MELLANOX
, 0x634a), MLX4_PCI_DEV_FORCE_SENSE_PORT
},
3068 /* MT25408 "Hermon" QDR */
3069 { PCI_VDEVICE(MELLANOX
, 0x6354), MLX4_PCI_DEV_FORCE_SENSE_PORT
},
3070 /* MT25408 "Hermon" DDR PCIe gen2 */
3071 { PCI_VDEVICE(MELLANOX
, 0x6732), MLX4_PCI_DEV_FORCE_SENSE_PORT
},
3072 /* MT25408 "Hermon" QDR PCIe gen2 */
3073 { PCI_VDEVICE(MELLANOX
, 0x673c), MLX4_PCI_DEV_FORCE_SENSE_PORT
},
3074 /* MT25408 "Hermon" EN 10GigE */
3075 { PCI_VDEVICE(MELLANOX
, 0x6368), MLX4_PCI_DEV_FORCE_SENSE_PORT
},
3076 /* MT25408 "Hermon" EN 10GigE PCIe gen2 */
3077 { PCI_VDEVICE(MELLANOX
, 0x6750), MLX4_PCI_DEV_FORCE_SENSE_PORT
},
3078 /* MT25458 ConnectX EN 10GBASE-T 10GigE */
3079 { PCI_VDEVICE(MELLANOX
, 0x6372), MLX4_PCI_DEV_FORCE_SENSE_PORT
},
3080 /* MT25458 ConnectX EN 10GBASE-T+Gen2 10GigE */
3081 { PCI_VDEVICE(MELLANOX
, 0x675a), MLX4_PCI_DEV_FORCE_SENSE_PORT
},
3082 /* MT26468 ConnectX EN 10GigE PCIe gen2*/
3083 { PCI_VDEVICE(MELLANOX
, 0x6764), MLX4_PCI_DEV_FORCE_SENSE_PORT
},
3084 /* MT26438 ConnectX EN 40GigE PCIe gen2 5GT/s */
3085 { PCI_VDEVICE(MELLANOX
, 0x6746), MLX4_PCI_DEV_FORCE_SENSE_PORT
},
3086 /* MT26478 ConnectX2 40GigE PCIe gen2 */
3087 { PCI_VDEVICE(MELLANOX
, 0x676e), MLX4_PCI_DEV_FORCE_SENSE_PORT
},
3088 /* MT25400 Family [ConnectX-2 Virtual Function] */
3089 { PCI_VDEVICE(MELLANOX
, 0x1002), MLX4_PCI_DEV_IS_VF
},
3090 /* MT27500 Family [ConnectX-3] */
3091 { PCI_VDEVICE(MELLANOX
, 0x1003), 0 },
3092 /* MT27500 Family [ConnectX-3 Virtual Function] */
3093 { PCI_VDEVICE(MELLANOX
, 0x1004), MLX4_PCI_DEV_IS_VF
},
3094 { PCI_VDEVICE(MELLANOX
, 0x1005), 0 }, /* MT27510 Family */
3095 { PCI_VDEVICE(MELLANOX
, 0x1006), 0 }, /* MT27511 Family */
3096 { PCI_VDEVICE(MELLANOX
, 0x1007), 0 }, /* MT27520 Family */
3097 { PCI_VDEVICE(MELLANOX
, 0x1008), 0 }, /* MT27521 Family */
3098 { PCI_VDEVICE(MELLANOX
, 0x1009), 0 }, /* MT27530 Family */
3099 { PCI_VDEVICE(MELLANOX
, 0x100a), 0 }, /* MT27531 Family */
3100 { PCI_VDEVICE(MELLANOX
, 0x100b), 0 }, /* MT27540 Family */
3101 { PCI_VDEVICE(MELLANOX
, 0x100c), 0 }, /* MT27541 Family */
3102 { PCI_VDEVICE(MELLANOX
, 0x100d), 0 }, /* MT27550 Family */
3103 { PCI_VDEVICE(MELLANOX
, 0x100e), 0 }, /* MT27551 Family */
3104 { PCI_VDEVICE(MELLANOX
, 0x100f), 0 }, /* MT27560 Family */
3105 { PCI_VDEVICE(MELLANOX
, 0x1010), 0 }, /* MT27561 Family */
3109 MODULE_DEVICE_TABLE(pci
, mlx4_pci_table
);
3111 static pci_ers_result_t
mlx4_pci_err_detected(struct pci_dev
*pdev
,
3112 pci_channel_state_t state
)
3114 mlx4_unload_one(pdev
);
3116 return state
== pci_channel_io_perm_failure
?
3117 PCI_ERS_RESULT_DISCONNECT
: PCI_ERS_RESULT_NEED_RESET
;
3120 static pci_ers_result_t
mlx4_pci_slot_reset(struct pci_dev
*pdev
)
3122 struct mlx4_dev
*dev
= pci_get_drvdata(pdev
);
3123 struct mlx4_priv
*priv
= mlx4_priv(dev
);
3126 ret
= __mlx4_init_one(pdev
, priv
->pci_dev_data
, priv
);
3128 return ret
? PCI_ERS_RESULT_DISCONNECT
: PCI_ERS_RESULT_RECOVERED
;
3131 static const struct pci_error_handlers mlx4_err_handler
= {
3132 .error_detected
= mlx4_pci_err_detected
,
3133 .slot_reset
= mlx4_pci_slot_reset
,
3136 static struct pci_driver mlx4_driver
= {
3138 .id_table
= mlx4_pci_table
,
3139 .probe
= mlx4_init_one
,
3140 .shutdown
= mlx4_unload_one
,
3141 .remove
= mlx4_remove_one
,
3142 .err_handler
= &mlx4_err_handler
,
3145 static int __init
mlx4_verify_params(void)
3147 if ((log_num_mac
< 0) || (log_num_mac
> 7)) {
3148 pr_warn("mlx4_core: bad num_mac: %d\n", log_num_mac
);
3152 if (log_num_vlan
!= 0)
3153 pr_warn("mlx4_core: log_num_vlan - obsolete module param, using %d\n",
3154 MLX4_LOG_NUM_VLANS
);
3157 pr_warn("mlx4_core: use_prio - obsolete module param, ignored\n");
3159 if ((log_mtts_per_seg
< 1) || (log_mtts_per_seg
> 7)) {
3160 pr_warn("mlx4_core: bad log_mtts_per_seg: %d\n",
3165 /* Check if module param for ports type has legal combination */
3166 if (port_type_array
[0] == false && port_type_array
[1] == true) {
3167 pr_warn("Module parameter configuration ETH/IB is not supported. Switching to default configuration IB/IB\n");
3168 port_type_array
[0] = true;
3171 if (mlx4_log_num_mgm_entry_size
!= -1 &&
3172 (mlx4_log_num_mgm_entry_size
< MLX4_MIN_MGM_LOG_ENTRY_SIZE
||
3173 mlx4_log_num_mgm_entry_size
> MLX4_MAX_MGM_LOG_ENTRY_SIZE
)) {
3174 pr_warn("mlx4_core: mlx4_log_num_mgm_entry_size (%d) not in legal range (-1 or %d..%d)\n",
3175 mlx4_log_num_mgm_entry_size
,
3176 MLX4_MIN_MGM_LOG_ENTRY_SIZE
,
3177 MLX4_MAX_MGM_LOG_ENTRY_SIZE
);
3184 static int __init
mlx4_init(void)
3188 if (mlx4_verify_params())
3193 mlx4_wq
= create_singlethread_workqueue("mlx4");
3197 ret
= pci_register_driver(&mlx4_driver
);
3199 destroy_workqueue(mlx4_wq
);
3200 return ret
< 0 ? ret
: 0;
3203 static void __exit
mlx4_cleanup(void)
3205 pci_unregister_driver(&mlx4_driver
);
3206 destroy_workqueue(mlx4_wq
);
3209 module_init(mlx4_init
);
3210 module_exit(mlx4_cleanup
);