2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
5 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * OpenIB.org BSD license below:
13 * Redistribution and use in source and binary forms, with or
14 * without modification, are permitted provided that the following
17 * - Redistributions of source code must retain the above
18 * copyright notice, this list of conditions and the following
21 * - Redistributions in binary form must reproduce the above
22 * copyright notice, this list of conditions and the following
23 * disclaimer in the documentation and/or other materials
24 * provided with the distribution.
26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/module.h>
37 #include <linux/init.h>
38 #include <linux/errno.h>
39 #include <linux/pci.h>
40 #include <linux/dma-mapping.h>
41 #include <linux/slab.h>
42 #include <linux/io-mapping.h>
43 #include <linux/delay.h>
44 #include <linux/kmod.h>
46 #include <linux/mlx4/device.h>
47 #include <linux/mlx4/doorbell.h>
53 MODULE_AUTHOR("Roland Dreier");
54 MODULE_DESCRIPTION("Mellanox ConnectX HCA low-level driver");
55 MODULE_LICENSE("Dual BSD/GPL");
56 MODULE_VERSION(DRV_VERSION
);
58 struct workqueue_struct
*mlx4_wq
;
60 #ifdef CONFIG_MLX4_DEBUG
62 int mlx4_debug_level
= 0;
63 module_param_named(debug_level
, mlx4_debug_level
, int, 0644);
64 MODULE_PARM_DESC(debug_level
, "Enable debug tracing if > 0");
66 #endif /* CONFIG_MLX4_DEBUG */
71 module_param(msi_x
, int, 0444);
72 MODULE_PARM_DESC(msi_x
, "attempt to use MSI-X if nonzero");
74 #else /* CONFIG_PCI_MSI */
78 #endif /* CONFIG_PCI_MSI */
80 static uint8_t num_vfs
[3] = {0, 0, 0};
81 static int num_vfs_argc
= 3;
82 module_param_array(num_vfs
, byte
, &num_vfs_argc
, 0444);
83 MODULE_PARM_DESC(num_vfs
, "enable #num_vfs functions if num_vfs > 0\n"
84 "num_vfs=port1,port2,port1+2");
86 static uint8_t probe_vf
[3] = {0, 0, 0};
87 static int probe_vfs_argc
= 3;
88 module_param_array(probe_vf
, byte
, &probe_vfs_argc
, 0444);
89 MODULE_PARM_DESC(probe_vf
, "number of vfs to probe by pf driver (num_vfs > 0)\n"
90 "probe_vf=port1,port2,port1+2");
92 int mlx4_log_num_mgm_entry_size
= MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE
;
93 module_param_named(log_num_mgm_entry_size
,
94 mlx4_log_num_mgm_entry_size
, int, 0444);
95 MODULE_PARM_DESC(log_num_mgm_entry_size
, "log mgm size, that defines the num"
96 " of qp per mcg, for example:"
97 " 10 gives 248.range: 7 <="
98 " log_num_mgm_entry_size <= 12."
99 " To activate device managed"
100 " flow steering when available, set to -1");
102 static bool enable_64b_cqe_eqe
= true;
103 module_param(enable_64b_cqe_eqe
, bool, 0444);
104 MODULE_PARM_DESC(enable_64b_cqe_eqe
,
105 "Enable 64 byte CQEs/EQEs when the FW supports this (default: True)");
107 #define HCA_GLOBAL_CAP_MASK 0
109 #define PF_CONTEXT_BEHAVIOUR_MASK MLX4_FUNC_CAP_64B_EQE_CQE
111 static char mlx4_version
[] =
112 DRV_NAME
": Mellanox ConnectX core driver v"
113 DRV_VERSION
" (" DRV_RELDATE
")\n";
115 static struct mlx4_profile default_profile
= {
118 .rdmarc_per_qp
= 1 << 4,
122 .num_mtt
= 1 << 20, /* It is really num mtt segements */
125 static int log_num_mac
= 7;
126 module_param_named(log_num_mac
, log_num_mac
, int, 0444);
127 MODULE_PARM_DESC(log_num_mac
, "Log2 max number of MACs per ETH port (1-7)");
129 static int log_num_vlan
;
130 module_param_named(log_num_vlan
, log_num_vlan
, int, 0444);
131 MODULE_PARM_DESC(log_num_vlan
, "Log2 max number of VLANs per ETH port (0-7)");
132 /* Log2 max number of VLANs per ETH port (0-7) */
133 #define MLX4_LOG_NUM_VLANS 7
135 static bool use_prio
;
136 module_param_named(use_prio
, use_prio
, bool, 0444);
137 MODULE_PARM_DESC(use_prio
, "Enable steering by VLAN priority on ETH ports "
140 int log_mtts_per_seg
= ilog2(MLX4_MTT_ENTRY_PER_SEG
);
141 module_param_named(log_mtts_per_seg
, log_mtts_per_seg
, int, 0444);
142 MODULE_PARM_DESC(log_mtts_per_seg
, "Log2 number of MTT entries per segment (1-7)");
144 static int port_type_array
[2] = {MLX4_PORT_TYPE_NONE
, MLX4_PORT_TYPE_NONE
};
145 static int arr_argc
= 2;
146 module_param_array(port_type_array
, int, &arr_argc
, 0444);
147 MODULE_PARM_DESC(port_type_array
, "Array of port types: HW_DEFAULT (0) is default "
148 "1 for IB, 2 for Ethernet");
150 struct mlx4_port_config
{
151 struct list_head list
;
152 enum mlx4_port_type port_type
[MLX4_MAX_PORTS
+ 1];
153 struct pci_dev
*pdev
;
156 static atomic_t pf_loading
= ATOMIC_INIT(0);
158 int mlx4_check_port_params(struct mlx4_dev
*dev
,
159 enum mlx4_port_type
*port_type
)
163 for (i
= 0; i
< dev
->caps
.num_ports
- 1; i
++) {
164 if (port_type
[i
] != port_type
[i
+ 1]) {
165 if (!(dev
->caps
.flags
& MLX4_DEV_CAP_FLAG_DPDP
)) {
166 mlx4_err(dev
, "Only same port types supported "
167 "on this HCA, aborting.\n");
173 for (i
= 0; i
< dev
->caps
.num_ports
; i
++) {
174 if (!(port_type
[i
] & dev
->caps
.supported_type
[i
+1])) {
175 mlx4_err(dev
, "Requested port type for port %d is not "
176 "supported on this HCA\n", i
+ 1);
183 static void mlx4_set_port_mask(struct mlx4_dev
*dev
)
187 for (i
= 1; i
<= dev
->caps
.num_ports
; ++i
)
188 dev
->caps
.port_mask
[i
] = dev
->caps
.port_type
[i
];
191 static int mlx4_dev_cap(struct mlx4_dev
*dev
, struct mlx4_dev_cap
*dev_cap
)
196 err
= mlx4_QUERY_DEV_CAP(dev
, dev_cap
);
198 mlx4_err(dev
, "QUERY_DEV_CAP command failed, aborting.\n");
202 if (dev_cap
->min_page_sz
> PAGE_SIZE
) {
203 mlx4_err(dev
, "HCA minimum page size of %d bigger than "
204 "kernel PAGE_SIZE of %ld, aborting.\n",
205 dev_cap
->min_page_sz
, PAGE_SIZE
);
208 if (dev_cap
->num_ports
> MLX4_MAX_PORTS
) {
209 mlx4_err(dev
, "HCA has %d ports, but we only support %d, "
211 dev_cap
->num_ports
, MLX4_MAX_PORTS
);
215 if (dev_cap
->uar_size
> pci_resource_len(dev
->pdev
, 2)) {
216 mlx4_err(dev
, "HCA reported UAR size of 0x%x bigger than "
217 "PCI resource 2 size of 0x%llx, aborting.\n",
219 (unsigned long long) pci_resource_len(dev
->pdev
, 2));
223 dev
->caps
.num_ports
= dev_cap
->num_ports
;
224 dev
->phys_caps
.num_phys_eqs
= MLX4_MAX_EQ_NUM
;
225 for (i
= 1; i
<= dev
->caps
.num_ports
; ++i
) {
226 dev
->caps
.vl_cap
[i
] = dev_cap
->max_vl
[i
];
227 dev
->caps
.ib_mtu_cap
[i
] = dev_cap
->ib_mtu
[i
];
228 dev
->phys_caps
.gid_phys_table_len
[i
] = dev_cap
->max_gids
[i
];
229 dev
->phys_caps
.pkey_phys_table_len
[i
] = dev_cap
->max_pkeys
[i
];
230 /* set gid and pkey table operating lengths by default
231 * to non-sriov values */
232 dev
->caps
.gid_table_len
[i
] = dev_cap
->max_gids
[i
];
233 dev
->caps
.pkey_table_len
[i
] = dev_cap
->max_pkeys
[i
];
234 dev
->caps
.port_width_cap
[i
] = dev_cap
->max_port_width
[i
];
235 dev
->caps
.eth_mtu_cap
[i
] = dev_cap
->eth_mtu
[i
];
236 dev
->caps
.def_mac
[i
] = dev_cap
->def_mac
[i
];
237 dev
->caps
.supported_type
[i
] = dev_cap
->supported_port_types
[i
];
238 dev
->caps
.suggested_type
[i
] = dev_cap
->suggested_type
[i
];
239 dev
->caps
.default_sense
[i
] = dev_cap
->default_sense
[i
];
240 dev
->caps
.trans_type
[i
] = dev_cap
->trans_type
[i
];
241 dev
->caps
.vendor_oui
[i
] = dev_cap
->vendor_oui
[i
];
242 dev
->caps
.wavelength
[i
] = dev_cap
->wavelength
[i
];
243 dev
->caps
.trans_code
[i
] = dev_cap
->trans_code
[i
];
246 dev
->caps
.uar_page_size
= PAGE_SIZE
;
247 dev
->caps
.num_uars
= dev_cap
->uar_size
/ PAGE_SIZE
;
248 dev
->caps
.local_ca_ack_delay
= dev_cap
->local_ca_ack_delay
;
249 dev
->caps
.bf_reg_size
= dev_cap
->bf_reg_size
;
250 dev
->caps
.bf_regs_per_page
= dev_cap
->bf_regs_per_page
;
251 dev
->caps
.max_sq_sg
= dev_cap
->max_sq_sg
;
252 dev
->caps
.max_rq_sg
= dev_cap
->max_rq_sg
;
253 dev
->caps
.max_wqes
= dev_cap
->max_qp_sz
;
254 dev
->caps
.max_qp_init_rdma
= dev_cap
->max_requester_per_qp
;
255 dev
->caps
.max_srq_wqes
= dev_cap
->max_srq_sz
;
256 dev
->caps
.max_srq_sge
= dev_cap
->max_rq_sg
- 1;
257 dev
->caps
.reserved_srqs
= dev_cap
->reserved_srqs
;
258 dev
->caps
.max_sq_desc_sz
= dev_cap
->max_sq_desc_sz
;
259 dev
->caps
.max_rq_desc_sz
= dev_cap
->max_rq_desc_sz
;
261 * Subtract 1 from the limit because we need to allocate a
262 * spare CQE so the HCA HW can tell the difference between an
263 * empty CQ and a full CQ.
265 dev
->caps
.max_cqes
= dev_cap
->max_cq_sz
- 1;
266 dev
->caps
.reserved_cqs
= dev_cap
->reserved_cqs
;
267 dev
->caps
.reserved_eqs
= dev_cap
->reserved_eqs
;
268 dev
->caps
.reserved_mtts
= dev_cap
->reserved_mtts
;
269 dev
->caps
.reserved_mrws
= dev_cap
->reserved_mrws
;
271 /* The first 128 UARs are used for EQ doorbells */
272 dev
->caps
.reserved_uars
= max_t(int, 128, dev_cap
->reserved_uars
);
273 dev
->caps
.reserved_pds
= dev_cap
->reserved_pds
;
274 dev
->caps
.reserved_xrcds
= (dev
->caps
.flags
& MLX4_DEV_CAP_FLAG_XRC
) ?
275 dev_cap
->reserved_xrcds
: 0;
276 dev
->caps
.max_xrcds
= (dev
->caps
.flags
& MLX4_DEV_CAP_FLAG_XRC
) ?
277 dev_cap
->max_xrcds
: 0;
278 dev
->caps
.mtt_entry_sz
= dev_cap
->mtt_entry_sz
;
280 dev
->caps
.max_msg_sz
= dev_cap
->max_msg_sz
;
281 dev
->caps
.page_size_cap
= ~(u32
) (dev_cap
->min_page_sz
- 1);
282 dev
->caps
.flags
= dev_cap
->flags
;
283 dev
->caps
.flags2
= dev_cap
->flags2
;
284 dev
->caps
.bmme_flags
= dev_cap
->bmme_flags
;
285 dev
->caps
.reserved_lkey
= dev_cap
->reserved_lkey
;
286 dev
->caps
.stat_rate_support
= dev_cap
->stat_rate_support
;
287 dev
->caps
.max_gso_sz
= dev_cap
->max_gso_sz
;
288 dev
->caps
.max_rss_tbl_sz
= dev_cap
->max_rss_tbl_sz
;
290 /* Sense port always allowed on supported devices for ConnectX-1 and -2 */
291 if (mlx4_priv(dev
)->pci_dev_data
& MLX4_PCI_DEV_FORCE_SENSE_PORT
)
292 dev
->caps
.flags
|= MLX4_DEV_CAP_FLAG_SENSE_SUPPORT
;
293 /* Don't do sense port on multifunction devices (for now at least) */
294 if (mlx4_is_mfunc(dev
))
295 dev
->caps
.flags
&= ~MLX4_DEV_CAP_FLAG_SENSE_SUPPORT
;
297 dev
->caps
.log_num_macs
= log_num_mac
;
298 dev
->caps
.log_num_vlans
= MLX4_LOG_NUM_VLANS
;
299 dev
->caps
.log_num_prios
= use_prio
? 3 : 0;
301 for (i
= 1; i
<= dev
->caps
.num_ports
; ++i
) {
302 dev
->caps
.port_type
[i
] = MLX4_PORT_TYPE_NONE
;
303 if (dev
->caps
.supported_type
[i
]) {
304 /* if only ETH is supported - assign ETH */
305 if (dev
->caps
.supported_type
[i
] == MLX4_PORT_TYPE_ETH
)
306 dev
->caps
.port_type
[i
] = MLX4_PORT_TYPE_ETH
;
307 /* if only IB is supported, assign IB */
308 else if (dev
->caps
.supported_type
[i
] ==
310 dev
->caps
.port_type
[i
] = MLX4_PORT_TYPE_IB
;
312 /* if IB and ETH are supported, we set the port
313 * type according to user selection of port type;
314 * if user selected none, take the FW hint */
315 if (port_type_array
[i
- 1] == MLX4_PORT_TYPE_NONE
)
316 dev
->caps
.port_type
[i
] = dev
->caps
.suggested_type
[i
] ?
317 MLX4_PORT_TYPE_ETH
: MLX4_PORT_TYPE_IB
;
319 dev
->caps
.port_type
[i
] = port_type_array
[i
- 1];
323 * Link sensing is allowed on the port if 3 conditions are true:
324 * 1. Both protocols are supported on the port.
325 * 2. Different types are supported on the port
326 * 3. FW declared that it supports link sensing
328 mlx4_priv(dev
)->sense
.sense_allowed
[i
] =
329 ((dev
->caps
.supported_type
[i
] == MLX4_PORT_TYPE_AUTO
) &&
330 (dev
->caps
.flags
& MLX4_DEV_CAP_FLAG_DPDP
) &&
331 (dev
->caps
.flags
& MLX4_DEV_CAP_FLAG_SENSE_SUPPORT
));
334 * If "default_sense" bit is set, we move the port to "AUTO" mode
335 * and perform sense_port FW command to try and set the correct
336 * port type from beginning
338 if (mlx4_priv(dev
)->sense
.sense_allowed
[i
] && dev
->caps
.default_sense
[i
]) {
339 enum mlx4_port_type sensed_port
= MLX4_PORT_TYPE_NONE
;
340 dev
->caps
.possible_type
[i
] = MLX4_PORT_TYPE_AUTO
;
341 mlx4_SENSE_PORT(dev
, i
, &sensed_port
);
342 if (sensed_port
!= MLX4_PORT_TYPE_NONE
)
343 dev
->caps
.port_type
[i
] = sensed_port
;
345 dev
->caps
.possible_type
[i
] = dev
->caps
.port_type
[i
];
348 if (dev
->caps
.log_num_macs
> dev_cap
->log_max_macs
[i
]) {
349 dev
->caps
.log_num_macs
= dev_cap
->log_max_macs
[i
];
350 mlx4_warn(dev
, "Requested number of MACs is too much "
351 "for port %d, reducing to %d.\n",
352 i
, 1 << dev
->caps
.log_num_macs
);
354 if (dev
->caps
.log_num_vlans
> dev_cap
->log_max_vlans
[i
]) {
355 dev
->caps
.log_num_vlans
= dev_cap
->log_max_vlans
[i
];
356 mlx4_warn(dev
, "Requested number of VLANs is too much "
357 "for port %d, reducing to %d.\n",
358 i
, 1 << dev
->caps
.log_num_vlans
);
362 dev
->caps
.max_counters
= 1 << ilog2(dev_cap
->max_counters
);
364 dev
->caps
.reserved_qps_cnt
[MLX4_QP_REGION_FW
] = dev_cap
->reserved_qps
;
365 dev
->caps
.reserved_qps_cnt
[MLX4_QP_REGION_ETH_ADDR
] =
366 dev
->caps
.reserved_qps_cnt
[MLX4_QP_REGION_FC_ADDR
] =
367 (1 << dev
->caps
.log_num_macs
) *
368 (1 << dev
->caps
.log_num_vlans
) *
369 (1 << dev
->caps
.log_num_prios
) *
371 dev
->caps
.reserved_qps_cnt
[MLX4_QP_REGION_FC_EXCH
] = MLX4_NUM_FEXCH
;
373 dev
->caps
.reserved_qps
= dev
->caps
.reserved_qps_cnt
[MLX4_QP_REGION_FW
] +
374 dev
->caps
.reserved_qps_cnt
[MLX4_QP_REGION_ETH_ADDR
] +
375 dev
->caps
.reserved_qps_cnt
[MLX4_QP_REGION_FC_ADDR
] +
376 dev
->caps
.reserved_qps_cnt
[MLX4_QP_REGION_FC_EXCH
];
378 dev
->caps
.sqp_demux
= (mlx4_is_master(dev
)) ? MLX4_MAX_NUM_SLAVES
: 0;
380 if (!enable_64b_cqe_eqe
&& !mlx4_is_slave(dev
)) {
382 (MLX4_DEV_CAP_FLAG_64B_CQE
| MLX4_DEV_CAP_FLAG_64B_EQE
)) {
383 mlx4_warn(dev
, "64B EQEs/CQEs supported by the device but not enabled\n");
384 dev
->caps
.flags
&= ~MLX4_DEV_CAP_FLAG_64B_CQE
;
385 dev
->caps
.flags
&= ~MLX4_DEV_CAP_FLAG_64B_EQE
;
389 if ((dev
->caps
.flags
&
390 (MLX4_DEV_CAP_FLAG_64B_CQE
| MLX4_DEV_CAP_FLAG_64B_EQE
)) &&
392 dev
->caps
.function_caps
|= MLX4_FUNC_CAP_64B_EQE_CQE
;
397 static int mlx4_get_pcie_dev_link_caps(struct mlx4_dev
*dev
,
398 enum pci_bus_speed
*speed
,
399 enum pcie_link_width
*width
)
401 u32 lnkcap1
, lnkcap2
;
404 #define PCIE_MLW_CAP_SHIFT 4 /* start of MLW mask in link capabilities */
406 *speed
= PCI_SPEED_UNKNOWN
;
407 *width
= PCIE_LNK_WIDTH_UNKNOWN
;
409 err1
= pcie_capability_read_dword(dev
->pdev
, PCI_EXP_LNKCAP
, &lnkcap1
);
410 err2
= pcie_capability_read_dword(dev
->pdev
, PCI_EXP_LNKCAP2
, &lnkcap2
);
411 if (!err2
&& lnkcap2
) { /* PCIe r3.0-compliant */
412 if (lnkcap2
& PCI_EXP_LNKCAP2_SLS_8_0GB
)
413 *speed
= PCIE_SPEED_8_0GT
;
414 else if (lnkcap2
& PCI_EXP_LNKCAP2_SLS_5_0GB
)
415 *speed
= PCIE_SPEED_5_0GT
;
416 else if (lnkcap2
& PCI_EXP_LNKCAP2_SLS_2_5GB
)
417 *speed
= PCIE_SPEED_2_5GT
;
420 *width
= (lnkcap1
& PCI_EXP_LNKCAP_MLW
) >> PCIE_MLW_CAP_SHIFT
;
421 if (!lnkcap2
) { /* pre-r3.0 */
422 if (lnkcap1
& PCI_EXP_LNKCAP_SLS_5_0GB
)
423 *speed
= PCIE_SPEED_5_0GT
;
424 else if (lnkcap1
& PCI_EXP_LNKCAP_SLS_2_5GB
)
425 *speed
= PCIE_SPEED_2_5GT
;
429 if (*speed
== PCI_SPEED_UNKNOWN
|| *width
== PCIE_LNK_WIDTH_UNKNOWN
) {
431 err2
? err2
: -EINVAL
;
436 static void mlx4_check_pcie_caps(struct mlx4_dev
*dev
)
438 enum pcie_link_width width
, width_cap
;
439 enum pci_bus_speed speed
, speed_cap
;
442 #define PCIE_SPEED_STR(speed) \
443 (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" : \
444 speed == PCIE_SPEED_5_0GT ? "5.0GT/s" : \
445 speed == PCIE_SPEED_2_5GT ? "2.5GT/s" : \
448 err
= mlx4_get_pcie_dev_link_caps(dev
, &speed_cap
, &width_cap
);
451 "Unable to determine PCIe device BW capabilities\n");
455 err
= pcie_get_minimum_link(dev
->pdev
, &speed
, &width
);
456 if (err
|| speed
== PCI_SPEED_UNKNOWN
||
457 width
== PCIE_LNK_WIDTH_UNKNOWN
) {
459 "Unable to determine PCI device chain minimum BW\n");
463 if (width
!= width_cap
|| speed
!= speed_cap
)
465 "PCIe BW is different than device's capability\n");
467 mlx4_info(dev
, "PCIe link speed is %s, device supports %s\n",
468 PCIE_SPEED_STR(speed
), PCIE_SPEED_STR(speed_cap
));
469 mlx4_info(dev
, "PCIe link width is x%d, device supports x%d\n",
474 /*The function checks if there are live vf, return the num of them*/
475 static int mlx4_how_many_lives_vf(struct mlx4_dev
*dev
)
477 struct mlx4_priv
*priv
= mlx4_priv(dev
);
478 struct mlx4_slave_state
*s_state
;
482 for (i
= 1/*the ppf is 0*/; i
< dev
->num_slaves
; ++i
) {
483 s_state
= &priv
->mfunc
.master
.slave_state
[i
];
484 if (s_state
->active
&& s_state
->last_cmd
!=
485 MLX4_COMM_CMD_RESET
) {
486 mlx4_warn(dev
, "%s: slave: %d is still active\n",
494 int mlx4_get_parav_qkey(struct mlx4_dev
*dev
, u32 qpn
, u32
*qkey
)
496 u32 qk
= MLX4_RESERVED_QKEY_BASE
;
498 if (qpn
>= dev
->phys_caps
.base_tunnel_sqpn
+ 8 * MLX4_MFUNC_MAX
||
499 qpn
< dev
->phys_caps
.base_proxy_sqpn
)
502 if (qpn
>= dev
->phys_caps
.base_tunnel_sqpn
)
504 qk
+= qpn
- dev
->phys_caps
.base_tunnel_sqpn
;
506 qk
+= qpn
- dev
->phys_caps
.base_proxy_sqpn
;
510 EXPORT_SYMBOL(mlx4_get_parav_qkey
);
512 void mlx4_sync_pkey_table(struct mlx4_dev
*dev
, int slave
, int port
, int i
, int val
)
514 struct mlx4_priv
*priv
= container_of(dev
, struct mlx4_priv
, dev
);
516 if (!mlx4_is_master(dev
))
519 priv
->virt2phys_pkey
[slave
][port
- 1][i
] = val
;
521 EXPORT_SYMBOL(mlx4_sync_pkey_table
);
523 void mlx4_put_slave_node_guid(struct mlx4_dev
*dev
, int slave
, __be64 guid
)
525 struct mlx4_priv
*priv
= container_of(dev
, struct mlx4_priv
, dev
);
527 if (!mlx4_is_master(dev
))
530 priv
->slave_node_guids
[slave
] = guid
;
532 EXPORT_SYMBOL(mlx4_put_slave_node_guid
);
534 __be64
mlx4_get_slave_node_guid(struct mlx4_dev
*dev
, int slave
)
536 struct mlx4_priv
*priv
= container_of(dev
, struct mlx4_priv
, dev
);
538 if (!mlx4_is_master(dev
))
541 return priv
->slave_node_guids
[slave
];
543 EXPORT_SYMBOL(mlx4_get_slave_node_guid
);
545 int mlx4_is_slave_active(struct mlx4_dev
*dev
, int slave
)
547 struct mlx4_priv
*priv
= mlx4_priv(dev
);
548 struct mlx4_slave_state
*s_slave
;
550 if (!mlx4_is_master(dev
))
553 s_slave
= &priv
->mfunc
.master
.slave_state
[slave
];
554 return !!s_slave
->active
;
556 EXPORT_SYMBOL(mlx4_is_slave_active
);
558 static void slave_adjust_steering_mode(struct mlx4_dev
*dev
,
559 struct mlx4_dev_cap
*dev_cap
,
560 struct mlx4_init_hca_param
*hca_param
)
562 dev
->caps
.steering_mode
= hca_param
->steering_mode
;
563 if (dev
->caps
.steering_mode
== MLX4_STEERING_MODE_DEVICE_MANAGED
) {
564 dev
->caps
.num_qp_per_mgm
= dev_cap
->fs_max_num_qp_per_entry
;
565 dev
->caps
.fs_log_max_ucast_qp_range_size
=
566 dev_cap
->fs_log_max_ucast_qp_range_size
;
568 dev
->caps
.num_qp_per_mgm
=
569 4 * ((1 << hca_param
->log_mc_entry_sz
)/16 - 2);
571 mlx4_dbg(dev
, "Steering mode is: %s\n",
572 mlx4_steering_mode_str(dev
->caps
.steering_mode
));
575 static int mlx4_slave_cap(struct mlx4_dev
*dev
)
579 struct mlx4_dev_cap dev_cap
;
580 struct mlx4_func_cap func_cap
;
581 struct mlx4_init_hca_param hca_param
;
584 memset(&hca_param
, 0, sizeof(hca_param
));
585 err
= mlx4_QUERY_HCA(dev
, &hca_param
);
587 mlx4_err(dev
, "QUERY_HCA command failed, aborting.\n");
591 /*fail if the hca has an unknown capability */
592 if ((hca_param
.global_caps
| HCA_GLOBAL_CAP_MASK
) !=
593 HCA_GLOBAL_CAP_MASK
) {
594 mlx4_err(dev
, "Unknown hca global capabilities\n");
598 mlx4_log_num_mgm_entry_size
= hca_param
.log_mc_entry_sz
;
600 dev
->caps
.hca_core_clock
= hca_param
.hca_core_clock
;
602 memset(&dev_cap
, 0, sizeof(dev_cap
));
603 dev
->caps
.max_qp_dest_rdma
= 1 << hca_param
.log_rd_per_qp
;
604 err
= mlx4_dev_cap(dev
, &dev_cap
);
606 mlx4_err(dev
, "QUERY_DEV_CAP command failed, aborting.\n");
610 err
= mlx4_QUERY_FW(dev
);
612 mlx4_err(dev
, "QUERY_FW command failed: could not get FW version.\n");
614 page_size
= ~dev
->caps
.page_size_cap
+ 1;
615 mlx4_warn(dev
, "HCA minimum page size:%d\n", page_size
);
616 if (page_size
> PAGE_SIZE
) {
617 mlx4_err(dev
, "HCA minimum page size of %d bigger than "
618 "kernel PAGE_SIZE of %ld, aborting.\n",
619 page_size
, PAGE_SIZE
);
623 /* slave gets uar page size from QUERY_HCA fw command */
624 dev
->caps
.uar_page_size
= 1 << (hca_param
.uar_page_sz
+ 12);
626 /* TODO: relax this assumption */
627 if (dev
->caps
.uar_page_size
!= PAGE_SIZE
) {
628 mlx4_err(dev
, "UAR size:%d != kernel PAGE_SIZE of %ld\n",
629 dev
->caps
.uar_page_size
, PAGE_SIZE
);
633 memset(&func_cap
, 0, sizeof(func_cap
));
634 err
= mlx4_QUERY_FUNC_CAP(dev
, 0, &func_cap
);
636 mlx4_err(dev
, "QUERY_FUNC_CAP general command failed, aborting (%d).\n",
641 if ((func_cap
.pf_context_behaviour
| PF_CONTEXT_BEHAVIOUR_MASK
) !=
642 PF_CONTEXT_BEHAVIOUR_MASK
) {
643 mlx4_err(dev
, "Unknown pf context behaviour\n");
647 dev
->caps
.num_ports
= func_cap
.num_ports
;
648 dev
->quotas
.qp
= func_cap
.qp_quota
;
649 dev
->quotas
.srq
= func_cap
.srq_quota
;
650 dev
->quotas
.cq
= func_cap
.cq_quota
;
651 dev
->quotas
.mpt
= func_cap
.mpt_quota
;
652 dev
->quotas
.mtt
= func_cap
.mtt_quota
;
653 dev
->caps
.num_qps
= 1 << hca_param
.log_num_qps
;
654 dev
->caps
.num_srqs
= 1 << hca_param
.log_num_srqs
;
655 dev
->caps
.num_cqs
= 1 << hca_param
.log_num_cqs
;
656 dev
->caps
.num_mpts
= 1 << hca_param
.log_mpt_sz
;
657 dev
->caps
.num_eqs
= func_cap
.max_eq
;
658 dev
->caps
.reserved_eqs
= func_cap
.reserved_eq
;
659 dev
->caps
.num_pds
= MLX4_NUM_PDS
;
660 dev
->caps
.num_mgms
= 0;
661 dev
->caps
.num_amgms
= 0;
663 if (dev
->caps
.num_ports
> MLX4_MAX_PORTS
) {
664 mlx4_err(dev
, "HCA has %d ports, but we only support %d, "
665 "aborting.\n", dev
->caps
.num_ports
, MLX4_MAX_PORTS
);
669 dev
->caps
.qp0_tunnel
= kcalloc(dev
->caps
.num_ports
, sizeof (u32
), GFP_KERNEL
);
670 dev
->caps
.qp0_proxy
= kcalloc(dev
->caps
.num_ports
, sizeof (u32
), GFP_KERNEL
);
671 dev
->caps
.qp1_tunnel
= kcalloc(dev
->caps
.num_ports
, sizeof (u32
), GFP_KERNEL
);
672 dev
->caps
.qp1_proxy
= kcalloc(dev
->caps
.num_ports
, sizeof (u32
), GFP_KERNEL
);
674 if (!dev
->caps
.qp0_tunnel
|| !dev
->caps
.qp0_proxy
||
675 !dev
->caps
.qp1_tunnel
|| !dev
->caps
.qp1_proxy
) {
680 for (i
= 1; i
<= dev
->caps
.num_ports
; ++i
) {
681 err
= mlx4_QUERY_FUNC_CAP(dev
, (u32
) i
, &func_cap
);
683 mlx4_err(dev
, "QUERY_FUNC_CAP port command failed for"
684 " port %d, aborting (%d).\n", i
, err
);
687 dev
->caps
.qp0_tunnel
[i
- 1] = func_cap
.qp0_tunnel_qpn
;
688 dev
->caps
.qp0_proxy
[i
- 1] = func_cap
.qp0_proxy_qpn
;
689 dev
->caps
.qp1_tunnel
[i
- 1] = func_cap
.qp1_tunnel_qpn
;
690 dev
->caps
.qp1_proxy
[i
- 1] = func_cap
.qp1_proxy_qpn
;
691 dev
->caps
.port_mask
[i
] = dev
->caps
.port_type
[i
];
692 dev
->caps
.phys_port_id
[i
] = func_cap
.phys_port_id
;
693 if (mlx4_get_slave_pkey_gid_tbl_len(dev
, i
,
694 &dev
->caps
.gid_table_len
[i
],
695 &dev
->caps
.pkey_table_len
[i
]))
699 if (dev
->caps
.uar_page_size
* (dev
->caps
.num_uars
-
700 dev
->caps
.reserved_uars
) >
701 pci_resource_len(dev
->pdev
, 2)) {
702 mlx4_err(dev
, "HCA reported UAR region size of 0x%x bigger than "
703 "PCI resource 2 size of 0x%llx, aborting.\n",
704 dev
->caps
.uar_page_size
* dev
->caps
.num_uars
,
705 (unsigned long long) pci_resource_len(dev
->pdev
, 2));
709 if (hca_param
.dev_cap_enabled
& MLX4_DEV_CAP_64B_EQE_ENABLED
) {
710 dev
->caps
.eqe_size
= 64;
711 dev
->caps
.eqe_factor
= 1;
713 dev
->caps
.eqe_size
= 32;
714 dev
->caps
.eqe_factor
= 0;
717 if (hca_param
.dev_cap_enabled
& MLX4_DEV_CAP_64B_CQE_ENABLED
) {
718 dev
->caps
.cqe_size
= 64;
719 dev
->caps
.userspace_caps
|= MLX4_USER_DEV_CAP_64B_CQE
;
721 dev
->caps
.cqe_size
= 32;
724 dev
->caps
.flags2
&= ~MLX4_DEV_CAP_FLAG2_TS
;
725 mlx4_warn(dev
, "Timestamping is not supported in slave mode.\n");
727 slave_adjust_steering_mode(dev
, &dev_cap
, &hca_param
);
732 kfree(dev
->caps
.qp0_tunnel
);
733 kfree(dev
->caps
.qp0_proxy
);
734 kfree(dev
->caps
.qp1_tunnel
);
735 kfree(dev
->caps
.qp1_proxy
);
736 dev
->caps
.qp0_tunnel
= dev
->caps
.qp0_proxy
=
737 dev
->caps
.qp1_tunnel
= dev
->caps
.qp1_proxy
= NULL
;
742 static void mlx4_request_modules(struct mlx4_dev
*dev
)
745 int has_ib_port
= false;
746 int has_eth_port
= false;
747 #define EN_DRV_NAME "mlx4_en"
748 #define IB_DRV_NAME "mlx4_ib"
750 for (port
= 1; port
<= dev
->caps
.num_ports
; port
++) {
751 if (dev
->caps
.port_type
[port
] == MLX4_PORT_TYPE_IB
)
753 else if (dev
->caps
.port_type
[port
] == MLX4_PORT_TYPE_ETH
)
757 if (has_ib_port
|| (dev
->caps
.flags
& MLX4_DEV_CAP_FLAG_IBOE
))
758 request_module_nowait(IB_DRV_NAME
);
760 request_module_nowait(EN_DRV_NAME
);
764 * Change the port configuration of the device.
765 * Every user of this function must hold the port mutex.
767 int mlx4_change_port_types(struct mlx4_dev
*dev
,
768 enum mlx4_port_type
*port_types
)
774 for (port
= 0; port
< dev
->caps
.num_ports
; port
++) {
775 /* Change the port type only if the new type is different
776 * from the current, and not set to Auto */
777 if (port_types
[port
] != dev
->caps
.port_type
[port
+ 1])
781 mlx4_unregister_device(dev
);
782 for (port
= 1; port
<= dev
->caps
.num_ports
; port
++) {
783 mlx4_CLOSE_PORT(dev
, port
);
784 dev
->caps
.port_type
[port
] = port_types
[port
- 1];
785 err
= mlx4_SET_PORT(dev
, port
, -1);
787 mlx4_err(dev
, "Failed to set port %d, "
792 mlx4_set_port_mask(dev
);
793 err
= mlx4_register_device(dev
);
795 mlx4_err(dev
, "Failed to register device\n");
798 mlx4_request_modules(dev
);
805 static ssize_t
show_port_type(struct device
*dev
,
806 struct device_attribute
*attr
,
809 struct mlx4_port_info
*info
= container_of(attr
, struct mlx4_port_info
,
811 struct mlx4_dev
*mdev
= info
->dev
;
815 (mdev
->caps
.port_type
[info
->port
] == MLX4_PORT_TYPE_IB
) ?
817 if (mdev
->caps
.possible_type
[info
->port
] == MLX4_PORT_TYPE_AUTO
)
818 sprintf(buf
, "auto (%s)\n", type
);
820 sprintf(buf
, "%s\n", type
);
825 static ssize_t
set_port_type(struct device
*dev
,
826 struct device_attribute
*attr
,
827 const char *buf
, size_t count
)
829 struct mlx4_port_info
*info
= container_of(attr
, struct mlx4_port_info
,
831 struct mlx4_dev
*mdev
= info
->dev
;
832 struct mlx4_priv
*priv
= mlx4_priv(mdev
);
833 enum mlx4_port_type types
[MLX4_MAX_PORTS
];
834 enum mlx4_port_type new_types
[MLX4_MAX_PORTS
];
838 if (!strcmp(buf
, "ib\n"))
839 info
->tmp_type
= MLX4_PORT_TYPE_IB
;
840 else if (!strcmp(buf
, "eth\n"))
841 info
->tmp_type
= MLX4_PORT_TYPE_ETH
;
842 else if (!strcmp(buf
, "auto\n"))
843 info
->tmp_type
= MLX4_PORT_TYPE_AUTO
;
845 mlx4_err(mdev
, "%s is not supported port type\n", buf
);
849 mlx4_stop_sense(mdev
);
850 mutex_lock(&priv
->port_mutex
);
851 /* Possible type is always the one that was delivered */
852 mdev
->caps
.possible_type
[info
->port
] = info
->tmp_type
;
854 for (i
= 0; i
< mdev
->caps
.num_ports
; i
++) {
855 types
[i
] = priv
->port
[i
+1].tmp_type
? priv
->port
[i
+1].tmp_type
:
856 mdev
->caps
.possible_type
[i
+1];
857 if (types
[i
] == MLX4_PORT_TYPE_AUTO
)
858 types
[i
] = mdev
->caps
.port_type
[i
+1];
861 if (!(mdev
->caps
.flags
& MLX4_DEV_CAP_FLAG_DPDP
) &&
862 !(mdev
->caps
.flags
& MLX4_DEV_CAP_FLAG_SENSE_SUPPORT
)) {
863 for (i
= 1; i
<= mdev
->caps
.num_ports
; i
++) {
864 if (mdev
->caps
.possible_type
[i
] == MLX4_PORT_TYPE_AUTO
) {
865 mdev
->caps
.possible_type
[i
] = mdev
->caps
.port_type
[i
];
871 mlx4_err(mdev
, "Auto sensing is not supported on this HCA. "
872 "Set only 'eth' or 'ib' for both ports "
873 "(should be the same)\n");
877 mlx4_do_sense_ports(mdev
, new_types
, types
);
879 err
= mlx4_check_port_params(mdev
, new_types
);
883 /* We are about to apply the changes after the configuration
884 * was verified, no need to remember the temporary types
886 for (i
= 0; i
< mdev
->caps
.num_ports
; i
++)
887 priv
->port
[i
+ 1].tmp_type
= 0;
889 err
= mlx4_change_port_types(mdev
, new_types
);
892 mlx4_start_sense(mdev
);
893 mutex_unlock(&priv
->port_mutex
);
894 return err
? err
: count
;
905 static inline int int_to_ibta_mtu(int mtu
)
908 case 256: return IB_MTU_256
;
909 case 512: return IB_MTU_512
;
910 case 1024: return IB_MTU_1024
;
911 case 2048: return IB_MTU_2048
;
912 case 4096: return IB_MTU_4096
;
917 static inline int ibta_mtu_to_int(enum ibta_mtu mtu
)
920 case IB_MTU_256
: return 256;
921 case IB_MTU_512
: return 512;
922 case IB_MTU_1024
: return 1024;
923 case IB_MTU_2048
: return 2048;
924 case IB_MTU_4096
: return 4096;
929 static ssize_t
show_port_ib_mtu(struct device
*dev
,
930 struct device_attribute
*attr
,
933 struct mlx4_port_info
*info
= container_of(attr
, struct mlx4_port_info
,
935 struct mlx4_dev
*mdev
= info
->dev
;
937 if (mdev
->caps
.port_type
[info
->port
] == MLX4_PORT_TYPE_ETH
)
938 mlx4_warn(mdev
, "port level mtu is only used for IB ports\n");
941 ibta_mtu_to_int(mdev
->caps
.port_ib_mtu
[info
->port
]));
945 static ssize_t
set_port_ib_mtu(struct device
*dev
,
946 struct device_attribute
*attr
,
947 const char *buf
, size_t count
)
949 struct mlx4_port_info
*info
= container_of(attr
, struct mlx4_port_info
,
951 struct mlx4_dev
*mdev
= info
->dev
;
952 struct mlx4_priv
*priv
= mlx4_priv(mdev
);
953 int err
, port
, mtu
, ibta_mtu
= -1;
955 if (mdev
->caps
.port_type
[info
->port
] == MLX4_PORT_TYPE_ETH
) {
956 mlx4_warn(mdev
, "port level mtu is only used for IB ports\n");
960 err
= kstrtoint(buf
, 0, &mtu
);
962 ibta_mtu
= int_to_ibta_mtu(mtu
);
964 if (err
|| ibta_mtu
< 0) {
965 mlx4_err(mdev
, "%s is invalid IBTA mtu\n", buf
);
969 mdev
->caps
.port_ib_mtu
[info
->port
] = ibta_mtu
;
971 mlx4_stop_sense(mdev
);
972 mutex_lock(&priv
->port_mutex
);
973 mlx4_unregister_device(mdev
);
974 for (port
= 1; port
<= mdev
->caps
.num_ports
; port
++) {
975 mlx4_CLOSE_PORT(mdev
, port
);
976 err
= mlx4_SET_PORT(mdev
, port
, -1);
978 mlx4_err(mdev
, "Failed to set port %d, "
983 err
= mlx4_register_device(mdev
);
985 mutex_unlock(&priv
->port_mutex
);
986 mlx4_start_sense(mdev
);
987 return err
? err
: count
;
990 static int mlx4_load_fw(struct mlx4_dev
*dev
)
992 struct mlx4_priv
*priv
= mlx4_priv(dev
);
995 priv
->fw
.fw_icm
= mlx4_alloc_icm(dev
, priv
->fw
.fw_pages
,
996 GFP_HIGHUSER
| __GFP_NOWARN
, 0);
997 if (!priv
->fw
.fw_icm
) {
998 mlx4_err(dev
, "Couldn't allocate FW area, aborting.\n");
1002 err
= mlx4_MAP_FA(dev
, priv
->fw
.fw_icm
);
1004 mlx4_err(dev
, "MAP_FA command failed, aborting.\n");
1008 err
= mlx4_RUN_FW(dev
);
1010 mlx4_err(dev
, "RUN_FW command failed, aborting.\n");
1020 mlx4_free_icm(dev
, priv
->fw
.fw_icm
, 0);
1024 static int mlx4_init_cmpt_table(struct mlx4_dev
*dev
, u64 cmpt_base
,
1027 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1031 err
= mlx4_init_icm_table(dev
, &priv
->qp_table
.cmpt_table
,
1033 ((u64
) (MLX4_CMPT_TYPE_QP
*
1034 cmpt_entry_sz
) << MLX4_CMPT_SHIFT
),
1035 cmpt_entry_sz
, dev
->caps
.num_qps
,
1036 dev
->caps
.reserved_qps_cnt
[MLX4_QP_REGION_FW
],
1041 err
= mlx4_init_icm_table(dev
, &priv
->srq_table
.cmpt_table
,
1043 ((u64
) (MLX4_CMPT_TYPE_SRQ
*
1044 cmpt_entry_sz
) << MLX4_CMPT_SHIFT
),
1045 cmpt_entry_sz
, dev
->caps
.num_srqs
,
1046 dev
->caps
.reserved_srqs
, 0, 0);
1050 err
= mlx4_init_icm_table(dev
, &priv
->cq_table
.cmpt_table
,
1052 ((u64
) (MLX4_CMPT_TYPE_CQ
*
1053 cmpt_entry_sz
) << MLX4_CMPT_SHIFT
),
1054 cmpt_entry_sz
, dev
->caps
.num_cqs
,
1055 dev
->caps
.reserved_cqs
, 0, 0);
1059 num_eqs
= (mlx4_is_master(dev
)) ? dev
->phys_caps
.num_phys_eqs
:
1061 err
= mlx4_init_icm_table(dev
, &priv
->eq_table
.cmpt_table
,
1063 ((u64
) (MLX4_CMPT_TYPE_EQ
*
1064 cmpt_entry_sz
) << MLX4_CMPT_SHIFT
),
1065 cmpt_entry_sz
, num_eqs
, num_eqs
, 0, 0);
1072 mlx4_cleanup_icm_table(dev
, &priv
->cq_table
.cmpt_table
);
1075 mlx4_cleanup_icm_table(dev
, &priv
->srq_table
.cmpt_table
);
1078 mlx4_cleanup_icm_table(dev
, &priv
->qp_table
.cmpt_table
);
1084 static int mlx4_init_icm(struct mlx4_dev
*dev
, struct mlx4_dev_cap
*dev_cap
,
1085 struct mlx4_init_hca_param
*init_hca
, u64 icm_size
)
1087 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1092 err
= mlx4_SET_ICM_SIZE(dev
, icm_size
, &aux_pages
);
1094 mlx4_err(dev
, "SET_ICM_SIZE command failed, aborting.\n");
1098 mlx4_dbg(dev
, "%lld KB of HCA context requires %lld KB aux memory.\n",
1099 (unsigned long long) icm_size
>> 10,
1100 (unsigned long long) aux_pages
<< 2);
1102 priv
->fw
.aux_icm
= mlx4_alloc_icm(dev
, aux_pages
,
1103 GFP_HIGHUSER
| __GFP_NOWARN
, 0);
1104 if (!priv
->fw
.aux_icm
) {
1105 mlx4_err(dev
, "Couldn't allocate aux memory, aborting.\n");
1109 err
= mlx4_MAP_ICM_AUX(dev
, priv
->fw
.aux_icm
);
1111 mlx4_err(dev
, "MAP_ICM_AUX command failed, aborting.\n");
1115 err
= mlx4_init_cmpt_table(dev
, init_hca
->cmpt_base
, dev_cap
->cmpt_entry_sz
);
1117 mlx4_err(dev
, "Failed to map cMPT context memory, aborting.\n");
1122 num_eqs
= (mlx4_is_master(dev
)) ? dev
->phys_caps
.num_phys_eqs
:
1124 err
= mlx4_init_icm_table(dev
, &priv
->eq_table
.table
,
1125 init_hca
->eqc_base
, dev_cap
->eqc_entry_sz
,
1126 num_eqs
, num_eqs
, 0, 0);
1128 mlx4_err(dev
, "Failed to map EQ context memory, aborting.\n");
1129 goto err_unmap_cmpt
;
1133 * Reserved MTT entries must be aligned up to a cacheline
1134 * boundary, since the FW will write to them, while the driver
1135 * writes to all other MTT entries. (The variable
1136 * dev->caps.mtt_entry_sz below is really the MTT segment
1137 * size, not the raw entry size)
1139 dev
->caps
.reserved_mtts
=
1140 ALIGN(dev
->caps
.reserved_mtts
* dev
->caps
.mtt_entry_sz
,
1141 dma_get_cache_alignment()) / dev
->caps
.mtt_entry_sz
;
1143 err
= mlx4_init_icm_table(dev
, &priv
->mr_table
.mtt_table
,
1145 dev
->caps
.mtt_entry_sz
,
1147 dev
->caps
.reserved_mtts
, 1, 0);
1149 mlx4_err(dev
, "Failed to map MTT context memory, aborting.\n");
1153 err
= mlx4_init_icm_table(dev
, &priv
->mr_table
.dmpt_table
,
1154 init_hca
->dmpt_base
,
1155 dev_cap
->dmpt_entry_sz
,
1157 dev
->caps
.reserved_mrws
, 1, 1);
1159 mlx4_err(dev
, "Failed to map dMPT context memory, aborting.\n");
1163 err
= mlx4_init_icm_table(dev
, &priv
->qp_table
.qp_table
,
1165 dev_cap
->qpc_entry_sz
,
1167 dev
->caps
.reserved_qps_cnt
[MLX4_QP_REGION_FW
],
1170 mlx4_err(dev
, "Failed to map QP context memory, aborting.\n");
1171 goto err_unmap_dmpt
;
1174 err
= mlx4_init_icm_table(dev
, &priv
->qp_table
.auxc_table
,
1175 init_hca
->auxc_base
,
1176 dev_cap
->aux_entry_sz
,
1178 dev
->caps
.reserved_qps_cnt
[MLX4_QP_REGION_FW
],
1181 mlx4_err(dev
, "Failed to map AUXC context memory, aborting.\n");
1185 err
= mlx4_init_icm_table(dev
, &priv
->qp_table
.altc_table
,
1186 init_hca
->altc_base
,
1187 dev_cap
->altc_entry_sz
,
1189 dev
->caps
.reserved_qps_cnt
[MLX4_QP_REGION_FW
],
1192 mlx4_err(dev
, "Failed to map ALTC context memory, aborting.\n");
1193 goto err_unmap_auxc
;
1196 err
= mlx4_init_icm_table(dev
, &priv
->qp_table
.rdmarc_table
,
1197 init_hca
->rdmarc_base
,
1198 dev_cap
->rdmarc_entry_sz
<< priv
->qp_table
.rdmarc_shift
,
1200 dev
->caps
.reserved_qps_cnt
[MLX4_QP_REGION_FW
],
1203 mlx4_err(dev
, "Failed to map RDMARC context memory, aborting\n");
1204 goto err_unmap_altc
;
1207 err
= mlx4_init_icm_table(dev
, &priv
->cq_table
.table
,
1209 dev_cap
->cqc_entry_sz
,
1211 dev
->caps
.reserved_cqs
, 0, 0);
1213 mlx4_err(dev
, "Failed to map CQ context memory, aborting.\n");
1214 goto err_unmap_rdmarc
;
1217 err
= mlx4_init_icm_table(dev
, &priv
->srq_table
.table
,
1218 init_hca
->srqc_base
,
1219 dev_cap
->srq_entry_sz
,
1221 dev
->caps
.reserved_srqs
, 0, 0);
1223 mlx4_err(dev
, "Failed to map SRQ context memory, aborting.\n");
1228 * For flow steering device managed mode it is required to use
1229 * mlx4_init_icm_table. For B0 steering mode it's not strictly
1230 * required, but for simplicity just map the whole multicast
1231 * group table now. The table isn't very big and it's a lot
1232 * easier than trying to track ref counts.
1234 err
= mlx4_init_icm_table(dev
, &priv
->mcg_table
.table
,
1236 mlx4_get_mgm_entry_size(dev
),
1237 dev
->caps
.num_mgms
+ dev
->caps
.num_amgms
,
1238 dev
->caps
.num_mgms
+ dev
->caps
.num_amgms
,
1241 mlx4_err(dev
, "Failed to map MCG context memory, aborting.\n");
1248 mlx4_cleanup_icm_table(dev
, &priv
->srq_table
.table
);
1251 mlx4_cleanup_icm_table(dev
, &priv
->cq_table
.table
);
1254 mlx4_cleanup_icm_table(dev
, &priv
->qp_table
.rdmarc_table
);
1257 mlx4_cleanup_icm_table(dev
, &priv
->qp_table
.altc_table
);
1260 mlx4_cleanup_icm_table(dev
, &priv
->qp_table
.auxc_table
);
1263 mlx4_cleanup_icm_table(dev
, &priv
->qp_table
.qp_table
);
1266 mlx4_cleanup_icm_table(dev
, &priv
->mr_table
.dmpt_table
);
1269 mlx4_cleanup_icm_table(dev
, &priv
->mr_table
.mtt_table
);
1272 mlx4_cleanup_icm_table(dev
, &priv
->eq_table
.table
);
1275 mlx4_cleanup_icm_table(dev
, &priv
->eq_table
.cmpt_table
);
1276 mlx4_cleanup_icm_table(dev
, &priv
->cq_table
.cmpt_table
);
1277 mlx4_cleanup_icm_table(dev
, &priv
->srq_table
.cmpt_table
);
1278 mlx4_cleanup_icm_table(dev
, &priv
->qp_table
.cmpt_table
);
1281 mlx4_UNMAP_ICM_AUX(dev
);
1284 mlx4_free_icm(dev
, priv
->fw
.aux_icm
, 0);
1289 static void mlx4_free_icms(struct mlx4_dev
*dev
)
1291 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1293 mlx4_cleanup_icm_table(dev
, &priv
->mcg_table
.table
);
1294 mlx4_cleanup_icm_table(dev
, &priv
->srq_table
.table
);
1295 mlx4_cleanup_icm_table(dev
, &priv
->cq_table
.table
);
1296 mlx4_cleanup_icm_table(dev
, &priv
->qp_table
.rdmarc_table
);
1297 mlx4_cleanup_icm_table(dev
, &priv
->qp_table
.altc_table
);
1298 mlx4_cleanup_icm_table(dev
, &priv
->qp_table
.auxc_table
);
1299 mlx4_cleanup_icm_table(dev
, &priv
->qp_table
.qp_table
);
1300 mlx4_cleanup_icm_table(dev
, &priv
->mr_table
.dmpt_table
);
1301 mlx4_cleanup_icm_table(dev
, &priv
->mr_table
.mtt_table
);
1302 mlx4_cleanup_icm_table(dev
, &priv
->eq_table
.table
);
1303 mlx4_cleanup_icm_table(dev
, &priv
->eq_table
.cmpt_table
);
1304 mlx4_cleanup_icm_table(dev
, &priv
->cq_table
.cmpt_table
);
1305 mlx4_cleanup_icm_table(dev
, &priv
->srq_table
.cmpt_table
);
1306 mlx4_cleanup_icm_table(dev
, &priv
->qp_table
.cmpt_table
);
1308 mlx4_UNMAP_ICM_AUX(dev
);
1309 mlx4_free_icm(dev
, priv
->fw
.aux_icm
, 0);
1312 static void mlx4_slave_exit(struct mlx4_dev
*dev
)
1314 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1316 mutex_lock(&priv
->cmd
.slave_cmd_mutex
);
1317 if (mlx4_comm_cmd(dev
, MLX4_COMM_CMD_RESET
, 0, MLX4_COMM_TIME
))
1318 mlx4_warn(dev
, "Failed to close slave function.\n");
1319 mutex_unlock(&priv
->cmd
.slave_cmd_mutex
);
1322 static int map_bf_area(struct mlx4_dev
*dev
)
1324 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1325 resource_size_t bf_start
;
1326 resource_size_t bf_len
;
1329 if (!dev
->caps
.bf_reg_size
)
1332 bf_start
= pci_resource_start(dev
->pdev
, 2) +
1333 (dev
->caps
.num_uars
<< PAGE_SHIFT
);
1334 bf_len
= pci_resource_len(dev
->pdev
, 2) -
1335 (dev
->caps
.num_uars
<< PAGE_SHIFT
);
1336 priv
->bf_mapping
= io_mapping_create_wc(bf_start
, bf_len
);
1337 if (!priv
->bf_mapping
)
1343 static void unmap_bf_area(struct mlx4_dev
*dev
)
1345 if (mlx4_priv(dev
)->bf_mapping
)
1346 io_mapping_free(mlx4_priv(dev
)->bf_mapping
);
1349 cycle_t
mlx4_read_clock(struct mlx4_dev
*dev
)
1351 u32 clockhi
, clocklo
, clockhi1
;
1354 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1356 for (i
= 0; i
< 10; i
++) {
1357 clockhi
= swab32(readl(priv
->clock_mapping
));
1358 clocklo
= swab32(readl(priv
->clock_mapping
+ 4));
1359 clockhi1
= swab32(readl(priv
->clock_mapping
));
1360 if (clockhi
== clockhi1
)
1364 cycles
= (u64
) clockhi
<< 32 | (u64
) clocklo
;
1368 EXPORT_SYMBOL_GPL(mlx4_read_clock
);
1371 static int map_internal_clock(struct mlx4_dev
*dev
)
1373 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1375 priv
->clock_mapping
=
1376 ioremap(pci_resource_start(dev
->pdev
, priv
->fw
.clock_bar
) +
1377 priv
->fw
.clock_offset
, MLX4_CLOCK_SIZE
);
1379 if (!priv
->clock_mapping
)
1385 static void unmap_internal_clock(struct mlx4_dev
*dev
)
1387 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1389 if (priv
->clock_mapping
)
1390 iounmap(priv
->clock_mapping
);
1393 static void mlx4_close_hca(struct mlx4_dev
*dev
)
1395 unmap_internal_clock(dev
);
1397 if (mlx4_is_slave(dev
))
1398 mlx4_slave_exit(dev
);
1400 mlx4_CLOSE_HCA(dev
, 0);
1401 mlx4_free_icms(dev
);
1403 mlx4_free_icm(dev
, mlx4_priv(dev
)->fw
.fw_icm
, 0);
1407 static int mlx4_init_slave(struct mlx4_dev
*dev
)
1409 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1410 u64 dma
= (u64
) priv
->mfunc
.vhcr_dma
;
1411 int ret_from_reset
= 0;
1413 u32 cmd_channel_ver
;
1415 if (atomic_read(&pf_loading
)) {
1416 mlx4_warn(dev
, "PF is not ready. Deferring probe\n");
1417 return -EPROBE_DEFER
;
1420 mutex_lock(&priv
->cmd
.slave_cmd_mutex
);
1421 priv
->cmd
.max_cmds
= 1;
1422 mlx4_warn(dev
, "Sending reset\n");
1423 ret_from_reset
= mlx4_comm_cmd(dev
, MLX4_COMM_CMD_RESET
, 0,
1425 /* if we are in the middle of flr the slave will try
1426 * NUM_OF_RESET_RETRIES times before leaving.*/
1427 if (ret_from_reset
) {
1428 if (MLX4_DELAY_RESET_SLAVE
== ret_from_reset
) {
1429 mlx4_warn(dev
, "slave is currently in the "
1430 "middle of FLR. Deferring probe.\n");
1431 mutex_unlock(&priv
->cmd
.slave_cmd_mutex
);
1432 return -EPROBE_DEFER
;
1437 /* check the driver version - the slave I/F revision
1438 * must match the master's */
1439 slave_read
= swab32(readl(&priv
->mfunc
.comm
->slave_read
));
1440 cmd_channel_ver
= mlx4_comm_get_version();
1442 if (MLX4_COMM_GET_IF_REV(cmd_channel_ver
) !=
1443 MLX4_COMM_GET_IF_REV(slave_read
)) {
1444 mlx4_err(dev
, "slave driver version is not supported"
1445 " by the master\n");
1449 mlx4_warn(dev
, "Sending vhcr0\n");
1450 if (mlx4_comm_cmd(dev
, MLX4_COMM_CMD_VHCR0
, dma
>> 48,
1453 if (mlx4_comm_cmd(dev
, MLX4_COMM_CMD_VHCR1
, dma
>> 32,
1456 if (mlx4_comm_cmd(dev
, MLX4_COMM_CMD_VHCR2
, dma
>> 16,
1459 if (mlx4_comm_cmd(dev
, MLX4_COMM_CMD_VHCR_EN
, dma
, MLX4_COMM_TIME
))
1462 mutex_unlock(&priv
->cmd
.slave_cmd_mutex
);
1466 mlx4_comm_cmd(dev
, MLX4_COMM_CMD_RESET
, 0, 0);
1467 mutex_unlock(&priv
->cmd
.slave_cmd_mutex
);
1471 static void mlx4_parav_master_pf_caps(struct mlx4_dev
*dev
)
1475 for (i
= 1; i
<= dev
->caps
.num_ports
; i
++) {
1476 if (dev
->caps
.port_type
[i
] == MLX4_PORT_TYPE_ETH
)
1477 dev
->caps
.gid_table_len
[i
] =
1478 mlx4_get_slave_num_gids(dev
, 0, i
);
1480 dev
->caps
.gid_table_len
[i
] = 1;
1481 dev
->caps
.pkey_table_len
[i
] =
1482 dev
->phys_caps
.pkey_phys_table_len
[i
] - 1;
1486 static int choose_log_fs_mgm_entry_size(int qp_per_entry
)
1488 int i
= MLX4_MIN_MGM_LOG_ENTRY_SIZE
;
1490 for (i
= MLX4_MIN_MGM_LOG_ENTRY_SIZE
; i
<= MLX4_MAX_MGM_LOG_ENTRY_SIZE
;
1492 if (qp_per_entry
<= 4 * ((1 << i
) / 16 - 2))
1496 return (i
<= MLX4_MAX_MGM_LOG_ENTRY_SIZE
) ? i
: -1;
1499 static void choose_steering_mode(struct mlx4_dev
*dev
,
1500 struct mlx4_dev_cap
*dev_cap
)
1502 if (mlx4_log_num_mgm_entry_size
== -1 &&
1503 dev_cap
->flags2
& MLX4_DEV_CAP_FLAG2_FS_EN
&&
1504 (!mlx4_is_mfunc(dev
) ||
1505 (dev_cap
->fs_max_num_qp_per_entry
>= (dev
->num_vfs
+ 1))) &&
1506 choose_log_fs_mgm_entry_size(dev_cap
->fs_max_num_qp_per_entry
) >=
1507 MLX4_MIN_MGM_LOG_ENTRY_SIZE
) {
1508 dev
->oper_log_mgm_entry_size
=
1509 choose_log_fs_mgm_entry_size(dev_cap
->fs_max_num_qp_per_entry
);
1510 dev
->caps
.steering_mode
= MLX4_STEERING_MODE_DEVICE_MANAGED
;
1511 dev
->caps
.num_qp_per_mgm
= dev_cap
->fs_max_num_qp_per_entry
;
1512 dev
->caps
.fs_log_max_ucast_qp_range_size
=
1513 dev_cap
->fs_log_max_ucast_qp_range_size
;
1515 if (dev
->caps
.flags
& MLX4_DEV_CAP_FLAG_VEP_UC_STEER
&&
1516 dev
->caps
.flags
& MLX4_DEV_CAP_FLAG_VEP_MC_STEER
)
1517 dev
->caps
.steering_mode
= MLX4_STEERING_MODE_B0
;
1519 dev
->caps
.steering_mode
= MLX4_STEERING_MODE_A0
;
1521 if (dev
->caps
.flags
& MLX4_DEV_CAP_FLAG_VEP_UC_STEER
||
1522 dev
->caps
.flags
& MLX4_DEV_CAP_FLAG_VEP_MC_STEER
)
1523 mlx4_warn(dev
, "Must have both UC_STEER and MC_STEER flags "
1524 "set to use B0 steering. Falling back to A0 steering mode.\n");
1526 dev
->oper_log_mgm_entry_size
=
1527 mlx4_log_num_mgm_entry_size
> 0 ?
1528 mlx4_log_num_mgm_entry_size
:
1529 MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE
;
1530 dev
->caps
.num_qp_per_mgm
= mlx4_get_qp_per_mgm(dev
);
1532 mlx4_dbg(dev
, "Steering mode is: %s, oper_log_mgm_entry_size = %d, "
1533 "modparam log_num_mgm_entry_size = %d\n",
1534 mlx4_steering_mode_str(dev
->caps
.steering_mode
),
1535 dev
->oper_log_mgm_entry_size
,
1536 mlx4_log_num_mgm_entry_size
);
1539 static void choose_tunnel_offload_mode(struct mlx4_dev
*dev
,
1540 struct mlx4_dev_cap
*dev_cap
)
1542 if (dev
->caps
.steering_mode
== MLX4_STEERING_MODE_DEVICE_MANAGED
&&
1543 dev_cap
->flags2
& MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS
)
1544 dev
->caps
.tunnel_offload_mode
= MLX4_TUNNEL_OFFLOAD_MODE_VXLAN
;
1546 dev
->caps
.tunnel_offload_mode
= MLX4_TUNNEL_OFFLOAD_MODE_NONE
;
1548 mlx4_dbg(dev
, "Tunneling offload mode is: %s\n", (dev
->caps
.tunnel_offload_mode
1549 == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN
) ? "vxlan" : "none");
1552 static int mlx4_init_hca(struct mlx4_dev
*dev
)
1554 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1555 struct mlx4_adapter adapter
;
1556 struct mlx4_dev_cap dev_cap
;
1557 struct mlx4_mod_stat_cfg mlx4_cfg
;
1558 struct mlx4_profile profile
;
1559 struct mlx4_init_hca_param init_hca
;
1563 if (!mlx4_is_slave(dev
)) {
1564 err
= mlx4_QUERY_FW(dev
);
1567 mlx4_info(dev
, "non-primary physical function, skipping.\n");
1569 mlx4_err(dev
, "QUERY_FW command failed, aborting.\n");
1573 err
= mlx4_load_fw(dev
);
1575 mlx4_err(dev
, "Failed to start FW, aborting.\n");
1579 mlx4_cfg
.log_pg_sz_m
= 1;
1580 mlx4_cfg
.log_pg_sz
= 0;
1581 err
= mlx4_MOD_STAT_CFG(dev
, &mlx4_cfg
);
1583 mlx4_warn(dev
, "Failed to override log_pg_sz parameter\n");
1585 err
= mlx4_dev_cap(dev
, &dev_cap
);
1587 mlx4_err(dev
, "QUERY_DEV_CAP command failed, aborting.\n");
1591 choose_steering_mode(dev
, &dev_cap
);
1592 choose_tunnel_offload_mode(dev
, &dev_cap
);
1594 err
= mlx4_get_phys_port_id(dev
);
1596 mlx4_err(dev
, "Fail to get physical port id\n");
1598 if (mlx4_is_master(dev
))
1599 mlx4_parav_master_pf_caps(dev
);
1601 profile
= default_profile
;
1602 if (dev
->caps
.steering_mode
==
1603 MLX4_STEERING_MODE_DEVICE_MANAGED
)
1604 profile
.num_mcg
= MLX4_FS_NUM_MCG
;
1606 icm_size
= mlx4_make_profile(dev
, &profile
, &dev_cap
,
1608 if ((long long) icm_size
< 0) {
1613 dev
->caps
.max_fmr_maps
= (1 << (32 - ilog2(dev
->caps
.num_mpts
))) - 1;
1615 init_hca
.log_uar_sz
= ilog2(dev
->caps
.num_uars
);
1616 init_hca
.uar_page_sz
= PAGE_SHIFT
- 12;
1617 init_hca
.mw_enabled
= 0;
1618 if (dev
->caps
.flags
& MLX4_DEV_CAP_FLAG_MEM_WINDOW
||
1619 dev
->caps
.bmme_flags
& MLX4_BMME_FLAG_TYPE_2_WIN
)
1620 init_hca
.mw_enabled
= INIT_HCA_TPT_MW_ENABLE
;
1622 err
= mlx4_init_icm(dev
, &dev_cap
, &init_hca
, icm_size
);
1626 err
= mlx4_INIT_HCA(dev
, &init_hca
);
1628 mlx4_err(dev
, "INIT_HCA command failed, aborting.\n");
1632 * If TS is supported by FW
1633 * read HCA frequency by QUERY_HCA command
1635 if (dev
->caps
.flags2
& MLX4_DEV_CAP_FLAG2_TS
) {
1636 memset(&init_hca
, 0, sizeof(init_hca
));
1637 err
= mlx4_QUERY_HCA(dev
, &init_hca
);
1639 mlx4_err(dev
, "QUERY_HCA command failed, disable timestamp.\n");
1640 dev
->caps
.flags2
&= ~MLX4_DEV_CAP_FLAG2_TS
;
1642 dev
->caps
.hca_core_clock
=
1643 init_hca
.hca_core_clock
;
1646 /* In case we got HCA frequency 0 - disable timestamping
1647 * to avoid dividing by zero
1649 if (!dev
->caps
.hca_core_clock
) {
1650 dev
->caps
.flags2
&= ~MLX4_DEV_CAP_FLAG2_TS
;
1652 "HCA frequency is 0. Timestamping is not supported.");
1653 } else if (map_internal_clock(dev
)) {
1655 * Map internal clock,
1656 * in case of failure disable timestamping
1658 dev
->caps
.flags2
&= ~MLX4_DEV_CAP_FLAG2_TS
;
1659 mlx4_err(dev
, "Failed to map internal clock. Timestamping is not supported.\n");
1663 err
= mlx4_init_slave(dev
);
1665 if (err
!= -EPROBE_DEFER
)
1666 mlx4_err(dev
, "Failed to initialize slave\n");
1670 err
= mlx4_slave_cap(dev
);
1672 mlx4_err(dev
, "Failed to obtain slave caps\n");
1677 if (map_bf_area(dev
))
1678 mlx4_dbg(dev
, "Failed to map blue flame area\n");
1680 /*Only the master set the ports, all the rest got it from it.*/
1681 if (!mlx4_is_slave(dev
))
1682 mlx4_set_port_mask(dev
);
1684 err
= mlx4_QUERY_ADAPTER(dev
, &adapter
);
1686 mlx4_err(dev
, "QUERY_ADAPTER command failed, aborting.\n");
1690 priv
->eq_table
.inta_pin
= adapter
.inta_pin
;
1691 memcpy(dev
->board_id
, adapter
.board_id
, sizeof dev
->board_id
);
1696 unmap_internal_clock(dev
);
1700 if (mlx4_is_slave(dev
))
1701 mlx4_slave_exit(dev
);
1703 mlx4_CLOSE_HCA(dev
, 0);
1706 if (!mlx4_is_slave(dev
))
1707 mlx4_free_icms(dev
);
1710 if (!mlx4_is_slave(dev
)) {
1712 mlx4_free_icm(dev
, priv
->fw
.fw_icm
, 0);
1717 static int mlx4_init_counters_table(struct mlx4_dev
*dev
)
1719 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1722 if (!(dev
->caps
.flags
& MLX4_DEV_CAP_FLAG_COUNTERS
))
1725 nent
= dev
->caps
.max_counters
;
1726 return mlx4_bitmap_init(&priv
->counters_bitmap
, nent
, nent
- 1, 0, 0);
1729 static void mlx4_cleanup_counters_table(struct mlx4_dev
*dev
)
1731 mlx4_bitmap_cleanup(&mlx4_priv(dev
)->counters_bitmap
);
1734 int __mlx4_counter_alloc(struct mlx4_dev
*dev
, u32
*idx
)
1736 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1738 if (!(dev
->caps
.flags
& MLX4_DEV_CAP_FLAG_COUNTERS
))
1741 *idx
= mlx4_bitmap_alloc(&priv
->counters_bitmap
);
1748 int mlx4_counter_alloc(struct mlx4_dev
*dev
, u32
*idx
)
1753 if (mlx4_is_mfunc(dev
)) {
1754 err
= mlx4_cmd_imm(dev
, 0, &out_param
, RES_COUNTER
,
1755 RES_OP_RESERVE
, MLX4_CMD_ALLOC_RES
,
1756 MLX4_CMD_TIME_CLASS_A
, MLX4_CMD_WRAPPED
);
1758 *idx
= get_param_l(&out_param
);
1762 return __mlx4_counter_alloc(dev
, idx
);
1764 EXPORT_SYMBOL_GPL(mlx4_counter_alloc
);
1766 void __mlx4_counter_free(struct mlx4_dev
*dev
, u32 idx
)
1768 mlx4_bitmap_free(&mlx4_priv(dev
)->counters_bitmap
, idx
, MLX4_USE_RR
);
1772 void mlx4_counter_free(struct mlx4_dev
*dev
, u32 idx
)
1776 if (mlx4_is_mfunc(dev
)) {
1777 set_param_l(&in_param
, idx
);
1778 mlx4_cmd(dev
, in_param
, RES_COUNTER
, RES_OP_RESERVE
,
1779 MLX4_CMD_FREE_RES
, MLX4_CMD_TIME_CLASS_A
,
1783 __mlx4_counter_free(dev
, idx
);
1785 EXPORT_SYMBOL_GPL(mlx4_counter_free
);
1787 static int mlx4_setup_hca(struct mlx4_dev
*dev
)
1789 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1792 __be32 ib_port_default_caps
;
1794 err
= mlx4_init_uar_table(dev
);
1796 mlx4_err(dev
, "Failed to initialize "
1797 "user access region table, aborting.\n");
1801 err
= mlx4_uar_alloc(dev
, &priv
->driver_uar
);
1803 mlx4_err(dev
, "Failed to allocate driver access region, "
1805 goto err_uar_table_free
;
1808 priv
->kar
= ioremap((phys_addr_t
) priv
->driver_uar
.pfn
<< PAGE_SHIFT
, PAGE_SIZE
);
1810 mlx4_err(dev
, "Couldn't map kernel access region, "
1816 err
= mlx4_init_pd_table(dev
);
1818 mlx4_err(dev
, "Failed to initialize "
1819 "protection domain table, aborting.\n");
1823 err
= mlx4_init_xrcd_table(dev
);
1825 mlx4_err(dev
, "Failed to initialize "
1826 "reliable connection domain table, aborting.\n");
1827 goto err_pd_table_free
;
1830 err
= mlx4_init_mr_table(dev
);
1832 mlx4_err(dev
, "Failed to initialize "
1833 "memory region table, aborting.\n");
1834 goto err_xrcd_table_free
;
1837 if (!mlx4_is_slave(dev
)) {
1838 err
= mlx4_init_mcg_table(dev
);
1840 mlx4_err(dev
, "Failed to initialize multicast group table, aborting.\n");
1841 goto err_mr_table_free
;
1845 err
= mlx4_init_eq_table(dev
);
1847 mlx4_err(dev
, "Failed to initialize "
1848 "event queue table, aborting.\n");
1849 goto err_mcg_table_free
;
1852 err
= mlx4_cmd_use_events(dev
);
1854 mlx4_err(dev
, "Failed to switch to event-driven "
1855 "firmware commands, aborting.\n");
1856 goto err_eq_table_free
;
1859 err
= mlx4_NOP(dev
);
1861 if (dev
->flags
& MLX4_FLAG_MSI_X
) {
1862 mlx4_warn(dev
, "NOP command failed to generate MSI-X "
1863 "interrupt IRQ %d).\n",
1864 priv
->eq_table
.eq
[dev
->caps
.num_comp_vectors
].irq
);
1865 mlx4_warn(dev
, "Trying again without MSI-X.\n");
1867 mlx4_err(dev
, "NOP command failed to generate interrupt "
1868 "(IRQ %d), aborting.\n",
1869 priv
->eq_table
.eq
[dev
->caps
.num_comp_vectors
].irq
);
1870 mlx4_err(dev
, "BIOS or ACPI interrupt routing problem?\n");
1876 mlx4_dbg(dev
, "NOP command IRQ test passed\n");
1878 err
= mlx4_init_cq_table(dev
);
1880 mlx4_err(dev
, "Failed to initialize "
1881 "completion queue table, aborting.\n");
1885 err
= mlx4_init_srq_table(dev
);
1887 mlx4_err(dev
, "Failed to initialize "
1888 "shared receive queue table, aborting.\n");
1889 goto err_cq_table_free
;
1892 err
= mlx4_init_qp_table(dev
);
1894 mlx4_err(dev
, "Failed to initialize "
1895 "queue pair table, aborting.\n");
1896 goto err_srq_table_free
;
1899 err
= mlx4_init_counters_table(dev
);
1900 if (err
&& err
!= -ENOENT
) {
1901 mlx4_err(dev
, "Failed to initialize counters table, aborting.\n");
1902 goto err_qp_table_free
;
1905 if (!mlx4_is_slave(dev
)) {
1906 for (port
= 1; port
<= dev
->caps
.num_ports
; port
++) {
1907 ib_port_default_caps
= 0;
1908 err
= mlx4_get_port_ib_caps(dev
, port
,
1909 &ib_port_default_caps
);
1911 mlx4_warn(dev
, "failed to get port %d default "
1912 "ib capabilities (%d). Continuing "
1913 "with caps = 0\n", port
, err
);
1914 dev
->caps
.ib_port_def_cap
[port
] = ib_port_default_caps
;
1916 /* initialize per-slave default ib port capabilities */
1917 if (mlx4_is_master(dev
)) {
1919 for (i
= 0; i
< dev
->num_slaves
; i
++) {
1920 if (i
== mlx4_master_func_num(dev
))
1922 priv
->mfunc
.master
.slave_state
[i
].ib_cap_mask
[port
] =
1923 ib_port_default_caps
;
1927 if (mlx4_is_mfunc(dev
))
1928 dev
->caps
.port_ib_mtu
[port
] = IB_MTU_2048
;
1930 dev
->caps
.port_ib_mtu
[port
] = IB_MTU_4096
;
1932 err
= mlx4_SET_PORT(dev
, port
, mlx4_is_master(dev
) ?
1933 dev
->caps
.pkey_table_len
[port
] : -1);
1935 mlx4_err(dev
, "Failed to set port %d, aborting\n",
1937 goto err_counters_table_free
;
1944 err_counters_table_free
:
1945 mlx4_cleanup_counters_table(dev
);
1948 mlx4_cleanup_qp_table(dev
);
1951 mlx4_cleanup_srq_table(dev
);
1954 mlx4_cleanup_cq_table(dev
);
1957 mlx4_cmd_use_polling(dev
);
1960 mlx4_cleanup_eq_table(dev
);
1963 if (!mlx4_is_slave(dev
))
1964 mlx4_cleanup_mcg_table(dev
);
1967 mlx4_cleanup_mr_table(dev
);
1969 err_xrcd_table_free
:
1970 mlx4_cleanup_xrcd_table(dev
);
1973 mlx4_cleanup_pd_table(dev
);
1979 mlx4_uar_free(dev
, &priv
->driver_uar
);
1982 mlx4_cleanup_uar_table(dev
);
1986 static void mlx4_enable_msi_x(struct mlx4_dev
*dev
)
1988 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1989 struct msix_entry
*entries
;
1990 int nreq
= min_t(int, dev
->caps
.num_ports
*
1991 min_t(int, num_online_cpus() + 1,
1992 MAX_MSIX_P_PORT
) + MSIX_LEGACY_SZ
, MAX_MSIX
);
1996 nreq
= min_t(int, dev
->caps
.num_eqs
- dev
->caps
.reserved_eqs
,
1999 entries
= kcalloc(nreq
, sizeof *entries
, GFP_KERNEL
);
2003 for (i
= 0; i
< nreq
; ++i
)
2004 entries
[i
].entry
= i
;
2006 nreq
= pci_enable_msix_range(dev
->pdev
, entries
, 2, nreq
);
2011 } else if (nreq
< MSIX_LEGACY_SZ
+
2012 dev
->caps
.num_ports
* MIN_MSIX_P_PORT
) {
2013 /*Working in legacy mode , all EQ's shared*/
2014 dev
->caps
.comp_pool
= 0;
2015 dev
->caps
.num_comp_vectors
= nreq
- 1;
2017 dev
->caps
.comp_pool
= nreq
- MSIX_LEGACY_SZ
;
2018 dev
->caps
.num_comp_vectors
= MSIX_LEGACY_SZ
- 1;
2020 for (i
= 0; i
< nreq
; ++i
)
2021 priv
->eq_table
.eq
[i
].irq
= entries
[i
].vector
;
2023 dev
->flags
|= MLX4_FLAG_MSI_X
;
2030 dev
->caps
.num_comp_vectors
= 1;
2031 dev
->caps
.comp_pool
= 0;
2033 for (i
= 0; i
< 2; ++i
)
2034 priv
->eq_table
.eq
[i
].irq
= dev
->pdev
->irq
;
2037 static int mlx4_init_port_info(struct mlx4_dev
*dev
, int port
)
2039 struct mlx4_port_info
*info
= &mlx4_priv(dev
)->port
[port
];
2044 if (!mlx4_is_slave(dev
)) {
2045 mlx4_init_mac_table(dev
, &info
->mac_table
);
2046 mlx4_init_vlan_table(dev
, &info
->vlan_table
);
2047 info
->base_qpn
= mlx4_get_base_qpn(dev
, port
);
2050 sprintf(info
->dev_name
, "mlx4_port%d", port
);
2051 info
->port_attr
.attr
.name
= info
->dev_name
;
2052 if (mlx4_is_mfunc(dev
))
2053 info
->port_attr
.attr
.mode
= S_IRUGO
;
2055 info
->port_attr
.attr
.mode
= S_IRUGO
| S_IWUSR
;
2056 info
->port_attr
.store
= set_port_type
;
2058 info
->port_attr
.show
= show_port_type
;
2059 sysfs_attr_init(&info
->port_attr
.attr
);
2061 err
= device_create_file(&dev
->pdev
->dev
, &info
->port_attr
);
2063 mlx4_err(dev
, "Failed to create file for port %d\n", port
);
2067 sprintf(info
->dev_mtu_name
, "mlx4_port%d_mtu", port
);
2068 info
->port_mtu_attr
.attr
.name
= info
->dev_mtu_name
;
2069 if (mlx4_is_mfunc(dev
))
2070 info
->port_mtu_attr
.attr
.mode
= S_IRUGO
;
2072 info
->port_mtu_attr
.attr
.mode
= S_IRUGO
| S_IWUSR
;
2073 info
->port_mtu_attr
.store
= set_port_ib_mtu
;
2075 info
->port_mtu_attr
.show
= show_port_ib_mtu
;
2076 sysfs_attr_init(&info
->port_mtu_attr
.attr
);
2078 err
= device_create_file(&dev
->pdev
->dev
, &info
->port_mtu_attr
);
2080 mlx4_err(dev
, "Failed to create mtu file for port %d\n", port
);
2081 device_remove_file(&info
->dev
->pdev
->dev
, &info
->port_attr
);
2088 static void mlx4_cleanup_port_info(struct mlx4_port_info
*info
)
2093 device_remove_file(&info
->dev
->pdev
->dev
, &info
->port_attr
);
2094 device_remove_file(&info
->dev
->pdev
->dev
, &info
->port_mtu_attr
);
2097 static int mlx4_init_steering(struct mlx4_dev
*dev
)
2099 struct mlx4_priv
*priv
= mlx4_priv(dev
);
2100 int num_entries
= dev
->caps
.num_ports
;
2103 priv
->steer
= kzalloc(sizeof(struct mlx4_steer
) * num_entries
, GFP_KERNEL
);
2107 for (i
= 0; i
< num_entries
; i
++)
2108 for (j
= 0; j
< MLX4_NUM_STEERS
; j
++) {
2109 INIT_LIST_HEAD(&priv
->steer
[i
].promisc_qps
[j
]);
2110 INIT_LIST_HEAD(&priv
->steer
[i
].steer_entries
[j
]);
2115 static void mlx4_clear_steering(struct mlx4_dev
*dev
)
2117 struct mlx4_priv
*priv
= mlx4_priv(dev
);
2118 struct mlx4_steer_index
*entry
, *tmp_entry
;
2119 struct mlx4_promisc_qp
*pqp
, *tmp_pqp
;
2120 int num_entries
= dev
->caps
.num_ports
;
2123 for (i
= 0; i
< num_entries
; i
++) {
2124 for (j
= 0; j
< MLX4_NUM_STEERS
; j
++) {
2125 list_for_each_entry_safe(pqp
, tmp_pqp
,
2126 &priv
->steer
[i
].promisc_qps
[j
],
2128 list_del(&pqp
->list
);
2131 list_for_each_entry_safe(entry
, tmp_entry
,
2132 &priv
->steer
[i
].steer_entries
[j
],
2134 list_del(&entry
->list
);
2135 list_for_each_entry_safe(pqp
, tmp_pqp
,
2138 list_del(&pqp
->list
);
2148 static int extended_func_num(struct pci_dev
*pdev
)
2150 return PCI_SLOT(pdev
->devfn
) * 8 + PCI_FUNC(pdev
->devfn
);
2153 #define MLX4_OWNER_BASE 0x8069c
2154 #define MLX4_OWNER_SIZE 4
2156 static int mlx4_get_ownership(struct mlx4_dev
*dev
)
2158 void __iomem
*owner
;
2161 if (pci_channel_offline(dev
->pdev
))
2164 owner
= ioremap(pci_resource_start(dev
->pdev
, 0) + MLX4_OWNER_BASE
,
2167 mlx4_err(dev
, "Failed to obtain ownership bit\n");
2176 static void mlx4_free_ownership(struct mlx4_dev
*dev
)
2178 void __iomem
*owner
;
2180 if (pci_channel_offline(dev
->pdev
))
2183 owner
= ioremap(pci_resource_start(dev
->pdev
, 0) + MLX4_OWNER_BASE
,
2186 mlx4_err(dev
, "Failed to obtain ownership bit\n");
2194 static int __mlx4_init_one(struct pci_dev
*pdev
, int pci_dev_data
)
2196 struct mlx4_priv
*priv
;
2197 struct mlx4_dev
*dev
;
2200 int nvfs
[MLX4_MAX_PORTS
+ 1] = {0, 0, 0};
2201 int prb_vf
[MLX4_MAX_PORTS
+ 1] = {0, 0, 0};
2202 const int param_map
[MLX4_MAX_PORTS
+ 1][MLX4_MAX_PORTS
+ 1] = {
2203 {2, 0, 0}, {0, 1, 2}, {0, 1, 2} };
2204 unsigned total_vfs
= 0;
2205 int sriov_initialized
= 0;
2208 pr_info(DRV_NAME
": Initializing %s\n", pci_name(pdev
));
2210 err
= pci_enable_device(pdev
);
2212 dev_err(&pdev
->dev
, "Cannot enable PCI device, "
2217 /* Due to requirement that all VFs and the PF are *guaranteed* 2 MACS
2218 * per port, we must limit the number of VFs to 63 (since their are
2221 for (i
= 0; i
< sizeof(nvfs
)/sizeof(nvfs
[0]) && i
< num_vfs_argc
;
2222 total_vfs
+= nvfs
[param_map
[num_vfs_argc
- 1][i
]], i
++) {
2223 nvfs
[param_map
[num_vfs_argc
- 1][i
]] = num_vfs
[i
];
2225 dev_err(&pdev
->dev
, "num_vfs module parameter cannot be negative\n");
2229 for (i
= 0; i
< sizeof(prb_vf
)/sizeof(prb_vf
[0]) && i
< probe_vfs_argc
;
2231 prb_vf
[param_map
[probe_vfs_argc
- 1][i
]] = probe_vf
[i
];
2232 if (prb_vf
[i
] < 0 || prb_vf
[i
] > nvfs
[i
]) {
2233 dev_err(&pdev
->dev
, "probe_vf module parameter cannot be negative or greater than num_vfs\n");
2237 if (total_vfs
>= MLX4_MAX_NUM_VF
) {
2239 "Requested more VF's (%d) than allowed (%d)\n",
2240 total_vfs
, MLX4_MAX_NUM_VF
- 1);
2244 for (i
= 0; i
< MLX4_MAX_PORTS
; i
++) {
2245 if (nvfs
[i
] + nvfs
[2] >= MLX4_MAX_NUM_VF_P_PORT
) {
2247 "Requested more VF's (%d) for port (%d) than allowed (%d)\n",
2248 nvfs
[i
] + nvfs
[2], i
+ 1,
2249 MLX4_MAX_NUM_VF_P_PORT
- 1);
2258 if (!(pci_dev_data
& MLX4_PCI_DEV_IS_VF
) &&
2259 !(pci_resource_flags(pdev
, 0) & IORESOURCE_MEM
)) {
2260 dev_err(&pdev
->dev
, "Missing DCS, aborting."
2261 "(driver_data: 0x%x, pci_resource_flags(pdev, 0):0x%lx)\n",
2262 pci_dev_data
, pci_resource_flags(pdev
, 0));
2264 goto err_disable_pdev
;
2266 if (!(pci_resource_flags(pdev
, 2) & IORESOURCE_MEM
)) {
2267 dev_err(&pdev
->dev
, "Missing UAR, aborting.\n");
2269 goto err_disable_pdev
;
2272 err
= pci_request_regions(pdev
, DRV_NAME
);
2274 dev_err(&pdev
->dev
, "Couldn't get PCI resources, aborting\n");
2275 goto err_disable_pdev
;
2278 pci_set_master(pdev
);
2280 err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(64));
2282 dev_warn(&pdev
->dev
, "Warning: couldn't set 64-bit PCI DMA mask.\n");
2283 err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
2285 dev_err(&pdev
->dev
, "Can't set PCI DMA mask, aborting.\n");
2286 goto err_release_regions
;
2289 err
= pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(64));
2291 dev_warn(&pdev
->dev
, "Warning: couldn't set 64-bit "
2292 "consistent PCI DMA mask.\n");
2293 err
= pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(32));
2295 dev_err(&pdev
->dev
, "Can't set consistent PCI DMA mask, "
2297 goto err_release_regions
;
2301 /* Allow large DMA segments, up to the firmware limit of 1 GB */
2302 dma_set_max_seg_size(&pdev
->dev
, 1024 * 1024 * 1024);
2304 priv
= kzalloc(sizeof(*priv
), GFP_KERNEL
);
2307 goto err_release_regions
;
2312 INIT_LIST_HEAD(&priv
->ctx_list
);
2313 spin_lock_init(&priv
->ctx_lock
);
2315 mutex_init(&priv
->port_mutex
);
2317 INIT_LIST_HEAD(&priv
->pgdir_list
);
2318 mutex_init(&priv
->pgdir_mutex
);
2320 INIT_LIST_HEAD(&priv
->bf_list
);
2321 mutex_init(&priv
->bf_mutex
);
2323 dev
->rev_id
= pdev
->revision
;
2324 dev
->numa_node
= dev_to_node(&pdev
->dev
);
2325 /* Detect if this device is a virtual function */
2326 if (pci_dev_data
& MLX4_PCI_DEV_IS_VF
) {
2327 /* When acting as pf, we normally skip vfs unless explicitly
2328 * requested to probe them. */
2330 unsigned vfs_offset
= 0;
2331 for (i
= 0; i
< sizeof(nvfs
)/sizeof(nvfs
[0]) &&
2332 vfs_offset
+ nvfs
[i
] < extended_func_num(pdev
);
2333 vfs_offset
+= nvfs
[i
], i
++)
2335 if (i
== sizeof(nvfs
)/sizeof(nvfs
[0])) {
2339 if ((extended_func_num(pdev
) - vfs_offset
)
2341 mlx4_warn(dev
, "Skipping virtual function:%d\n",
2342 extended_func_num(pdev
));
2347 mlx4_warn(dev
, "Detected virtual function - running in slave mode\n");
2348 dev
->flags
|= MLX4_FLAG_SLAVE
;
2350 /* We reset the device and enable SRIOV only for physical
2351 * devices. Try to claim ownership on the device;
2352 * if already taken, skip -- do not allow multiple PFs */
2353 err
= mlx4_get_ownership(dev
);
2358 mlx4_warn(dev
, "Multiple PFs not yet supported."
2366 mlx4_warn(dev
, "Enabling SR-IOV with %d VFs\n",
2368 dev
->dev_vfs
= kzalloc(
2369 total_vfs
* sizeof(*dev
->dev_vfs
),
2371 if (NULL
== dev
->dev_vfs
) {
2372 mlx4_err(dev
, "Failed to allocate memory for VFs\n");
2375 atomic_inc(&pf_loading
);
2376 err
= pci_enable_sriov(pdev
, total_vfs
);
2377 atomic_dec(&pf_loading
);
2379 mlx4_err(dev
, "Failed to enable SR-IOV, continuing without SR-IOV (err = %d).\n",
2383 mlx4_warn(dev
, "Running in master mode\n");
2384 dev
->flags
|= MLX4_FLAG_SRIOV
|
2386 dev
->num_vfs
= total_vfs
;
2387 sriov_initialized
= 1;
2392 atomic_set(&priv
->opreq_count
, 0);
2393 INIT_WORK(&priv
->opreq_task
, mlx4_opreq_action
);
2396 * Now reset the HCA before we touch the PCI capabilities or
2397 * attempt a firmware command, since a boot ROM may have left
2398 * the HCA in an undefined state.
2400 err
= mlx4_reset(dev
);
2402 mlx4_err(dev
, "Failed to reset HCA, aborting.\n");
2408 err
= mlx4_cmd_init(dev
);
2410 mlx4_err(dev
, "Failed to init command interface, aborting.\n");
2414 /* In slave functions, the communication channel must be initialized
2415 * before posting commands. Also, init num_slaves before calling
2417 if (mlx4_is_mfunc(dev
)) {
2418 if (mlx4_is_master(dev
))
2419 dev
->num_slaves
= MLX4_MAX_NUM_SLAVES
;
2421 dev
->num_slaves
= 0;
2422 err
= mlx4_multi_func_init(dev
);
2424 mlx4_err(dev
, "Failed to init slave mfunc"
2425 " interface, aborting.\n");
2431 err
= mlx4_init_hca(dev
);
2433 if (err
== -EACCES
) {
2434 /* Not primary Physical function
2435 * Running in slave mode */
2436 mlx4_cmd_cleanup(dev
);
2437 dev
->flags
|= MLX4_FLAG_SLAVE
;
2438 dev
->flags
&= ~MLX4_FLAG_MASTER
;
2444 /* check if the device is functioning at its maximum possible speed.
2445 * No return code for this call, just warn the user in case of PCI
2446 * express device capabilities are under-satisfied by the bus.
2448 mlx4_check_pcie_caps(dev
);
2450 /* In master functions, the communication channel must be initialized
2451 * after obtaining its address from fw */
2452 if (mlx4_is_master(dev
)) {
2454 err
= mlx4_multi_func_init(dev
);
2456 mlx4_err(dev
, "Failed to init master mfunc"
2457 "interface, aborting.\n");
2460 if (sriov_initialized
) {
2462 mlx4_foreach_port(i
, dev
, MLX4_PORT_TYPE_IB
)
2466 (num_vfs_argc
> 1 || probe_vfs_argc
> 1)) {
2468 "Invalid syntax of num_vfs/probe_vfs "
2469 "with IB port. Single port VFs syntax"
2470 " is only supported when all ports "
2471 "are configured as ethernet\n");
2474 for (i
= 0; i
< sizeof(nvfs
)/sizeof(nvfs
[0]); i
++) {
2476 for (j
= 0; j
< nvfs
[i
]; ++sum
, ++j
) {
2477 dev
->dev_vfs
[sum
].min_port
=
2479 dev
->dev_vfs
[sum
].n_ports
= i
< 2 ? 1 :
2480 dev
->caps
.num_ports
;
2486 err
= mlx4_alloc_eq_table(dev
);
2488 goto err_master_mfunc
;
2490 priv
->msix_ctl
.pool_bm
= 0;
2491 mutex_init(&priv
->msix_ctl
.pool_lock
);
2493 mlx4_enable_msi_x(dev
);
2494 if ((mlx4_is_mfunc(dev
)) &&
2495 !(dev
->flags
& MLX4_FLAG_MSI_X
)) {
2497 mlx4_err(dev
, "INTx is not supported in multi-function mode."
2502 if (!mlx4_is_slave(dev
)) {
2503 err
= mlx4_init_steering(dev
);
2508 err
= mlx4_setup_hca(dev
);
2509 if (err
== -EBUSY
&& (dev
->flags
& MLX4_FLAG_MSI_X
) &&
2510 !mlx4_is_mfunc(dev
)) {
2511 dev
->flags
&= ~MLX4_FLAG_MSI_X
;
2512 dev
->caps
.num_comp_vectors
= 1;
2513 dev
->caps
.comp_pool
= 0;
2514 pci_disable_msix(pdev
);
2515 err
= mlx4_setup_hca(dev
);
2521 mlx4_init_quotas(dev
);
2523 for (port
= 1; port
<= dev
->caps
.num_ports
; port
++) {
2524 err
= mlx4_init_port_info(dev
, port
);
2529 err
= mlx4_register_device(dev
);
2533 mlx4_request_modules(dev
);
2535 mlx4_sense_init(dev
);
2536 mlx4_start_sense(dev
);
2538 priv
->pci_dev_data
= pci_dev_data
;
2539 pci_set_drvdata(pdev
, dev
);
2544 for (--port
; port
>= 1; --port
)
2545 mlx4_cleanup_port_info(&priv
->port
[port
]);
2547 mlx4_cleanup_counters_table(dev
);
2548 mlx4_cleanup_qp_table(dev
);
2549 mlx4_cleanup_srq_table(dev
);
2550 mlx4_cleanup_cq_table(dev
);
2551 mlx4_cmd_use_polling(dev
);
2552 mlx4_cleanup_eq_table(dev
);
2553 mlx4_cleanup_mcg_table(dev
);
2554 mlx4_cleanup_mr_table(dev
);
2555 mlx4_cleanup_xrcd_table(dev
);
2556 mlx4_cleanup_pd_table(dev
);
2557 mlx4_cleanup_uar_table(dev
);
2560 if (!mlx4_is_slave(dev
))
2561 mlx4_clear_steering(dev
);
2564 mlx4_free_eq_table(dev
);
2567 if (mlx4_is_master(dev
))
2568 mlx4_multi_func_cleanup(dev
);
2571 if (dev
->flags
& MLX4_FLAG_MSI_X
)
2572 pci_disable_msix(pdev
);
2574 mlx4_close_hca(dev
);
2577 if (mlx4_is_slave(dev
))
2578 mlx4_multi_func_cleanup(dev
);
2581 mlx4_cmd_cleanup(dev
);
2584 if (dev
->flags
& MLX4_FLAG_SRIOV
)
2585 pci_disable_sriov(pdev
);
2588 if (!mlx4_is_slave(dev
))
2589 mlx4_free_ownership(dev
);
2591 kfree(priv
->dev
.dev_vfs
);
2596 err_release_regions
:
2597 pci_release_regions(pdev
);
2600 pci_disable_device(pdev
);
2601 pci_set_drvdata(pdev
, NULL
);
2605 static int mlx4_init_one(struct pci_dev
*pdev
, const struct pci_device_id
*id
)
2607 printk_once(KERN_INFO
"%s", mlx4_version
);
2609 return __mlx4_init_one(pdev
, id
->driver_data
);
2612 static void mlx4_remove_one(struct pci_dev
*pdev
)
2614 struct mlx4_dev
*dev
= pci_get_drvdata(pdev
);
2615 struct mlx4_priv
*priv
= mlx4_priv(dev
);
2619 /* in SRIOV it is not allowed to unload the pf's
2620 * driver while there are alive vf's */
2621 if (mlx4_is_master(dev
)) {
2622 if (mlx4_how_many_lives_vf(dev
))
2623 printk(KERN_ERR
"Removing PF when there are assigned VF's !!!\n");
2625 mlx4_stop_sense(dev
);
2626 mlx4_unregister_device(dev
);
2628 for (p
= 1; p
<= dev
->caps
.num_ports
; p
++) {
2629 mlx4_cleanup_port_info(&priv
->port
[p
]);
2630 mlx4_CLOSE_PORT(dev
, p
);
2633 if (mlx4_is_master(dev
))
2634 mlx4_free_resource_tracker(dev
,
2635 RES_TR_FREE_SLAVES_ONLY
);
2637 mlx4_cleanup_counters_table(dev
);
2638 mlx4_cleanup_qp_table(dev
);
2639 mlx4_cleanup_srq_table(dev
);
2640 mlx4_cleanup_cq_table(dev
);
2641 mlx4_cmd_use_polling(dev
);
2642 mlx4_cleanup_eq_table(dev
);
2643 mlx4_cleanup_mcg_table(dev
);
2644 mlx4_cleanup_mr_table(dev
);
2645 mlx4_cleanup_xrcd_table(dev
);
2646 mlx4_cleanup_pd_table(dev
);
2648 if (mlx4_is_master(dev
))
2649 mlx4_free_resource_tracker(dev
,
2650 RES_TR_FREE_STRUCTS_ONLY
);
2653 mlx4_uar_free(dev
, &priv
->driver_uar
);
2654 mlx4_cleanup_uar_table(dev
);
2655 if (!mlx4_is_slave(dev
))
2656 mlx4_clear_steering(dev
);
2657 mlx4_free_eq_table(dev
);
2658 if (mlx4_is_master(dev
))
2659 mlx4_multi_func_cleanup(dev
);
2660 mlx4_close_hca(dev
);
2661 if (mlx4_is_slave(dev
))
2662 mlx4_multi_func_cleanup(dev
);
2663 mlx4_cmd_cleanup(dev
);
2665 if (dev
->flags
& MLX4_FLAG_MSI_X
)
2666 pci_disable_msix(pdev
);
2667 if (dev
->flags
& MLX4_FLAG_SRIOV
) {
2668 mlx4_warn(dev
, "Disabling SR-IOV\n");
2669 pci_disable_sriov(pdev
);
2672 if (!mlx4_is_slave(dev
))
2673 mlx4_free_ownership(dev
);
2675 kfree(dev
->caps
.qp0_tunnel
);
2676 kfree(dev
->caps
.qp0_proxy
);
2677 kfree(dev
->caps
.qp1_tunnel
);
2678 kfree(dev
->caps
.qp1_proxy
);
2679 kfree(dev
->dev_vfs
);
2682 pci_release_regions(pdev
);
2683 pci_disable_device(pdev
);
2684 pci_set_drvdata(pdev
, NULL
);
2688 int mlx4_restart_one(struct pci_dev
*pdev
)
2690 struct mlx4_dev
*dev
= pci_get_drvdata(pdev
);
2691 struct mlx4_priv
*priv
= mlx4_priv(dev
);
2694 pci_dev_data
= priv
->pci_dev_data
;
2695 mlx4_remove_one(pdev
);
2696 return __mlx4_init_one(pdev
, pci_dev_data
);
2699 static DEFINE_PCI_DEVICE_TABLE(mlx4_pci_table
) = {
2700 /* MT25408 "Hermon" SDR */
2701 { PCI_VDEVICE(MELLANOX
, 0x6340), MLX4_PCI_DEV_FORCE_SENSE_PORT
},
2702 /* MT25408 "Hermon" DDR */
2703 { PCI_VDEVICE(MELLANOX
, 0x634a), MLX4_PCI_DEV_FORCE_SENSE_PORT
},
2704 /* MT25408 "Hermon" QDR */
2705 { PCI_VDEVICE(MELLANOX
, 0x6354), MLX4_PCI_DEV_FORCE_SENSE_PORT
},
2706 /* MT25408 "Hermon" DDR PCIe gen2 */
2707 { PCI_VDEVICE(MELLANOX
, 0x6732), MLX4_PCI_DEV_FORCE_SENSE_PORT
},
2708 /* MT25408 "Hermon" QDR PCIe gen2 */
2709 { PCI_VDEVICE(MELLANOX
, 0x673c), MLX4_PCI_DEV_FORCE_SENSE_PORT
},
2710 /* MT25408 "Hermon" EN 10GigE */
2711 { PCI_VDEVICE(MELLANOX
, 0x6368), MLX4_PCI_DEV_FORCE_SENSE_PORT
},
2712 /* MT25408 "Hermon" EN 10GigE PCIe gen2 */
2713 { PCI_VDEVICE(MELLANOX
, 0x6750), MLX4_PCI_DEV_FORCE_SENSE_PORT
},
2714 /* MT25458 ConnectX EN 10GBASE-T 10GigE */
2715 { PCI_VDEVICE(MELLANOX
, 0x6372), MLX4_PCI_DEV_FORCE_SENSE_PORT
},
2716 /* MT25458 ConnectX EN 10GBASE-T+Gen2 10GigE */
2717 { PCI_VDEVICE(MELLANOX
, 0x675a), MLX4_PCI_DEV_FORCE_SENSE_PORT
},
2718 /* MT26468 ConnectX EN 10GigE PCIe gen2*/
2719 { PCI_VDEVICE(MELLANOX
, 0x6764), MLX4_PCI_DEV_FORCE_SENSE_PORT
},
2720 /* MT26438 ConnectX EN 40GigE PCIe gen2 5GT/s */
2721 { PCI_VDEVICE(MELLANOX
, 0x6746), MLX4_PCI_DEV_FORCE_SENSE_PORT
},
2722 /* MT26478 ConnectX2 40GigE PCIe gen2 */
2723 { PCI_VDEVICE(MELLANOX
, 0x676e), MLX4_PCI_DEV_FORCE_SENSE_PORT
},
2724 /* MT25400 Family [ConnectX-2 Virtual Function] */
2725 { PCI_VDEVICE(MELLANOX
, 0x1002), MLX4_PCI_DEV_IS_VF
},
2726 /* MT27500 Family [ConnectX-3] */
2727 { PCI_VDEVICE(MELLANOX
, 0x1003), 0 },
2728 /* MT27500 Family [ConnectX-3 Virtual Function] */
2729 { PCI_VDEVICE(MELLANOX
, 0x1004), MLX4_PCI_DEV_IS_VF
},
2730 { PCI_VDEVICE(MELLANOX
, 0x1005), 0 }, /* MT27510 Family */
2731 { PCI_VDEVICE(MELLANOX
, 0x1006), 0 }, /* MT27511 Family */
2732 { PCI_VDEVICE(MELLANOX
, 0x1007), 0 }, /* MT27520 Family */
2733 { PCI_VDEVICE(MELLANOX
, 0x1008), 0 }, /* MT27521 Family */
2734 { PCI_VDEVICE(MELLANOX
, 0x1009), 0 }, /* MT27530 Family */
2735 { PCI_VDEVICE(MELLANOX
, 0x100a), 0 }, /* MT27531 Family */
2736 { PCI_VDEVICE(MELLANOX
, 0x100b), 0 }, /* MT27540 Family */
2737 { PCI_VDEVICE(MELLANOX
, 0x100c), 0 }, /* MT27541 Family */
2738 { PCI_VDEVICE(MELLANOX
, 0x100d), 0 }, /* MT27550 Family */
2739 { PCI_VDEVICE(MELLANOX
, 0x100e), 0 }, /* MT27551 Family */
2740 { PCI_VDEVICE(MELLANOX
, 0x100f), 0 }, /* MT27560 Family */
2741 { PCI_VDEVICE(MELLANOX
, 0x1010), 0 }, /* MT27561 Family */
2745 MODULE_DEVICE_TABLE(pci
, mlx4_pci_table
);
2747 static pci_ers_result_t
mlx4_pci_err_detected(struct pci_dev
*pdev
,
2748 pci_channel_state_t state
)
2750 mlx4_remove_one(pdev
);
2752 return state
== pci_channel_io_perm_failure
?
2753 PCI_ERS_RESULT_DISCONNECT
: PCI_ERS_RESULT_NEED_RESET
;
2756 static pci_ers_result_t
mlx4_pci_slot_reset(struct pci_dev
*pdev
)
2758 const struct pci_device_id
*id
;
2761 id
= pci_match_id(mlx4_pci_table
, pdev
);
2762 ret
= __mlx4_init_one(pdev
, id
->driver_data
);
2764 return ret
? PCI_ERS_RESULT_DISCONNECT
: PCI_ERS_RESULT_RECOVERED
;
2767 static const struct pci_error_handlers mlx4_err_handler
= {
2768 .error_detected
= mlx4_pci_err_detected
,
2769 .slot_reset
= mlx4_pci_slot_reset
,
2772 static struct pci_driver mlx4_driver
= {
2774 .id_table
= mlx4_pci_table
,
2775 .probe
= mlx4_init_one
,
2776 .shutdown
= mlx4_remove_one
,
2777 .remove
= mlx4_remove_one
,
2778 .err_handler
= &mlx4_err_handler
,
2781 static int __init
mlx4_verify_params(void)
2783 if ((log_num_mac
< 0) || (log_num_mac
> 7)) {
2784 pr_warning("mlx4_core: bad num_mac: %d\n", log_num_mac
);
2788 if (log_num_vlan
!= 0)
2789 pr_warning("mlx4_core: log_num_vlan - obsolete module param, using %d\n",
2790 MLX4_LOG_NUM_VLANS
);
2792 if ((log_mtts_per_seg
< 1) || (log_mtts_per_seg
> 7)) {
2793 pr_warning("mlx4_core: bad log_mtts_per_seg: %d\n", log_mtts_per_seg
);
2797 /* Check if module param for ports type has legal combination */
2798 if (port_type_array
[0] == false && port_type_array
[1] == true) {
2799 printk(KERN_WARNING
"Module parameter configuration ETH/IB is not supported. Switching to default configuration IB/IB\n");
2800 port_type_array
[0] = true;
2803 if (mlx4_log_num_mgm_entry_size
!= -1 &&
2804 (mlx4_log_num_mgm_entry_size
< MLX4_MIN_MGM_LOG_ENTRY_SIZE
||
2805 mlx4_log_num_mgm_entry_size
> MLX4_MAX_MGM_LOG_ENTRY_SIZE
)) {
2806 pr_warning("mlx4_core: mlx4_log_num_mgm_entry_size (%d) not "
2807 "in legal range (-1 or %d..%d)\n",
2808 mlx4_log_num_mgm_entry_size
,
2809 MLX4_MIN_MGM_LOG_ENTRY_SIZE
,
2810 MLX4_MAX_MGM_LOG_ENTRY_SIZE
);
2817 static int __init
mlx4_init(void)
2821 if (mlx4_verify_params())
2826 mlx4_wq
= create_singlethread_workqueue("mlx4");
2830 ret
= pci_register_driver(&mlx4_driver
);
2832 destroy_workqueue(mlx4_wq
);
2833 return ret
< 0 ? ret
: 0;
2836 static void __exit
mlx4_cleanup(void)
2838 pci_unregister_driver(&mlx4_driver
);
2839 destroy_workqueue(mlx4_wq
);
2842 module_init(mlx4_init
);
2843 module_exit(mlx4_cleanup
);