2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
5 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * OpenIB.org BSD license below:
13 * Redistribution and use in source and binary forms, with or
14 * without modification, are permitted provided that the following
17 * - Redistributions of source code must retain the above
18 * copyright notice, this list of conditions and the following
21 * - Redistributions in binary form must reproduce the above
22 * copyright notice, this list of conditions and the following
23 * disclaimer in the documentation and/or other materials
24 * provided with the distribution.
26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/module.h>
37 #include <linux/init.h>
38 #include <linux/errno.h>
39 #include <linux/pci.h>
40 #include <linux/dma-mapping.h>
41 #include <linux/slab.h>
42 #include <linux/io-mapping.h>
43 #include <linux/delay.h>
44 #include <linux/kmod.h>
46 #include <linux/mlx4/device.h>
47 #include <linux/mlx4/doorbell.h>
53 MODULE_AUTHOR("Roland Dreier");
54 MODULE_DESCRIPTION("Mellanox ConnectX HCA low-level driver");
55 MODULE_LICENSE("Dual BSD/GPL");
56 MODULE_VERSION(DRV_VERSION
);
58 struct workqueue_struct
*mlx4_wq
;
60 #ifdef CONFIG_MLX4_DEBUG
62 int mlx4_debug_level
= 0;
63 module_param_named(debug_level
, mlx4_debug_level
, int, 0644);
64 MODULE_PARM_DESC(debug_level
, "Enable debug tracing if > 0");
66 #endif /* CONFIG_MLX4_DEBUG */
71 module_param(msi_x
, int, 0444);
72 MODULE_PARM_DESC(msi_x
, "attempt to use MSI-X if nonzero");
74 #else /* CONFIG_PCI_MSI */
78 #endif /* CONFIG_PCI_MSI */
80 static uint8_t num_vfs
[3] = {0, 0, 0};
81 static int num_vfs_argc
;
82 module_param_array(num_vfs
, byte
, &num_vfs_argc
, 0444);
83 MODULE_PARM_DESC(num_vfs
, "enable #num_vfs functions if num_vfs > 0\n"
84 "num_vfs=port1,port2,port1+2");
86 static uint8_t probe_vf
[3] = {0, 0, 0};
87 static int probe_vfs_argc
;
88 module_param_array(probe_vf
, byte
, &probe_vfs_argc
, 0444);
89 MODULE_PARM_DESC(probe_vf
, "number of vfs to probe by pf driver (num_vfs > 0)\n"
90 "probe_vf=port1,port2,port1+2");
92 int mlx4_log_num_mgm_entry_size
= MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE
;
93 module_param_named(log_num_mgm_entry_size
,
94 mlx4_log_num_mgm_entry_size
, int, 0444);
95 MODULE_PARM_DESC(log_num_mgm_entry_size
, "log mgm size, that defines the num"
96 " of qp per mcg, for example:"
97 " 10 gives 248.range: 7 <="
98 " log_num_mgm_entry_size <= 12."
99 " To activate device managed"
100 " flow steering when available, set to -1");
102 static bool enable_64b_cqe_eqe
= true;
103 module_param(enable_64b_cqe_eqe
, bool, 0444);
104 MODULE_PARM_DESC(enable_64b_cqe_eqe
,
105 "Enable 64 byte CQEs/EQEs when the FW supports this (default: True)");
107 #define PF_CONTEXT_BEHAVIOUR_MASK (MLX4_FUNC_CAP_64B_EQE_CQE | \
108 MLX4_FUNC_CAP_EQE_CQE_STRIDE)
110 static char mlx4_version
[] =
111 DRV_NAME
": Mellanox ConnectX core driver v"
112 DRV_VERSION
" (" DRV_RELDATE
")\n";
114 static struct mlx4_profile default_profile
= {
117 .rdmarc_per_qp
= 1 << 4,
121 .num_mtt
= 1 << 20, /* It is really num mtt segements */
124 static struct mlx4_profile low_mem_profile
= {
127 .rdmarc_per_qp
= 1 << 4,
134 static int log_num_mac
= 7;
135 module_param_named(log_num_mac
, log_num_mac
, int, 0444);
136 MODULE_PARM_DESC(log_num_mac
, "Log2 max number of MACs per ETH port (1-7)");
138 static int log_num_vlan
;
139 module_param_named(log_num_vlan
, log_num_vlan
, int, 0444);
140 MODULE_PARM_DESC(log_num_vlan
, "Log2 max number of VLANs per ETH port (0-7)");
141 /* Log2 max number of VLANs per ETH port (0-7) */
142 #define MLX4_LOG_NUM_VLANS 7
143 #define MLX4_MIN_LOG_NUM_VLANS 0
144 #define MLX4_MIN_LOG_NUM_MAC 1
146 static bool use_prio
;
147 module_param_named(use_prio
, use_prio
, bool, 0444);
148 MODULE_PARM_DESC(use_prio
, "Enable steering by VLAN priority on ETH ports (deprecated)");
150 int log_mtts_per_seg
= ilog2(MLX4_MTT_ENTRY_PER_SEG
);
151 module_param_named(log_mtts_per_seg
, log_mtts_per_seg
, int, 0444);
152 MODULE_PARM_DESC(log_mtts_per_seg
, "Log2 number of MTT entries per segment (1-7)");
154 static int port_type_array
[2] = {MLX4_PORT_TYPE_NONE
, MLX4_PORT_TYPE_NONE
};
155 static int arr_argc
= 2;
156 module_param_array(port_type_array
, int, &arr_argc
, 0444);
157 MODULE_PARM_DESC(port_type_array
, "Array of port types: HW_DEFAULT (0) is default "
158 "1 for IB, 2 for Ethernet");
160 struct mlx4_port_config
{
161 struct list_head list
;
162 enum mlx4_port_type port_type
[MLX4_MAX_PORTS
+ 1];
163 struct pci_dev
*pdev
;
166 static atomic_t pf_loading
= ATOMIC_INIT(0);
168 int mlx4_check_port_params(struct mlx4_dev
*dev
,
169 enum mlx4_port_type
*port_type
)
173 for (i
= 0; i
< dev
->caps
.num_ports
- 1; i
++) {
174 if (port_type
[i
] != port_type
[i
+ 1]) {
175 if (!(dev
->caps
.flags
& MLX4_DEV_CAP_FLAG_DPDP
)) {
176 mlx4_err(dev
, "Only same port types supported on this HCA, aborting\n");
182 for (i
= 0; i
< dev
->caps
.num_ports
; i
++) {
183 if (!(port_type
[i
] & dev
->caps
.supported_type
[i
+1])) {
184 mlx4_err(dev
, "Requested port type for port %d is not supported on this HCA\n",
192 static void mlx4_set_port_mask(struct mlx4_dev
*dev
)
196 for (i
= 1; i
<= dev
->caps
.num_ports
; ++i
)
197 dev
->caps
.port_mask
[i
] = dev
->caps
.port_type
[i
];
200 static void mlx4_enable_cqe_eqe_stride(struct mlx4_dev
*dev
)
202 struct mlx4_caps
*dev_cap
= &dev
->caps
;
204 /* FW not supporting or cancelled by user */
205 if (!(dev_cap
->flags2
& MLX4_DEV_CAP_FLAG2_EQE_STRIDE
) ||
206 !(dev_cap
->flags2
& MLX4_DEV_CAP_FLAG2_CQE_STRIDE
))
209 /* Must have 64B CQE_EQE enabled by FW to use bigger stride
210 * When FW has NCSI it may decide not to report 64B CQE/EQEs
212 if (!(dev_cap
->flags
& MLX4_DEV_CAP_FLAG_64B_EQE
) ||
213 !(dev_cap
->flags
& MLX4_DEV_CAP_FLAG_64B_CQE
)) {
214 dev_cap
->flags2
&= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE
;
215 dev_cap
->flags2
&= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE
;
219 if (cache_line_size() == 128 || cache_line_size() == 256) {
220 mlx4_dbg(dev
, "Enabling CQE stride cacheLine supported\n");
221 /* Changing the real data inside CQE size to 32B */
222 dev_cap
->flags
&= ~MLX4_DEV_CAP_FLAG_64B_CQE
;
223 dev_cap
->flags
&= ~MLX4_DEV_CAP_FLAG_64B_EQE
;
225 if (mlx4_is_master(dev
))
226 dev_cap
->function_caps
|= MLX4_FUNC_CAP_EQE_CQE_STRIDE
;
228 mlx4_dbg(dev
, "Disabling CQE stride cacheLine unsupported\n");
229 dev_cap
->flags2
&= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE
;
230 dev_cap
->flags2
&= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE
;
234 static int mlx4_dev_cap(struct mlx4_dev
*dev
, struct mlx4_dev_cap
*dev_cap
)
239 err
= mlx4_QUERY_DEV_CAP(dev
, dev_cap
);
241 mlx4_err(dev
, "QUERY_DEV_CAP command failed, aborting\n");
245 if (dev_cap
->min_page_sz
> PAGE_SIZE
) {
246 mlx4_err(dev
, "HCA minimum page size of %d bigger than kernel PAGE_SIZE of %ld, aborting\n",
247 dev_cap
->min_page_sz
, PAGE_SIZE
);
250 if (dev_cap
->num_ports
> MLX4_MAX_PORTS
) {
251 mlx4_err(dev
, "HCA has %d ports, but we only support %d, aborting\n",
252 dev_cap
->num_ports
, MLX4_MAX_PORTS
);
256 if (dev_cap
->uar_size
> pci_resource_len(dev
->pdev
, 2)) {
257 mlx4_err(dev
, "HCA reported UAR size of 0x%x bigger than PCI resource 2 size of 0x%llx, aborting\n",
259 (unsigned long long) pci_resource_len(dev
->pdev
, 2));
263 dev
->caps
.num_ports
= dev_cap
->num_ports
;
264 dev
->phys_caps
.num_phys_eqs
= MLX4_MAX_EQ_NUM
;
265 for (i
= 1; i
<= dev
->caps
.num_ports
; ++i
) {
266 dev
->caps
.vl_cap
[i
] = dev_cap
->max_vl
[i
];
267 dev
->caps
.ib_mtu_cap
[i
] = dev_cap
->ib_mtu
[i
];
268 dev
->phys_caps
.gid_phys_table_len
[i
] = dev_cap
->max_gids
[i
];
269 dev
->phys_caps
.pkey_phys_table_len
[i
] = dev_cap
->max_pkeys
[i
];
270 /* set gid and pkey table operating lengths by default
271 * to non-sriov values */
272 dev
->caps
.gid_table_len
[i
] = dev_cap
->max_gids
[i
];
273 dev
->caps
.pkey_table_len
[i
] = dev_cap
->max_pkeys
[i
];
274 dev
->caps
.port_width_cap
[i
] = dev_cap
->max_port_width
[i
];
275 dev
->caps
.eth_mtu_cap
[i
] = dev_cap
->eth_mtu
[i
];
276 dev
->caps
.def_mac
[i
] = dev_cap
->def_mac
[i
];
277 dev
->caps
.supported_type
[i
] = dev_cap
->supported_port_types
[i
];
278 dev
->caps
.suggested_type
[i
] = dev_cap
->suggested_type
[i
];
279 dev
->caps
.default_sense
[i
] = dev_cap
->default_sense
[i
];
280 dev
->caps
.trans_type
[i
] = dev_cap
->trans_type
[i
];
281 dev
->caps
.vendor_oui
[i
] = dev_cap
->vendor_oui
[i
];
282 dev
->caps
.wavelength
[i
] = dev_cap
->wavelength
[i
];
283 dev
->caps
.trans_code
[i
] = dev_cap
->trans_code
[i
];
286 dev
->caps
.uar_page_size
= PAGE_SIZE
;
287 dev
->caps
.num_uars
= dev_cap
->uar_size
/ PAGE_SIZE
;
288 dev
->caps
.local_ca_ack_delay
= dev_cap
->local_ca_ack_delay
;
289 dev
->caps
.bf_reg_size
= dev_cap
->bf_reg_size
;
290 dev
->caps
.bf_regs_per_page
= dev_cap
->bf_regs_per_page
;
291 dev
->caps
.max_sq_sg
= dev_cap
->max_sq_sg
;
292 dev
->caps
.max_rq_sg
= dev_cap
->max_rq_sg
;
293 dev
->caps
.max_wqes
= dev_cap
->max_qp_sz
;
294 dev
->caps
.max_qp_init_rdma
= dev_cap
->max_requester_per_qp
;
295 dev
->caps
.max_srq_wqes
= dev_cap
->max_srq_sz
;
296 dev
->caps
.max_srq_sge
= dev_cap
->max_rq_sg
- 1;
297 dev
->caps
.reserved_srqs
= dev_cap
->reserved_srqs
;
298 dev
->caps
.max_sq_desc_sz
= dev_cap
->max_sq_desc_sz
;
299 dev
->caps
.max_rq_desc_sz
= dev_cap
->max_rq_desc_sz
;
301 * Subtract 1 from the limit because we need to allocate a
302 * spare CQE so the HCA HW can tell the difference between an
303 * empty CQ and a full CQ.
305 dev
->caps
.max_cqes
= dev_cap
->max_cq_sz
- 1;
306 dev
->caps
.reserved_cqs
= dev_cap
->reserved_cqs
;
307 dev
->caps
.reserved_eqs
= dev_cap
->reserved_eqs
;
308 dev
->caps
.reserved_mtts
= dev_cap
->reserved_mtts
;
309 dev
->caps
.reserved_mrws
= dev_cap
->reserved_mrws
;
311 /* The first 128 UARs are used for EQ doorbells */
312 dev
->caps
.reserved_uars
= max_t(int, 128, dev_cap
->reserved_uars
);
313 dev
->caps
.reserved_pds
= dev_cap
->reserved_pds
;
314 dev
->caps
.reserved_xrcds
= (dev
->caps
.flags
& MLX4_DEV_CAP_FLAG_XRC
) ?
315 dev_cap
->reserved_xrcds
: 0;
316 dev
->caps
.max_xrcds
= (dev
->caps
.flags
& MLX4_DEV_CAP_FLAG_XRC
) ?
317 dev_cap
->max_xrcds
: 0;
318 dev
->caps
.mtt_entry_sz
= dev_cap
->mtt_entry_sz
;
320 dev
->caps
.max_msg_sz
= dev_cap
->max_msg_sz
;
321 dev
->caps
.page_size_cap
= ~(u32
) (dev_cap
->min_page_sz
- 1);
322 dev
->caps
.flags
= dev_cap
->flags
;
323 dev
->caps
.flags2
= dev_cap
->flags2
;
324 dev
->caps
.bmme_flags
= dev_cap
->bmme_flags
;
325 dev
->caps
.reserved_lkey
= dev_cap
->reserved_lkey
;
326 dev
->caps
.stat_rate_support
= dev_cap
->stat_rate_support
;
327 dev
->caps
.max_gso_sz
= dev_cap
->max_gso_sz
;
328 dev
->caps
.max_rss_tbl_sz
= dev_cap
->max_rss_tbl_sz
;
330 /* Sense port always allowed on supported devices for ConnectX-1 and -2 */
331 if (mlx4_priv(dev
)->pci_dev_data
& MLX4_PCI_DEV_FORCE_SENSE_PORT
)
332 dev
->caps
.flags
|= MLX4_DEV_CAP_FLAG_SENSE_SUPPORT
;
333 /* Don't do sense port on multifunction devices (for now at least) */
334 if (mlx4_is_mfunc(dev
))
335 dev
->caps
.flags
&= ~MLX4_DEV_CAP_FLAG_SENSE_SUPPORT
;
337 if (mlx4_low_memory_profile()) {
338 dev
->caps
.log_num_macs
= MLX4_MIN_LOG_NUM_MAC
;
339 dev
->caps
.log_num_vlans
= MLX4_MIN_LOG_NUM_VLANS
;
341 dev
->caps
.log_num_macs
= log_num_mac
;
342 dev
->caps
.log_num_vlans
= MLX4_LOG_NUM_VLANS
;
345 for (i
= 1; i
<= dev
->caps
.num_ports
; ++i
) {
346 dev
->caps
.port_type
[i
] = MLX4_PORT_TYPE_NONE
;
347 if (dev
->caps
.supported_type
[i
]) {
348 /* if only ETH is supported - assign ETH */
349 if (dev
->caps
.supported_type
[i
] == MLX4_PORT_TYPE_ETH
)
350 dev
->caps
.port_type
[i
] = MLX4_PORT_TYPE_ETH
;
351 /* if only IB is supported, assign IB */
352 else if (dev
->caps
.supported_type
[i
] ==
354 dev
->caps
.port_type
[i
] = MLX4_PORT_TYPE_IB
;
356 /* if IB and ETH are supported, we set the port
357 * type according to user selection of port type;
358 * if user selected none, take the FW hint */
359 if (port_type_array
[i
- 1] == MLX4_PORT_TYPE_NONE
)
360 dev
->caps
.port_type
[i
] = dev
->caps
.suggested_type
[i
] ?
361 MLX4_PORT_TYPE_ETH
: MLX4_PORT_TYPE_IB
;
363 dev
->caps
.port_type
[i
] = port_type_array
[i
- 1];
367 * Link sensing is allowed on the port if 3 conditions are true:
368 * 1. Both protocols are supported on the port.
369 * 2. Different types are supported on the port
370 * 3. FW declared that it supports link sensing
372 mlx4_priv(dev
)->sense
.sense_allowed
[i
] =
373 ((dev
->caps
.supported_type
[i
] == MLX4_PORT_TYPE_AUTO
) &&
374 (dev
->caps
.flags
& MLX4_DEV_CAP_FLAG_DPDP
) &&
375 (dev
->caps
.flags
& MLX4_DEV_CAP_FLAG_SENSE_SUPPORT
));
378 * If "default_sense" bit is set, we move the port to "AUTO" mode
379 * and perform sense_port FW command to try and set the correct
380 * port type from beginning
382 if (mlx4_priv(dev
)->sense
.sense_allowed
[i
] && dev
->caps
.default_sense
[i
]) {
383 enum mlx4_port_type sensed_port
= MLX4_PORT_TYPE_NONE
;
384 dev
->caps
.possible_type
[i
] = MLX4_PORT_TYPE_AUTO
;
385 mlx4_SENSE_PORT(dev
, i
, &sensed_port
);
386 if (sensed_port
!= MLX4_PORT_TYPE_NONE
)
387 dev
->caps
.port_type
[i
] = sensed_port
;
389 dev
->caps
.possible_type
[i
] = dev
->caps
.port_type
[i
];
392 if (dev
->caps
.log_num_macs
> dev_cap
->log_max_macs
[i
]) {
393 dev
->caps
.log_num_macs
= dev_cap
->log_max_macs
[i
];
394 mlx4_warn(dev
, "Requested number of MACs is too much for port %d, reducing to %d\n",
395 i
, 1 << dev
->caps
.log_num_macs
);
397 if (dev
->caps
.log_num_vlans
> dev_cap
->log_max_vlans
[i
]) {
398 dev
->caps
.log_num_vlans
= dev_cap
->log_max_vlans
[i
];
399 mlx4_warn(dev
, "Requested number of VLANs is too much for port %d, reducing to %d\n",
400 i
, 1 << dev
->caps
.log_num_vlans
);
404 dev
->caps
.max_counters
= 1 << ilog2(dev_cap
->max_counters
);
406 dev
->caps
.reserved_qps_cnt
[MLX4_QP_REGION_FW
] = dev_cap
->reserved_qps
;
407 dev
->caps
.reserved_qps_cnt
[MLX4_QP_REGION_ETH_ADDR
] =
408 dev
->caps
.reserved_qps_cnt
[MLX4_QP_REGION_FC_ADDR
] =
409 (1 << dev
->caps
.log_num_macs
) *
410 (1 << dev
->caps
.log_num_vlans
) *
412 dev
->caps
.reserved_qps_cnt
[MLX4_QP_REGION_FC_EXCH
] = MLX4_NUM_FEXCH
;
414 dev
->caps
.reserved_qps
= dev
->caps
.reserved_qps_cnt
[MLX4_QP_REGION_FW
] +
415 dev
->caps
.reserved_qps_cnt
[MLX4_QP_REGION_ETH_ADDR
] +
416 dev
->caps
.reserved_qps_cnt
[MLX4_QP_REGION_FC_ADDR
] +
417 dev
->caps
.reserved_qps_cnt
[MLX4_QP_REGION_FC_EXCH
];
419 dev
->caps
.sqp_demux
= (mlx4_is_master(dev
)) ? MLX4_MAX_NUM_SLAVES
: 0;
421 if (!enable_64b_cqe_eqe
&& !mlx4_is_slave(dev
)) {
423 (MLX4_DEV_CAP_FLAG_64B_CQE
| MLX4_DEV_CAP_FLAG_64B_EQE
)) {
424 mlx4_warn(dev
, "64B EQEs/CQEs supported by the device but not enabled\n");
425 dev
->caps
.flags
&= ~MLX4_DEV_CAP_FLAG_64B_CQE
;
426 dev
->caps
.flags
&= ~MLX4_DEV_CAP_FLAG_64B_EQE
;
429 if (dev_cap
->flags2
&
430 (MLX4_DEV_CAP_FLAG2_CQE_STRIDE
|
431 MLX4_DEV_CAP_FLAG2_EQE_STRIDE
)) {
432 mlx4_warn(dev
, "Disabling EQE/CQE stride per user request\n");
433 dev_cap
->flags2
&= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE
;
434 dev_cap
->flags2
&= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE
;
438 if ((dev
->caps
.flags
&
439 (MLX4_DEV_CAP_FLAG_64B_CQE
| MLX4_DEV_CAP_FLAG_64B_EQE
)) &&
441 dev
->caps
.function_caps
|= MLX4_FUNC_CAP_64B_EQE_CQE
;
443 if (!mlx4_is_slave(dev
))
444 mlx4_enable_cqe_eqe_stride(dev
);
449 static int mlx4_get_pcie_dev_link_caps(struct mlx4_dev
*dev
,
450 enum pci_bus_speed
*speed
,
451 enum pcie_link_width
*width
)
453 u32 lnkcap1
, lnkcap2
;
456 #define PCIE_MLW_CAP_SHIFT 4 /* start of MLW mask in link capabilities */
458 *speed
= PCI_SPEED_UNKNOWN
;
459 *width
= PCIE_LNK_WIDTH_UNKNOWN
;
461 err1
= pcie_capability_read_dword(dev
->pdev
, PCI_EXP_LNKCAP
, &lnkcap1
);
462 err2
= pcie_capability_read_dword(dev
->pdev
, PCI_EXP_LNKCAP2
, &lnkcap2
);
463 if (!err2
&& lnkcap2
) { /* PCIe r3.0-compliant */
464 if (lnkcap2
& PCI_EXP_LNKCAP2_SLS_8_0GB
)
465 *speed
= PCIE_SPEED_8_0GT
;
466 else if (lnkcap2
& PCI_EXP_LNKCAP2_SLS_5_0GB
)
467 *speed
= PCIE_SPEED_5_0GT
;
468 else if (lnkcap2
& PCI_EXP_LNKCAP2_SLS_2_5GB
)
469 *speed
= PCIE_SPEED_2_5GT
;
472 *width
= (lnkcap1
& PCI_EXP_LNKCAP_MLW
) >> PCIE_MLW_CAP_SHIFT
;
473 if (!lnkcap2
) { /* pre-r3.0 */
474 if (lnkcap1
& PCI_EXP_LNKCAP_SLS_5_0GB
)
475 *speed
= PCIE_SPEED_5_0GT
;
476 else if (lnkcap1
& PCI_EXP_LNKCAP_SLS_2_5GB
)
477 *speed
= PCIE_SPEED_2_5GT
;
481 if (*speed
== PCI_SPEED_UNKNOWN
|| *width
== PCIE_LNK_WIDTH_UNKNOWN
) {
483 err2
? err2
: -EINVAL
;
488 static void mlx4_check_pcie_caps(struct mlx4_dev
*dev
)
490 enum pcie_link_width width
, width_cap
;
491 enum pci_bus_speed speed
, speed_cap
;
494 #define PCIE_SPEED_STR(speed) \
495 (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" : \
496 speed == PCIE_SPEED_5_0GT ? "5.0GT/s" : \
497 speed == PCIE_SPEED_2_5GT ? "2.5GT/s" : \
500 err
= mlx4_get_pcie_dev_link_caps(dev
, &speed_cap
, &width_cap
);
503 "Unable to determine PCIe device BW capabilities\n");
507 err
= pcie_get_minimum_link(dev
->pdev
, &speed
, &width
);
508 if (err
|| speed
== PCI_SPEED_UNKNOWN
||
509 width
== PCIE_LNK_WIDTH_UNKNOWN
) {
511 "Unable to determine PCI device chain minimum BW\n");
515 if (width
!= width_cap
|| speed
!= speed_cap
)
517 "PCIe BW is different than device's capability\n");
519 mlx4_info(dev
, "PCIe link speed is %s, device supports %s\n",
520 PCIE_SPEED_STR(speed
), PCIE_SPEED_STR(speed_cap
));
521 mlx4_info(dev
, "PCIe link width is x%d, device supports x%d\n",
526 /*The function checks if there are live vf, return the num of them*/
527 static int mlx4_how_many_lives_vf(struct mlx4_dev
*dev
)
529 struct mlx4_priv
*priv
= mlx4_priv(dev
);
530 struct mlx4_slave_state
*s_state
;
534 for (i
= 1/*the ppf is 0*/; i
< dev
->num_slaves
; ++i
) {
535 s_state
= &priv
->mfunc
.master
.slave_state
[i
];
536 if (s_state
->active
&& s_state
->last_cmd
!=
537 MLX4_COMM_CMD_RESET
) {
538 mlx4_warn(dev
, "%s: slave: %d is still active\n",
546 int mlx4_get_parav_qkey(struct mlx4_dev
*dev
, u32 qpn
, u32
*qkey
)
548 u32 qk
= MLX4_RESERVED_QKEY_BASE
;
550 if (qpn
>= dev
->phys_caps
.base_tunnel_sqpn
+ 8 * MLX4_MFUNC_MAX
||
551 qpn
< dev
->phys_caps
.base_proxy_sqpn
)
554 if (qpn
>= dev
->phys_caps
.base_tunnel_sqpn
)
556 qk
+= qpn
- dev
->phys_caps
.base_tunnel_sqpn
;
558 qk
+= qpn
- dev
->phys_caps
.base_proxy_sqpn
;
562 EXPORT_SYMBOL(mlx4_get_parav_qkey
);
564 void mlx4_sync_pkey_table(struct mlx4_dev
*dev
, int slave
, int port
, int i
, int val
)
566 struct mlx4_priv
*priv
= container_of(dev
, struct mlx4_priv
, dev
);
568 if (!mlx4_is_master(dev
))
571 priv
->virt2phys_pkey
[slave
][port
- 1][i
] = val
;
573 EXPORT_SYMBOL(mlx4_sync_pkey_table
);
575 void mlx4_put_slave_node_guid(struct mlx4_dev
*dev
, int slave
, __be64 guid
)
577 struct mlx4_priv
*priv
= container_of(dev
, struct mlx4_priv
, dev
);
579 if (!mlx4_is_master(dev
))
582 priv
->slave_node_guids
[slave
] = guid
;
584 EXPORT_SYMBOL(mlx4_put_slave_node_guid
);
586 __be64
mlx4_get_slave_node_guid(struct mlx4_dev
*dev
, int slave
)
588 struct mlx4_priv
*priv
= container_of(dev
, struct mlx4_priv
, dev
);
590 if (!mlx4_is_master(dev
))
593 return priv
->slave_node_guids
[slave
];
595 EXPORT_SYMBOL(mlx4_get_slave_node_guid
);
597 int mlx4_is_slave_active(struct mlx4_dev
*dev
, int slave
)
599 struct mlx4_priv
*priv
= mlx4_priv(dev
);
600 struct mlx4_slave_state
*s_slave
;
602 if (!mlx4_is_master(dev
))
605 s_slave
= &priv
->mfunc
.master
.slave_state
[slave
];
606 return !!s_slave
->active
;
608 EXPORT_SYMBOL(mlx4_is_slave_active
);
610 static void slave_adjust_steering_mode(struct mlx4_dev
*dev
,
611 struct mlx4_dev_cap
*dev_cap
,
612 struct mlx4_init_hca_param
*hca_param
)
614 dev
->caps
.steering_mode
= hca_param
->steering_mode
;
615 if (dev
->caps
.steering_mode
== MLX4_STEERING_MODE_DEVICE_MANAGED
) {
616 dev
->caps
.num_qp_per_mgm
= dev_cap
->fs_max_num_qp_per_entry
;
617 dev
->caps
.fs_log_max_ucast_qp_range_size
=
618 dev_cap
->fs_log_max_ucast_qp_range_size
;
620 dev
->caps
.num_qp_per_mgm
=
621 4 * ((1 << hca_param
->log_mc_entry_sz
)/16 - 2);
623 mlx4_dbg(dev
, "Steering mode is: %s\n",
624 mlx4_steering_mode_str(dev
->caps
.steering_mode
));
627 static int mlx4_slave_cap(struct mlx4_dev
*dev
)
631 struct mlx4_dev_cap dev_cap
;
632 struct mlx4_func_cap func_cap
;
633 struct mlx4_init_hca_param hca_param
;
636 memset(&hca_param
, 0, sizeof(hca_param
));
637 err
= mlx4_QUERY_HCA(dev
, &hca_param
);
639 mlx4_err(dev
, "QUERY_HCA command failed, aborting\n");
643 /* fail if the hca has an unknown global capability
644 * at this time global_caps should be always zeroed
646 if (hca_param
.global_caps
) {
647 mlx4_err(dev
, "Unknown hca global capabilities\n");
651 mlx4_log_num_mgm_entry_size
= hca_param
.log_mc_entry_sz
;
653 dev
->caps
.hca_core_clock
= hca_param
.hca_core_clock
;
655 memset(&dev_cap
, 0, sizeof(dev_cap
));
656 dev
->caps
.max_qp_dest_rdma
= 1 << hca_param
.log_rd_per_qp
;
657 err
= mlx4_dev_cap(dev
, &dev_cap
);
659 mlx4_err(dev
, "QUERY_DEV_CAP command failed, aborting\n");
663 err
= mlx4_QUERY_FW(dev
);
665 mlx4_err(dev
, "QUERY_FW command failed: could not get FW version\n");
667 page_size
= ~dev
->caps
.page_size_cap
+ 1;
668 mlx4_warn(dev
, "HCA minimum page size:%d\n", page_size
);
669 if (page_size
> PAGE_SIZE
) {
670 mlx4_err(dev
, "HCA minimum page size of %d bigger than kernel PAGE_SIZE of %ld, aborting\n",
671 page_size
, PAGE_SIZE
);
675 /* slave gets uar page size from QUERY_HCA fw command */
676 dev
->caps
.uar_page_size
= 1 << (hca_param
.uar_page_sz
+ 12);
678 /* TODO: relax this assumption */
679 if (dev
->caps
.uar_page_size
!= PAGE_SIZE
) {
680 mlx4_err(dev
, "UAR size:%d != kernel PAGE_SIZE of %ld\n",
681 dev
->caps
.uar_page_size
, PAGE_SIZE
);
685 memset(&func_cap
, 0, sizeof(func_cap
));
686 err
= mlx4_QUERY_FUNC_CAP(dev
, 0, &func_cap
);
688 mlx4_err(dev
, "QUERY_FUNC_CAP general command failed, aborting (%d)\n",
693 if ((func_cap
.pf_context_behaviour
| PF_CONTEXT_BEHAVIOUR_MASK
) !=
694 PF_CONTEXT_BEHAVIOUR_MASK
) {
695 mlx4_err(dev
, "Unknown pf context behaviour\n");
699 dev
->caps
.num_ports
= func_cap
.num_ports
;
700 dev
->quotas
.qp
= func_cap
.qp_quota
;
701 dev
->quotas
.srq
= func_cap
.srq_quota
;
702 dev
->quotas
.cq
= func_cap
.cq_quota
;
703 dev
->quotas
.mpt
= func_cap
.mpt_quota
;
704 dev
->quotas
.mtt
= func_cap
.mtt_quota
;
705 dev
->caps
.num_qps
= 1 << hca_param
.log_num_qps
;
706 dev
->caps
.num_srqs
= 1 << hca_param
.log_num_srqs
;
707 dev
->caps
.num_cqs
= 1 << hca_param
.log_num_cqs
;
708 dev
->caps
.num_mpts
= 1 << hca_param
.log_mpt_sz
;
709 dev
->caps
.num_eqs
= func_cap
.max_eq
;
710 dev
->caps
.reserved_eqs
= func_cap
.reserved_eq
;
711 dev
->caps
.num_pds
= MLX4_NUM_PDS
;
712 dev
->caps
.num_mgms
= 0;
713 dev
->caps
.num_amgms
= 0;
715 if (dev
->caps
.num_ports
> MLX4_MAX_PORTS
) {
716 mlx4_err(dev
, "HCA has %d ports, but we only support %d, aborting\n",
717 dev
->caps
.num_ports
, MLX4_MAX_PORTS
);
721 dev
->caps
.qp0_qkey
= kcalloc(dev
->caps
.num_ports
, sizeof(u32
), GFP_KERNEL
);
722 dev
->caps
.qp0_tunnel
= kcalloc(dev
->caps
.num_ports
, sizeof (u32
), GFP_KERNEL
);
723 dev
->caps
.qp0_proxy
= kcalloc(dev
->caps
.num_ports
, sizeof (u32
), GFP_KERNEL
);
724 dev
->caps
.qp1_tunnel
= kcalloc(dev
->caps
.num_ports
, sizeof (u32
), GFP_KERNEL
);
725 dev
->caps
.qp1_proxy
= kcalloc(dev
->caps
.num_ports
, sizeof (u32
), GFP_KERNEL
);
727 if (!dev
->caps
.qp0_tunnel
|| !dev
->caps
.qp0_proxy
||
728 !dev
->caps
.qp1_tunnel
|| !dev
->caps
.qp1_proxy
||
729 !dev
->caps
.qp0_qkey
) {
734 for (i
= 1; i
<= dev
->caps
.num_ports
; ++i
) {
735 err
= mlx4_QUERY_FUNC_CAP(dev
, (u32
) i
, &func_cap
);
737 mlx4_err(dev
, "QUERY_FUNC_CAP port command failed for port %d, aborting (%d)\n",
741 dev
->caps
.qp0_qkey
[i
- 1] = func_cap
.qp0_qkey
;
742 dev
->caps
.qp0_tunnel
[i
- 1] = func_cap
.qp0_tunnel_qpn
;
743 dev
->caps
.qp0_proxy
[i
- 1] = func_cap
.qp0_proxy_qpn
;
744 dev
->caps
.qp1_tunnel
[i
- 1] = func_cap
.qp1_tunnel_qpn
;
745 dev
->caps
.qp1_proxy
[i
- 1] = func_cap
.qp1_proxy_qpn
;
746 dev
->caps
.port_mask
[i
] = dev
->caps
.port_type
[i
];
747 dev
->caps
.phys_port_id
[i
] = func_cap
.phys_port_id
;
748 if (mlx4_get_slave_pkey_gid_tbl_len(dev
, i
,
749 &dev
->caps
.gid_table_len
[i
],
750 &dev
->caps
.pkey_table_len
[i
]))
754 if (dev
->caps
.uar_page_size
* (dev
->caps
.num_uars
-
755 dev
->caps
.reserved_uars
) >
756 pci_resource_len(dev
->pdev
, 2)) {
757 mlx4_err(dev
, "HCA reported UAR region size of 0x%x bigger than PCI resource 2 size of 0x%llx, aborting\n",
758 dev
->caps
.uar_page_size
* dev
->caps
.num_uars
,
759 (unsigned long long) pci_resource_len(dev
->pdev
, 2));
763 if (hca_param
.dev_cap_enabled
& MLX4_DEV_CAP_64B_EQE_ENABLED
) {
764 dev
->caps
.eqe_size
= 64;
765 dev
->caps
.eqe_factor
= 1;
767 dev
->caps
.eqe_size
= 32;
768 dev
->caps
.eqe_factor
= 0;
771 if (hca_param
.dev_cap_enabled
& MLX4_DEV_CAP_64B_CQE_ENABLED
) {
772 dev
->caps
.cqe_size
= 64;
773 dev
->caps
.userspace_caps
|= MLX4_USER_DEV_CAP_LARGE_CQE
;
775 dev
->caps
.cqe_size
= 32;
778 if (hca_param
.dev_cap_enabled
& MLX4_DEV_CAP_EQE_STRIDE_ENABLED
) {
779 dev
->caps
.eqe_size
= hca_param
.eqe_size
;
780 dev
->caps
.eqe_factor
= 0;
783 if (hca_param
.dev_cap_enabled
& MLX4_DEV_CAP_CQE_STRIDE_ENABLED
) {
784 dev
->caps
.cqe_size
= hca_param
.cqe_size
;
785 /* User still need to know when CQE > 32B */
786 dev
->caps
.userspace_caps
|= MLX4_USER_DEV_CAP_LARGE_CQE
;
789 dev
->caps
.flags2
&= ~MLX4_DEV_CAP_FLAG2_TS
;
790 mlx4_warn(dev
, "Timestamping is not supported in slave mode\n");
792 slave_adjust_steering_mode(dev
, &dev_cap
, &hca_param
);
797 kfree(dev
->caps
.qp0_qkey
);
798 kfree(dev
->caps
.qp0_tunnel
);
799 kfree(dev
->caps
.qp0_proxy
);
800 kfree(dev
->caps
.qp1_tunnel
);
801 kfree(dev
->caps
.qp1_proxy
);
802 dev
->caps
.qp0_qkey
= NULL
;
803 dev
->caps
.qp0_tunnel
= NULL
;
804 dev
->caps
.qp0_proxy
= NULL
;
805 dev
->caps
.qp1_tunnel
= NULL
;
806 dev
->caps
.qp1_proxy
= NULL
;
811 static void mlx4_request_modules(struct mlx4_dev
*dev
)
814 int has_ib_port
= false;
815 int has_eth_port
= false;
816 #define EN_DRV_NAME "mlx4_en"
817 #define IB_DRV_NAME "mlx4_ib"
819 for (port
= 1; port
<= dev
->caps
.num_ports
; port
++) {
820 if (dev
->caps
.port_type
[port
] == MLX4_PORT_TYPE_IB
)
822 else if (dev
->caps
.port_type
[port
] == MLX4_PORT_TYPE_ETH
)
827 request_module_nowait(EN_DRV_NAME
);
828 if (has_ib_port
|| (dev
->caps
.flags
& MLX4_DEV_CAP_FLAG_IBOE
))
829 request_module_nowait(IB_DRV_NAME
);
833 * Change the port configuration of the device.
834 * Every user of this function must hold the port mutex.
836 int mlx4_change_port_types(struct mlx4_dev
*dev
,
837 enum mlx4_port_type
*port_types
)
843 for (port
= 0; port
< dev
->caps
.num_ports
; port
++) {
844 /* Change the port type only if the new type is different
845 * from the current, and not set to Auto */
846 if (port_types
[port
] != dev
->caps
.port_type
[port
+ 1])
850 mlx4_unregister_device(dev
);
851 for (port
= 1; port
<= dev
->caps
.num_ports
; port
++) {
852 mlx4_CLOSE_PORT(dev
, port
);
853 dev
->caps
.port_type
[port
] = port_types
[port
- 1];
854 err
= mlx4_SET_PORT(dev
, port
, -1);
856 mlx4_err(dev
, "Failed to set port %d, aborting\n",
861 mlx4_set_port_mask(dev
);
862 err
= mlx4_register_device(dev
);
864 mlx4_err(dev
, "Failed to register device\n");
867 mlx4_request_modules(dev
);
874 static ssize_t
show_port_type(struct device
*dev
,
875 struct device_attribute
*attr
,
878 struct mlx4_port_info
*info
= container_of(attr
, struct mlx4_port_info
,
880 struct mlx4_dev
*mdev
= info
->dev
;
884 (mdev
->caps
.port_type
[info
->port
] == MLX4_PORT_TYPE_IB
) ?
886 if (mdev
->caps
.possible_type
[info
->port
] == MLX4_PORT_TYPE_AUTO
)
887 sprintf(buf
, "auto (%s)\n", type
);
889 sprintf(buf
, "%s\n", type
);
894 static ssize_t
set_port_type(struct device
*dev
,
895 struct device_attribute
*attr
,
896 const char *buf
, size_t count
)
898 struct mlx4_port_info
*info
= container_of(attr
, struct mlx4_port_info
,
900 struct mlx4_dev
*mdev
= info
->dev
;
901 struct mlx4_priv
*priv
= mlx4_priv(mdev
);
902 enum mlx4_port_type types
[MLX4_MAX_PORTS
];
903 enum mlx4_port_type new_types
[MLX4_MAX_PORTS
];
904 static DEFINE_MUTEX(set_port_type_mutex
);
908 mutex_lock(&set_port_type_mutex
);
910 if (!strcmp(buf
, "ib\n"))
911 info
->tmp_type
= MLX4_PORT_TYPE_IB
;
912 else if (!strcmp(buf
, "eth\n"))
913 info
->tmp_type
= MLX4_PORT_TYPE_ETH
;
914 else if (!strcmp(buf
, "auto\n"))
915 info
->tmp_type
= MLX4_PORT_TYPE_AUTO
;
917 mlx4_err(mdev
, "%s is not supported port type\n", buf
);
922 mlx4_stop_sense(mdev
);
923 mutex_lock(&priv
->port_mutex
);
924 /* Possible type is always the one that was delivered */
925 mdev
->caps
.possible_type
[info
->port
] = info
->tmp_type
;
927 for (i
= 0; i
< mdev
->caps
.num_ports
; i
++) {
928 types
[i
] = priv
->port
[i
+1].tmp_type
? priv
->port
[i
+1].tmp_type
:
929 mdev
->caps
.possible_type
[i
+1];
930 if (types
[i
] == MLX4_PORT_TYPE_AUTO
)
931 types
[i
] = mdev
->caps
.port_type
[i
+1];
934 if (!(mdev
->caps
.flags
& MLX4_DEV_CAP_FLAG_DPDP
) &&
935 !(mdev
->caps
.flags
& MLX4_DEV_CAP_FLAG_SENSE_SUPPORT
)) {
936 for (i
= 1; i
<= mdev
->caps
.num_ports
; i
++) {
937 if (mdev
->caps
.possible_type
[i
] == MLX4_PORT_TYPE_AUTO
) {
938 mdev
->caps
.possible_type
[i
] = mdev
->caps
.port_type
[i
];
944 mlx4_err(mdev
, "Auto sensing is not supported on this HCA. Set only 'eth' or 'ib' for both ports (should be the same)\n");
948 mlx4_do_sense_ports(mdev
, new_types
, types
);
950 err
= mlx4_check_port_params(mdev
, new_types
);
954 /* We are about to apply the changes after the configuration
955 * was verified, no need to remember the temporary types
957 for (i
= 0; i
< mdev
->caps
.num_ports
; i
++)
958 priv
->port
[i
+ 1].tmp_type
= 0;
960 err
= mlx4_change_port_types(mdev
, new_types
);
963 mlx4_start_sense(mdev
);
964 mutex_unlock(&priv
->port_mutex
);
966 mutex_unlock(&set_port_type_mutex
);
968 return err
? err
: count
;
979 static inline int int_to_ibta_mtu(int mtu
)
982 case 256: return IB_MTU_256
;
983 case 512: return IB_MTU_512
;
984 case 1024: return IB_MTU_1024
;
985 case 2048: return IB_MTU_2048
;
986 case 4096: return IB_MTU_4096
;
991 static inline int ibta_mtu_to_int(enum ibta_mtu mtu
)
994 case IB_MTU_256
: return 256;
995 case IB_MTU_512
: return 512;
996 case IB_MTU_1024
: return 1024;
997 case IB_MTU_2048
: return 2048;
998 case IB_MTU_4096
: return 4096;
1003 static ssize_t
show_port_ib_mtu(struct device
*dev
,
1004 struct device_attribute
*attr
,
1007 struct mlx4_port_info
*info
= container_of(attr
, struct mlx4_port_info
,
1009 struct mlx4_dev
*mdev
= info
->dev
;
1011 if (mdev
->caps
.port_type
[info
->port
] == MLX4_PORT_TYPE_ETH
)
1012 mlx4_warn(mdev
, "port level mtu is only used for IB ports\n");
1014 sprintf(buf
, "%d\n",
1015 ibta_mtu_to_int(mdev
->caps
.port_ib_mtu
[info
->port
]));
1019 static ssize_t
set_port_ib_mtu(struct device
*dev
,
1020 struct device_attribute
*attr
,
1021 const char *buf
, size_t count
)
1023 struct mlx4_port_info
*info
= container_of(attr
, struct mlx4_port_info
,
1025 struct mlx4_dev
*mdev
= info
->dev
;
1026 struct mlx4_priv
*priv
= mlx4_priv(mdev
);
1027 int err
, port
, mtu
, ibta_mtu
= -1;
1029 if (mdev
->caps
.port_type
[info
->port
] == MLX4_PORT_TYPE_ETH
) {
1030 mlx4_warn(mdev
, "port level mtu is only used for IB ports\n");
1034 err
= kstrtoint(buf
, 0, &mtu
);
1036 ibta_mtu
= int_to_ibta_mtu(mtu
);
1038 if (err
|| ibta_mtu
< 0) {
1039 mlx4_err(mdev
, "%s is invalid IBTA mtu\n", buf
);
1043 mdev
->caps
.port_ib_mtu
[info
->port
] = ibta_mtu
;
1045 mlx4_stop_sense(mdev
);
1046 mutex_lock(&priv
->port_mutex
);
1047 mlx4_unregister_device(mdev
);
1048 for (port
= 1; port
<= mdev
->caps
.num_ports
; port
++) {
1049 mlx4_CLOSE_PORT(mdev
, port
);
1050 err
= mlx4_SET_PORT(mdev
, port
, -1);
1052 mlx4_err(mdev
, "Failed to set port %d, aborting\n",
1057 err
= mlx4_register_device(mdev
);
1059 mutex_unlock(&priv
->port_mutex
);
1060 mlx4_start_sense(mdev
);
1061 return err
? err
: count
;
1064 static int mlx4_load_fw(struct mlx4_dev
*dev
)
1066 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1069 priv
->fw
.fw_icm
= mlx4_alloc_icm(dev
, priv
->fw
.fw_pages
,
1070 GFP_HIGHUSER
| __GFP_NOWARN
, 0);
1071 if (!priv
->fw
.fw_icm
) {
1072 mlx4_err(dev
, "Couldn't allocate FW area, aborting\n");
1076 err
= mlx4_MAP_FA(dev
, priv
->fw
.fw_icm
);
1078 mlx4_err(dev
, "MAP_FA command failed, aborting\n");
1082 err
= mlx4_RUN_FW(dev
);
1084 mlx4_err(dev
, "RUN_FW command failed, aborting\n");
1094 mlx4_free_icm(dev
, priv
->fw
.fw_icm
, 0);
1098 static int mlx4_init_cmpt_table(struct mlx4_dev
*dev
, u64 cmpt_base
,
1101 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1105 err
= mlx4_init_icm_table(dev
, &priv
->qp_table
.cmpt_table
,
1107 ((u64
) (MLX4_CMPT_TYPE_QP
*
1108 cmpt_entry_sz
) << MLX4_CMPT_SHIFT
),
1109 cmpt_entry_sz
, dev
->caps
.num_qps
,
1110 dev
->caps
.reserved_qps_cnt
[MLX4_QP_REGION_FW
],
1115 err
= mlx4_init_icm_table(dev
, &priv
->srq_table
.cmpt_table
,
1117 ((u64
) (MLX4_CMPT_TYPE_SRQ
*
1118 cmpt_entry_sz
) << MLX4_CMPT_SHIFT
),
1119 cmpt_entry_sz
, dev
->caps
.num_srqs
,
1120 dev
->caps
.reserved_srqs
, 0, 0);
1124 err
= mlx4_init_icm_table(dev
, &priv
->cq_table
.cmpt_table
,
1126 ((u64
) (MLX4_CMPT_TYPE_CQ
*
1127 cmpt_entry_sz
) << MLX4_CMPT_SHIFT
),
1128 cmpt_entry_sz
, dev
->caps
.num_cqs
,
1129 dev
->caps
.reserved_cqs
, 0, 0);
1133 num_eqs
= (mlx4_is_master(dev
)) ? dev
->phys_caps
.num_phys_eqs
:
1135 err
= mlx4_init_icm_table(dev
, &priv
->eq_table
.cmpt_table
,
1137 ((u64
) (MLX4_CMPT_TYPE_EQ
*
1138 cmpt_entry_sz
) << MLX4_CMPT_SHIFT
),
1139 cmpt_entry_sz
, num_eqs
, num_eqs
, 0, 0);
1146 mlx4_cleanup_icm_table(dev
, &priv
->cq_table
.cmpt_table
);
1149 mlx4_cleanup_icm_table(dev
, &priv
->srq_table
.cmpt_table
);
1152 mlx4_cleanup_icm_table(dev
, &priv
->qp_table
.cmpt_table
);
1158 static int mlx4_init_icm(struct mlx4_dev
*dev
, struct mlx4_dev_cap
*dev_cap
,
1159 struct mlx4_init_hca_param
*init_hca
, u64 icm_size
)
1161 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1166 err
= mlx4_SET_ICM_SIZE(dev
, icm_size
, &aux_pages
);
1168 mlx4_err(dev
, "SET_ICM_SIZE command failed, aborting\n");
1172 mlx4_dbg(dev
, "%lld KB of HCA context requires %lld KB aux memory\n",
1173 (unsigned long long) icm_size
>> 10,
1174 (unsigned long long) aux_pages
<< 2);
1176 priv
->fw
.aux_icm
= mlx4_alloc_icm(dev
, aux_pages
,
1177 GFP_HIGHUSER
| __GFP_NOWARN
, 0);
1178 if (!priv
->fw
.aux_icm
) {
1179 mlx4_err(dev
, "Couldn't allocate aux memory, aborting\n");
1183 err
= mlx4_MAP_ICM_AUX(dev
, priv
->fw
.aux_icm
);
1185 mlx4_err(dev
, "MAP_ICM_AUX command failed, aborting\n");
1189 err
= mlx4_init_cmpt_table(dev
, init_hca
->cmpt_base
, dev_cap
->cmpt_entry_sz
);
1191 mlx4_err(dev
, "Failed to map cMPT context memory, aborting\n");
1196 num_eqs
= (mlx4_is_master(dev
)) ? dev
->phys_caps
.num_phys_eqs
:
1198 err
= mlx4_init_icm_table(dev
, &priv
->eq_table
.table
,
1199 init_hca
->eqc_base
, dev_cap
->eqc_entry_sz
,
1200 num_eqs
, num_eqs
, 0, 0);
1202 mlx4_err(dev
, "Failed to map EQ context memory, aborting\n");
1203 goto err_unmap_cmpt
;
1207 * Reserved MTT entries must be aligned up to a cacheline
1208 * boundary, since the FW will write to them, while the driver
1209 * writes to all other MTT entries. (The variable
1210 * dev->caps.mtt_entry_sz below is really the MTT segment
1211 * size, not the raw entry size)
1213 dev
->caps
.reserved_mtts
=
1214 ALIGN(dev
->caps
.reserved_mtts
* dev
->caps
.mtt_entry_sz
,
1215 dma_get_cache_alignment()) / dev
->caps
.mtt_entry_sz
;
1217 err
= mlx4_init_icm_table(dev
, &priv
->mr_table
.mtt_table
,
1219 dev
->caps
.mtt_entry_sz
,
1221 dev
->caps
.reserved_mtts
, 1, 0);
1223 mlx4_err(dev
, "Failed to map MTT context memory, aborting\n");
1227 err
= mlx4_init_icm_table(dev
, &priv
->mr_table
.dmpt_table
,
1228 init_hca
->dmpt_base
,
1229 dev_cap
->dmpt_entry_sz
,
1231 dev
->caps
.reserved_mrws
, 1, 1);
1233 mlx4_err(dev
, "Failed to map dMPT context memory, aborting\n");
1237 err
= mlx4_init_icm_table(dev
, &priv
->qp_table
.qp_table
,
1239 dev_cap
->qpc_entry_sz
,
1241 dev
->caps
.reserved_qps_cnt
[MLX4_QP_REGION_FW
],
1244 mlx4_err(dev
, "Failed to map QP context memory, aborting\n");
1245 goto err_unmap_dmpt
;
1248 err
= mlx4_init_icm_table(dev
, &priv
->qp_table
.auxc_table
,
1249 init_hca
->auxc_base
,
1250 dev_cap
->aux_entry_sz
,
1252 dev
->caps
.reserved_qps_cnt
[MLX4_QP_REGION_FW
],
1255 mlx4_err(dev
, "Failed to map AUXC context memory, aborting\n");
1259 err
= mlx4_init_icm_table(dev
, &priv
->qp_table
.altc_table
,
1260 init_hca
->altc_base
,
1261 dev_cap
->altc_entry_sz
,
1263 dev
->caps
.reserved_qps_cnt
[MLX4_QP_REGION_FW
],
1266 mlx4_err(dev
, "Failed to map ALTC context memory, aborting\n");
1267 goto err_unmap_auxc
;
1270 err
= mlx4_init_icm_table(dev
, &priv
->qp_table
.rdmarc_table
,
1271 init_hca
->rdmarc_base
,
1272 dev_cap
->rdmarc_entry_sz
<< priv
->qp_table
.rdmarc_shift
,
1274 dev
->caps
.reserved_qps_cnt
[MLX4_QP_REGION_FW
],
1277 mlx4_err(dev
, "Failed to map RDMARC context memory, aborting\n");
1278 goto err_unmap_altc
;
1281 err
= mlx4_init_icm_table(dev
, &priv
->cq_table
.table
,
1283 dev_cap
->cqc_entry_sz
,
1285 dev
->caps
.reserved_cqs
, 0, 0);
1287 mlx4_err(dev
, "Failed to map CQ context memory, aborting\n");
1288 goto err_unmap_rdmarc
;
1291 err
= mlx4_init_icm_table(dev
, &priv
->srq_table
.table
,
1292 init_hca
->srqc_base
,
1293 dev_cap
->srq_entry_sz
,
1295 dev
->caps
.reserved_srqs
, 0, 0);
1297 mlx4_err(dev
, "Failed to map SRQ context memory, aborting\n");
1302 * For flow steering device managed mode it is required to use
1303 * mlx4_init_icm_table. For B0 steering mode it's not strictly
1304 * required, but for simplicity just map the whole multicast
1305 * group table now. The table isn't very big and it's a lot
1306 * easier than trying to track ref counts.
1308 err
= mlx4_init_icm_table(dev
, &priv
->mcg_table
.table
,
1310 mlx4_get_mgm_entry_size(dev
),
1311 dev
->caps
.num_mgms
+ dev
->caps
.num_amgms
,
1312 dev
->caps
.num_mgms
+ dev
->caps
.num_amgms
,
1315 mlx4_err(dev
, "Failed to map MCG context memory, aborting\n");
1322 mlx4_cleanup_icm_table(dev
, &priv
->srq_table
.table
);
1325 mlx4_cleanup_icm_table(dev
, &priv
->cq_table
.table
);
1328 mlx4_cleanup_icm_table(dev
, &priv
->qp_table
.rdmarc_table
);
1331 mlx4_cleanup_icm_table(dev
, &priv
->qp_table
.altc_table
);
1334 mlx4_cleanup_icm_table(dev
, &priv
->qp_table
.auxc_table
);
1337 mlx4_cleanup_icm_table(dev
, &priv
->qp_table
.qp_table
);
1340 mlx4_cleanup_icm_table(dev
, &priv
->mr_table
.dmpt_table
);
1343 mlx4_cleanup_icm_table(dev
, &priv
->mr_table
.mtt_table
);
1346 mlx4_cleanup_icm_table(dev
, &priv
->eq_table
.table
);
1349 mlx4_cleanup_icm_table(dev
, &priv
->eq_table
.cmpt_table
);
1350 mlx4_cleanup_icm_table(dev
, &priv
->cq_table
.cmpt_table
);
1351 mlx4_cleanup_icm_table(dev
, &priv
->srq_table
.cmpt_table
);
1352 mlx4_cleanup_icm_table(dev
, &priv
->qp_table
.cmpt_table
);
1355 mlx4_UNMAP_ICM_AUX(dev
);
1358 mlx4_free_icm(dev
, priv
->fw
.aux_icm
, 0);
1363 static void mlx4_free_icms(struct mlx4_dev
*dev
)
1365 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1367 mlx4_cleanup_icm_table(dev
, &priv
->mcg_table
.table
);
1368 mlx4_cleanup_icm_table(dev
, &priv
->srq_table
.table
);
1369 mlx4_cleanup_icm_table(dev
, &priv
->cq_table
.table
);
1370 mlx4_cleanup_icm_table(dev
, &priv
->qp_table
.rdmarc_table
);
1371 mlx4_cleanup_icm_table(dev
, &priv
->qp_table
.altc_table
);
1372 mlx4_cleanup_icm_table(dev
, &priv
->qp_table
.auxc_table
);
1373 mlx4_cleanup_icm_table(dev
, &priv
->qp_table
.qp_table
);
1374 mlx4_cleanup_icm_table(dev
, &priv
->mr_table
.dmpt_table
);
1375 mlx4_cleanup_icm_table(dev
, &priv
->mr_table
.mtt_table
);
1376 mlx4_cleanup_icm_table(dev
, &priv
->eq_table
.table
);
1377 mlx4_cleanup_icm_table(dev
, &priv
->eq_table
.cmpt_table
);
1378 mlx4_cleanup_icm_table(dev
, &priv
->cq_table
.cmpt_table
);
1379 mlx4_cleanup_icm_table(dev
, &priv
->srq_table
.cmpt_table
);
1380 mlx4_cleanup_icm_table(dev
, &priv
->qp_table
.cmpt_table
);
1382 mlx4_UNMAP_ICM_AUX(dev
);
1383 mlx4_free_icm(dev
, priv
->fw
.aux_icm
, 0);
1386 static void mlx4_slave_exit(struct mlx4_dev
*dev
)
1388 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1390 mutex_lock(&priv
->cmd
.slave_cmd_mutex
);
1391 if (mlx4_comm_cmd(dev
, MLX4_COMM_CMD_RESET
, 0, MLX4_COMM_TIME
))
1392 mlx4_warn(dev
, "Failed to close slave function\n");
1393 mutex_unlock(&priv
->cmd
.slave_cmd_mutex
);
1396 static int map_bf_area(struct mlx4_dev
*dev
)
1398 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1399 resource_size_t bf_start
;
1400 resource_size_t bf_len
;
1403 if (!dev
->caps
.bf_reg_size
)
1406 bf_start
= pci_resource_start(dev
->pdev
, 2) +
1407 (dev
->caps
.num_uars
<< PAGE_SHIFT
);
1408 bf_len
= pci_resource_len(dev
->pdev
, 2) -
1409 (dev
->caps
.num_uars
<< PAGE_SHIFT
);
1410 priv
->bf_mapping
= io_mapping_create_wc(bf_start
, bf_len
);
1411 if (!priv
->bf_mapping
)
1417 static void unmap_bf_area(struct mlx4_dev
*dev
)
1419 if (mlx4_priv(dev
)->bf_mapping
)
1420 io_mapping_free(mlx4_priv(dev
)->bf_mapping
);
1423 cycle_t
mlx4_read_clock(struct mlx4_dev
*dev
)
1425 u32 clockhi
, clocklo
, clockhi1
;
1428 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1430 for (i
= 0; i
< 10; i
++) {
1431 clockhi
= swab32(readl(priv
->clock_mapping
));
1432 clocklo
= swab32(readl(priv
->clock_mapping
+ 4));
1433 clockhi1
= swab32(readl(priv
->clock_mapping
));
1434 if (clockhi
== clockhi1
)
1438 cycles
= (u64
) clockhi
<< 32 | (u64
) clocklo
;
1442 EXPORT_SYMBOL_GPL(mlx4_read_clock
);
1445 static int map_internal_clock(struct mlx4_dev
*dev
)
1447 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1449 priv
->clock_mapping
=
1450 ioremap(pci_resource_start(dev
->pdev
, priv
->fw
.clock_bar
) +
1451 priv
->fw
.clock_offset
, MLX4_CLOCK_SIZE
);
1453 if (!priv
->clock_mapping
)
1459 static void unmap_internal_clock(struct mlx4_dev
*dev
)
1461 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1463 if (priv
->clock_mapping
)
1464 iounmap(priv
->clock_mapping
);
1467 static void mlx4_close_hca(struct mlx4_dev
*dev
)
1469 unmap_internal_clock(dev
);
1471 if (mlx4_is_slave(dev
))
1472 mlx4_slave_exit(dev
);
1474 mlx4_CLOSE_HCA(dev
, 0);
1475 mlx4_free_icms(dev
);
1477 mlx4_free_icm(dev
, mlx4_priv(dev
)->fw
.fw_icm
, 0);
1481 static int mlx4_init_slave(struct mlx4_dev
*dev
)
1483 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1484 u64 dma
= (u64
) priv
->mfunc
.vhcr_dma
;
1485 int ret_from_reset
= 0;
1487 u32 cmd_channel_ver
;
1489 if (atomic_read(&pf_loading
)) {
1490 mlx4_warn(dev
, "PF is not ready - Deferring probe\n");
1491 return -EPROBE_DEFER
;
1494 mutex_lock(&priv
->cmd
.slave_cmd_mutex
);
1495 priv
->cmd
.max_cmds
= 1;
1496 mlx4_warn(dev
, "Sending reset\n");
1497 ret_from_reset
= mlx4_comm_cmd(dev
, MLX4_COMM_CMD_RESET
, 0,
1499 /* if we are in the middle of flr the slave will try
1500 * NUM_OF_RESET_RETRIES times before leaving.*/
1501 if (ret_from_reset
) {
1502 if (MLX4_DELAY_RESET_SLAVE
== ret_from_reset
) {
1503 mlx4_warn(dev
, "slave is currently in the middle of FLR - Deferring probe\n");
1504 mutex_unlock(&priv
->cmd
.slave_cmd_mutex
);
1505 return -EPROBE_DEFER
;
1510 /* check the driver version - the slave I/F revision
1511 * must match the master's */
1512 slave_read
= swab32(readl(&priv
->mfunc
.comm
->slave_read
));
1513 cmd_channel_ver
= mlx4_comm_get_version();
1515 if (MLX4_COMM_GET_IF_REV(cmd_channel_ver
) !=
1516 MLX4_COMM_GET_IF_REV(slave_read
)) {
1517 mlx4_err(dev
, "slave driver version is not supported by the master\n");
1521 mlx4_warn(dev
, "Sending vhcr0\n");
1522 if (mlx4_comm_cmd(dev
, MLX4_COMM_CMD_VHCR0
, dma
>> 48,
1525 if (mlx4_comm_cmd(dev
, MLX4_COMM_CMD_VHCR1
, dma
>> 32,
1528 if (mlx4_comm_cmd(dev
, MLX4_COMM_CMD_VHCR2
, dma
>> 16,
1531 if (mlx4_comm_cmd(dev
, MLX4_COMM_CMD_VHCR_EN
, dma
, MLX4_COMM_TIME
))
1534 mutex_unlock(&priv
->cmd
.slave_cmd_mutex
);
1538 mlx4_comm_cmd(dev
, MLX4_COMM_CMD_RESET
, 0, 0);
1539 mutex_unlock(&priv
->cmd
.slave_cmd_mutex
);
1543 static void mlx4_parav_master_pf_caps(struct mlx4_dev
*dev
)
1547 for (i
= 1; i
<= dev
->caps
.num_ports
; i
++) {
1548 if (dev
->caps
.port_type
[i
] == MLX4_PORT_TYPE_ETH
)
1549 dev
->caps
.gid_table_len
[i
] =
1550 mlx4_get_slave_num_gids(dev
, 0, i
);
1552 dev
->caps
.gid_table_len
[i
] = 1;
1553 dev
->caps
.pkey_table_len
[i
] =
1554 dev
->phys_caps
.pkey_phys_table_len
[i
] - 1;
1558 static int choose_log_fs_mgm_entry_size(int qp_per_entry
)
1560 int i
= MLX4_MIN_MGM_LOG_ENTRY_SIZE
;
1562 for (i
= MLX4_MIN_MGM_LOG_ENTRY_SIZE
; i
<= MLX4_MAX_MGM_LOG_ENTRY_SIZE
;
1564 if (qp_per_entry
<= 4 * ((1 << i
) / 16 - 2))
1568 return (i
<= MLX4_MAX_MGM_LOG_ENTRY_SIZE
) ? i
: -1;
1571 static void choose_steering_mode(struct mlx4_dev
*dev
,
1572 struct mlx4_dev_cap
*dev_cap
)
1574 if (mlx4_log_num_mgm_entry_size
== -1 &&
1575 dev_cap
->flags2
& MLX4_DEV_CAP_FLAG2_FS_EN
&&
1576 (!mlx4_is_mfunc(dev
) ||
1577 (dev_cap
->fs_max_num_qp_per_entry
>= (dev
->num_vfs
+ 1))) &&
1578 choose_log_fs_mgm_entry_size(dev_cap
->fs_max_num_qp_per_entry
) >=
1579 MLX4_MIN_MGM_LOG_ENTRY_SIZE
) {
1580 dev
->oper_log_mgm_entry_size
=
1581 choose_log_fs_mgm_entry_size(dev_cap
->fs_max_num_qp_per_entry
);
1582 dev
->caps
.steering_mode
= MLX4_STEERING_MODE_DEVICE_MANAGED
;
1583 dev
->caps
.num_qp_per_mgm
= dev_cap
->fs_max_num_qp_per_entry
;
1584 dev
->caps
.fs_log_max_ucast_qp_range_size
=
1585 dev_cap
->fs_log_max_ucast_qp_range_size
;
1587 if (dev
->caps
.flags
& MLX4_DEV_CAP_FLAG_VEP_UC_STEER
&&
1588 dev
->caps
.flags
& MLX4_DEV_CAP_FLAG_VEP_MC_STEER
)
1589 dev
->caps
.steering_mode
= MLX4_STEERING_MODE_B0
;
1591 dev
->caps
.steering_mode
= MLX4_STEERING_MODE_A0
;
1593 if (dev
->caps
.flags
& MLX4_DEV_CAP_FLAG_VEP_UC_STEER
||
1594 dev
->caps
.flags
& MLX4_DEV_CAP_FLAG_VEP_MC_STEER
)
1595 mlx4_warn(dev
, "Must have both UC_STEER and MC_STEER flags set to use B0 steering - falling back to A0 steering mode\n");
1597 dev
->oper_log_mgm_entry_size
=
1598 mlx4_log_num_mgm_entry_size
> 0 ?
1599 mlx4_log_num_mgm_entry_size
:
1600 MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE
;
1601 dev
->caps
.num_qp_per_mgm
= mlx4_get_qp_per_mgm(dev
);
1603 mlx4_dbg(dev
, "Steering mode is: %s, oper_log_mgm_entry_size = %d, modparam log_num_mgm_entry_size = %d\n",
1604 mlx4_steering_mode_str(dev
->caps
.steering_mode
),
1605 dev
->oper_log_mgm_entry_size
,
1606 mlx4_log_num_mgm_entry_size
);
1609 static void choose_tunnel_offload_mode(struct mlx4_dev
*dev
,
1610 struct mlx4_dev_cap
*dev_cap
)
1612 if (dev
->caps
.steering_mode
== MLX4_STEERING_MODE_DEVICE_MANAGED
&&
1613 dev_cap
->flags2
& MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS
)
1614 dev
->caps
.tunnel_offload_mode
= MLX4_TUNNEL_OFFLOAD_MODE_VXLAN
;
1616 dev
->caps
.tunnel_offload_mode
= MLX4_TUNNEL_OFFLOAD_MODE_NONE
;
1618 mlx4_dbg(dev
, "Tunneling offload mode is: %s\n", (dev
->caps
.tunnel_offload_mode
1619 == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN
) ? "vxlan" : "none");
1622 static int mlx4_init_hca(struct mlx4_dev
*dev
)
1624 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1625 struct mlx4_adapter adapter
;
1626 struct mlx4_dev_cap dev_cap
;
1627 struct mlx4_mod_stat_cfg mlx4_cfg
;
1628 struct mlx4_profile profile
;
1629 struct mlx4_init_hca_param init_hca
;
1633 if (!mlx4_is_slave(dev
)) {
1634 err
= mlx4_QUERY_FW(dev
);
1637 mlx4_info(dev
, "non-primary physical function, skipping\n");
1639 mlx4_err(dev
, "QUERY_FW command failed, aborting\n");
1643 err
= mlx4_load_fw(dev
);
1645 mlx4_err(dev
, "Failed to start FW, aborting\n");
1649 mlx4_cfg
.log_pg_sz_m
= 1;
1650 mlx4_cfg
.log_pg_sz
= 0;
1651 err
= mlx4_MOD_STAT_CFG(dev
, &mlx4_cfg
);
1653 mlx4_warn(dev
, "Failed to override log_pg_sz parameter\n");
1655 err
= mlx4_dev_cap(dev
, &dev_cap
);
1657 mlx4_err(dev
, "QUERY_DEV_CAP command failed, aborting\n");
1661 choose_steering_mode(dev
, &dev_cap
);
1662 choose_tunnel_offload_mode(dev
, &dev_cap
);
1664 err
= mlx4_get_phys_port_id(dev
);
1666 mlx4_err(dev
, "Fail to get physical port id\n");
1668 if (mlx4_is_master(dev
))
1669 mlx4_parav_master_pf_caps(dev
);
1671 if (mlx4_low_memory_profile()) {
1672 mlx4_info(dev
, "Running from within kdump kernel. Using low memory profile\n");
1673 profile
= low_mem_profile
;
1675 profile
= default_profile
;
1677 if (dev
->caps
.steering_mode
==
1678 MLX4_STEERING_MODE_DEVICE_MANAGED
)
1679 profile
.num_mcg
= MLX4_FS_NUM_MCG
;
1681 icm_size
= mlx4_make_profile(dev
, &profile
, &dev_cap
,
1683 if ((long long) icm_size
< 0) {
1688 dev
->caps
.max_fmr_maps
= (1 << (32 - ilog2(dev
->caps
.num_mpts
))) - 1;
1690 init_hca
.log_uar_sz
= ilog2(dev
->caps
.num_uars
);
1691 init_hca
.uar_page_sz
= PAGE_SHIFT
- 12;
1692 init_hca
.mw_enabled
= 0;
1693 if (dev
->caps
.flags
& MLX4_DEV_CAP_FLAG_MEM_WINDOW
||
1694 dev
->caps
.bmme_flags
& MLX4_BMME_FLAG_TYPE_2_WIN
)
1695 init_hca
.mw_enabled
= INIT_HCA_TPT_MW_ENABLE
;
1697 err
= mlx4_init_icm(dev
, &dev_cap
, &init_hca
, icm_size
);
1701 err
= mlx4_INIT_HCA(dev
, &init_hca
);
1703 mlx4_err(dev
, "INIT_HCA command failed, aborting\n");
1707 * If TS is supported by FW
1708 * read HCA frequency by QUERY_HCA command
1710 if (dev
->caps
.flags2
& MLX4_DEV_CAP_FLAG2_TS
) {
1711 memset(&init_hca
, 0, sizeof(init_hca
));
1712 err
= mlx4_QUERY_HCA(dev
, &init_hca
);
1714 mlx4_err(dev
, "QUERY_HCA command failed, disable timestamp\n");
1715 dev
->caps
.flags2
&= ~MLX4_DEV_CAP_FLAG2_TS
;
1717 dev
->caps
.hca_core_clock
=
1718 init_hca
.hca_core_clock
;
1721 /* In case we got HCA frequency 0 - disable timestamping
1722 * to avoid dividing by zero
1724 if (!dev
->caps
.hca_core_clock
) {
1725 dev
->caps
.flags2
&= ~MLX4_DEV_CAP_FLAG2_TS
;
1727 "HCA frequency is 0 - timestamping is not supported\n");
1728 } else if (map_internal_clock(dev
)) {
1730 * Map internal clock,
1731 * in case of failure disable timestamping
1733 dev
->caps
.flags2
&= ~MLX4_DEV_CAP_FLAG2_TS
;
1734 mlx4_err(dev
, "Failed to map internal clock. Timestamping is not supported\n");
1738 err
= mlx4_init_slave(dev
);
1740 if (err
!= -EPROBE_DEFER
)
1741 mlx4_err(dev
, "Failed to initialize slave\n");
1745 err
= mlx4_slave_cap(dev
);
1747 mlx4_err(dev
, "Failed to obtain slave caps\n");
1752 if (map_bf_area(dev
))
1753 mlx4_dbg(dev
, "Failed to map blue flame area\n");
1755 /*Only the master set the ports, all the rest got it from it.*/
1756 if (!mlx4_is_slave(dev
))
1757 mlx4_set_port_mask(dev
);
1759 err
= mlx4_QUERY_ADAPTER(dev
, &adapter
);
1761 mlx4_err(dev
, "QUERY_ADAPTER command failed, aborting\n");
1765 priv
->eq_table
.inta_pin
= adapter
.inta_pin
;
1766 memcpy(dev
->board_id
, adapter
.board_id
, sizeof dev
->board_id
);
1771 unmap_internal_clock(dev
);
1774 if (mlx4_is_slave(dev
)) {
1775 kfree(dev
->caps
.qp0_qkey
);
1776 kfree(dev
->caps
.qp0_tunnel
);
1777 kfree(dev
->caps
.qp0_proxy
);
1778 kfree(dev
->caps
.qp1_tunnel
);
1779 kfree(dev
->caps
.qp1_proxy
);
1783 if (mlx4_is_slave(dev
))
1784 mlx4_slave_exit(dev
);
1786 mlx4_CLOSE_HCA(dev
, 0);
1789 if (!mlx4_is_slave(dev
))
1790 mlx4_free_icms(dev
);
1793 if (!mlx4_is_slave(dev
)) {
1795 mlx4_free_icm(dev
, priv
->fw
.fw_icm
, 0);
1800 static int mlx4_init_counters_table(struct mlx4_dev
*dev
)
1802 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1805 if (!(dev
->caps
.flags
& MLX4_DEV_CAP_FLAG_COUNTERS
))
1808 nent
= dev
->caps
.max_counters
;
1809 return mlx4_bitmap_init(&priv
->counters_bitmap
, nent
, nent
- 1, 0, 0);
1812 static void mlx4_cleanup_counters_table(struct mlx4_dev
*dev
)
1814 mlx4_bitmap_cleanup(&mlx4_priv(dev
)->counters_bitmap
);
1817 int __mlx4_counter_alloc(struct mlx4_dev
*dev
, u32
*idx
)
1819 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1821 if (!(dev
->caps
.flags
& MLX4_DEV_CAP_FLAG_COUNTERS
))
1824 *idx
= mlx4_bitmap_alloc(&priv
->counters_bitmap
);
1831 int mlx4_counter_alloc(struct mlx4_dev
*dev
, u32
*idx
)
1836 if (mlx4_is_mfunc(dev
)) {
1837 err
= mlx4_cmd_imm(dev
, 0, &out_param
, RES_COUNTER
,
1838 RES_OP_RESERVE
, MLX4_CMD_ALLOC_RES
,
1839 MLX4_CMD_TIME_CLASS_A
, MLX4_CMD_WRAPPED
);
1841 *idx
= get_param_l(&out_param
);
1845 return __mlx4_counter_alloc(dev
, idx
);
1847 EXPORT_SYMBOL_GPL(mlx4_counter_alloc
);
1849 void __mlx4_counter_free(struct mlx4_dev
*dev
, u32 idx
)
1851 mlx4_bitmap_free(&mlx4_priv(dev
)->counters_bitmap
, idx
, MLX4_USE_RR
);
1855 void mlx4_counter_free(struct mlx4_dev
*dev
, u32 idx
)
1859 if (mlx4_is_mfunc(dev
)) {
1860 set_param_l(&in_param
, idx
);
1861 mlx4_cmd(dev
, in_param
, RES_COUNTER
, RES_OP_RESERVE
,
1862 MLX4_CMD_FREE_RES
, MLX4_CMD_TIME_CLASS_A
,
1866 __mlx4_counter_free(dev
, idx
);
1868 EXPORT_SYMBOL_GPL(mlx4_counter_free
);
1870 static int mlx4_setup_hca(struct mlx4_dev
*dev
)
1872 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1875 __be32 ib_port_default_caps
;
1877 err
= mlx4_init_uar_table(dev
);
1879 mlx4_err(dev
, "Failed to initialize user access region table, aborting\n");
1883 err
= mlx4_uar_alloc(dev
, &priv
->driver_uar
);
1885 mlx4_err(dev
, "Failed to allocate driver access region, aborting\n");
1886 goto err_uar_table_free
;
1889 priv
->kar
= ioremap((phys_addr_t
) priv
->driver_uar
.pfn
<< PAGE_SHIFT
, PAGE_SIZE
);
1891 mlx4_err(dev
, "Couldn't map kernel access region, aborting\n");
1896 err
= mlx4_init_pd_table(dev
);
1898 mlx4_err(dev
, "Failed to initialize protection domain table, aborting\n");
1902 err
= mlx4_init_xrcd_table(dev
);
1904 mlx4_err(dev
, "Failed to initialize reliable connection domain table, aborting\n");
1905 goto err_pd_table_free
;
1908 err
= mlx4_init_mr_table(dev
);
1910 mlx4_err(dev
, "Failed to initialize memory region table, aborting\n");
1911 goto err_xrcd_table_free
;
1914 if (!mlx4_is_slave(dev
)) {
1915 err
= mlx4_init_mcg_table(dev
);
1917 mlx4_err(dev
, "Failed to initialize multicast group table, aborting\n");
1918 goto err_mr_table_free
;
1920 err
= mlx4_config_mad_demux(dev
);
1922 mlx4_err(dev
, "Failed in config_mad_demux, aborting\n");
1923 goto err_mcg_table_free
;
1927 err
= mlx4_init_eq_table(dev
);
1929 mlx4_err(dev
, "Failed to initialize event queue table, aborting\n");
1930 goto err_mcg_table_free
;
1933 err
= mlx4_cmd_use_events(dev
);
1935 mlx4_err(dev
, "Failed to switch to event-driven firmware commands, aborting\n");
1936 goto err_eq_table_free
;
1939 err
= mlx4_NOP(dev
);
1941 if (dev
->flags
& MLX4_FLAG_MSI_X
) {
1942 mlx4_warn(dev
, "NOP command failed to generate MSI-X interrupt IRQ %d)\n",
1943 priv
->eq_table
.eq
[dev
->caps
.num_comp_vectors
].irq
);
1944 mlx4_warn(dev
, "Trying again without MSI-X\n");
1946 mlx4_err(dev
, "NOP command failed to generate interrupt (IRQ %d), aborting\n",
1947 priv
->eq_table
.eq
[dev
->caps
.num_comp_vectors
].irq
);
1948 mlx4_err(dev
, "BIOS or ACPI interrupt routing problem?\n");
1954 mlx4_dbg(dev
, "NOP command IRQ test passed\n");
1956 err
= mlx4_init_cq_table(dev
);
1958 mlx4_err(dev
, "Failed to initialize completion queue table, aborting\n");
1962 err
= mlx4_init_srq_table(dev
);
1964 mlx4_err(dev
, "Failed to initialize shared receive queue table, aborting\n");
1965 goto err_cq_table_free
;
1968 err
= mlx4_init_qp_table(dev
);
1970 mlx4_err(dev
, "Failed to initialize queue pair table, aborting\n");
1971 goto err_srq_table_free
;
1974 err
= mlx4_init_counters_table(dev
);
1975 if (err
&& err
!= -ENOENT
) {
1976 mlx4_err(dev
, "Failed to initialize counters table, aborting\n");
1977 goto err_qp_table_free
;
1980 if (!mlx4_is_slave(dev
)) {
1981 for (port
= 1; port
<= dev
->caps
.num_ports
; port
++) {
1982 ib_port_default_caps
= 0;
1983 err
= mlx4_get_port_ib_caps(dev
, port
,
1984 &ib_port_default_caps
);
1986 mlx4_warn(dev
, "failed to get port %d default ib capabilities (%d). Continuing with caps = 0\n",
1988 dev
->caps
.ib_port_def_cap
[port
] = ib_port_default_caps
;
1990 /* initialize per-slave default ib port capabilities */
1991 if (mlx4_is_master(dev
)) {
1993 for (i
= 0; i
< dev
->num_slaves
; i
++) {
1994 if (i
== mlx4_master_func_num(dev
))
1996 priv
->mfunc
.master
.slave_state
[i
].ib_cap_mask
[port
] =
1997 ib_port_default_caps
;
2001 if (mlx4_is_mfunc(dev
))
2002 dev
->caps
.port_ib_mtu
[port
] = IB_MTU_2048
;
2004 dev
->caps
.port_ib_mtu
[port
] = IB_MTU_4096
;
2006 err
= mlx4_SET_PORT(dev
, port
, mlx4_is_master(dev
) ?
2007 dev
->caps
.pkey_table_len
[port
] : -1);
2009 mlx4_err(dev
, "Failed to set port %d, aborting\n",
2011 goto err_counters_table_free
;
2018 err_counters_table_free
:
2019 mlx4_cleanup_counters_table(dev
);
2022 mlx4_cleanup_qp_table(dev
);
2025 mlx4_cleanup_srq_table(dev
);
2028 mlx4_cleanup_cq_table(dev
);
2031 mlx4_cmd_use_polling(dev
);
2034 mlx4_cleanup_eq_table(dev
);
2037 if (!mlx4_is_slave(dev
))
2038 mlx4_cleanup_mcg_table(dev
);
2041 mlx4_cleanup_mr_table(dev
);
2043 err_xrcd_table_free
:
2044 mlx4_cleanup_xrcd_table(dev
);
2047 mlx4_cleanup_pd_table(dev
);
2053 mlx4_uar_free(dev
, &priv
->driver_uar
);
2056 mlx4_cleanup_uar_table(dev
);
2060 static void mlx4_enable_msi_x(struct mlx4_dev
*dev
)
2062 struct mlx4_priv
*priv
= mlx4_priv(dev
);
2063 struct msix_entry
*entries
;
2064 int nreq
= min_t(int, dev
->caps
.num_ports
*
2065 min_t(int, num_online_cpus() + 1,
2066 MAX_MSIX_P_PORT
) + MSIX_LEGACY_SZ
, MAX_MSIX
);
2070 nreq
= min_t(int, dev
->caps
.num_eqs
- dev
->caps
.reserved_eqs
,
2073 entries
= kcalloc(nreq
, sizeof *entries
, GFP_KERNEL
);
2077 for (i
= 0; i
< nreq
; ++i
)
2078 entries
[i
].entry
= i
;
2080 nreq
= pci_enable_msix_range(dev
->pdev
, entries
, 2, nreq
);
2085 } else if (nreq
< MSIX_LEGACY_SZ
+
2086 dev
->caps
.num_ports
* MIN_MSIX_P_PORT
) {
2087 /*Working in legacy mode , all EQ's shared*/
2088 dev
->caps
.comp_pool
= 0;
2089 dev
->caps
.num_comp_vectors
= nreq
- 1;
2091 dev
->caps
.comp_pool
= nreq
- MSIX_LEGACY_SZ
;
2092 dev
->caps
.num_comp_vectors
= MSIX_LEGACY_SZ
- 1;
2094 for (i
= 0; i
< nreq
; ++i
)
2095 priv
->eq_table
.eq
[i
].irq
= entries
[i
].vector
;
2097 dev
->flags
|= MLX4_FLAG_MSI_X
;
2104 dev
->caps
.num_comp_vectors
= 1;
2105 dev
->caps
.comp_pool
= 0;
2107 for (i
= 0; i
< 2; ++i
)
2108 priv
->eq_table
.eq
[i
].irq
= dev
->pdev
->irq
;
2111 static int mlx4_init_port_info(struct mlx4_dev
*dev
, int port
)
2113 struct mlx4_port_info
*info
= &mlx4_priv(dev
)->port
[port
];
2118 if (!mlx4_is_slave(dev
)) {
2119 mlx4_init_mac_table(dev
, &info
->mac_table
);
2120 mlx4_init_vlan_table(dev
, &info
->vlan_table
);
2121 mlx4_init_roce_gid_table(dev
, &info
->gid_table
);
2122 info
->base_qpn
= mlx4_get_base_qpn(dev
, port
);
2125 sprintf(info
->dev_name
, "mlx4_port%d", port
);
2126 info
->port_attr
.attr
.name
= info
->dev_name
;
2127 if (mlx4_is_mfunc(dev
))
2128 info
->port_attr
.attr
.mode
= S_IRUGO
;
2130 info
->port_attr
.attr
.mode
= S_IRUGO
| S_IWUSR
;
2131 info
->port_attr
.store
= set_port_type
;
2133 info
->port_attr
.show
= show_port_type
;
2134 sysfs_attr_init(&info
->port_attr
.attr
);
2136 err
= device_create_file(&dev
->pdev
->dev
, &info
->port_attr
);
2138 mlx4_err(dev
, "Failed to create file for port %d\n", port
);
2142 sprintf(info
->dev_mtu_name
, "mlx4_port%d_mtu", port
);
2143 info
->port_mtu_attr
.attr
.name
= info
->dev_mtu_name
;
2144 if (mlx4_is_mfunc(dev
))
2145 info
->port_mtu_attr
.attr
.mode
= S_IRUGO
;
2147 info
->port_mtu_attr
.attr
.mode
= S_IRUGO
| S_IWUSR
;
2148 info
->port_mtu_attr
.store
= set_port_ib_mtu
;
2150 info
->port_mtu_attr
.show
= show_port_ib_mtu
;
2151 sysfs_attr_init(&info
->port_mtu_attr
.attr
);
2153 err
= device_create_file(&dev
->pdev
->dev
, &info
->port_mtu_attr
);
2155 mlx4_err(dev
, "Failed to create mtu file for port %d\n", port
);
2156 device_remove_file(&info
->dev
->pdev
->dev
, &info
->port_attr
);
2163 static void mlx4_cleanup_port_info(struct mlx4_port_info
*info
)
2168 device_remove_file(&info
->dev
->pdev
->dev
, &info
->port_attr
);
2169 device_remove_file(&info
->dev
->pdev
->dev
, &info
->port_mtu_attr
);
2172 static int mlx4_init_steering(struct mlx4_dev
*dev
)
2174 struct mlx4_priv
*priv
= mlx4_priv(dev
);
2175 int num_entries
= dev
->caps
.num_ports
;
2178 priv
->steer
= kzalloc(sizeof(struct mlx4_steer
) * num_entries
, GFP_KERNEL
);
2182 for (i
= 0; i
< num_entries
; i
++)
2183 for (j
= 0; j
< MLX4_NUM_STEERS
; j
++) {
2184 INIT_LIST_HEAD(&priv
->steer
[i
].promisc_qps
[j
]);
2185 INIT_LIST_HEAD(&priv
->steer
[i
].steer_entries
[j
]);
2190 static void mlx4_clear_steering(struct mlx4_dev
*dev
)
2192 struct mlx4_priv
*priv
= mlx4_priv(dev
);
2193 struct mlx4_steer_index
*entry
, *tmp_entry
;
2194 struct mlx4_promisc_qp
*pqp
, *tmp_pqp
;
2195 int num_entries
= dev
->caps
.num_ports
;
2198 for (i
= 0; i
< num_entries
; i
++) {
2199 for (j
= 0; j
< MLX4_NUM_STEERS
; j
++) {
2200 list_for_each_entry_safe(pqp
, tmp_pqp
,
2201 &priv
->steer
[i
].promisc_qps
[j
],
2203 list_del(&pqp
->list
);
2206 list_for_each_entry_safe(entry
, tmp_entry
,
2207 &priv
->steer
[i
].steer_entries
[j
],
2209 list_del(&entry
->list
);
2210 list_for_each_entry_safe(pqp
, tmp_pqp
,
2213 list_del(&pqp
->list
);
2223 static int extended_func_num(struct pci_dev
*pdev
)
2225 return PCI_SLOT(pdev
->devfn
) * 8 + PCI_FUNC(pdev
->devfn
);
2228 #define MLX4_OWNER_BASE 0x8069c
2229 #define MLX4_OWNER_SIZE 4
2231 static int mlx4_get_ownership(struct mlx4_dev
*dev
)
2233 void __iomem
*owner
;
2236 if (pci_channel_offline(dev
->pdev
))
2239 owner
= ioremap(pci_resource_start(dev
->pdev
, 0) + MLX4_OWNER_BASE
,
2242 mlx4_err(dev
, "Failed to obtain ownership bit\n");
2251 static void mlx4_free_ownership(struct mlx4_dev
*dev
)
2253 void __iomem
*owner
;
2255 if (pci_channel_offline(dev
->pdev
))
2258 owner
= ioremap(pci_resource_start(dev
->pdev
, 0) + MLX4_OWNER_BASE
,
2261 mlx4_err(dev
, "Failed to obtain ownership bit\n");
2269 static int mlx4_load_one(struct pci_dev
*pdev
, int pci_dev_data
,
2270 int total_vfs
, int *nvfs
, struct mlx4_priv
*priv
)
2272 struct mlx4_dev
*dev
;
2277 int existing_vfs
= 0;
2281 INIT_LIST_HEAD(&priv
->ctx_list
);
2282 spin_lock_init(&priv
->ctx_lock
);
2284 mutex_init(&priv
->port_mutex
);
2286 INIT_LIST_HEAD(&priv
->pgdir_list
);
2287 mutex_init(&priv
->pgdir_mutex
);
2289 INIT_LIST_HEAD(&priv
->bf_list
);
2290 mutex_init(&priv
->bf_mutex
);
2292 dev
->rev_id
= pdev
->revision
;
2293 dev
->numa_node
= dev_to_node(&pdev
->dev
);
2295 /* Detect if this device is a virtual function */
2296 if (pci_dev_data
& MLX4_PCI_DEV_IS_VF
) {
2297 mlx4_warn(dev
, "Detected virtual function - running in slave mode\n");
2298 dev
->flags
|= MLX4_FLAG_SLAVE
;
2300 /* We reset the device and enable SRIOV only for physical
2301 * devices. Try to claim ownership on the device;
2302 * if already taken, skip -- do not allow multiple PFs */
2303 err
= mlx4_get_ownership(dev
);
2308 mlx4_warn(dev
, "Multiple PFs not yet supported - Skipping PF\n");
2314 mlx4_warn(dev
, "Enabling SR-IOV with %d VFs\n",
2316 dev
->dev_vfs
= kzalloc(
2317 total_vfs
* sizeof(*dev
->dev_vfs
),
2319 if (NULL
== dev
->dev_vfs
) {
2320 mlx4_err(dev
, "Failed to allocate memory for VFs\n");
2324 atomic_inc(&pf_loading
);
2325 existing_vfs
= pci_num_vf(pdev
);
2328 if (existing_vfs
!= total_vfs
)
2329 mlx4_err(dev
, "SR-IOV was already enabled, but with num_vfs (%d) different than requested (%d)\n",
2330 existing_vfs
, total_vfs
);
2332 err
= pci_enable_sriov(pdev
, total_vfs
);
2335 mlx4_err(dev
, "Failed to enable SR-IOV, continuing without SR-IOV (err = %d)\n",
2337 atomic_dec(&pf_loading
);
2339 mlx4_warn(dev
, "Running in master mode\n");
2340 dev
->flags
|= MLX4_FLAG_SRIOV
|
2342 dev
->num_vfs
= total_vfs
;
2347 atomic_set(&priv
->opreq_count
, 0);
2348 INIT_WORK(&priv
->opreq_task
, mlx4_opreq_action
);
2351 * Now reset the HCA before we touch the PCI capabilities or
2352 * attempt a firmware command, since a boot ROM may have left
2353 * the HCA in an undefined state.
2355 err
= mlx4_reset(dev
);
2357 mlx4_err(dev
, "Failed to reset HCA, aborting\n");
2363 err
= mlx4_cmd_init(dev
);
2365 mlx4_err(dev
, "Failed to init command interface, aborting\n");
2369 /* In slave functions, the communication channel must be initialized
2370 * before posting commands. Also, init num_slaves before calling
2372 if (mlx4_is_mfunc(dev
)) {
2373 if (mlx4_is_master(dev
))
2374 dev
->num_slaves
= MLX4_MAX_NUM_SLAVES
;
2376 dev
->num_slaves
= 0;
2377 err
= mlx4_multi_func_init(dev
);
2379 mlx4_err(dev
, "Failed to init slave mfunc interface, aborting\n");
2385 err
= mlx4_init_hca(dev
);
2387 if (err
== -EACCES
) {
2388 /* Not primary Physical function
2389 * Running in slave mode */
2390 mlx4_cmd_cleanup(dev
);
2391 dev
->flags
|= MLX4_FLAG_SLAVE
;
2392 dev
->flags
&= ~MLX4_FLAG_MASTER
;
2398 /* check if the device is functioning at its maximum possible speed.
2399 * No return code for this call, just warn the user in case of PCI
2400 * express device capabilities are under-satisfied by the bus.
2402 if (!mlx4_is_slave(dev
))
2403 mlx4_check_pcie_caps(dev
);
2405 /* In master functions, the communication channel must be initialized
2406 * after obtaining its address from fw */
2407 if (mlx4_is_master(dev
)) {
2410 mlx4_foreach_port(i
, dev
, MLX4_PORT_TYPE_IB
)
2414 (num_vfs_argc
> 1 || probe_vfs_argc
> 1)) {
2416 "Invalid syntax of num_vfs/probe_vfs with IB port - single port VFs syntax is only supported when all ports are configured as ethernet\n");
2420 if (dev
->caps
.num_ports
< 2 &&
2424 "Error: Trying to configure VFs on port 2, but HCA has only %d physical ports\n",
2425 dev
->caps
.num_ports
);
2428 memcpy(dev
->nvfs
, nvfs
, sizeof(dev
->nvfs
));
2430 for (i
= 0; i
< sizeof(dev
->nvfs
)/sizeof(dev
->nvfs
[0]); i
++) {
2433 for (j
= 0; j
< dev
->nvfs
[i
]; ++sum
, ++j
) {
2434 dev
->dev_vfs
[sum
].min_port
= i
< 2 ? i
+ 1 : 1;
2435 dev
->dev_vfs
[sum
].n_ports
= i
< 2 ? 1 :
2436 dev
->caps
.num_ports
;
2440 /* In master functions, the communication channel
2441 * must be initialized after obtaining its address from fw
2443 err
= mlx4_multi_func_init(dev
);
2445 mlx4_err(dev
, "Failed to init master mfunc interface, aborting.\n");
2450 err
= mlx4_alloc_eq_table(dev
);
2452 goto err_master_mfunc
;
2454 priv
->msix_ctl
.pool_bm
= 0;
2455 mutex_init(&priv
->msix_ctl
.pool_lock
);
2457 mlx4_enable_msi_x(dev
);
2458 if ((mlx4_is_mfunc(dev
)) &&
2459 !(dev
->flags
& MLX4_FLAG_MSI_X
)) {
2461 mlx4_err(dev
, "INTx is not supported in multi-function mode, aborting\n");
2465 if (!mlx4_is_slave(dev
)) {
2466 err
= mlx4_init_steering(dev
);
2468 goto err_disable_msix
;
2471 err
= mlx4_setup_hca(dev
);
2472 if (err
== -EBUSY
&& (dev
->flags
& MLX4_FLAG_MSI_X
) &&
2473 !mlx4_is_mfunc(dev
)) {
2474 dev
->flags
&= ~MLX4_FLAG_MSI_X
;
2475 dev
->caps
.num_comp_vectors
= 1;
2476 dev
->caps
.comp_pool
= 0;
2477 pci_disable_msix(pdev
);
2478 err
= mlx4_setup_hca(dev
);
2484 mlx4_init_quotas(dev
);
2486 for (port
= 1; port
<= dev
->caps
.num_ports
; port
++) {
2487 err
= mlx4_init_port_info(dev
, port
);
2492 err
= mlx4_register_device(dev
);
2496 mlx4_request_modules(dev
);
2498 mlx4_sense_init(dev
);
2499 mlx4_start_sense(dev
);
2503 if (mlx4_is_master(dev
) && dev
->num_vfs
)
2504 atomic_dec(&pf_loading
);
2509 for (--port
; port
>= 1; --port
)
2510 mlx4_cleanup_port_info(&priv
->port
[port
]);
2512 mlx4_cleanup_counters_table(dev
);
2513 mlx4_cleanup_qp_table(dev
);
2514 mlx4_cleanup_srq_table(dev
);
2515 mlx4_cleanup_cq_table(dev
);
2516 mlx4_cmd_use_polling(dev
);
2517 mlx4_cleanup_eq_table(dev
);
2518 mlx4_cleanup_mcg_table(dev
);
2519 mlx4_cleanup_mr_table(dev
);
2520 mlx4_cleanup_xrcd_table(dev
);
2521 mlx4_cleanup_pd_table(dev
);
2522 mlx4_cleanup_uar_table(dev
);
2525 if (!mlx4_is_slave(dev
))
2526 mlx4_clear_steering(dev
);
2529 if (dev
->flags
& MLX4_FLAG_MSI_X
)
2530 pci_disable_msix(pdev
);
2533 mlx4_free_eq_table(dev
);
2536 if (mlx4_is_master(dev
))
2537 mlx4_multi_func_cleanup(dev
);
2539 if (mlx4_is_slave(dev
)) {
2540 kfree(dev
->caps
.qp0_qkey
);
2541 kfree(dev
->caps
.qp0_tunnel
);
2542 kfree(dev
->caps
.qp0_proxy
);
2543 kfree(dev
->caps
.qp1_tunnel
);
2544 kfree(dev
->caps
.qp1_proxy
);
2548 mlx4_close_hca(dev
);
2551 if (mlx4_is_slave(dev
))
2552 mlx4_multi_func_cleanup(dev
);
2555 mlx4_cmd_cleanup(dev
);
2558 if (dev
->flags
& MLX4_FLAG_SRIOV
&& !existing_vfs
)
2559 pci_disable_sriov(pdev
);
2561 if (mlx4_is_master(dev
) && dev
->num_vfs
)
2562 atomic_dec(&pf_loading
);
2564 kfree(priv
->dev
.dev_vfs
);
2567 if (!mlx4_is_slave(dev
))
2568 mlx4_free_ownership(dev
);
2573 static int __mlx4_init_one(struct pci_dev
*pdev
, int pci_dev_data
,
2574 struct mlx4_priv
*priv
)
2577 int nvfs
[MLX4_MAX_PORTS
+ 1] = {0, 0, 0};
2578 int prb_vf
[MLX4_MAX_PORTS
+ 1] = {0, 0, 0};
2579 const int param_map
[MLX4_MAX_PORTS
+ 1][MLX4_MAX_PORTS
+ 1] = {
2580 {2, 0, 0}, {0, 1, 2}, {0, 1, 2} };
2581 unsigned total_vfs
= 0;
2584 pr_info(DRV_NAME
": Initializing %s\n", pci_name(pdev
));
2586 err
= pci_enable_device(pdev
);
2588 dev_err(&pdev
->dev
, "Cannot enable PCI device, aborting\n");
2592 /* Due to requirement that all VFs and the PF are *guaranteed* 2 MACS
2593 * per port, we must limit the number of VFs to 63 (since their are
2596 for (i
= 0; i
< sizeof(nvfs
)/sizeof(nvfs
[0]) && i
< num_vfs_argc
;
2597 total_vfs
+= nvfs
[param_map
[num_vfs_argc
- 1][i
]], i
++) {
2598 nvfs
[param_map
[num_vfs_argc
- 1][i
]] = num_vfs
[i
];
2600 dev_err(&pdev
->dev
, "num_vfs module parameter cannot be negative\n");
2602 goto err_disable_pdev
;
2605 for (i
= 0; i
< sizeof(prb_vf
)/sizeof(prb_vf
[0]) && i
< probe_vfs_argc
;
2607 prb_vf
[param_map
[probe_vfs_argc
- 1][i
]] = probe_vf
[i
];
2608 if (prb_vf
[i
] < 0 || prb_vf
[i
] > nvfs
[i
]) {
2609 dev_err(&pdev
->dev
, "probe_vf module parameter cannot be negative or greater than num_vfs\n");
2611 goto err_disable_pdev
;
2614 if (total_vfs
>= MLX4_MAX_NUM_VF
) {
2616 "Requested more VF's (%d) than allowed (%d)\n",
2617 total_vfs
, MLX4_MAX_NUM_VF
- 1);
2619 goto err_disable_pdev
;
2622 for (i
= 0; i
< MLX4_MAX_PORTS
; i
++) {
2623 if (nvfs
[i
] + nvfs
[2] >= MLX4_MAX_NUM_VF_P_PORT
) {
2625 "Requested more VF's (%d) for port (%d) than allowed (%d)\n",
2626 nvfs
[i
] + nvfs
[2], i
+ 1,
2627 MLX4_MAX_NUM_VF_P_PORT
- 1);
2629 goto err_disable_pdev
;
2633 /* Check for BARs. */
2634 if (!(pci_dev_data
& MLX4_PCI_DEV_IS_VF
) &&
2635 !(pci_resource_flags(pdev
, 0) & IORESOURCE_MEM
)) {
2636 dev_err(&pdev
->dev
, "Missing DCS, aborting (driver_data: 0x%x, pci_resource_flags(pdev, 0):0x%lx)\n",
2637 pci_dev_data
, pci_resource_flags(pdev
, 0));
2639 goto err_disable_pdev
;
2641 if (!(pci_resource_flags(pdev
, 2) & IORESOURCE_MEM
)) {
2642 dev_err(&pdev
->dev
, "Missing UAR, aborting\n");
2644 goto err_disable_pdev
;
2647 err
= pci_request_regions(pdev
, DRV_NAME
);
2649 dev_err(&pdev
->dev
, "Couldn't get PCI resources, aborting\n");
2650 goto err_disable_pdev
;
2653 pci_set_master(pdev
);
2655 err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(64));
2657 dev_warn(&pdev
->dev
, "Warning: couldn't set 64-bit PCI DMA mask\n");
2658 err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
2660 dev_err(&pdev
->dev
, "Can't set PCI DMA mask, aborting\n");
2661 goto err_release_regions
;
2664 err
= pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(64));
2666 dev_warn(&pdev
->dev
, "Warning: couldn't set 64-bit consistent PCI DMA mask\n");
2667 err
= pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(32));
2669 dev_err(&pdev
->dev
, "Can't set consistent PCI DMA mask, aborting\n");
2670 goto err_release_regions
;
2674 /* Allow large DMA segments, up to the firmware limit of 1 GB */
2675 dma_set_max_seg_size(&pdev
->dev
, 1024 * 1024 * 1024);
2676 /* Detect if this device is a virtual function */
2677 if (pci_dev_data
& MLX4_PCI_DEV_IS_VF
) {
2678 /* When acting as pf, we normally skip vfs unless explicitly
2679 * requested to probe them.
2682 unsigned vfs_offset
= 0;
2684 for (i
= 0; i
< sizeof(nvfs
)/sizeof(nvfs
[0]) &&
2685 vfs_offset
+ nvfs
[i
] < extended_func_num(pdev
);
2686 vfs_offset
+= nvfs
[i
], i
++)
2688 if (i
== sizeof(nvfs
)/sizeof(nvfs
[0])) {
2690 goto err_release_regions
;
2692 if ((extended_func_num(pdev
) - vfs_offset
)
2694 dev_warn(&pdev
->dev
, "Skipping virtual function:%d\n",
2695 extended_func_num(pdev
));
2697 goto err_release_regions
;
2702 err
= mlx4_load_one(pdev
, pci_dev_data
, total_vfs
, nvfs
, priv
);
2704 goto err_release_regions
;
2707 err_release_regions
:
2708 pci_release_regions(pdev
);
2711 pci_disable_device(pdev
);
2712 pci_set_drvdata(pdev
, NULL
);
2716 static int mlx4_init_one(struct pci_dev
*pdev
, const struct pci_device_id
*id
)
2718 struct mlx4_priv
*priv
;
2719 struct mlx4_dev
*dev
;
2722 printk_once(KERN_INFO
"%s", mlx4_version
);
2724 priv
= kzalloc(sizeof(*priv
), GFP_KERNEL
);
2730 pci_set_drvdata(pdev
, dev
);
2731 priv
->pci_dev_data
= id
->driver_data
;
2733 ret
= __mlx4_init_one(pdev
, id
->driver_data
, priv
);
2740 static void mlx4_unload_one(struct pci_dev
*pdev
)
2742 struct mlx4_dev
*dev
= pci_get_drvdata(pdev
);
2743 struct mlx4_priv
*priv
= mlx4_priv(dev
);
2751 pci_dev_data
= priv
->pci_dev_data
;
2753 /* Disabling SR-IOV is not allowed while there are active vf's */
2754 if (mlx4_is_master(dev
)) {
2755 active_vfs
= mlx4_how_many_lives_vf(dev
);
2757 pr_warn("Removing PF when there are active VF's !!\n");
2758 pr_warn("Will not disable SR-IOV.\n");
2761 mlx4_stop_sense(dev
);
2762 mlx4_unregister_device(dev
);
2764 for (p
= 1; p
<= dev
->caps
.num_ports
; p
++) {
2765 mlx4_cleanup_port_info(&priv
->port
[p
]);
2766 mlx4_CLOSE_PORT(dev
, p
);
2769 if (mlx4_is_master(dev
))
2770 mlx4_free_resource_tracker(dev
,
2771 RES_TR_FREE_SLAVES_ONLY
);
2773 mlx4_cleanup_counters_table(dev
);
2774 mlx4_cleanup_qp_table(dev
);
2775 mlx4_cleanup_srq_table(dev
);
2776 mlx4_cleanup_cq_table(dev
);
2777 mlx4_cmd_use_polling(dev
);
2778 mlx4_cleanup_eq_table(dev
);
2779 mlx4_cleanup_mcg_table(dev
);
2780 mlx4_cleanup_mr_table(dev
);
2781 mlx4_cleanup_xrcd_table(dev
);
2782 mlx4_cleanup_pd_table(dev
);
2784 if (mlx4_is_master(dev
))
2785 mlx4_free_resource_tracker(dev
,
2786 RES_TR_FREE_STRUCTS_ONLY
);
2789 mlx4_uar_free(dev
, &priv
->driver_uar
);
2790 mlx4_cleanup_uar_table(dev
);
2791 if (!mlx4_is_slave(dev
))
2792 mlx4_clear_steering(dev
);
2793 mlx4_free_eq_table(dev
);
2794 if (mlx4_is_master(dev
))
2795 mlx4_multi_func_cleanup(dev
);
2796 mlx4_close_hca(dev
);
2797 if (mlx4_is_slave(dev
))
2798 mlx4_multi_func_cleanup(dev
);
2799 mlx4_cmd_cleanup(dev
);
2801 if (dev
->flags
& MLX4_FLAG_MSI_X
)
2802 pci_disable_msix(pdev
);
2803 if (dev
->flags
& MLX4_FLAG_SRIOV
&& !active_vfs
) {
2804 mlx4_warn(dev
, "Disabling SR-IOV\n");
2805 pci_disable_sriov(pdev
);
2809 if (!mlx4_is_slave(dev
))
2810 mlx4_free_ownership(dev
);
2812 kfree(dev
->caps
.qp0_qkey
);
2813 kfree(dev
->caps
.qp0_tunnel
);
2814 kfree(dev
->caps
.qp0_proxy
);
2815 kfree(dev
->caps
.qp1_tunnel
);
2816 kfree(dev
->caps
.qp1_proxy
);
2817 kfree(dev
->dev_vfs
);
2819 memset(priv
, 0, sizeof(*priv
));
2820 priv
->pci_dev_data
= pci_dev_data
;
2824 static void mlx4_remove_one(struct pci_dev
*pdev
)
2826 struct mlx4_dev
*dev
= pci_get_drvdata(pdev
);
2827 struct mlx4_priv
*priv
= mlx4_priv(dev
);
2829 mlx4_unload_one(pdev
);
2830 pci_release_regions(pdev
);
2831 pci_disable_device(pdev
);
2833 pci_set_drvdata(pdev
, NULL
);
2836 int mlx4_restart_one(struct pci_dev
*pdev
)
2838 struct mlx4_dev
*dev
= pci_get_drvdata(pdev
);
2839 struct mlx4_priv
*priv
= mlx4_priv(dev
);
2840 int nvfs
[MLX4_MAX_PORTS
+ 1] = {0, 0, 0};
2841 int pci_dev_data
, err
, total_vfs
;
2843 pci_dev_data
= priv
->pci_dev_data
;
2844 total_vfs
= dev
->num_vfs
;
2845 memcpy(nvfs
, dev
->nvfs
, sizeof(dev
->nvfs
));
2847 mlx4_unload_one(pdev
);
2848 err
= mlx4_load_one(pdev
, pci_dev_data
, total_vfs
, nvfs
, priv
);
2850 mlx4_err(dev
, "%s: ERROR: mlx4_load_one failed, pci_name=%s, err=%d\n",
2851 __func__
, pci_name(pdev
), err
);
2858 static const struct pci_device_id mlx4_pci_table
[] = {
2859 /* MT25408 "Hermon" SDR */
2860 { PCI_VDEVICE(MELLANOX
, 0x6340), MLX4_PCI_DEV_FORCE_SENSE_PORT
},
2861 /* MT25408 "Hermon" DDR */
2862 { PCI_VDEVICE(MELLANOX
, 0x634a), MLX4_PCI_DEV_FORCE_SENSE_PORT
},
2863 /* MT25408 "Hermon" QDR */
2864 { PCI_VDEVICE(MELLANOX
, 0x6354), MLX4_PCI_DEV_FORCE_SENSE_PORT
},
2865 /* MT25408 "Hermon" DDR PCIe gen2 */
2866 { PCI_VDEVICE(MELLANOX
, 0x6732), MLX4_PCI_DEV_FORCE_SENSE_PORT
},
2867 /* MT25408 "Hermon" QDR PCIe gen2 */
2868 { PCI_VDEVICE(MELLANOX
, 0x673c), MLX4_PCI_DEV_FORCE_SENSE_PORT
},
2869 /* MT25408 "Hermon" EN 10GigE */
2870 { PCI_VDEVICE(MELLANOX
, 0x6368), MLX4_PCI_DEV_FORCE_SENSE_PORT
},
2871 /* MT25408 "Hermon" EN 10GigE PCIe gen2 */
2872 { PCI_VDEVICE(MELLANOX
, 0x6750), MLX4_PCI_DEV_FORCE_SENSE_PORT
},
2873 /* MT25458 ConnectX EN 10GBASE-T 10GigE */
2874 { PCI_VDEVICE(MELLANOX
, 0x6372), MLX4_PCI_DEV_FORCE_SENSE_PORT
},
2875 /* MT25458 ConnectX EN 10GBASE-T+Gen2 10GigE */
2876 { PCI_VDEVICE(MELLANOX
, 0x675a), MLX4_PCI_DEV_FORCE_SENSE_PORT
},
2877 /* MT26468 ConnectX EN 10GigE PCIe gen2*/
2878 { PCI_VDEVICE(MELLANOX
, 0x6764), MLX4_PCI_DEV_FORCE_SENSE_PORT
},
2879 /* MT26438 ConnectX EN 40GigE PCIe gen2 5GT/s */
2880 { PCI_VDEVICE(MELLANOX
, 0x6746), MLX4_PCI_DEV_FORCE_SENSE_PORT
},
2881 /* MT26478 ConnectX2 40GigE PCIe gen2 */
2882 { PCI_VDEVICE(MELLANOX
, 0x676e), MLX4_PCI_DEV_FORCE_SENSE_PORT
},
2883 /* MT25400 Family [ConnectX-2 Virtual Function] */
2884 { PCI_VDEVICE(MELLANOX
, 0x1002), MLX4_PCI_DEV_IS_VF
},
2885 /* MT27500 Family [ConnectX-3] */
2886 { PCI_VDEVICE(MELLANOX
, 0x1003), 0 },
2887 /* MT27500 Family [ConnectX-3 Virtual Function] */
2888 { PCI_VDEVICE(MELLANOX
, 0x1004), MLX4_PCI_DEV_IS_VF
},
2889 { PCI_VDEVICE(MELLANOX
, 0x1005), 0 }, /* MT27510 Family */
2890 { PCI_VDEVICE(MELLANOX
, 0x1006), 0 }, /* MT27511 Family */
2891 { PCI_VDEVICE(MELLANOX
, 0x1007), 0 }, /* MT27520 Family */
2892 { PCI_VDEVICE(MELLANOX
, 0x1008), 0 }, /* MT27521 Family */
2893 { PCI_VDEVICE(MELLANOX
, 0x1009), 0 }, /* MT27530 Family */
2894 { PCI_VDEVICE(MELLANOX
, 0x100a), 0 }, /* MT27531 Family */
2895 { PCI_VDEVICE(MELLANOX
, 0x100b), 0 }, /* MT27540 Family */
2896 { PCI_VDEVICE(MELLANOX
, 0x100c), 0 }, /* MT27541 Family */
2897 { PCI_VDEVICE(MELLANOX
, 0x100d), 0 }, /* MT27550 Family */
2898 { PCI_VDEVICE(MELLANOX
, 0x100e), 0 }, /* MT27551 Family */
2899 { PCI_VDEVICE(MELLANOX
, 0x100f), 0 }, /* MT27560 Family */
2900 { PCI_VDEVICE(MELLANOX
, 0x1010), 0 }, /* MT27561 Family */
2904 MODULE_DEVICE_TABLE(pci
, mlx4_pci_table
);
2906 static pci_ers_result_t
mlx4_pci_err_detected(struct pci_dev
*pdev
,
2907 pci_channel_state_t state
)
2909 mlx4_unload_one(pdev
);
2911 return state
== pci_channel_io_perm_failure
?
2912 PCI_ERS_RESULT_DISCONNECT
: PCI_ERS_RESULT_NEED_RESET
;
2915 static pci_ers_result_t
mlx4_pci_slot_reset(struct pci_dev
*pdev
)
2917 struct mlx4_dev
*dev
= pci_get_drvdata(pdev
);
2918 struct mlx4_priv
*priv
= mlx4_priv(dev
);
2921 ret
= __mlx4_init_one(pdev
, priv
->pci_dev_data
, priv
);
2923 return ret
? PCI_ERS_RESULT_DISCONNECT
: PCI_ERS_RESULT_RECOVERED
;
2926 static const struct pci_error_handlers mlx4_err_handler
= {
2927 .error_detected
= mlx4_pci_err_detected
,
2928 .slot_reset
= mlx4_pci_slot_reset
,
2931 static struct pci_driver mlx4_driver
= {
2933 .id_table
= mlx4_pci_table
,
2934 .probe
= mlx4_init_one
,
2935 .shutdown
= mlx4_unload_one
,
2936 .remove
= mlx4_remove_one
,
2937 .err_handler
= &mlx4_err_handler
,
2940 static int __init
mlx4_verify_params(void)
2942 if ((log_num_mac
< 0) || (log_num_mac
> 7)) {
2943 pr_warn("mlx4_core: bad num_mac: %d\n", log_num_mac
);
2947 if (log_num_vlan
!= 0)
2948 pr_warn("mlx4_core: log_num_vlan - obsolete module param, using %d\n",
2949 MLX4_LOG_NUM_VLANS
);
2952 pr_warn("mlx4_core: use_prio - obsolete module param, ignored\n");
2954 if ((log_mtts_per_seg
< 1) || (log_mtts_per_seg
> 7)) {
2955 pr_warn("mlx4_core: bad log_mtts_per_seg: %d\n",
2960 /* Check if module param for ports type has legal combination */
2961 if (port_type_array
[0] == false && port_type_array
[1] == true) {
2962 pr_warn("Module parameter configuration ETH/IB is not supported. Switching to default configuration IB/IB\n");
2963 port_type_array
[0] = true;
2966 if (mlx4_log_num_mgm_entry_size
!= -1 &&
2967 (mlx4_log_num_mgm_entry_size
< MLX4_MIN_MGM_LOG_ENTRY_SIZE
||
2968 mlx4_log_num_mgm_entry_size
> MLX4_MAX_MGM_LOG_ENTRY_SIZE
)) {
2969 pr_warn("mlx4_core: mlx4_log_num_mgm_entry_size (%d) not in legal range (-1 or %d..%d)\n",
2970 mlx4_log_num_mgm_entry_size
,
2971 MLX4_MIN_MGM_LOG_ENTRY_SIZE
,
2972 MLX4_MAX_MGM_LOG_ENTRY_SIZE
);
2979 static int __init
mlx4_init(void)
2983 if (mlx4_verify_params())
2988 mlx4_wq
= create_singlethread_workqueue("mlx4");
2992 ret
= pci_register_driver(&mlx4_driver
);
2994 destroy_workqueue(mlx4_wq
);
2995 return ret
< 0 ? ret
: 0;
2998 static void __exit
mlx4_cleanup(void)
3000 pci_unregister_driver(&mlx4_driver
);
3001 destroy_workqueue(mlx4_wq
);
3004 module_init(mlx4_init
);
3005 module_exit(mlx4_cleanup
);