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net/mlx4_core: Make sure that negative array index isn't used
[deliverable/linux.git] / drivers / net / ethernet / mellanox / mlx4 / mcg.c
1 /*
2 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
10 *
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
13 * conditions are met:
14 *
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
17 * disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 */
33
34 #include <linux/string.h>
35 #include <linux/etherdevice.h>
36
37 #include <linux/mlx4/cmd.h>
38 #include <linux/export.h>
39
40 #include "mlx4.h"
41
42 static const u8 zero_gid[16]; /* automatically initialized to 0 */
43
44 int mlx4_get_mgm_entry_size(struct mlx4_dev *dev)
45 {
46 return 1 << dev->oper_log_mgm_entry_size;
47 }
48
49 int mlx4_get_qp_per_mgm(struct mlx4_dev *dev)
50 {
51 return 4 * (mlx4_get_mgm_entry_size(dev) / 16 - 2);
52 }
53
54 static int mlx4_QP_FLOW_STEERING_ATTACH(struct mlx4_dev *dev,
55 struct mlx4_cmd_mailbox *mailbox,
56 u32 size,
57 u64 *reg_id)
58 {
59 u64 imm;
60 int err = 0;
61
62 err = mlx4_cmd_imm(dev, mailbox->dma, &imm, size, 0,
63 MLX4_QP_FLOW_STEERING_ATTACH, MLX4_CMD_TIME_CLASS_A,
64 MLX4_CMD_NATIVE);
65 if (err)
66 return err;
67 *reg_id = imm;
68
69 return err;
70 }
71
72 static int mlx4_QP_FLOW_STEERING_DETACH(struct mlx4_dev *dev, u64 regid)
73 {
74 int err = 0;
75
76 err = mlx4_cmd(dev, regid, 0, 0,
77 MLX4_QP_FLOW_STEERING_DETACH, MLX4_CMD_TIME_CLASS_A,
78 MLX4_CMD_NATIVE);
79
80 return err;
81 }
82
83 static int mlx4_READ_ENTRY(struct mlx4_dev *dev, int index,
84 struct mlx4_cmd_mailbox *mailbox)
85 {
86 return mlx4_cmd_box(dev, 0, mailbox->dma, index, 0, MLX4_CMD_READ_MCG,
87 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
88 }
89
90 static int mlx4_WRITE_ENTRY(struct mlx4_dev *dev, int index,
91 struct mlx4_cmd_mailbox *mailbox)
92 {
93 return mlx4_cmd(dev, mailbox->dma, index, 0, MLX4_CMD_WRITE_MCG,
94 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
95 }
96
97 static int mlx4_WRITE_PROMISC(struct mlx4_dev *dev, u8 port, u8 steer,
98 struct mlx4_cmd_mailbox *mailbox)
99 {
100 u32 in_mod;
101
102 in_mod = (u32) port << 16 | steer << 1;
103 return mlx4_cmd(dev, mailbox->dma, in_mod, 0x1,
104 MLX4_CMD_WRITE_MCG, MLX4_CMD_TIME_CLASS_A,
105 MLX4_CMD_NATIVE);
106 }
107
108 static int mlx4_GID_HASH(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
109 u16 *hash, u8 op_mod)
110 {
111 u64 imm;
112 int err;
113
114 err = mlx4_cmd_imm(dev, mailbox->dma, &imm, 0, op_mod,
115 MLX4_CMD_MGID_HASH, MLX4_CMD_TIME_CLASS_A,
116 MLX4_CMD_NATIVE);
117
118 if (!err)
119 *hash = imm;
120
121 return err;
122 }
123
124 static struct mlx4_promisc_qp *get_promisc_qp(struct mlx4_dev *dev, u8 port,
125 enum mlx4_steer_type steer,
126 u32 qpn)
127 {
128 struct mlx4_steer *s_steer;
129 struct mlx4_promisc_qp *pqp;
130
131 if (port < 1 || port > dev->caps.num_ports)
132 return NULL;
133
134 s_steer = &mlx4_priv(dev)->steer[port - 1];
135
136 list_for_each_entry(pqp, &s_steer->promisc_qps[steer], list) {
137 if (pqp->qpn == qpn)
138 return pqp;
139 }
140 /* not found */
141 return NULL;
142 }
143
144 /*
145 * Add new entry to steering data structure.
146 * All promisc QPs should be added as well
147 */
148 static int new_steering_entry(struct mlx4_dev *dev, u8 port,
149 enum mlx4_steer_type steer,
150 unsigned int index, u32 qpn)
151 {
152 struct mlx4_steer *s_steer;
153 struct mlx4_cmd_mailbox *mailbox;
154 struct mlx4_mgm *mgm;
155 u32 members_count;
156 struct mlx4_steer_index *new_entry;
157 struct mlx4_promisc_qp *pqp;
158 struct mlx4_promisc_qp *dqp = NULL;
159 u32 prot;
160 int err;
161
162 if (port < 1 || port > dev->caps.num_ports)
163 return -EINVAL;
164
165 s_steer = &mlx4_priv(dev)->steer[port - 1];
166 new_entry = kzalloc(sizeof *new_entry, GFP_KERNEL);
167 if (!new_entry)
168 return -ENOMEM;
169
170 INIT_LIST_HEAD(&new_entry->duplicates);
171 new_entry->index = index;
172 list_add_tail(&new_entry->list, &s_steer->steer_entries[steer]);
173
174 /* If the given qpn is also a promisc qp,
175 * it should be inserted to duplicates list
176 */
177 pqp = get_promisc_qp(dev, port, steer, qpn);
178 if (pqp) {
179 dqp = kmalloc(sizeof *dqp, GFP_KERNEL);
180 if (!dqp) {
181 err = -ENOMEM;
182 goto out_alloc;
183 }
184 dqp->qpn = qpn;
185 list_add_tail(&dqp->list, &new_entry->duplicates);
186 }
187
188 /* if no promisc qps for this vep, we are done */
189 if (list_empty(&s_steer->promisc_qps[steer]))
190 return 0;
191
192 /* now need to add all the promisc qps to the new
193 * steering entry, as they should also receive the packets
194 * destined to this address */
195 mailbox = mlx4_alloc_cmd_mailbox(dev);
196 if (IS_ERR(mailbox)) {
197 err = -ENOMEM;
198 goto out_alloc;
199 }
200 mgm = mailbox->buf;
201
202 err = mlx4_READ_ENTRY(dev, index, mailbox);
203 if (err)
204 goto out_mailbox;
205
206 members_count = be32_to_cpu(mgm->members_count) & 0xffffff;
207 prot = be32_to_cpu(mgm->members_count) >> 30;
208 list_for_each_entry(pqp, &s_steer->promisc_qps[steer], list) {
209 /* don't add already existing qpn */
210 if (pqp->qpn == qpn)
211 continue;
212 if (members_count == dev->caps.num_qp_per_mgm) {
213 /* out of space */
214 err = -ENOMEM;
215 goto out_mailbox;
216 }
217
218 /* add the qpn */
219 mgm->qp[members_count++] = cpu_to_be32(pqp->qpn & MGM_QPN_MASK);
220 }
221 /* update the qps count and update the entry with all the promisc qps*/
222 mgm->members_count = cpu_to_be32(members_count | (prot << 30));
223 err = mlx4_WRITE_ENTRY(dev, index, mailbox);
224
225 out_mailbox:
226 mlx4_free_cmd_mailbox(dev, mailbox);
227 if (!err)
228 return 0;
229 out_alloc:
230 if (dqp) {
231 list_del(&dqp->list);
232 kfree(dqp);
233 }
234 list_del(&new_entry->list);
235 kfree(new_entry);
236 return err;
237 }
238
239 /* update the data structures with existing steering entry */
240 static int existing_steering_entry(struct mlx4_dev *dev, u8 port,
241 enum mlx4_steer_type steer,
242 unsigned int index, u32 qpn)
243 {
244 struct mlx4_steer *s_steer;
245 struct mlx4_steer_index *tmp_entry, *entry = NULL;
246 struct mlx4_promisc_qp *pqp;
247 struct mlx4_promisc_qp *dqp;
248
249 if (port < 1 || port > dev->caps.num_ports)
250 return -EINVAL;
251
252 s_steer = &mlx4_priv(dev)->steer[port - 1];
253
254 pqp = get_promisc_qp(dev, port, steer, qpn);
255 if (!pqp)
256 return 0; /* nothing to do */
257
258 list_for_each_entry(tmp_entry, &s_steer->steer_entries[steer], list) {
259 if (tmp_entry->index == index) {
260 entry = tmp_entry;
261 break;
262 }
263 }
264 if (unlikely(!entry)) {
265 mlx4_warn(dev, "Steering entry at index %x is not registered\n", index);
266 return -EINVAL;
267 }
268
269 /* the given qpn is listed as a promisc qpn
270 * we need to add it as a duplicate to this entry
271 * for future references */
272 list_for_each_entry(dqp, &entry->duplicates, list) {
273 if (qpn == pqp->qpn)
274 return 0; /* qp is already duplicated */
275 }
276
277 /* add the qp as a duplicate on this index */
278 dqp = kmalloc(sizeof *dqp, GFP_KERNEL);
279 if (!dqp)
280 return -ENOMEM;
281 dqp->qpn = qpn;
282 list_add_tail(&dqp->list, &entry->duplicates);
283
284 return 0;
285 }
286
287 /* Check whether a qpn is a duplicate on steering entry
288 * If so, it should not be removed from mgm */
289 static bool check_duplicate_entry(struct mlx4_dev *dev, u8 port,
290 enum mlx4_steer_type steer,
291 unsigned int index, u32 qpn)
292 {
293 struct mlx4_steer *s_steer;
294 struct mlx4_steer_index *tmp_entry, *entry = NULL;
295 struct mlx4_promisc_qp *dqp, *tmp_dqp;
296
297 if (port < 1 || port > dev->caps.num_ports)
298 return NULL;
299
300 s_steer = &mlx4_priv(dev)->steer[port - 1];
301
302 /* if qp is not promisc, it cannot be duplicated */
303 if (!get_promisc_qp(dev, port, steer, qpn))
304 return false;
305
306 /* The qp is promisc qp so it is a duplicate on this index
307 * Find the index entry, and remove the duplicate */
308 list_for_each_entry(tmp_entry, &s_steer->steer_entries[steer], list) {
309 if (tmp_entry->index == index) {
310 entry = tmp_entry;
311 break;
312 }
313 }
314 if (unlikely(!entry)) {
315 mlx4_warn(dev, "Steering entry for index %x is not registered\n", index);
316 return false;
317 }
318 list_for_each_entry_safe(dqp, tmp_dqp, &entry->duplicates, list) {
319 if (dqp->qpn == qpn) {
320 list_del(&dqp->list);
321 kfree(dqp);
322 }
323 }
324 return true;
325 }
326
327 /* I a steering entry contains only promisc QPs, it can be removed. */
328 static bool can_remove_steering_entry(struct mlx4_dev *dev, u8 port,
329 enum mlx4_steer_type steer,
330 unsigned int index, u32 tqpn)
331 {
332 struct mlx4_steer *s_steer;
333 struct mlx4_cmd_mailbox *mailbox;
334 struct mlx4_mgm *mgm;
335 struct mlx4_steer_index *entry = NULL, *tmp_entry;
336 u32 qpn;
337 u32 members_count;
338 bool ret = false;
339 int i;
340
341 if (port < 1 || port > dev->caps.num_ports)
342 return NULL;
343
344 s_steer = &mlx4_priv(dev)->steer[port - 1];
345
346 mailbox = mlx4_alloc_cmd_mailbox(dev);
347 if (IS_ERR(mailbox))
348 return false;
349 mgm = mailbox->buf;
350
351 if (mlx4_READ_ENTRY(dev, index, mailbox))
352 goto out;
353 members_count = be32_to_cpu(mgm->members_count) & 0xffffff;
354 for (i = 0; i < members_count; i++) {
355 qpn = be32_to_cpu(mgm->qp[i]) & MGM_QPN_MASK;
356 if (!get_promisc_qp(dev, port, steer, qpn) && qpn != tqpn) {
357 /* the qp is not promisc, the entry can't be removed */
358 goto out;
359 }
360 }
361 /* All the qps currently registered for this entry are promiscuous,
362 * Checking for duplicates */
363 ret = true;
364 list_for_each_entry_safe(entry, tmp_entry, &s_steer->steer_entries[steer], list) {
365 if (entry->index == index) {
366 if (list_empty(&entry->duplicates) ||
367 members_count == 1) {
368 struct mlx4_promisc_qp *pqp, *tmp_pqp;
369 /* If there is only 1 entry in duplicates then
370 * this is the QP we want to delete, going over
371 * the list and deleting the entry.
372 */
373 list_del(&entry->list);
374 list_for_each_entry_safe(pqp, tmp_pqp,
375 &entry->duplicates,
376 list) {
377 list_del(&pqp->list);
378 kfree(pqp);
379 }
380 kfree(entry);
381 } else {
382 /* This entry contains duplicates so it shouldn't be removed */
383 ret = false;
384 goto out;
385 }
386 }
387 }
388
389 out:
390 mlx4_free_cmd_mailbox(dev, mailbox);
391 return ret;
392 }
393
394 static int add_promisc_qp(struct mlx4_dev *dev, u8 port,
395 enum mlx4_steer_type steer, u32 qpn)
396 {
397 struct mlx4_steer *s_steer;
398 struct mlx4_cmd_mailbox *mailbox;
399 struct mlx4_mgm *mgm;
400 struct mlx4_steer_index *entry;
401 struct mlx4_promisc_qp *pqp;
402 struct mlx4_promisc_qp *dqp;
403 u32 members_count;
404 u32 prot;
405 int i;
406 bool found;
407 int err;
408 struct mlx4_priv *priv = mlx4_priv(dev);
409
410 if (port < 1 || port > dev->caps.num_ports)
411 return -EINVAL;
412
413 s_steer = &mlx4_priv(dev)->steer[port - 1];
414
415 mutex_lock(&priv->mcg_table.mutex);
416
417 if (get_promisc_qp(dev, port, steer, qpn)) {
418 err = 0; /* Noting to do, already exists */
419 goto out_mutex;
420 }
421
422 pqp = kmalloc(sizeof *pqp, GFP_KERNEL);
423 if (!pqp) {
424 err = -ENOMEM;
425 goto out_mutex;
426 }
427 pqp->qpn = qpn;
428
429 mailbox = mlx4_alloc_cmd_mailbox(dev);
430 if (IS_ERR(mailbox)) {
431 err = -ENOMEM;
432 goto out_alloc;
433 }
434 mgm = mailbox->buf;
435
436 /* the promisc qp needs to be added for each one of the steering
437 * entries, if it already exists, needs to be added as a duplicate
438 * for this entry */
439 list_for_each_entry(entry, &s_steer->steer_entries[steer], list) {
440 err = mlx4_READ_ENTRY(dev, entry->index, mailbox);
441 if (err)
442 goto out_mailbox;
443
444 members_count = be32_to_cpu(mgm->members_count) & 0xffffff;
445 prot = be32_to_cpu(mgm->members_count) >> 30;
446 found = false;
447 for (i = 0; i < members_count; i++) {
448 if ((be32_to_cpu(mgm->qp[i]) & MGM_QPN_MASK) == qpn) {
449 /* Entry already exists, add to duplicates */
450 dqp = kmalloc(sizeof *dqp, GFP_KERNEL);
451 if (!dqp) {
452 err = -ENOMEM;
453 goto out_mailbox;
454 }
455 dqp->qpn = qpn;
456 list_add_tail(&dqp->list, &entry->duplicates);
457 found = true;
458 }
459 }
460 if (!found) {
461 /* Need to add the qpn to mgm */
462 if (members_count == dev->caps.num_qp_per_mgm) {
463 /* entry is full */
464 err = -ENOMEM;
465 goto out_mailbox;
466 }
467 mgm->qp[members_count++] = cpu_to_be32(qpn & MGM_QPN_MASK);
468 mgm->members_count = cpu_to_be32(members_count | (prot << 30));
469 err = mlx4_WRITE_ENTRY(dev, entry->index, mailbox);
470 if (err)
471 goto out_mailbox;
472 }
473 }
474
475 /* add the new qpn to list of promisc qps */
476 list_add_tail(&pqp->list, &s_steer->promisc_qps[steer]);
477 /* now need to add all the promisc qps to default entry */
478 memset(mgm, 0, sizeof *mgm);
479 members_count = 0;
480 list_for_each_entry(dqp, &s_steer->promisc_qps[steer], list)
481 mgm->qp[members_count++] = cpu_to_be32(dqp->qpn & MGM_QPN_MASK);
482 mgm->members_count = cpu_to_be32(members_count | MLX4_PROT_ETH << 30);
483
484 err = mlx4_WRITE_PROMISC(dev, port, steer, mailbox);
485 if (err)
486 goto out_list;
487
488 mlx4_free_cmd_mailbox(dev, mailbox);
489 mutex_unlock(&priv->mcg_table.mutex);
490 return 0;
491
492 out_list:
493 list_del(&pqp->list);
494 out_mailbox:
495 mlx4_free_cmd_mailbox(dev, mailbox);
496 out_alloc:
497 kfree(pqp);
498 out_mutex:
499 mutex_unlock(&priv->mcg_table.mutex);
500 return err;
501 }
502
503 static int remove_promisc_qp(struct mlx4_dev *dev, u8 port,
504 enum mlx4_steer_type steer, u32 qpn)
505 {
506 struct mlx4_priv *priv = mlx4_priv(dev);
507 struct mlx4_steer *s_steer;
508 struct mlx4_cmd_mailbox *mailbox;
509 struct mlx4_mgm *mgm;
510 struct mlx4_steer_index *entry;
511 struct mlx4_promisc_qp *pqp;
512 struct mlx4_promisc_qp *dqp;
513 u32 members_count;
514 bool found;
515 bool back_to_list = false;
516 int i;
517 int err;
518
519 if (port < 1 || port > dev->caps.num_ports)
520 return -EINVAL;
521
522 s_steer = &mlx4_priv(dev)->steer[port - 1];
523 mutex_lock(&priv->mcg_table.mutex);
524
525 pqp = get_promisc_qp(dev, port, steer, qpn);
526 if (unlikely(!pqp)) {
527 mlx4_warn(dev, "QP %x is not promiscuous QP\n", qpn);
528 /* nothing to do */
529 err = 0;
530 goto out_mutex;
531 }
532
533 /*remove from list of promisc qps */
534 list_del(&pqp->list);
535
536 /* set the default entry not to include the removed one */
537 mailbox = mlx4_alloc_cmd_mailbox(dev);
538 if (IS_ERR(mailbox)) {
539 err = -ENOMEM;
540 back_to_list = true;
541 goto out_list;
542 }
543 mgm = mailbox->buf;
544 members_count = 0;
545 list_for_each_entry(dqp, &s_steer->promisc_qps[steer], list)
546 mgm->qp[members_count++] = cpu_to_be32(dqp->qpn & MGM_QPN_MASK);
547 mgm->members_count = cpu_to_be32(members_count | MLX4_PROT_ETH << 30);
548
549 err = mlx4_WRITE_PROMISC(dev, port, steer, mailbox);
550 if (err)
551 goto out_mailbox;
552
553 /* remove the qp from all the steering entries*/
554 list_for_each_entry(entry, &s_steer->steer_entries[steer], list) {
555 found = false;
556 list_for_each_entry(dqp, &entry->duplicates, list) {
557 if (dqp->qpn == qpn) {
558 found = true;
559 break;
560 }
561 }
562 if (found) {
563 /* a duplicate, no need to change the mgm,
564 * only update the duplicates list */
565 list_del(&dqp->list);
566 kfree(dqp);
567 } else {
568 int loc = -1;
569 err = mlx4_READ_ENTRY(dev, entry->index, mailbox);
570 if (err)
571 goto out_mailbox;
572 members_count = be32_to_cpu(mgm->members_count) & 0xffffff;
573 for (i = 0; i < members_count; ++i)
574 if ((be32_to_cpu(mgm->qp[i]) &
575 MGM_QPN_MASK) == qpn) {
576 loc = i;
577 break;
578 }
579
580 if (loc < 0) {
581 mlx4_err(dev, "QP %06x wasn't found in entry %d\n",
582 qpn, entry->index);
583 err = -EINVAL;
584 goto out_mailbox;
585 }
586
587 /* copy the last QP in this MGM over removed QP */
588 mgm->qp[loc] = mgm->qp[members_count - 1];
589 mgm->qp[members_count - 1] = 0;
590 mgm->members_count = cpu_to_be32(--members_count |
591 (MLX4_PROT_ETH << 30));
592
593 err = mlx4_WRITE_ENTRY(dev, entry->index, mailbox);
594 if (err)
595 goto out_mailbox;
596 }
597
598 }
599
600 out_mailbox:
601 mlx4_free_cmd_mailbox(dev, mailbox);
602 out_list:
603 if (back_to_list)
604 list_add_tail(&pqp->list, &s_steer->promisc_qps[steer]);
605 else
606 kfree(pqp);
607 out_mutex:
608 mutex_unlock(&priv->mcg_table.mutex);
609 return err;
610 }
611
612 /*
613 * Caller must hold MCG table semaphore. gid and mgm parameters must
614 * be properly aligned for command interface.
615 *
616 * Returns 0 unless a firmware command error occurs.
617 *
618 * If GID is found in MGM or MGM is empty, *index = *hash, *prev = -1
619 * and *mgm holds MGM entry.
620 *
621 * if GID is found in AMGM, *index = index in AMGM, *prev = index of
622 * previous entry in hash chain and *mgm holds AMGM entry.
623 *
624 * If no AMGM exists for given gid, *index = -1, *prev = index of last
625 * entry in hash chain and *mgm holds end of hash chain.
626 */
627 static int find_entry(struct mlx4_dev *dev, u8 port,
628 u8 *gid, enum mlx4_protocol prot,
629 struct mlx4_cmd_mailbox *mgm_mailbox,
630 int *prev, int *index)
631 {
632 struct mlx4_cmd_mailbox *mailbox;
633 struct mlx4_mgm *mgm = mgm_mailbox->buf;
634 u8 *mgid;
635 int err;
636 u16 hash;
637 u8 op_mod = (prot == MLX4_PROT_ETH) ?
638 !!(dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER) : 0;
639
640 mailbox = mlx4_alloc_cmd_mailbox(dev);
641 if (IS_ERR(mailbox))
642 return -ENOMEM;
643 mgid = mailbox->buf;
644
645 memcpy(mgid, gid, 16);
646
647 err = mlx4_GID_HASH(dev, mailbox, &hash, op_mod);
648 mlx4_free_cmd_mailbox(dev, mailbox);
649 if (err)
650 return err;
651
652 if (0)
653 mlx4_dbg(dev, "Hash for %pI6 is %04x\n", gid, hash);
654
655 *index = hash;
656 *prev = -1;
657
658 do {
659 err = mlx4_READ_ENTRY(dev, *index, mgm_mailbox);
660 if (err)
661 return err;
662
663 if (!(be32_to_cpu(mgm->members_count) & 0xffffff)) {
664 if (*index != hash) {
665 mlx4_err(dev, "Found zero MGID in AMGM\n");
666 err = -EINVAL;
667 }
668 return err;
669 }
670
671 if (!memcmp(mgm->gid, gid, 16) &&
672 be32_to_cpu(mgm->members_count) >> 30 == prot)
673 return err;
674
675 *prev = *index;
676 *index = be32_to_cpu(mgm->next_gid_index) >> 6;
677 } while (*index);
678
679 *index = -1;
680 return err;
681 }
682
683 static const u8 __promisc_mode[] = {
684 [MLX4_FS_REGULAR] = 0x0,
685 [MLX4_FS_ALL_DEFAULT] = 0x1,
686 [MLX4_FS_MC_DEFAULT] = 0x3,
687 [MLX4_FS_UC_SNIFFER] = 0x4,
688 [MLX4_FS_MC_SNIFFER] = 0x5,
689 };
690
691 int mlx4_map_sw_to_hw_steering_mode(struct mlx4_dev *dev,
692 enum mlx4_net_trans_promisc_mode flow_type)
693 {
694 if (flow_type >= MLX4_FS_MODE_NUM) {
695 mlx4_err(dev, "Invalid flow type. type = %d\n", flow_type);
696 return -EINVAL;
697 }
698 return __promisc_mode[flow_type];
699 }
700 EXPORT_SYMBOL_GPL(mlx4_map_sw_to_hw_steering_mode);
701
702 static void trans_rule_ctrl_to_hw(struct mlx4_net_trans_rule *ctrl,
703 struct mlx4_net_trans_rule_hw_ctrl *hw)
704 {
705 u8 flags = 0;
706
707 flags = ctrl->queue_mode == MLX4_NET_TRANS_Q_LIFO ? 1 : 0;
708 flags |= ctrl->exclusive ? (1 << 2) : 0;
709 flags |= ctrl->allow_loopback ? (1 << 3) : 0;
710
711 hw->flags = flags;
712 hw->type = __promisc_mode[ctrl->promisc_mode];
713 hw->prio = cpu_to_be16(ctrl->priority);
714 hw->port = ctrl->port;
715 hw->qpn = cpu_to_be32(ctrl->qpn);
716 }
717
718 const u16 __sw_id_hw[] = {
719 [MLX4_NET_TRANS_RULE_ID_ETH] = 0xE001,
720 [MLX4_NET_TRANS_RULE_ID_IB] = 0xE005,
721 [MLX4_NET_TRANS_RULE_ID_IPV6] = 0xE003,
722 [MLX4_NET_TRANS_RULE_ID_IPV4] = 0xE002,
723 [MLX4_NET_TRANS_RULE_ID_TCP] = 0xE004,
724 [MLX4_NET_TRANS_RULE_ID_UDP] = 0xE006,
725 [MLX4_NET_TRANS_RULE_ID_VXLAN] = 0xE008
726 };
727
728 int mlx4_map_sw_to_hw_steering_id(struct mlx4_dev *dev,
729 enum mlx4_net_trans_rule_id id)
730 {
731 if (id >= MLX4_NET_TRANS_RULE_NUM) {
732 mlx4_err(dev, "Invalid network rule id. id = %d\n", id);
733 return -EINVAL;
734 }
735 return __sw_id_hw[id];
736 }
737 EXPORT_SYMBOL_GPL(mlx4_map_sw_to_hw_steering_id);
738
739 static const int __rule_hw_sz[] = {
740 [MLX4_NET_TRANS_RULE_ID_ETH] =
741 sizeof(struct mlx4_net_trans_rule_hw_eth),
742 [MLX4_NET_TRANS_RULE_ID_IB] =
743 sizeof(struct mlx4_net_trans_rule_hw_ib),
744 [MLX4_NET_TRANS_RULE_ID_IPV6] = 0,
745 [MLX4_NET_TRANS_RULE_ID_IPV4] =
746 sizeof(struct mlx4_net_trans_rule_hw_ipv4),
747 [MLX4_NET_TRANS_RULE_ID_TCP] =
748 sizeof(struct mlx4_net_trans_rule_hw_tcp_udp),
749 [MLX4_NET_TRANS_RULE_ID_UDP] =
750 sizeof(struct mlx4_net_trans_rule_hw_tcp_udp),
751 [MLX4_NET_TRANS_RULE_ID_VXLAN] =
752 sizeof(struct mlx4_net_trans_rule_hw_vxlan)
753 };
754
755 int mlx4_hw_rule_sz(struct mlx4_dev *dev,
756 enum mlx4_net_trans_rule_id id)
757 {
758 if (id >= MLX4_NET_TRANS_RULE_NUM) {
759 mlx4_err(dev, "Invalid network rule id. id = %d\n", id);
760 return -EINVAL;
761 }
762
763 return __rule_hw_sz[id];
764 }
765 EXPORT_SYMBOL_GPL(mlx4_hw_rule_sz);
766
767 static int parse_trans_rule(struct mlx4_dev *dev, struct mlx4_spec_list *spec,
768 struct _rule_hw *rule_hw)
769 {
770 if (mlx4_hw_rule_sz(dev, spec->id) < 0)
771 return -EINVAL;
772 memset(rule_hw, 0, mlx4_hw_rule_sz(dev, spec->id));
773 rule_hw->id = cpu_to_be16(__sw_id_hw[spec->id]);
774 rule_hw->size = mlx4_hw_rule_sz(dev, spec->id) >> 2;
775
776 switch (spec->id) {
777 case MLX4_NET_TRANS_RULE_ID_ETH:
778 memcpy(rule_hw->eth.dst_mac, spec->eth.dst_mac, ETH_ALEN);
779 memcpy(rule_hw->eth.dst_mac_msk, spec->eth.dst_mac_msk,
780 ETH_ALEN);
781 memcpy(rule_hw->eth.src_mac, spec->eth.src_mac, ETH_ALEN);
782 memcpy(rule_hw->eth.src_mac_msk, spec->eth.src_mac_msk,
783 ETH_ALEN);
784 if (spec->eth.ether_type_enable) {
785 rule_hw->eth.ether_type_enable = 1;
786 rule_hw->eth.ether_type = spec->eth.ether_type;
787 }
788 rule_hw->eth.vlan_tag = spec->eth.vlan_id;
789 rule_hw->eth.vlan_tag_msk = spec->eth.vlan_id_msk;
790 break;
791
792 case MLX4_NET_TRANS_RULE_ID_IB:
793 rule_hw->ib.l3_qpn = spec->ib.l3_qpn;
794 rule_hw->ib.qpn_mask = spec->ib.qpn_msk;
795 memcpy(&rule_hw->ib.dst_gid, &spec->ib.dst_gid, 16);
796 memcpy(&rule_hw->ib.dst_gid_msk, &spec->ib.dst_gid_msk, 16);
797 break;
798
799 case MLX4_NET_TRANS_RULE_ID_IPV6:
800 return -EOPNOTSUPP;
801
802 case MLX4_NET_TRANS_RULE_ID_IPV4:
803 rule_hw->ipv4.src_ip = spec->ipv4.src_ip;
804 rule_hw->ipv4.src_ip_msk = spec->ipv4.src_ip_msk;
805 rule_hw->ipv4.dst_ip = spec->ipv4.dst_ip;
806 rule_hw->ipv4.dst_ip_msk = spec->ipv4.dst_ip_msk;
807 break;
808
809 case MLX4_NET_TRANS_RULE_ID_TCP:
810 case MLX4_NET_TRANS_RULE_ID_UDP:
811 rule_hw->tcp_udp.dst_port = spec->tcp_udp.dst_port;
812 rule_hw->tcp_udp.dst_port_msk = spec->tcp_udp.dst_port_msk;
813 rule_hw->tcp_udp.src_port = spec->tcp_udp.src_port;
814 rule_hw->tcp_udp.src_port_msk = spec->tcp_udp.src_port_msk;
815 break;
816
817 case MLX4_NET_TRANS_RULE_ID_VXLAN:
818 rule_hw->vxlan.vni =
819 cpu_to_be32(be32_to_cpu(spec->vxlan.vni) << 8);
820 rule_hw->vxlan.vni_mask =
821 cpu_to_be32(be32_to_cpu(spec->vxlan.vni_mask) << 8);
822 break;
823
824 default:
825 return -EINVAL;
826 }
827
828 return __rule_hw_sz[spec->id];
829 }
830
831 static void mlx4_err_rule(struct mlx4_dev *dev, char *str,
832 struct mlx4_net_trans_rule *rule)
833 {
834 #define BUF_SIZE 256
835 struct mlx4_spec_list *cur;
836 char buf[BUF_SIZE];
837 int len = 0;
838
839 mlx4_err(dev, "%s", str);
840 len += snprintf(buf + len, BUF_SIZE - len,
841 "port = %d prio = 0x%x qp = 0x%x ",
842 rule->port, rule->priority, rule->qpn);
843
844 list_for_each_entry(cur, &rule->list, list) {
845 switch (cur->id) {
846 case MLX4_NET_TRANS_RULE_ID_ETH:
847 len += snprintf(buf + len, BUF_SIZE - len,
848 "dmac = %pM ", &cur->eth.dst_mac);
849 if (cur->eth.ether_type)
850 len += snprintf(buf + len, BUF_SIZE - len,
851 "ethertype = 0x%x ",
852 be16_to_cpu(cur->eth.ether_type));
853 if (cur->eth.vlan_id)
854 len += snprintf(buf + len, BUF_SIZE - len,
855 "vlan-id = %d ",
856 be16_to_cpu(cur->eth.vlan_id));
857 break;
858
859 case MLX4_NET_TRANS_RULE_ID_IPV4:
860 if (cur->ipv4.src_ip)
861 len += snprintf(buf + len, BUF_SIZE - len,
862 "src-ip = %pI4 ",
863 &cur->ipv4.src_ip);
864 if (cur->ipv4.dst_ip)
865 len += snprintf(buf + len, BUF_SIZE - len,
866 "dst-ip = %pI4 ",
867 &cur->ipv4.dst_ip);
868 break;
869
870 case MLX4_NET_TRANS_RULE_ID_TCP:
871 case MLX4_NET_TRANS_RULE_ID_UDP:
872 if (cur->tcp_udp.src_port)
873 len += snprintf(buf + len, BUF_SIZE - len,
874 "src-port = %d ",
875 be16_to_cpu(cur->tcp_udp.src_port));
876 if (cur->tcp_udp.dst_port)
877 len += snprintf(buf + len, BUF_SIZE - len,
878 "dst-port = %d ",
879 be16_to_cpu(cur->tcp_udp.dst_port));
880 break;
881
882 case MLX4_NET_TRANS_RULE_ID_IB:
883 len += snprintf(buf + len, BUF_SIZE - len,
884 "dst-gid = %pI6\n", cur->ib.dst_gid);
885 len += snprintf(buf + len, BUF_SIZE - len,
886 "dst-gid-mask = %pI6\n",
887 cur->ib.dst_gid_msk);
888 break;
889
890 case MLX4_NET_TRANS_RULE_ID_IPV6:
891 break;
892
893 default:
894 break;
895 }
896 }
897 len += snprintf(buf + len, BUF_SIZE - len, "\n");
898 mlx4_err(dev, "%s", buf);
899
900 if (len >= BUF_SIZE)
901 mlx4_err(dev, "Network rule error message was truncated, print buffer is too small\n");
902 }
903
904 int mlx4_flow_attach(struct mlx4_dev *dev,
905 struct mlx4_net_trans_rule *rule, u64 *reg_id)
906 {
907 struct mlx4_cmd_mailbox *mailbox;
908 struct mlx4_spec_list *cur;
909 u32 size = 0;
910 int ret;
911
912 mailbox = mlx4_alloc_cmd_mailbox(dev);
913 if (IS_ERR(mailbox))
914 return PTR_ERR(mailbox);
915
916 trans_rule_ctrl_to_hw(rule, mailbox->buf);
917
918 size += sizeof(struct mlx4_net_trans_rule_hw_ctrl);
919
920 list_for_each_entry(cur, &rule->list, list) {
921 ret = parse_trans_rule(dev, cur, mailbox->buf + size);
922 if (ret < 0) {
923 mlx4_free_cmd_mailbox(dev, mailbox);
924 return ret;
925 }
926 size += ret;
927 }
928
929 ret = mlx4_QP_FLOW_STEERING_ATTACH(dev, mailbox, size >> 2, reg_id);
930 if (ret == -ENOMEM)
931 mlx4_err_rule(dev,
932 "mcg table is full. Fail to register network rule\n",
933 rule);
934 else if (ret)
935 mlx4_err_rule(dev, "Fail to register network rule\n", rule);
936
937 mlx4_free_cmd_mailbox(dev, mailbox);
938
939 return ret;
940 }
941 EXPORT_SYMBOL_GPL(mlx4_flow_attach);
942
943 int mlx4_flow_detach(struct mlx4_dev *dev, u64 reg_id)
944 {
945 int err;
946
947 err = mlx4_QP_FLOW_STEERING_DETACH(dev, reg_id);
948 if (err)
949 mlx4_err(dev, "Fail to detach network rule. registration id = 0x%llx\n",
950 reg_id);
951 return err;
952 }
953 EXPORT_SYMBOL_GPL(mlx4_flow_detach);
954
955 int mlx4_FLOW_STEERING_IB_UC_QP_RANGE(struct mlx4_dev *dev, u32 min_range_qpn,
956 u32 max_range_qpn)
957 {
958 int err;
959 u64 in_param;
960
961 in_param = ((u64) min_range_qpn) << 32;
962 in_param |= ((u64) max_range_qpn) & 0xFFFFFFFF;
963
964 err = mlx4_cmd(dev, in_param, 0, 0,
965 MLX4_FLOW_STEERING_IB_UC_QP_RANGE,
966 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
967
968 return err;
969 }
970 EXPORT_SYMBOL_GPL(mlx4_FLOW_STEERING_IB_UC_QP_RANGE);
971
972 int mlx4_qp_attach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
973 int block_mcast_loopback, enum mlx4_protocol prot,
974 enum mlx4_steer_type steer)
975 {
976 struct mlx4_priv *priv = mlx4_priv(dev);
977 struct mlx4_cmd_mailbox *mailbox;
978 struct mlx4_mgm *mgm;
979 u32 members_count;
980 int index, prev;
981 int link = 0;
982 int i;
983 int err;
984 u8 port = gid[5];
985 u8 new_entry = 0;
986
987 mailbox = mlx4_alloc_cmd_mailbox(dev);
988 if (IS_ERR(mailbox))
989 return PTR_ERR(mailbox);
990 mgm = mailbox->buf;
991
992 mutex_lock(&priv->mcg_table.mutex);
993 err = find_entry(dev, port, gid, prot,
994 mailbox, &prev, &index);
995 if (err)
996 goto out;
997
998 if (index != -1) {
999 if (!(be32_to_cpu(mgm->members_count) & 0xffffff)) {
1000 new_entry = 1;
1001 memcpy(mgm->gid, gid, 16);
1002 }
1003 } else {
1004 link = 1;
1005
1006 index = mlx4_bitmap_alloc(&priv->mcg_table.bitmap);
1007 if (index == -1) {
1008 mlx4_err(dev, "No AMGM entries left\n");
1009 err = -ENOMEM;
1010 goto out;
1011 }
1012 index += dev->caps.num_mgms;
1013
1014 new_entry = 1;
1015 memset(mgm, 0, sizeof *mgm);
1016 memcpy(mgm->gid, gid, 16);
1017 }
1018
1019 members_count = be32_to_cpu(mgm->members_count) & 0xffffff;
1020 if (members_count == dev->caps.num_qp_per_mgm) {
1021 mlx4_err(dev, "MGM at index %x is full\n", index);
1022 err = -ENOMEM;
1023 goto out;
1024 }
1025
1026 for (i = 0; i < members_count; ++i)
1027 if ((be32_to_cpu(mgm->qp[i]) & MGM_QPN_MASK) == qp->qpn) {
1028 mlx4_dbg(dev, "QP %06x already a member of MGM\n", qp->qpn);
1029 err = 0;
1030 goto out;
1031 }
1032
1033 if (block_mcast_loopback)
1034 mgm->qp[members_count++] = cpu_to_be32((qp->qpn & MGM_QPN_MASK) |
1035 (1U << MGM_BLCK_LB_BIT));
1036 else
1037 mgm->qp[members_count++] = cpu_to_be32(qp->qpn & MGM_QPN_MASK);
1038
1039 mgm->members_count = cpu_to_be32(members_count | (u32) prot << 30);
1040
1041 err = mlx4_WRITE_ENTRY(dev, index, mailbox);
1042 if (err)
1043 goto out;
1044
1045 if (!link)
1046 goto out;
1047
1048 err = mlx4_READ_ENTRY(dev, prev, mailbox);
1049 if (err)
1050 goto out;
1051
1052 mgm->next_gid_index = cpu_to_be32(index << 6);
1053
1054 err = mlx4_WRITE_ENTRY(dev, prev, mailbox);
1055 if (err)
1056 goto out;
1057
1058 out:
1059 if (prot == MLX4_PROT_ETH) {
1060 /* manage the steering entry for promisc mode */
1061 if (new_entry)
1062 new_steering_entry(dev, port, steer, index, qp->qpn);
1063 else
1064 existing_steering_entry(dev, port, steer,
1065 index, qp->qpn);
1066 }
1067 if (err && link && index != -1) {
1068 if (index < dev->caps.num_mgms)
1069 mlx4_warn(dev, "Got AMGM index %d < %d\n",
1070 index, dev->caps.num_mgms);
1071 else
1072 mlx4_bitmap_free(&priv->mcg_table.bitmap,
1073 index - dev->caps.num_mgms, MLX4_USE_RR);
1074 }
1075 mutex_unlock(&priv->mcg_table.mutex);
1076
1077 mlx4_free_cmd_mailbox(dev, mailbox);
1078 return err;
1079 }
1080
1081 int mlx4_qp_detach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1082 enum mlx4_protocol prot, enum mlx4_steer_type steer)
1083 {
1084 struct mlx4_priv *priv = mlx4_priv(dev);
1085 struct mlx4_cmd_mailbox *mailbox;
1086 struct mlx4_mgm *mgm;
1087 u32 members_count;
1088 int prev, index;
1089 int i, loc = -1;
1090 int err;
1091 u8 port = gid[5];
1092 bool removed_entry = false;
1093
1094 mailbox = mlx4_alloc_cmd_mailbox(dev);
1095 if (IS_ERR(mailbox))
1096 return PTR_ERR(mailbox);
1097 mgm = mailbox->buf;
1098
1099 mutex_lock(&priv->mcg_table.mutex);
1100
1101 err = find_entry(dev, port, gid, prot,
1102 mailbox, &prev, &index);
1103 if (err)
1104 goto out;
1105
1106 if (index == -1) {
1107 mlx4_err(dev, "MGID %pI6 not found\n", gid);
1108 err = -EINVAL;
1109 goto out;
1110 }
1111
1112 /* if this pq is also a promisc qp, it shouldn't be removed */
1113 if (prot == MLX4_PROT_ETH &&
1114 check_duplicate_entry(dev, port, steer, index, qp->qpn))
1115 goto out;
1116
1117 members_count = be32_to_cpu(mgm->members_count) & 0xffffff;
1118 for (i = 0; i < members_count; ++i)
1119 if ((be32_to_cpu(mgm->qp[i]) & MGM_QPN_MASK) == qp->qpn) {
1120 loc = i;
1121 break;
1122 }
1123
1124 if (loc == -1) {
1125 mlx4_err(dev, "QP %06x not found in MGM\n", qp->qpn);
1126 err = -EINVAL;
1127 goto out;
1128 }
1129
1130 /* copy the last QP in this MGM over removed QP */
1131 mgm->qp[loc] = mgm->qp[members_count - 1];
1132 mgm->qp[members_count - 1] = 0;
1133 mgm->members_count = cpu_to_be32(--members_count | (u32) prot << 30);
1134
1135 if (prot == MLX4_PROT_ETH)
1136 removed_entry = can_remove_steering_entry(dev, port, steer,
1137 index, qp->qpn);
1138 if (members_count && (prot != MLX4_PROT_ETH || !removed_entry)) {
1139 err = mlx4_WRITE_ENTRY(dev, index, mailbox);
1140 goto out;
1141 }
1142
1143 /* We are going to delete the entry, members count should be 0 */
1144 mgm->members_count = cpu_to_be32((u32) prot << 30);
1145
1146 if (prev == -1) {
1147 /* Remove entry from MGM */
1148 int amgm_index = be32_to_cpu(mgm->next_gid_index) >> 6;
1149 if (amgm_index) {
1150 err = mlx4_READ_ENTRY(dev, amgm_index, mailbox);
1151 if (err)
1152 goto out;
1153 } else
1154 memset(mgm->gid, 0, 16);
1155
1156 err = mlx4_WRITE_ENTRY(dev, index, mailbox);
1157 if (err)
1158 goto out;
1159
1160 if (amgm_index) {
1161 if (amgm_index < dev->caps.num_mgms)
1162 mlx4_warn(dev, "MGM entry %d had AMGM index %d < %d\n",
1163 index, amgm_index, dev->caps.num_mgms);
1164 else
1165 mlx4_bitmap_free(&priv->mcg_table.bitmap,
1166 amgm_index - dev->caps.num_mgms, MLX4_USE_RR);
1167 }
1168 } else {
1169 /* Remove entry from AMGM */
1170 int cur_next_index = be32_to_cpu(mgm->next_gid_index) >> 6;
1171 err = mlx4_READ_ENTRY(dev, prev, mailbox);
1172 if (err)
1173 goto out;
1174
1175 mgm->next_gid_index = cpu_to_be32(cur_next_index << 6);
1176
1177 err = mlx4_WRITE_ENTRY(dev, prev, mailbox);
1178 if (err)
1179 goto out;
1180
1181 if (index < dev->caps.num_mgms)
1182 mlx4_warn(dev, "entry %d had next AMGM index %d < %d\n",
1183 prev, index, dev->caps.num_mgms);
1184 else
1185 mlx4_bitmap_free(&priv->mcg_table.bitmap,
1186 index - dev->caps.num_mgms, MLX4_USE_RR);
1187 }
1188
1189 out:
1190 mutex_unlock(&priv->mcg_table.mutex);
1191
1192 mlx4_free_cmd_mailbox(dev, mailbox);
1193 return err;
1194 }
1195
1196 static int mlx4_QP_ATTACH(struct mlx4_dev *dev, struct mlx4_qp *qp,
1197 u8 gid[16], u8 attach, u8 block_loopback,
1198 enum mlx4_protocol prot)
1199 {
1200 struct mlx4_cmd_mailbox *mailbox;
1201 int err = 0;
1202 int qpn;
1203
1204 if (!mlx4_is_mfunc(dev))
1205 return -EBADF;
1206
1207 mailbox = mlx4_alloc_cmd_mailbox(dev);
1208 if (IS_ERR(mailbox))
1209 return PTR_ERR(mailbox);
1210
1211 memcpy(mailbox->buf, gid, 16);
1212 qpn = qp->qpn;
1213 qpn |= (prot << 28);
1214 if (attach && block_loopback)
1215 qpn |= (1 << 31);
1216
1217 err = mlx4_cmd(dev, mailbox->dma, qpn, attach,
1218 MLX4_CMD_QP_ATTACH, MLX4_CMD_TIME_CLASS_A,
1219 MLX4_CMD_WRAPPED);
1220
1221 mlx4_free_cmd_mailbox(dev, mailbox);
1222 return err;
1223 }
1224
1225 int mlx4_trans_to_dmfs_attach(struct mlx4_dev *dev, struct mlx4_qp *qp,
1226 u8 gid[16], u8 port,
1227 int block_mcast_loopback,
1228 enum mlx4_protocol prot, u64 *reg_id)
1229 {
1230 struct mlx4_spec_list spec = { {NULL} };
1231 __be64 mac_mask = cpu_to_be64(MLX4_MAC_MASK << 16);
1232
1233 struct mlx4_net_trans_rule rule = {
1234 .queue_mode = MLX4_NET_TRANS_Q_FIFO,
1235 .exclusive = 0,
1236 .promisc_mode = MLX4_FS_REGULAR,
1237 .priority = MLX4_DOMAIN_NIC,
1238 };
1239
1240 rule.allow_loopback = !block_mcast_loopback;
1241 rule.port = port;
1242 rule.qpn = qp->qpn;
1243 INIT_LIST_HEAD(&rule.list);
1244
1245 switch (prot) {
1246 case MLX4_PROT_ETH:
1247 spec.id = MLX4_NET_TRANS_RULE_ID_ETH;
1248 memcpy(spec.eth.dst_mac, &gid[10], ETH_ALEN);
1249 memcpy(spec.eth.dst_mac_msk, &mac_mask, ETH_ALEN);
1250 break;
1251
1252 case MLX4_PROT_IB_IPV6:
1253 spec.id = MLX4_NET_TRANS_RULE_ID_IB;
1254 memcpy(spec.ib.dst_gid, gid, 16);
1255 memset(&spec.ib.dst_gid_msk, 0xff, 16);
1256 break;
1257 default:
1258 return -EINVAL;
1259 }
1260 list_add_tail(&spec.list, &rule.list);
1261
1262 return mlx4_flow_attach(dev, &rule, reg_id);
1263 }
1264
1265 int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1266 u8 port, int block_mcast_loopback,
1267 enum mlx4_protocol prot, u64 *reg_id)
1268 {
1269 switch (dev->caps.steering_mode) {
1270 case MLX4_STEERING_MODE_A0:
1271 if (prot == MLX4_PROT_ETH)
1272 return 0;
1273
1274 case MLX4_STEERING_MODE_B0:
1275 if (prot == MLX4_PROT_ETH)
1276 gid[7] |= (MLX4_MC_STEER << 1);
1277
1278 if (mlx4_is_mfunc(dev))
1279 return mlx4_QP_ATTACH(dev, qp, gid, 1,
1280 block_mcast_loopback, prot);
1281 return mlx4_qp_attach_common(dev, qp, gid,
1282 block_mcast_loopback, prot,
1283 MLX4_MC_STEER);
1284
1285 case MLX4_STEERING_MODE_DEVICE_MANAGED:
1286 return mlx4_trans_to_dmfs_attach(dev, qp, gid, port,
1287 block_mcast_loopback,
1288 prot, reg_id);
1289 default:
1290 return -EINVAL;
1291 }
1292 }
1293 EXPORT_SYMBOL_GPL(mlx4_multicast_attach);
1294
1295 int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1296 enum mlx4_protocol prot, u64 reg_id)
1297 {
1298 switch (dev->caps.steering_mode) {
1299 case MLX4_STEERING_MODE_A0:
1300 if (prot == MLX4_PROT_ETH)
1301 return 0;
1302
1303 case MLX4_STEERING_MODE_B0:
1304 if (prot == MLX4_PROT_ETH)
1305 gid[7] |= (MLX4_MC_STEER << 1);
1306
1307 if (mlx4_is_mfunc(dev))
1308 return mlx4_QP_ATTACH(dev, qp, gid, 0, 0, prot);
1309
1310 return mlx4_qp_detach_common(dev, qp, gid, prot,
1311 MLX4_MC_STEER);
1312
1313 case MLX4_STEERING_MODE_DEVICE_MANAGED:
1314 return mlx4_flow_detach(dev, reg_id);
1315
1316 default:
1317 return -EINVAL;
1318 }
1319 }
1320 EXPORT_SYMBOL_GPL(mlx4_multicast_detach);
1321
1322 int mlx4_flow_steer_promisc_add(struct mlx4_dev *dev, u8 port,
1323 u32 qpn, enum mlx4_net_trans_promisc_mode mode)
1324 {
1325 struct mlx4_net_trans_rule rule;
1326 u64 *regid_p;
1327
1328 switch (mode) {
1329 case MLX4_FS_ALL_DEFAULT:
1330 regid_p = &dev->regid_promisc_array[port];
1331 break;
1332 case MLX4_FS_MC_DEFAULT:
1333 regid_p = &dev->regid_allmulti_array[port];
1334 break;
1335 default:
1336 return -1;
1337 }
1338
1339 if (*regid_p != 0)
1340 return -1;
1341
1342 rule.promisc_mode = mode;
1343 rule.port = port;
1344 rule.qpn = qpn;
1345 INIT_LIST_HEAD(&rule.list);
1346 mlx4_err(dev, "going promisc on %x\n", port);
1347
1348 return mlx4_flow_attach(dev, &rule, regid_p);
1349 }
1350 EXPORT_SYMBOL_GPL(mlx4_flow_steer_promisc_add);
1351
1352 int mlx4_flow_steer_promisc_remove(struct mlx4_dev *dev, u8 port,
1353 enum mlx4_net_trans_promisc_mode mode)
1354 {
1355 int ret;
1356 u64 *regid_p;
1357
1358 switch (mode) {
1359 case MLX4_FS_ALL_DEFAULT:
1360 regid_p = &dev->regid_promisc_array[port];
1361 break;
1362 case MLX4_FS_MC_DEFAULT:
1363 regid_p = &dev->regid_allmulti_array[port];
1364 break;
1365 default:
1366 return -1;
1367 }
1368
1369 if (*regid_p == 0)
1370 return -1;
1371
1372 ret = mlx4_flow_detach(dev, *regid_p);
1373 if (ret == 0)
1374 *regid_p = 0;
1375
1376 return ret;
1377 }
1378 EXPORT_SYMBOL_GPL(mlx4_flow_steer_promisc_remove);
1379
1380 int mlx4_unicast_attach(struct mlx4_dev *dev,
1381 struct mlx4_qp *qp, u8 gid[16],
1382 int block_mcast_loopback, enum mlx4_protocol prot)
1383 {
1384 if (prot == MLX4_PROT_ETH)
1385 gid[7] |= (MLX4_UC_STEER << 1);
1386
1387 if (mlx4_is_mfunc(dev))
1388 return mlx4_QP_ATTACH(dev, qp, gid, 1,
1389 block_mcast_loopback, prot);
1390
1391 return mlx4_qp_attach_common(dev, qp, gid, block_mcast_loopback,
1392 prot, MLX4_UC_STEER);
1393 }
1394 EXPORT_SYMBOL_GPL(mlx4_unicast_attach);
1395
1396 int mlx4_unicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp,
1397 u8 gid[16], enum mlx4_protocol prot)
1398 {
1399 if (prot == MLX4_PROT_ETH)
1400 gid[7] |= (MLX4_UC_STEER << 1);
1401
1402 if (mlx4_is_mfunc(dev))
1403 return mlx4_QP_ATTACH(dev, qp, gid, 0, 0, prot);
1404
1405 return mlx4_qp_detach_common(dev, qp, gid, prot, MLX4_UC_STEER);
1406 }
1407 EXPORT_SYMBOL_GPL(mlx4_unicast_detach);
1408
1409 int mlx4_PROMISC_wrapper(struct mlx4_dev *dev, int slave,
1410 struct mlx4_vhcr *vhcr,
1411 struct mlx4_cmd_mailbox *inbox,
1412 struct mlx4_cmd_mailbox *outbox,
1413 struct mlx4_cmd_info *cmd)
1414 {
1415 u32 qpn = (u32) vhcr->in_param & 0xffffffff;
1416 int port = mlx4_slave_convert_port(dev, slave, vhcr->in_param >> 62);
1417 enum mlx4_steer_type steer = vhcr->in_modifier;
1418
1419 if (port < 0)
1420 return -EINVAL;
1421
1422 /* Promiscuous unicast is not allowed in mfunc */
1423 if (mlx4_is_mfunc(dev) && steer == MLX4_UC_STEER)
1424 return 0;
1425
1426 if (vhcr->op_modifier)
1427 return add_promisc_qp(dev, port, steer, qpn);
1428 else
1429 return remove_promisc_qp(dev, port, steer, qpn);
1430 }
1431
1432 static int mlx4_PROMISC(struct mlx4_dev *dev, u32 qpn,
1433 enum mlx4_steer_type steer, u8 add, u8 port)
1434 {
1435 return mlx4_cmd(dev, (u64) qpn | (u64) port << 62, (u32) steer, add,
1436 MLX4_CMD_PROMISC, MLX4_CMD_TIME_CLASS_A,
1437 MLX4_CMD_WRAPPED);
1438 }
1439
1440 int mlx4_multicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port)
1441 {
1442 if (mlx4_is_mfunc(dev))
1443 return mlx4_PROMISC(dev, qpn, MLX4_MC_STEER, 1, port);
1444
1445 return add_promisc_qp(dev, port, MLX4_MC_STEER, qpn);
1446 }
1447 EXPORT_SYMBOL_GPL(mlx4_multicast_promisc_add);
1448
1449 int mlx4_multicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port)
1450 {
1451 if (mlx4_is_mfunc(dev))
1452 return mlx4_PROMISC(dev, qpn, MLX4_MC_STEER, 0, port);
1453
1454 return remove_promisc_qp(dev, port, MLX4_MC_STEER, qpn);
1455 }
1456 EXPORT_SYMBOL_GPL(mlx4_multicast_promisc_remove);
1457
1458 int mlx4_unicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port)
1459 {
1460 if (mlx4_is_mfunc(dev))
1461 return mlx4_PROMISC(dev, qpn, MLX4_UC_STEER, 1, port);
1462
1463 return add_promisc_qp(dev, port, MLX4_UC_STEER, qpn);
1464 }
1465 EXPORT_SYMBOL_GPL(mlx4_unicast_promisc_add);
1466
1467 int mlx4_unicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port)
1468 {
1469 if (mlx4_is_mfunc(dev))
1470 return mlx4_PROMISC(dev, qpn, MLX4_UC_STEER, 0, port);
1471
1472 return remove_promisc_qp(dev, port, MLX4_UC_STEER, qpn);
1473 }
1474 EXPORT_SYMBOL_GPL(mlx4_unicast_promisc_remove);
1475
1476 int mlx4_init_mcg_table(struct mlx4_dev *dev)
1477 {
1478 struct mlx4_priv *priv = mlx4_priv(dev);
1479 int err;
1480
1481 /* No need for mcg_table when fw managed the mcg table*/
1482 if (dev->caps.steering_mode ==
1483 MLX4_STEERING_MODE_DEVICE_MANAGED)
1484 return 0;
1485 err = mlx4_bitmap_init(&priv->mcg_table.bitmap, dev->caps.num_amgms,
1486 dev->caps.num_amgms - 1, 0, 0);
1487 if (err)
1488 return err;
1489
1490 mutex_init(&priv->mcg_table.mutex);
1491
1492 return 0;
1493 }
1494
1495 void mlx4_cleanup_mcg_table(struct mlx4_dev *dev)
1496 {
1497 if (dev->caps.steering_mode !=
1498 MLX4_STEERING_MODE_DEVICE_MANAGED)
1499 mlx4_bitmap_cleanup(&mlx4_priv(dev)->mcg_table.bitmap);
1500 }
Linux kernel - Deliverables
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