2 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 #include <linux/string.h>
35 #include <linux/etherdevice.h>
37 #include <linux/mlx4/cmd.h>
38 #include <linux/export.h>
42 static const u8 zero_gid
[16]; /* automatically initialized to 0 */
44 int mlx4_get_mgm_entry_size(struct mlx4_dev
*dev
)
46 return 1 << dev
->oper_log_mgm_entry_size
;
49 int mlx4_get_qp_per_mgm(struct mlx4_dev
*dev
)
51 return 4 * (mlx4_get_mgm_entry_size(dev
) / 16 - 2);
54 static int mlx4_QP_FLOW_STEERING_ATTACH(struct mlx4_dev
*dev
,
55 struct mlx4_cmd_mailbox
*mailbox
,
62 err
= mlx4_cmd_imm(dev
, mailbox
->dma
, &imm
, size
, 0,
63 MLX4_QP_FLOW_STEERING_ATTACH
, MLX4_CMD_TIME_CLASS_A
,
72 static int mlx4_QP_FLOW_STEERING_DETACH(struct mlx4_dev
*dev
, u64 regid
)
76 err
= mlx4_cmd(dev
, regid
, 0, 0,
77 MLX4_QP_FLOW_STEERING_DETACH
, MLX4_CMD_TIME_CLASS_A
,
83 static int mlx4_READ_ENTRY(struct mlx4_dev
*dev
, int index
,
84 struct mlx4_cmd_mailbox
*mailbox
)
86 return mlx4_cmd_box(dev
, 0, mailbox
->dma
, index
, 0, MLX4_CMD_READ_MCG
,
87 MLX4_CMD_TIME_CLASS_A
, MLX4_CMD_NATIVE
);
90 static int mlx4_WRITE_ENTRY(struct mlx4_dev
*dev
, int index
,
91 struct mlx4_cmd_mailbox
*mailbox
)
93 return mlx4_cmd(dev
, mailbox
->dma
, index
, 0, MLX4_CMD_WRITE_MCG
,
94 MLX4_CMD_TIME_CLASS_A
, MLX4_CMD_NATIVE
);
97 static int mlx4_WRITE_PROMISC(struct mlx4_dev
*dev
, u8 port
, u8 steer
,
98 struct mlx4_cmd_mailbox
*mailbox
)
102 in_mod
= (u32
) port
<< 16 | steer
<< 1;
103 return mlx4_cmd(dev
, mailbox
->dma
, in_mod
, 0x1,
104 MLX4_CMD_WRITE_MCG
, MLX4_CMD_TIME_CLASS_A
,
108 static int mlx4_GID_HASH(struct mlx4_dev
*dev
, struct mlx4_cmd_mailbox
*mailbox
,
109 u16
*hash
, u8 op_mod
)
114 err
= mlx4_cmd_imm(dev
, mailbox
->dma
, &imm
, 0, op_mod
,
115 MLX4_CMD_MGID_HASH
, MLX4_CMD_TIME_CLASS_A
,
124 static struct mlx4_promisc_qp
*get_promisc_qp(struct mlx4_dev
*dev
, u8 port
,
125 enum mlx4_steer_type steer
,
128 struct mlx4_steer
*s_steer
;
129 struct mlx4_promisc_qp
*pqp
;
131 if (port
< 1 || port
> dev
->caps
.num_ports
)
134 s_steer
= &mlx4_priv(dev
)->steer
[port
- 1];
136 list_for_each_entry(pqp
, &s_steer
->promisc_qps
[steer
], list
) {
145 * Add new entry to steering data structure.
146 * All promisc QPs should be added as well
148 static int new_steering_entry(struct mlx4_dev
*dev
, u8 port
,
149 enum mlx4_steer_type steer
,
150 unsigned int index
, u32 qpn
)
152 struct mlx4_steer
*s_steer
;
153 struct mlx4_cmd_mailbox
*mailbox
;
154 struct mlx4_mgm
*mgm
;
156 struct mlx4_steer_index
*new_entry
;
157 struct mlx4_promisc_qp
*pqp
;
158 struct mlx4_promisc_qp
*dqp
= NULL
;
162 if (port
< 1 || port
> dev
->caps
.num_ports
)
165 s_steer
= &mlx4_priv(dev
)->steer
[port
- 1];
166 new_entry
= kzalloc(sizeof *new_entry
, GFP_KERNEL
);
170 INIT_LIST_HEAD(&new_entry
->duplicates
);
171 new_entry
->index
= index
;
172 list_add_tail(&new_entry
->list
, &s_steer
->steer_entries
[steer
]);
174 /* If the given qpn is also a promisc qp,
175 * it should be inserted to duplicates list
177 pqp
= get_promisc_qp(dev
, port
, steer
, qpn
);
179 dqp
= kmalloc(sizeof *dqp
, GFP_KERNEL
);
185 list_add_tail(&dqp
->list
, &new_entry
->duplicates
);
188 /* if no promisc qps for this vep, we are done */
189 if (list_empty(&s_steer
->promisc_qps
[steer
]))
192 /* now need to add all the promisc qps to the new
193 * steering entry, as they should also receive the packets
194 * destined to this address */
195 mailbox
= mlx4_alloc_cmd_mailbox(dev
);
196 if (IS_ERR(mailbox
)) {
202 err
= mlx4_READ_ENTRY(dev
, index
, mailbox
);
206 members_count
= be32_to_cpu(mgm
->members_count
) & 0xffffff;
207 prot
= be32_to_cpu(mgm
->members_count
) >> 30;
208 list_for_each_entry(pqp
, &s_steer
->promisc_qps
[steer
], list
) {
209 /* don't add already existing qpn */
212 if (members_count
== dev
->caps
.num_qp_per_mgm
) {
219 mgm
->qp
[members_count
++] = cpu_to_be32(pqp
->qpn
& MGM_QPN_MASK
);
221 /* update the qps count and update the entry with all the promisc qps*/
222 mgm
->members_count
= cpu_to_be32(members_count
| (prot
<< 30));
223 err
= mlx4_WRITE_ENTRY(dev
, index
, mailbox
);
226 mlx4_free_cmd_mailbox(dev
, mailbox
);
231 list_del(&dqp
->list
);
234 list_del(&new_entry
->list
);
239 /* update the data structures with existing steering entry */
240 static int existing_steering_entry(struct mlx4_dev
*dev
, u8 port
,
241 enum mlx4_steer_type steer
,
242 unsigned int index
, u32 qpn
)
244 struct mlx4_steer
*s_steer
;
245 struct mlx4_steer_index
*tmp_entry
, *entry
= NULL
;
246 struct mlx4_promisc_qp
*pqp
;
247 struct mlx4_promisc_qp
*dqp
;
249 if (port
< 1 || port
> dev
->caps
.num_ports
)
252 s_steer
= &mlx4_priv(dev
)->steer
[port
- 1];
254 pqp
= get_promisc_qp(dev
, port
, steer
, qpn
);
256 return 0; /* nothing to do */
258 list_for_each_entry(tmp_entry
, &s_steer
->steer_entries
[steer
], list
) {
259 if (tmp_entry
->index
== index
) {
264 if (unlikely(!entry
)) {
265 mlx4_warn(dev
, "Steering entry at index %x is not registered\n", index
);
269 /* the given qpn is listed as a promisc qpn
270 * we need to add it as a duplicate to this entry
271 * for future references */
272 list_for_each_entry(dqp
, &entry
->duplicates
, list
) {
274 return 0; /* qp is already duplicated */
277 /* add the qp as a duplicate on this index */
278 dqp
= kmalloc(sizeof *dqp
, GFP_KERNEL
);
282 list_add_tail(&dqp
->list
, &entry
->duplicates
);
287 /* Check whether a qpn is a duplicate on steering entry
288 * If so, it should not be removed from mgm */
289 static bool check_duplicate_entry(struct mlx4_dev
*dev
, u8 port
,
290 enum mlx4_steer_type steer
,
291 unsigned int index
, u32 qpn
)
293 struct mlx4_steer
*s_steer
;
294 struct mlx4_steer_index
*tmp_entry
, *entry
= NULL
;
295 struct mlx4_promisc_qp
*dqp
, *tmp_dqp
;
297 if (port
< 1 || port
> dev
->caps
.num_ports
)
300 s_steer
= &mlx4_priv(dev
)->steer
[port
- 1];
302 /* if qp is not promisc, it cannot be duplicated */
303 if (!get_promisc_qp(dev
, port
, steer
, qpn
))
306 /* The qp is promisc qp so it is a duplicate on this index
307 * Find the index entry, and remove the duplicate */
308 list_for_each_entry(tmp_entry
, &s_steer
->steer_entries
[steer
], list
) {
309 if (tmp_entry
->index
== index
) {
314 if (unlikely(!entry
)) {
315 mlx4_warn(dev
, "Steering entry for index %x is not registered\n", index
);
318 list_for_each_entry_safe(dqp
, tmp_dqp
, &entry
->duplicates
, list
) {
319 if (dqp
->qpn
== qpn
) {
320 list_del(&dqp
->list
);
327 /* I a steering entry contains only promisc QPs, it can be removed. */
328 static bool can_remove_steering_entry(struct mlx4_dev
*dev
, u8 port
,
329 enum mlx4_steer_type steer
,
330 unsigned int index
, u32 tqpn
)
332 struct mlx4_steer
*s_steer
;
333 struct mlx4_cmd_mailbox
*mailbox
;
334 struct mlx4_mgm
*mgm
;
335 struct mlx4_steer_index
*entry
= NULL
, *tmp_entry
;
341 if (port
< 1 || port
> dev
->caps
.num_ports
)
344 s_steer
= &mlx4_priv(dev
)->steer
[port
- 1];
346 mailbox
= mlx4_alloc_cmd_mailbox(dev
);
351 if (mlx4_READ_ENTRY(dev
, index
, mailbox
))
353 members_count
= be32_to_cpu(mgm
->members_count
) & 0xffffff;
354 for (i
= 0; i
< members_count
; i
++) {
355 qpn
= be32_to_cpu(mgm
->qp
[i
]) & MGM_QPN_MASK
;
356 if (!get_promisc_qp(dev
, port
, steer
, qpn
) && qpn
!= tqpn
) {
357 /* the qp is not promisc, the entry can't be removed */
361 /* All the qps currently registered for this entry are promiscuous,
362 * Checking for duplicates */
364 list_for_each_entry_safe(entry
, tmp_entry
, &s_steer
->steer_entries
[steer
], list
) {
365 if (entry
->index
== index
) {
366 if (list_empty(&entry
->duplicates
)) {
367 list_del(&entry
->list
);
370 /* This entry contains duplicates so it shouldn't be removed */
378 mlx4_free_cmd_mailbox(dev
, mailbox
);
382 static int add_promisc_qp(struct mlx4_dev
*dev
, u8 port
,
383 enum mlx4_steer_type steer
, u32 qpn
)
385 struct mlx4_steer
*s_steer
;
386 struct mlx4_cmd_mailbox
*mailbox
;
387 struct mlx4_mgm
*mgm
;
388 struct mlx4_steer_index
*entry
;
389 struct mlx4_promisc_qp
*pqp
;
390 struct mlx4_promisc_qp
*dqp
;
396 struct mlx4_priv
*priv
= mlx4_priv(dev
);
398 if (port
< 1 || port
> dev
->caps
.num_ports
)
401 s_steer
= &mlx4_priv(dev
)->steer
[port
- 1];
403 mutex_lock(&priv
->mcg_table
.mutex
);
405 if (get_promisc_qp(dev
, port
, steer
, qpn
)) {
406 err
= 0; /* Noting to do, already exists */
410 pqp
= kmalloc(sizeof *pqp
, GFP_KERNEL
);
417 mailbox
= mlx4_alloc_cmd_mailbox(dev
);
418 if (IS_ERR(mailbox
)) {
424 /* the promisc qp needs to be added for each one of the steering
425 * entries, if it already exists, needs to be added as a duplicate
427 list_for_each_entry(entry
, &s_steer
->steer_entries
[steer
], list
) {
428 err
= mlx4_READ_ENTRY(dev
, entry
->index
, mailbox
);
432 members_count
= be32_to_cpu(mgm
->members_count
) & 0xffffff;
433 prot
= be32_to_cpu(mgm
->members_count
) >> 30;
435 for (i
= 0; i
< members_count
; i
++) {
436 if ((be32_to_cpu(mgm
->qp
[i
]) & MGM_QPN_MASK
) == qpn
) {
437 /* Entry already exists, add to duplicates */
438 dqp
= kmalloc(sizeof *dqp
, GFP_KERNEL
);
444 list_add_tail(&dqp
->list
, &entry
->duplicates
);
449 /* Need to add the qpn to mgm */
450 if (members_count
== dev
->caps
.num_qp_per_mgm
) {
455 mgm
->qp
[members_count
++] = cpu_to_be32(qpn
& MGM_QPN_MASK
);
456 mgm
->members_count
= cpu_to_be32(members_count
| (prot
<< 30));
457 err
= mlx4_WRITE_ENTRY(dev
, entry
->index
, mailbox
);
463 /* add the new qpn to list of promisc qps */
464 list_add_tail(&pqp
->list
, &s_steer
->promisc_qps
[steer
]);
465 /* now need to add all the promisc qps to default entry */
466 memset(mgm
, 0, sizeof *mgm
);
468 list_for_each_entry(dqp
, &s_steer
->promisc_qps
[steer
], list
)
469 mgm
->qp
[members_count
++] = cpu_to_be32(dqp
->qpn
& MGM_QPN_MASK
);
470 mgm
->members_count
= cpu_to_be32(members_count
| MLX4_PROT_ETH
<< 30);
472 err
= mlx4_WRITE_PROMISC(dev
, port
, steer
, mailbox
);
476 mlx4_free_cmd_mailbox(dev
, mailbox
);
477 mutex_unlock(&priv
->mcg_table
.mutex
);
481 list_del(&pqp
->list
);
483 mlx4_free_cmd_mailbox(dev
, mailbox
);
487 mutex_unlock(&priv
->mcg_table
.mutex
);
491 static int remove_promisc_qp(struct mlx4_dev
*dev
, u8 port
,
492 enum mlx4_steer_type steer
, u32 qpn
)
494 struct mlx4_priv
*priv
= mlx4_priv(dev
);
495 struct mlx4_steer
*s_steer
;
496 struct mlx4_cmd_mailbox
*mailbox
;
497 struct mlx4_mgm
*mgm
;
498 struct mlx4_steer_index
*entry
;
499 struct mlx4_promisc_qp
*pqp
;
500 struct mlx4_promisc_qp
*dqp
;
503 bool back_to_list
= false;
507 if (port
< 1 || port
> dev
->caps
.num_ports
)
510 s_steer
= &mlx4_priv(dev
)->steer
[port
- 1];
511 mutex_lock(&priv
->mcg_table
.mutex
);
513 pqp
= get_promisc_qp(dev
, port
, steer
, qpn
);
514 if (unlikely(!pqp
)) {
515 mlx4_warn(dev
, "QP %x is not promiscuous QP\n", qpn
);
521 /*remove from list of promisc qps */
522 list_del(&pqp
->list
);
524 /* set the default entry not to include the removed one */
525 mailbox
= mlx4_alloc_cmd_mailbox(dev
);
526 if (IS_ERR(mailbox
)) {
533 list_for_each_entry(dqp
, &s_steer
->promisc_qps
[steer
], list
)
534 mgm
->qp
[members_count
++] = cpu_to_be32(dqp
->qpn
& MGM_QPN_MASK
);
535 mgm
->members_count
= cpu_to_be32(members_count
| MLX4_PROT_ETH
<< 30);
537 err
= mlx4_WRITE_PROMISC(dev
, port
, steer
, mailbox
);
541 /* remove the qp from all the steering entries*/
542 list_for_each_entry(entry
, &s_steer
->steer_entries
[steer
], list
) {
544 list_for_each_entry(dqp
, &entry
->duplicates
, list
) {
545 if (dqp
->qpn
== qpn
) {
551 /* a duplicate, no need to change the mgm,
552 * only update the duplicates list */
553 list_del(&dqp
->list
);
556 err
= mlx4_READ_ENTRY(dev
, entry
->index
, mailbox
);
559 members_count
= be32_to_cpu(mgm
->members_count
) & 0xffffff;
560 for (loc
= -1, i
= 0; i
< members_count
; ++i
)
561 if ((be32_to_cpu(mgm
->qp
[i
]) & MGM_QPN_MASK
) == qpn
)
564 mgm
->members_count
= cpu_to_be32(--members_count
|
565 (MLX4_PROT_ETH
<< 30));
566 mgm
->qp
[loc
] = mgm
->qp
[i
- 1];
569 err
= mlx4_WRITE_ENTRY(dev
, entry
->index
, mailbox
);
577 mlx4_free_cmd_mailbox(dev
, mailbox
);
580 list_add_tail(&pqp
->list
, &s_steer
->promisc_qps
[steer
]);
584 mutex_unlock(&priv
->mcg_table
.mutex
);
589 * Caller must hold MCG table semaphore. gid and mgm parameters must
590 * be properly aligned for command interface.
592 * Returns 0 unless a firmware command error occurs.
594 * If GID is found in MGM or MGM is empty, *index = *hash, *prev = -1
595 * and *mgm holds MGM entry.
597 * if GID is found in AMGM, *index = index in AMGM, *prev = index of
598 * previous entry in hash chain and *mgm holds AMGM entry.
600 * If no AMGM exists for given gid, *index = -1, *prev = index of last
601 * entry in hash chain and *mgm holds end of hash chain.
603 static int find_entry(struct mlx4_dev
*dev
, u8 port
,
604 u8
*gid
, enum mlx4_protocol prot
,
605 struct mlx4_cmd_mailbox
*mgm_mailbox
,
606 int *prev
, int *index
)
608 struct mlx4_cmd_mailbox
*mailbox
;
609 struct mlx4_mgm
*mgm
= mgm_mailbox
->buf
;
613 u8 op_mod
= (prot
== MLX4_PROT_ETH
) ?
614 !!(dev
->caps
.flags
& MLX4_DEV_CAP_FLAG_VEP_MC_STEER
) : 0;
616 mailbox
= mlx4_alloc_cmd_mailbox(dev
);
621 memcpy(mgid
, gid
, 16);
623 err
= mlx4_GID_HASH(dev
, mailbox
, &hash
, op_mod
);
624 mlx4_free_cmd_mailbox(dev
, mailbox
);
629 mlx4_dbg(dev
, "Hash for %pI6 is %04x\n", gid
, hash
);
635 err
= mlx4_READ_ENTRY(dev
, *index
, mgm_mailbox
);
639 if (!(be32_to_cpu(mgm
->members_count
) & 0xffffff)) {
640 if (*index
!= hash
) {
641 mlx4_err(dev
, "Found zero MGID in AMGM\n");
647 if (!memcmp(mgm
->gid
, gid
, 16) &&
648 be32_to_cpu(mgm
->members_count
) >> 30 == prot
)
652 *index
= be32_to_cpu(mgm
->next_gid_index
) >> 6;
659 static const u8 __promisc_mode
[] = {
660 [MLX4_FS_REGULAR
] = 0x0,
661 [MLX4_FS_ALL_DEFAULT
] = 0x1,
662 [MLX4_FS_MC_DEFAULT
] = 0x3,
663 [MLX4_FS_UC_SNIFFER
] = 0x4,
664 [MLX4_FS_MC_SNIFFER
] = 0x5,
667 int mlx4_map_sw_to_hw_steering_mode(struct mlx4_dev
*dev
,
668 enum mlx4_net_trans_promisc_mode flow_type
)
670 if (flow_type
>= MLX4_FS_MODE_NUM
) {
671 mlx4_err(dev
, "Invalid flow type. type = %d\n", flow_type
);
674 return __promisc_mode
[flow_type
];
676 EXPORT_SYMBOL_GPL(mlx4_map_sw_to_hw_steering_mode
);
678 static void trans_rule_ctrl_to_hw(struct mlx4_net_trans_rule
*ctrl
,
679 struct mlx4_net_trans_rule_hw_ctrl
*hw
)
683 flags
= ctrl
->queue_mode
== MLX4_NET_TRANS_Q_LIFO
? 1 : 0;
684 flags
|= ctrl
->exclusive
? (1 << 2) : 0;
685 flags
|= ctrl
->allow_loopback
? (1 << 3) : 0;
688 hw
->type
= __promisc_mode
[ctrl
->promisc_mode
];
689 hw
->prio
= cpu_to_be16(ctrl
->priority
);
690 hw
->port
= ctrl
->port
;
691 hw
->qpn
= cpu_to_be32(ctrl
->qpn
);
694 const u16 __sw_id_hw
[] = {
695 [MLX4_NET_TRANS_RULE_ID_ETH
] = 0xE001,
696 [MLX4_NET_TRANS_RULE_ID_IB
] = 0xE005,
697 [MLX4_NET_TRANS_RULE_ID_IPV6
] = 0xE003,
698 [MLX4_NET_TRANS_RULE_ID_IPV4
] = 0xE002,
699 [MLX4_NET_TRANS_RULE_ID_TCP
] = 0xE004,
700 [MLX4_NET_TRANS_RULE_ID_UDP
] = 0xE006,
701 [MLX4_NET_TRANS_RULE_ID_VXLAN
] = 0xE008
704 int mlx4_map_sw_to_hw_steering_id(struct mlx4_dev
*dev
,
705 enum mlx4_net_trans_rule_id id
)
707 if (id
>= MLX4_NET_TRANS_RULE_NUM
) {
708 mlx4_err(dev
, "Invalid network rule id. id = %d\n", id
);
711 return __sw_id_hw
[id
];
713 EXPORT_SYMBOL_GPL(mlx4_map_sw_to_hw_steering_id
);
715 static const int __rule_hw_sz
[] = {
716 [MLX4_NET_TRANS_RULE_ID_ETH
] =
717 sizeof(struct mlx4_net_trans_rule_hw_eth
),
718 [MLX4_NET_TRANS_RULE_ID_IB
] =
719 sizeof(struct mlx4_net_trans_rule_hw_ib
),
720 [MLX4_NET_TRANS_RULE_ID_IPV6
] = 0,
721 [MLX4_NET_TRANS_RULE_ID_IPV4
] =
722 sizeof(struct mlx4_net_trans_rule_hw_ipv4
),
723 [MLX4_NET_TRANS_RULE_ID_TCP
] =
724 sizeof(struct mlx4_net_trans_rule_hw_tcp_udp
),
725 [MLX4_NET_TRANS_RULE_ID_UDP
] =
726 sizeof(struct mlx4_net_trans_rule_hw_tcp_udp
),
727 [MLX4_NET_TRANS_RULE_ID_VXLAN
] =
728 sizeof(struct mlx4_net_trans_rule_hw_vxlan
)
731 int mlx4_hw_rule_sz(struct mlx4_dev
*dev
,
732 enum mlx4_net_trans_rule_id id
)
734 if (id
>= MLX4_NET_TRANS_RULE_NUM
) {
735 mlx4_err(dev
, "Invalid network rule id. id = %d\n", id
);
739 return __rule_hw_sz
[id
];
741 EXPORT_SYMBOL_GPL(mlx4_hw_rule_sz
);
743 static int parse_trans_rule(struct mlx4_dev
*dev
, struct mlx4_spec_list
*spec
,
744 struct _rule_hw
*rule_hw
)
746 if (mlx4_hw_rule_sz(dev
, spec
->id
) < 0)
748 memset(rule_hw
, 0, mlx4_hw_rule_sz(dev
, spec
->id
));
749 rule_hw
->id
= cpu_to_be16(__sw_id_hw
[spec
->id
]);
750 rule_hw
->size
= mlx4_hw_rule_sz(dev
, spec
->id
) >> 2;
753 case MLX4_NET_TRANS_RULE_ID_ETH
:
754 memcpy(rule_hw
->eth
.dst_mac
, spec
->eth
.dst_mac
, ETH_ALEN
);
755 memcpy(rule_hw
->eth
.dst_mac_msk
, spec
->eth
.dst_mac_msk
,
757 memcpy(rule_hw
->eth
.src_mac
, spec
->eth
.src_mac
, ETH_ALEN
);
758 memcpy(rule_hw
->eth
.src_mac_msk
, spec
->eth
.src_mac_msk
,
760 if (spec
->eth
.ether_type_enable
) {
761 rule_hw
->eth
.ether_type_enable
= 1;
762 rule_hw
->eth
.ether_type
= spec
->eth
.ether_type
;
764 rule_hw
->eth
.vlan_tag
= spec
->eth
.vlan_id
;
765 rule_hw
->eth
.vlan_tag_msk
= spec
->eth
.vlan_id_msk
;
768 case MLX4_NET_TRANS_RULE_ID_IB
:
769 rule_hw
->ib
.l3_qpn
= spec
->ib
.l3_qpn
;
770 rule_hw
->ib
.qpn_mask
= spec
->ib
.qpn_msk
;
771 memcpy(&rule_hw
->ib
.dst_gid
, &spec
->ib
.dst_gid
, 16);
772 memcpy(&rule_hw
->ib
.dst_gid_msk
, &spec
->ib
.dst_gid_msk
, 16);
775 case MLX4_NET_TRANS_RULE_ID_IPV6
:
778 case MLX4_NET_TRANS_RULE_ID_IPV4
:
779 rule_hw
->ipv4
.src_ip
= spec
->ipv4
.src_ip
;
780 rule_hw
->ipv4
.src_ip_msk
= spec
->ipv4
.src_ip_msk
;
781 rule_hw
->ipv4
.dst_ip
= spec
->ipv4
.dst_ip
;
782 rule_hw
->ipv4
.dst_ip_msk
= spec
->ipv4
.dst_ip_msk
;
785 case MLX4_NET_TRANS_RULE_ID_TCP
:
786 case MLX4_NET_TRANS_RULE_ID_UDP
:
787 rule_hw
->tcp_udp
.dst_port
= spec
->tcp_udp
.dst_port
;
788 rule_hw
->tcp_udp
.dst_port_msk
= spec
->tcp_udp
.dst_port_msk
;
789 rule_hw
->tcp_udp
.src_port
= spec
->tcp_udp
.src_port
;
790 rule_hw
->tcp_udp
.src_port_msk
= spec
->tcp_udp
.src_port_msk
;
793 case MLX4_NET_TRANS_RULE_ID_VXLAN
:
795 cpu_to_be32(be32_to_cpu(spec
->vxlan
.vni
) << 8);
796 rule_hw
->vxlan
.vni_mask
=
797 cpu_to_be32(be32_to_cpu(spec
->vxlan
.vni_mask
) << 8);
804 return __rule_hw_sz
[spec
->id
];
807 static void mlx4_err_rule(struct mlx4_dev
*dev
, char *str
,
808 struct mlx4_net_trans_rule
*rule
)
811 struct mlx4_spec_list
*cur
;
815 mlx4_err(dev
, "%s", str
);
816 len
+= snprintf(buf
+ len
, BUF_SIZE
- len
,
817 "port = %d prio = 0x%x qp = 0x%x ",
818 rule
->port
, rule
->priority
, rule
->qpn
);
820 list_for_each_entry(cur
, &rule
->list
, list
) {
822 case MLX4_NET_TRANS_RULE_ID_ETH
:
823 len
+= snprintf(buf
+ len
, BUF_SIZE
- len
,
824 "dmac = %pM ", &cur
->eth
.dst_mac
);
825 if (cur
->eth
.ether_type
)
826 len
+= snprintf(buf
+ len
, BUF_SIZE
- len
,
828 be16_to_cpu(cur
->eth
.ether_type
));
829 if (cur
->eth
.vlan_id
)
830 len
+= snprintf(buf
+ len
, BUF_SIZE
- len
,
832 be16_to_cpu(cur
->eth
.vlan_id
));
835 case MLX4_NET_TRANS_RULE_ID_IPV4
:
836 if (cur
->ipv4
.src_ip
)
837 len
+= snprintf(buf
+ len
, BUF_SIZE
- len
,
840 if (cur
->ipv4
.dst_ip
)
841 len
+= snprintf(buf
+ len
, BUF_SIZE
- len
,
846 case MLX4_NET_TRANS_RULE_ID_TCP
:
847 case MLX4_NET_TRANS_RULE_ID_UDP
:
848 if (cur
->tcp_udp
.src_port
)
849 len
+= snprintf(buf
+ len
, BUF_SIZE
- len
,
851 be16_to_cpu(cur
->tcp_udp
.src_port
));
852 if (cur
->tcp_udp
.dst_port
)
853 len
+= snprintf(buf
+ len
, BUF_SIZE
- len
,
855 be16_to_cpu(cur
->tcp_udp
.dst_port
));
858 case MLX4_NET_TRANS_RULE_ID_IB
:
859 len
+= snprintf(buf
+ len
, BUF_SIZE
- len
,
860 "dst-gid = %pI6\n", cur
->ib
.dst_gid
);
861 len
+= snprintf(buf
+ len
, BUF_SIZE
- len
,
862 "dst-gid-mask = %pI6\n",
863 cur
->ib
.dst_gid_msk
);
866 case MLX4_NET_TRANS_RULE_ID_IPV6
:
873 len
+= snprintf(buf
+ len
, BUF_SIZE
- len
, "\n");
874 mlx4_err(dev
, "%s", buf
);
877 mlx4_err(dev
, "Network rule error message was truncated, print buffer is too small\n");
880 int mlx4_flow_attach(struct mlx4_dev
*dev
,
881 struct mlx4_net_trans_rule
*rule
, u64
*reg_id
)
883 struct mlx4_cmd_mailbox
*mailbox
;
884 struct mlx4_spec_list
*cur
;
888 mailbox
= mlx4_alloc_cmd_mailbox(dev
);
890 return PTR_ERR(mailbox
);
892 trans_rule_ctrl_to_hw(rule
, mailbox
->buf
);
894 size
+= sizeof(struct mlx4_net_trans_rule_hw_ctrl
);
896 list_for_each_entry(cur
, &rule
->list
, list
) {
897 ret
= parse_trans_rule(dev
, cur
, mailbox
->buf
+ size
);
899 mlx4_free_cmd_mailbox(dev
, mailbox
);
905 ret
= mlx4_QP_FLOW_STEERING_ATTACH(dev
, mailbox
, size
>> 2, reg_id
);
908 "mcg table is full. Fail to register network rule\n",
911 mlx4_err_rule(dev
, "Fail to register network rule\n", rule
);
913 mlx4_free_cmd_mailbox(dev
, mailbox
);
917 EXPORT_SYMBOL_GPL(mlx4_flow_attach
);
919 int mlx4_flow_detach(struct mlx4_dev
*dev
, u64 reg_id
)
923 err
= mlx4_QP_FLOW_STEERING_DETACH(dev
, reg_id
);
925 mlx4_err(dev
, "Fail to detach network rule. registration id = 0x%llx\n",
929 EXPORT_SYMBOL_GPL(mlx4_flow_detach
);
931 int mlx4_FLOW_STEERING_IB_UC_QP_RANGE(struct mlx4_dev
*dev
, u32 min_range_qpn
,
937 in_param
= ((u64
) min_range_qpn
) << 32;
938 in_param
|= ((u64
) max_range_qpn
) & 0xFFFFFFFF;
940 err
= mlx4_cmd(dev
, in_param
, 0, 0,
941 MLX4_FLOW_STEERING_IB_UC_QP_RANGE
,
942 MLX4_CMD_TIME_CLASS_A
, MLX4_CMD_NATIVE
);
946 EXPORT_SYMBOL_GPL(mlx4_FLOW_STEERING_IB_UC_QP_RANGE
);
948 int mlx4_qp_attach_common(struct mlx4_dev
*dev
, struct mlx4_qp
*qp
, u8 gid
[16],
949 int block_mcast_loopback
, enum mlx4_protocol prot
,
950 enum mlx4_steer_type steer
)
952 struct mlx4_priv
*priv
= mlx4_priv(dev
);
953 struct mlx4_cmd_mailbox
*mailbox
;
954 struct mlx4_mgm
*mgm
;
963 mailbox
= mlx4_alloc_cmd_mailbox(dev
);
965 return PTR_ERR(mailbox
);
968 mutex_lock(&priv
->mcg_table
.mutex
);
969 err
= find_entry(dev
, port
, gid
, prot
,
970 mailbox
, &prev
, &index
);
975 if (!(be32_to_cpu(mgm
->members_count
) & 0xffffff)) {
977 memcpy(mgm
->gid
, gid
, 16);
982 index
= mlx4_bitmap_alloc(&priv
->mcg_table
.bitmap
);
984 mlx4_err(dev
, "No AMGM entries left\n");
988 index
+= dev
->caps
.num_mgms
;
991 memset(mgm
, 0, sizeof *mgm
);
992 memcpy(mgm
->gid
, gid
, 16);
995 members_count
= be32_to_cpu(mgm
->members_count
) & 0xffffff;
996 if (members_count
== dev
->caps
.num_qp_per_mgm
) {
997 mlx4_err(dev
, "MGM at index %x is full\n", index
);
1002 for (i
= 0; i
< members_count
; ++i
)
1003 if ((be32_to_cpu(mgm
->qp
[i
]) & MGM_QPN_MASK
) == qp
->qpn
) {
1004 mlx4_dbg(dev
, "QP %06x already a member of MGM\n", qp
->qpn
);
1009 if (block_mcast_loopback
)
1010 mgm
->qp
[members_count
++] = cpu_to_be32((qp
->qpn
& MGM_QPN_MASK
) |
1011 (1U << MGM_BLCK_LB_BIT
));
1013 mgm
->qp
[members_count
++] = cpu_to_be32(qp
->qpn
& MGM_QPN_MASK
);
1015 mgm
->members_count
= cpu_to_be32(members_count
| (u32
) prot
<< 30);
1017 err
= mlx4_WRITE_ENTRY(dev
, index
, mailbox
);
1024 err
= mlx4_READ_ENTRY(dev
, prev
, mailbox
);
1028 mgm
->next_gid_index
= cpu_to_be32(index
<< 6);
1030 err
= mlx4_WRITE_ENTRY(dev
, prev
, mailbox
);
1035 if (prot
== MLX4_PROT_ETH
) {
1036 /* manage the steering entry for promisc mode */
1038 new_steering_entry(dev
, port
, steer
, index
, qp
->qpn
);
1040 existing_steering_entry(dev
, port
, steer
,
1043 if (err
&& link
&& index
!= -1) {
1044 if (index
< dev
->caps
.num_mgms
)
1045 mlx4_warn(dev
, "Got AMGM index %d < %d\n",
1046 index
, dev
->caps
.num_mgms
);
1048 mlx4_bitmap_free(&priv
->mcg_table
.bitmap
,
1049 index
- dev
->caps
.num_mgms
, MLX4_USE_RR
);
1051 mutex_unlock(&priv
->mcg_table
.mutex
);
1053 mlx4_free_cmd_mailbox(dev
, mailbox
);
1057 int mlx4_qp_detach_common(struct mlx4_dev
*dev
, struct mlx4_qp
*qp
, u8 gid
[16],
1058 enum mlx4_protocol prot
, enum mlx4_steer_type steer
)
1060 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1061 struct mlx4_cmd_mailbox
*mailbox
;
1062 struct mlx4_mgm
*mgm
;
1068 bool removed_entry
= false;
1070 mailbox
= mlx4_alloc_cmd_mailbox(dev
);
1071 if (IS_ERR(mailbox
))
1072 return PTR_ERR(mailbox
);
1075 mutex_lock(&priv
->mcg_table
.mutex
);
1077 err
= find_entry(dev
, port
, gid
, prot
,
1078 mailbox
, &prev
, &index
);
1083 mlx4_err(dev
, "MGID %pI6 not found\n", gid
);
1088 /* if this pq is also a promisc qp, it shouldn't be removed */
1089 if (prot
== MLX4_PROT_ETH
&&
1090 check_duplicate_entry(dev
, port
, steer
, index
, qp
->qpn
))
1093 members_count
= be32_to_cpu(mgm
->members_count
) & 0xffffff;
1094 for (loc
= -1, i
= 0; i
< members_count
; ++i
)
1095 if ((be32_to_cpu(mgm
->qp
[i
]) & MGM_QPN_MASK
) == qp
->qpn
)
1099 mlx4_err(dev
, "QP %06x not found in MGM\n", qp
->qpn
);
1105 mgm
->members_count
= cpu_to_be32(--members_count
| (u32
) prot
<< 30);
1106 mgm
->qp
[loc
] = mgm
->qp
[i
- 1];
1109 if (prot
== MLX4_PROT_ETH
)
1110 removed_entry
= can_remove_steering_entry(dev
, port
, steer
,
1112 if (i
!= 1 && (prot
!= MLX4_PROT_ETH
|| !removed_entry
)) {
1113 err
= mlx4_WRITE_ENTRY(dev
, index
, mailbox
);
1117 /* We are going to delete the entry, members count should be 0 */
1118 mgm
->members_count
= cpu_to_be32((u32
) prot
<< 30);
1121 /* Remove entry from MGM */
1122 int amgm_index
= be32_to_cpu(mgm
->next_gid_index
) >> 6;
1124 err
= mlx4_READ_ENTRY(dev
, amgm_index
, mailbox
);
1128 memset(mgm
->gid
, 0, 16);
1130 err
= mlx4_WRITE_ENTRY(dev
, index
, mailbox
);
1135 if (amgm_index
< dev
->caps
.num_mgms
)
1136 mlx4_warn(dev
, "MGM entry %d had AMGM index %d < %d\n",
1137 index
, amgm_index
, dev
->caps
.num_mgms
);
1139 mlx4_bitmap_free(&priv
->mcg_table
.bitmap
,
1140 amgm_index
- dev
->caps
.num_mgms
, MLX4_USE_RR
);
1143 /* Remove entry from AMGM */
1144 int cur_next_index
= be32_to_cpu(mgm
->next_gid_index
) >> 6;
1145 err
= mlx4_READ_ENTRY(dev
, prev
, mailbox
);
1149 mgm
->next_gid_index
= cpu_to_be32(cur_next_index
<< 6);
1151 err
= mlx4_WRITE_ENTRY(dev
, prev
, mailbox
);
1155 if (index
< dev
->caps
.num_mgms
)
1156 mlx4_warn(dev
, "entry %d had next AMGM index %d < %d\n",
1157 prev
, index
, dev
->caps
.num_mgms
);
1159 mlx4_bitmap_free(&priv
->mcg_table
.bitmap
,
1160 index
- dev
->caps
.num_mgms
, MLX4_USE_RR
);
1164 mutex_unlock(&priv
->mcg_table
.mutex
);
1166 mlx4_free_cmd_mailbox(dev
, mailbox
);
1170 static int mlx4_QP_ATTACH(struct mlx4_dev
*dev
, struct mlx4_qp
*qp
,
1171 u8 gid
[16], u8 attach
, u8 block_loopback
,
1172 enum mlx4_protocol prot
)
1174 struct mlx4_cmd_mailbox
*mailbox
;
1178 if (!mlx4_is_mfunc(dev
))
1181 mailbox
= mlx4_alloc_cmd_mailbox(dev
);
1182 if (IS_ERR(mailbox
))
1183 return PTR_ERR(mailbox
);
1185 memcpy(mailbox
->buf
, gid
, 16);
1187 qpn
|= (prot
<< 28);
1188 if (attach
&& block_loopback
)
1191 err
= mlx4_cmd(dev
, mailbox
->dma
, qpn
, attach
,
1192 MLX4_CMD_QP_ATTACH
, MLX4_CMD_TIME_CLASS_A
,
1195 mlx4_free_cmd_mailbox(dev
, mailbox
);
1199 int mlx4_trans_to_dmfs_attach(struct mlx4_dev
*dev
, struct mlx4_qp
*qp
,
1200 u8 gid
[16], u8 port
,
1201 int block_mcast_loopback
,
1202 enum mlx4_protocol prot
, u64
*reg_id
)
1204 struct mlx4_spec_list spec
= { {NULL
} };
1205 __be64 mac_mask
= cpu_to_be64(MLX4_MAC_MASK
<< 16);
1207 struct mlx4_net_trans_rule rule
= {
1208 .queue_mode
= MLX4_NET_TRANS_Q_FIFO
,
1210 .promisc_mode
= MLX4_FS_REGULAR
,
1211 .priority
= MLX4_DOMAIN_NIC
,
1214 rule
.allow_loopback
= !block_mcast_loopback
;
1217 INIT_LIST_HEAD(&rule
.list
);
1221 spec
.id
= MLX4_NET_TRANS_RULE_ID_ETH
;
1222 memcpy(spec
.eth
.dst_mac
, &gid
[10], ETH_ALEN
);
1223 memcpy(spec
.eth
.dst_mac_msk
, &mac_mask
, ETH_ALEN
);
1226 case MLX4_PROT_IB_IPV6
:
1227 spec
.id
= MLX4_NET_TRANS_RULE_ID_IB
;
1228 memcpy(spec
.ib
.dst_gid
, gid
, 16);
1229 memset(&spec
.ib
.dst_gid_msk
, 0xff, 16);
1234 list_add_tail(&spec
.list
, &rule
.list
);
1236 return mlx4_flow_attach(dev
, &rule
, reg_id
);
1239 int mlx4_multicast_attach(struct mlx4_dev
*dev
, struct mlx4_qp
*qp
, u8 gid
[16],
1240 u8 port
, int block_mcast_loopback
,
1241 enum mlx4_protocol prot
, u64
*reg_id
)
1243 switch (dev
->caps
.steering_mode
) {
1244 case MLX4_STEERING_MODE_A0
:
1245 if (prot
== MLX4_PROT_ETH
)
1248 case MLX4_STEERING_MODE_B0
:
1249 if (prot
== MLX4_PROT_ETH
)
1250 gid
[7] |= (MLX4_MC_STEER
<< 1);
1252 if (mlx4_is_mfunc(dev
))
1253 return mlx4_QP_ATTACH(dev
, qp
, gid
, 1,
1254 block_mcast_loopback
, prot
);
1255 return mlx4_qp_attach_common(dev
, qp
, gid
,
1256 block_mcast_loopback
, prot
,
1259 case MLX4_STEERING_MODE_DEVICE_MANAGED
:
1260 return mlx4_trans_to_dmfs_attach(dev
, qp
, gid
, port
,
1261 block_mcast_loopback
,
1267 EXPORT_SYMBOL_GPL(mlx4_multicast_attach
);
1269 int mlx4_multicast_detach(struct mlx4_dev
*dev
, struct mlx4_qp
*qp
, u8 gid
[16],
1270 enum mlx4_protocol prot
, u64 reg_id
)
1272 switch (dev
->caps
.steering_mode
) {
1273 case MLX4_STEERING_MODE_A0
:
1274 if (prot
== MLX4_PROT_ETH
)
1277 case MLX4_STEERING_MODE_B0
:
1278 if (prot
== MLX4_PROT_ETH
)
1279 gid
[7] |= (MLX4_MC_STEER
<< 1);
1281 if (mlx4_is_mfunc(dev
))
1282 return mlx4_QP_ATTACH(dev
, qp
, gid
, 0, 0, prot
);
1284 return mlx4_qp_detach_common(dev
, qp
, gid
, prot
,
1287 case MLX4_STEERING_MODE_DEVICE_MANAGED
:
1288 return mlx4_flow_detach(dev
, reg_id
);
1294 EXPORT_SYMBOL_GPL(mlx4_multicast_detach
);
1296 int mlx4_flow_steer_promisc_add(struct mlx4_dev
*dev
, u8 port
,
1297 u32 qpn
, enum mlx4_net_trans_promisc_mode mode
)
1299 struct mlx4_net_trans_rule rule
;
1303 case MLX4_FS_ALL_DEFAULT
:
1304 regid_p
= &dev
->regid_promisc_array
[port
];
1306 case MLX4_FS_MC_DEFAULT
:
1307 regid_p
= &dev
->regid_allmulti_array
[port
];
1316 rule
.promisc_mode
= mode
;
1319 INIT_LIST_HEAD(&rule
.list
);
1320 mlx4_err(dev
, "going promisc on %x\n", port
);
1322 return mlx4_flow_attach(dev
, &rule
, regid_p
);
1324 EXPORT_SYMBOL_GPL(mlx4_flow_steer_promisc_add
);
1326 int mlx4_flow_steer_promisc_remove(struct mlx4_dev
*dev
, u8 port
,
1327 enum mlx4_net_trans_promisc_mode mode
)
1333 case MLX4_FS_ALL_DEFAULT
:
1334 regid_p
= &dev
->regid_promisc_array
[port
];
1336 case MLX4_FS_MC_DEFAULT
:
1337 regid_p
= &dev
->regid_allmulti_array
[port
];
1346 ret
= mlx4_flow_detach(dev
, *regid_p
);
1352 EXPORT_SYMBOL_GPL(mlx4_flow_steer_promisc_remove
);
1354 int mlx4_unicast_attach(struct mlx4_dev
*dev
,
1355 struct mlx4_qp
*qp
, u8 gid
[16],
1356 int block_mcast_loopback
, enum mlx4_protocol prot
)
1358 if (prot
== MLX4_PROT_ETH
)
1359 gid
[7] |= (MLX4_UC_STEER
<< 1);
1361 if (mlx4_is_mfunc(dev
))
1362 return mlx4_QP_ATTACH(dev
, qp
, gid
, 1,
1363 block_mcast_loopback
, prot
);
1365 return mlx4_qp_attach_common(dev
, qp
, gid
, block_mcast_loopback
,
1366 prot
, MLX4_UC_STEER
);
1368 EXPORT_SYMBOL_GPL(mlx4_unicast_attach
);
1370 int mlx4_unicast_detach(struct mlx4_dev
*dev
, struct mlx4_qp
*qp
,
1371 u8 gid
[16], enum mlx4_protocol prot
)
1373 if (prot
== MLX4_PROT_ETH
)
1374 gid
[7] |= (MLX4_UC_STEER
<< 1);
1376 if (mlx4_is_mfunc(dev
))
1377 return mlx4_QP_ATTACH(dev
, qp
, gid
, 0, 0, prot
);
1379 return mlx4_qp_detach_common(dev
, qp
, gid
, prot
, MLX4_UC_STEER
);
1381 EXPORT_SYMBOL_GPL(mlx4_unicast_detach
);
1383 int mlx4_PROMISC_wrapper(struct mlx4_dev
*dev
, int slave
,
1384 struct mlx4_vhcr
*vhcr
,
1385 struct mlx4_cmd_mailbox
*inbox
,
1386 struct mlx4_cmd_mailbox
*outbox
,
1387 struct mlx4_cmd_info
*cmd
)
1389 u32 qpn
= (u32
) vhcr
->in_param
& 0xffffffff;
1390 int port
= mlx4_slave_convert_port(dev
, slave
, vhcr
->in_param
>> 62);
1391 enum mlx4_steer_type steer
= vhcr
->in_modifier
;
1396 /* Promiscuous unicast is not allowed in mfunc */
1397 if (mlx4_is_mfunc(dev
) && steer
== MLX4_UC_STEER
)
1400 if (vhcr
->op_modifier
)
1401 return add_promisc_qp(dev
, port
, steer
, qpn
);
1403 return remove_promisc_qp(dev
, port
, steer
, qpn
);
1406 static int mlx4_PROMISC(struct mlx4_dev
*dev
, u32 qpn
,
1407 enum mlx4_steer_type steer
, u8 add
, u8 port
)
1409 return mlx4_cmd(dev
, (u64
) qpn
| (u64
) port
<< 62, (u32
) steer
, add
,
1410 MLX4_CMD_PROMISC
, MLX4_CMD_TIME_CLASS_A
,
1414 int mlx4_multicast_promisc_add(struct mlx4_dev
*dev
, u32 qpn
, u8 port
)
1416 if (mlx4_is_mfunc(dev
))
1417 return mlx4_PROMISC(dev
, qpn
, MLX4_MC_STEER
, 1, port
);
1419 return add_promisc_qp(dev
, port
, MLX4_MC_STEER
, qpn
);
1421 EXPORT_SYMBOL_GPL(mlx4_multicast_promisc_add
);
1423 int mlx4_multicast_promisc_remove(struct mlx4_dev
*dev
, u32 qpn
, u8 port
)
1425 if (mlx4_is_mfunc(dev
))
1426 return mlx4_PROMISC(dev
, qpn
, MLX4_MC_STEER
, 0, port
);
1428 return remove_promisc_qp(dev
, port
, MLX4_MC_STEER
, qpn
);
1430 EXPORT_SYMBOL_GPL(mlx4_multicast_promisc_remove
);
1432 int mlx4_unicast_promisc_add(struct mlx4_dev
*dev
, u32 qpn
, u8 port
)
1434 if (mlx4_is_mfunc(dev
))
1435 return mlx4_PROMISC(dev
, qpn
, MLX4_UC_STEER
, 1, port
);
1437 return add_promisc_qp(dev
, port
, MLX4_UC_STEER
, qpn
);
1439 EXPORT_SYMBOL_GPL(mlx4_unicast_promisc_add
);
1441 int mlx4_unicast_promisc_remove(struct mlx4_dev
*dev
, u32 qpn
, u8 port
)
1443 if (mlx4_is_mfunc(dev
))
1444 return mlx4_PROMISC(dev
, qpn
, MLX4_UC_STEER
, 0, port
);
1446 return remove_promisc_qp(dev
, port
, MLX4_UC_STEER
, qpn
);
1448 EXPORT_SYMBOL_GPL(mlx4_unicast_promisc_remove
);
1450 int mlx4_init_mcg_table(struct mlx4_dev
*dev
)
1452 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1455 /* No need for mcg_table when fw managed the mcg table*/
1456 if (dev
->caps
.steering_mode
==
1457 MLX4_STEERING_MODE_DEVICE_MANAGED
)
1459 err
= mlx4_bitmap_init(&priv
->mcg_table
.bitmap
, dev
->caps
.num_amgms
,
1460 dev
->caps
.num_amgms
- 1, 0, 0);
1464 mutex_init(&priv
->mcg_table
.mutex
);
1469 void mlx4_cleanup_mcg_table(struct mlx4_dev
*dev
)
1471 if (dev
->caps
.steering_mode
!=
1472 MLX4_STEERING_MODE_DEVICE_MANAGED
)
1473 mlx4_bitmap_cleanup(&mlx4_priv(dev
)->mcg_table
.bitmap
);