drivers/net/ethernet/mellanox/mlx4/mlx4.h

   1 /*
   2  * Copyright (c) 2004, 2005 Topspin Communications.  All rights reserved.
   3  * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
   4  * Copyright (c) 2005, 2006, 2007 Cisco Systems.  All rights reserved.
   5  * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
   6  * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
   7  *
   8  * This software is available to you under a choice of one of two
   9  * licenses.  You may choose to be licensed under the terms of the GNU
  10  * General Public License (GPL) Version 2, available from the file
  11  * COPYING in the main directory of this source tree, or the
  12  * OpenIB.org BSD license below:
  13  *
  14  *     Redistribution and use in source and binary forms, with or
  15  *     without modification, are permitted provided that the following
  16  *     conditions are met:
  17  *
  18  *      - Redistributions of source code must retain the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer.
  21  *
  22  *      - Redistributions in binary form must reproduce the above
  23  *        copyright notice, this list of conditions and the following
  24  *        disclaimer in the documentation and/or other materials
  25  *        provided with the distribution.
  26  *
  27  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  28  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  29  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  30  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  31  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  32  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  33  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  34  * SOFTWARE.
  35  */
  36
  37 #ifndef MLX4_H
  38 #define MLX4_H
  39
  40 #include <linux/mutex.h>
  41 #include <linux/radix-tree.h>
  42 #include <linux/rbtree.h>
  43 #include <linux/timer.h>
  44 #include <linux/semaphore.h>
  45 #include <linux/workqueue.h>
  46
  47 #include <linux/mlx4/device.h>
  48 #include <linux/mlx4/driver.h>
  49 #include <linux/mlx4/doorbell.h>
  50 #include <linux/mlx4/cmd.h>
  51
  52 #define DRV_NAME        "mlx4_core"
  53 #define PFX             DRV_NAME ": "
  54 #define DRV_VERSION     "1.1"
  55 #define DRV_RELDATE     "Dec, 2011"
  56
  57 #define MLX4_FS_UDP_UC_EN               (1 << 1)
  58 #define MLX4_FS_TCP_UC_EN               (1 << 2)
  59 #define MLX4_FS_NUM_OF_L2_ADDR          8
  60 #define MLX4_FS_MGM_LOG_ENTRY_SIZE      7
  61 #define MLX4_FS_NUM_MCG                 (1 << 17)
  62
  63 enum {
  64         MLX4_FS_L2_HASH = 0,
  65         MLX4_FS_L2_L3_L4_HASH,
  66 };
  67
  68 #define MLX4_NUM_UP             8
  69 #define MLX4_NUM_TC             8
  70 #define MLX4_RATELIMIT_UNITS 3 /* 100 Mbps */
  71 #define MLX4_RATELIMIT_DEFAULT 0xffff
  72
  73 struct mlx4_set_port_prio2tc_context {
  74         u8 prio2tc[4];
  75 };
  76
  77 struct mlx4_port_scheduler_tc_cfg_be {
  78         __be16 pg;
  79         __be16 bw_precentage;
  80         __be16 max_bw_units; /* 3-100Mbps, 4-1Gbps, other values - reserved */
  81         __be16 max_bw_value;
  82 };
  83
  84 struct mlx4_set_port_scheduler_context {
  85         struct mlx4_port_scheduler_tc_cfg_be tc[MLX4_NUM_TC];
  86 };
  87
  88 enum {
  89         MLX4_HCR_BASE           = 0x80680,
  90         MLX4_HCR_SIZE           = 0x0001c,
  91         MLX4_CLR_INT_SIZE       = 0x00008,
  92         MLX4_SLAVE_COMM_BASE    = 0x0,
  93         MLX4_COMM_PAGESIZE      = 0x1000
  94 };
  95
  96 enum {
  97         MLX4_MAX_MGM_ENTRY_SIZE = 0x1000,
  98         MLX4_MAX_QP_PER_MGM     = 4 * (MLX4_MAX_MGM_ENTRY_SIZE / 16 - 2),
  99         MLX4_MTT_ENTRY_PER_SEG  = 8,
 100 };
 101
 102 enum {
 103         MLX4_NUM_PDS            = 1 << 15
 104 };
 105
 106 enum {
 107         MLX4_CMPT_TYPE_QP       = 0,
 108         MLX4_CMPT_TYPE_SRQ      = 1,
 109         MLX4_CMPT_TYPE_CQ       = 2,
 110         MLX4_CMPT_TYPE_EQ       = 3,
 111         MLX4_CMPT_NUM_TYPE
 112 };
 113
 114 enum {
 115         MLX4_CMPT_SHIFT         = 24,
 116         MLX4_NUM_CMPTS          = MLX4_CMPT_NUM_TYPE << MLX4_CMPT_SHIFT
 117 };
 118
 119 enum mlx4_mr_state {
 120         MLX4_MR_DISABLED = 0,
 121         MLX4_MR_EN_HW,
 122         MLX4_MR_EN_SW
 123 };
 124
 125 #define MLX4_COMM_TIME          10000
 126 enum {
 127         MLX4_COMM_CMD_RESET,
 128         MLX4_COMM_CMD_VHCR0,
 129         MLX4_COMM_CMD_VHCR1,
 130         MLX4_COMM_CMD_VHCR2,
 131         MLX4_COMM_CMD_VHCR_EN,
 132         MLX4_COMM_CMD_VHCR_POST,
 133         MLX4_COMM_CMD_FLR = 254
 134 };
 135
 136 /*The flag indicates that the slave should delay the RESET cmd*/
 137 #define MLX4_DELAY_RESET_SLAVE 0xbbbbbbb
 138 /*indicates how many retries will be done if we are in the middle of FLR*/
 139 #define NUM_OF_RESET_RETRIES    10
 140 #define SLEEP_TIME_IN_RESET     (2 * 1000)
 141 enum mlx4_resource {
 142         RES_QP,
 143         RES_CQ,
 144         RES_SRQ,
 145         RES_XRCD,
 146         RES_MPT,
 147         RES_MTT,
 148         RES_MAC,
 149         RES_VLAN,
 150         RES_EQ,
 151         RES_COUNTER,
 152         MLX4_NUM_OF_RESOURCE_TYPE
 153 };
 154
 155 enum mlx4_alloc_mode {
 156         RES_OP_RESERVE,
 157         RES_OP_RESERVE_AND_MAP,
 158         RES_OP_MAP_ICM,
 159 };
 160
 161 enum mlx4_res_tracker_free_type {
 162         RES_TR_FREE_ALL,
 163         RES_TR_FREE_SLAVES_ONLY,
 164         RES_TR_FREE_STRUCTS_ONLY,
 165 };
 166
 167 /*
 168  *Virtual HCR structures.
 169  * mlx4_vhcr is the sw representation, in machine endianess
 170  *
 171  * mlx4_vhcr_cmd is the formalized structure, the one that is passed
 172  * to FW to go through communication channel.
 173  * It is big endian, and has the same structure as the physical HCR
 174  * used by command interface
 175  */
 176 struct mlx4_vhcr {
 177         u64     in_param;
 178         u64     out_param;
 179         u32     in_modifier;
 180         u32     errno;
 181         u16     op;
 182         u16     token;
 183         u8      op_modifier;
 184         u8      e_bit;
 185 };
 186
 187 struct mlx4_vhcr_cmd {
 188         __be64 in_param;
 189         __be32 in_modifier;
 190         __be64 out_param;
 191         __be16 token;
 192         u16 reserved;
 193         u8 status;
 194         u8 flags;
 195         __be16 opcode;
 196 };
 197
 198 struct mlx4_cmd_info {
 199         u16 opcode;
 200         bool has_inbox;
 201         bool has_outbox;
 202         bool out_is_imm;
 203         bool encode_slave_id;
 204         int (*verify)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr,
 205                       struct mlx4_cmd_mailbox *inbox);
 206         int (*wrapper)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr,
 207                        struct mlx4_cmd_mailbox *inbox,
 208                        struct mlx4_cmd_mailbox *outbox,
 209                        struct mlx4_cmd_info *cmd);
 210 };
 211
 212 #ifdef CONFIG_MLX4_DEBUG
 213 extern int mlx4_debug_level;
 214 #else /* CONFIG_MLX4_DEBUG */
 215 #define mlx4_debug_level        (0)
 216 #endif /* CONFIG_MLX4_DEBUG */
 217
 218 #define mlx4_dbg(mdev, format, arg...)                                  \
 219 do {                                                                    \
 220         if (mlx4_debug_level)                                           \
 221                 dev_printk(KERN_DEBUG, &mdev->pdev->dev, format, ##arg); \
 222 } while (0)
 223
 224 #define mlx4_err(mdev, format, arg...) \
 225         dev_err(&mdev->pdev->dev, format, ##arg)
 226 #define mlx4_info(mdev, format, arg...) \
 227         dev_info(&mdev->pdev->dev, format, ##arg)
 228 #define mlx4_warn(mdev, format, arg...) \
 229         dev_warn(&mdev->pdev->dev, format, ##arg)
 230
 231 extern int mlx4_log_num_mgm_entry_size;
 232 extern int log_mtts_per_seg;
 233
 234 #define MLX4_MAX_NUM_SLAVES     (MLX4_MAX_NUM_PF + MLX4_MAX_NUM_VF)
 235 #define ALL_SLAVES 0xff
 236
 237 struct mlx4_bitmap {
 238         u32                     last;
 239         u32                     top;
 240         u32                     max;
 241         u32                     reserved_top;
 242         u32                     mask;
 243         u32                     avail;
 244         spinlock_t              lock;
 245         unsigned long          *table;
 246 };
 247
 248 struct mlx4_buddy {
 249         unsigned long         **bits;
 250         unsigned int           *num_free;
 251         int                     max_order;
 252         spinlock_t              lock;
 253 };
 254
 255 struct mlx4_icm;
 256
 257 struct mlx4_icm_table {
 258         u64                     virt;
 259         int                     num_icm;
 260         int                     num_obj;
 261         int                     obj_size;
 262         int                     lowmem;
 263         int                     coherent;
 264         struct mutex            mutex;
 265         struct mlx4_icm       **icm;
 266 };
 267
 268 /*
 269  * Must be packed because mtt_seg is 64 bits but only aligned to 32 bits.
 270  */
 271 struct mlx4_mpt_entry {
 272         __be32 flags;
 273         __be32 qpn;
 274         __be32 key;
 275         __be32 pd_flags;
 276         __be64 start;
 277         __be64 length;
 278         __be32 lkey;
 279         __be32 win_cnt;
 280         u8      reserved1[3];
 281         u8      mtt_rep;
 282         __be64 mtt_addr;
 283         __be32 mtt_sz;
 284         __be32 entity_size;
 285         __be32 first_byte_offset;
 286 } __packed;
 287
 288 /*
 289  * Must be packed because start is 64 bits but only aligned to 32 bits.
 290  */
 291 struct mlx4_eq_context {
 292         __be32                  flags;
 293         u16                     reserved1[3];
 294         __be16                  page_offset;
 295         u8                      log_eq_size;
 296         u8                      reserved2[4];
 297         u8                      eq_period;
 298         u8                      reserved3;
 299         u8                      eq_max_count;
 300         u8                      reserved4[3];
 301         u8                      intr;
 302         u8                      log_page_size;
 303         u8                      reserved5[2];
 304         u8                      mtt_base_addr_h;
 305         __be32                  mtt_base_addr_l;
 306         u32                     reserved6[2];
 307         __be32                  consumer_index;
 308         __be32                  producer_index;
 309         u32                     reserved7[4];
 310 };
 311
 312 struct mlx4_cq_context {
 313         __be32                  flags;
 314         u16                     reserved1[3];
 315         __be16                  page_offset;
 316         __be32                  logsize_usrpage;
 317         __be16                  cq_period;
 318         __be16                  cq_max_count;
 319         u8                      reserved2[3];
 320         u8                      comp_eqn;
 321         u8                      log_page_size;
 322         u8                      reserved3[2];
 323         u8                      mtt_base_addr_h;
 324         __be32                  mtt_base_addr_l;
 325         __be32                  last_notified_index;
 326         __be32                  solicit_producer_index;
 327         __be32                  consumer_index;
 328         __be32                  producer_index;
 329         u32                     reserved4[2];
 330         __be64                  db_rec_addr;
 331 };
 332
 333 struct mlx4_srq_context {
 334         __be32                  state_logsize_srqn;
 335         u8                      logstride;
 336         u8                      reserved1;
 337         __be16                  xrcd;
 338         __be32                  pg_offset_cqn;
 339         u32                     reserved2;
 340         u8                      log_page_size;
 341         u8                      reserved3[2];
 342         u8                      mtt_base_addr_h;
 343         __be32                  mtt_base_addr_l;
 344         __be32                  pd;
 345         __be16                  limit_watermark;
 346         __be16                  wqe_cnt;
 347         u16                     reserved4;
 348         __be16                  wqe_counter;
 349         u32                     reserved5;
 350         __be64                  db_rec_addr;
 351 };
 352
 353 struct mlx4_eqe {
 354         u8                      reserved1;
 355         u8                      type;
 356         u8                      reserved2;
 357         u8                      subtype;
 358         union {
 359                 u32             raw[6];
 360                 struct {
 361                         __be32  cqn;
 362                 } __packed comp;
 363                 struct {
 364                         u16     reserved1;
 365                         __be16  token;
 366                         u32     reserved2;
 367                         u8      reserved3[3];
 368                         u8      status;
 369                         __be64  out_param;
 370                 } __packed cmd;
 371                 struct {
 372                         __be32  qpn;
 373                 } __packed qp;
 374                 struct {
 375                         __be32  srqn;
 376                 } __packed srq;
 377                 struct {
 378                         __be32  cqn;
 379                         u32     reserved1;
 380                         u8      reserved2[3];
 381                         u8      syndrome;
 382                 } __packed cq_err;
 383                 struct {
 384                         u32     reserved1[2];
 385                         __be32  port;
 386                 } __packed port_change;
 387                 struct {
 388                         #define COMM_CHANNEL_BIT_ARRAY_SIZE     4
 389                         u32 reserved;
 390                         u32 bit_vec[COMM_CHANNEL_BIT_ARRAY_SIZE];
 391                 } __packed comm_channel_arm;
 392                 struct {
 393                         u8      port;
 394                         u8      reserved[3];
 395                         __be64  mac;
 396                 } __packed mac_update;
 397                 struct {
 398                         u8      port;
 399                 } __packed sw_event;
 400                 struct {
 401                         __be32  slave_id;
 402                 } __packed flr_event;
 403                 struct {
 404                         __be16  current_temperature;
 405                         __be16  warning_threshold;
 406                 } __packed warming;
 407         }                       event;
 408         u8                      slave_id;
 409         u8                      reserved3[2];
 410         u8                      owner;
 411 } __packed;
 412
 413 struct mlx4_eq {
 414         struct mlx4_dev        *dev;
 415         void __iomem           *doorbell;
 416         int                     eqn;
 417         u32                     cons_index;
 418         u16                     irq;
 419         u16                     have_irq;
 420         int                     nent;
 421         struct mlx4_buf_list   *page_list;
 422         struct mlx4_mtt         mtt;
 423 };
 424
 425 struct mlx4_slave_eqe {
 426         u8 type;
 427         u8 port;
 428         u32 param;
 429 };
 430
 431 struct mlx4_slave_event_eq_info {
 432         int eqn;
 433         u16 token;
 434 };
 435
 436 struct mlx4_profile {
 437         int                     num_qp;
 438         int                     rdmarc_per_qp;
 439         int                     num_srq;
 440         int                     num_cq;
 441         int                     num_mcg;
 442         int                     num_mpt;
 443         unsigned                num_mtt;
 444 };
 445
 446 struct mlx4_fw {
 447         u64                     clr_int_base;
 448         u64                     catas_offset;
 449         u64                     comm_base;
 450         struct mlx4_icm        *fw_icm;
 451         struct mlx4_icm        *aux_icm;
 452         u32                     catas_size;
 453         u16                     fw_pages;
 454         u8                      clr_int_bar;
 455         u8                      catas_bar;
 456         u8                      comm_bar;
 457 };
 458
 459 struct mlx4_comm {
 460         u32                     slave_write;
 461         u32                     slave_read;
 462 };
 463
 464 enum {
 465         MLX4_MCAST_CONFIG       = 0,
 466         MLX4_MCAST_DISABLE      = 1,
 467         MLX4_MCAST_ENABLE       = 2,
 468 };
 469
 470 #define VLAN_FLTR_SIZE  128
 471
 472 struct mlx4_vlan_fltr {
 473         __be32 entry[VLAN_FLTR_SIZE];
 474 };
 475
 476 struct mlx4_mcast_entry {
 477         struct list_head list;
 478         u64 addr;
 479 };
 480
 481 struct mlx4_promisc_qp {
 482         struct list_head list;
 483         u32 qpn;
 484 };
 485
 486 struct mlx4_steer_index {
 487         struct list_head list;
 488         unsigned int index;
 489         struct list_head duplicates;
 490 };
 491
 492 #define MLX4_EVENT_TYPES_NUM 64
 493
 494 struct mlx4_slave_state {
 495         u8 comm_toggle;
 496         u8 last_cmd;
 497         u8 init_port_mask;
 498         bool active;
 499         u8 function;
 500         dma_addr_t vhcr_dma;
 501         u16 mtu[MLX4_MAX_PORTS + 1];
 502         __be32 ib_cap_mask[MLX4_MAX_PORTS + 1];
 503         struct mlx4_slave_eqe eq[MLX4_MFUNC_MAX_EQES];
 504         struct list_head mcast_filters[MLX4_MAX_PORTS + 1];
 505         struct mlx4_vlan_fltr *vlan_filter[MLX4_MAX_PORTS + 1];
 506         /* event type to eq number lookup */
 507         struct mlx4_slave_event_eq_info event_eq[MLX4_EVENT_TYPES_NUM];
 508         u16 eq_pi;
 509         u16 eq_ci;
 510         spinlock_t lock;
 511         /*initialized via the kzalloc*/
 512         u8 is_slave_going_down;
 513         u32 cookie;
 514 };
 515
 516 struct slave_list {
 517         struct mutex mutex;
 518         struct list_head res_list[MLX4_NUM_OF_RESOURCE_TYPE];
 519 };
 520
 521 struct mlx4_resource_tracker {
 522         spinlock_t lock;
 523         /* tree for each resources */
 524         struct rb_root res_tree[MLX4_NUM_OF_RESOURCE_TYPE];
 525         /* num_of_slave's lists, one per slave */
 526         struct slave_list *slave_list;
 527 };
 528
 529 #define SLAVE_EVENT_EQ_SIZE     128
 530 struct mlx4_slave_event_eq {
 531         u32 eqn;
 532         u32 cons;
 533         u32 prod;
 534         struct mlx4_eqe event_eqe[SLAVE_EVENT_EQ_SIZE];
 535 };
 536
 537 struct mlx4_master_qp0_state {
 538         int proxy_qp0_active;
 539         int qp0_active;
 540         int port_active;
 541 };
 542
 543 struct mlx4_mfunc_master_ctx {
 544         struct mlx4_slave_state *slave_state;
 545         struct mlx4_master_qp0_state qp0_state[MLX4_MAX_PORTS + 1];
 546         int                     init_port_ref[MLX4_MAX_PORTS + 1];
 547         u16                     max_mtu[MLX4_MAX_PORTS + 1];
 548         int                     disable_mcast_ref[MLX4_MAX_PORTS + 1];
 549         struct mlx4_resource_tracker res_tracker;
 550         struct workqueue_struct *comm_wq;
 551         struct work_struct      comm_work;
 552         struct work_struct      slave_event_work;
 553         struct work_struct      slave_flr_event_work;
 554         spinlock_t              slave_state_lock;
 555         __be32                  comm_arm_bit_vector[4];
 556         struct mlx4_eqe         cmd_eqe;
 557         struct mlx4_slave_event_eq slave_eq;
 558         struct mutex            gen_eqe_mutex[MLX4_MFUNC_MAX];
 559 };
 560
 561 struct mlx4_mfunc {
 562         struct mlx4_comm __iomem       *comm;
 563         struct mlx4_vhcr_cmd           *vhcr;
 564         dma_addr_t                      vhcr_dma;
 565
 566         struct mlx4_mfunc_master_ctx    master;
 567 };
 568
 569 struct mlx4_cmd {
 570         struct pci_pool        *pool;
 571         void __iomem           *hcr;
 572         struct mutex            hcr_mutex;
 573         struct semaphore        poll_sem;
 574         struct semaphore        event_sem;
 575         struct semaphore        slave_sem;
 576         int                     max_cmds;
 577         spinlock_t              context_lock;
 578         int                     free_head;
 579         struct mlx4_cmd_context *context;
 580         u16                     token_mask;
 581         u8                      use_events;
 582         u8                      toggle;
 583         u8                      comm_toggle;
 584 };
 585
 586 struct mlx4_uar_table {
 587         struct mlx4_bitmap      bitmap;
 588 };
 589
 590 struct mlx4_mr_table {
 591         struct mlx4_bitmap      mpt_bitmap;
 592         struct mlx4_buddy       mtt_buddy;
 593         u64                     mtt_base;
 594         u64                     mpt_base;
 595         struct mlx4_icm_table   mtt_table;
 596         struct mlx4_icm_table   dmpt_table;
 597 };
 598
 599 struct mlx4_cq_table {
 600         struct mlx4_bitmap      bitmap;
 601         spinlock_t              lock;
 602         struct radix_tree_root  tree;
 603         struct mlx4_icm_table   table;
 604         struct mlx4_icm_table   cmpt_table;
 605 };
 606
 607 struct mlx4_eq_table {
 608         struct mlx4_bitmap      bitmap;
 609         char                   *irq_names;
 610         void __iomem           *clr_int;
 611         void __iomem          **uar_map;
 612         u32                     clr_mask;
 613         struct mlx4_eq         *eq;
 614         struct mlx4_icm_table   table;
 615         struct mlx4_icm_table   cmpt_table;
 616         int                     have_irq;
 617         u8                      inta_pin;
 618 };
 619
 620 struct mlx4_srq_table {
 621         struct mlx4_bitmap      bitmap;
 622         spinlock_t              lock;
 623         struct radix_tree_root  tree;
 624         struct mlx4_icm_table   table;
 625         struct mlx4_icm_table   cmpt_table;
 626 };
 627
 628 struct mlx4_qp_table {
 629         struct mlx4_bitmap      bitmap;
 630         u32                     rdmarc_base;
 631         int                     rdmarc_shift;
 632         spinlock_t              lock;
 633         struct mlx4_icm_table   qp_table;
 634         struct mlx4_icm_table   auxc_table;
 635         struct mlx4_icm_table   altc_table;
 636         struct mlx4_icm_table   rdmarc_table;
 637         struct mlx4_icm_table   cmpt_table;
 638 };
 639
 640 struct mlx4_mcg_table {
 641         struct mutex            mutex;
 642         struct mlx4_bitmap      bitmap;
 643         struct mlx4_icm_table   table;
 644 };
 645
 646 struct mlx4_catas_err {
 647         u32 __iomem            *map;
 648         struct timer_list       timer;
 649         struct list_head        list;
 650 };
 651
 652 #define MLX4_MAX_MAC_NUM        128
 653 #define MLX4_MAC_TABLE_SIZE     (MLX4_MAX_MAC_NUM << 3)
 654
 655 struct mlx4_mac_table {
 656         __be64                  entries[MLX4_MAX_MAC_NUM];
 657         int                     refs[MLX4_MAX_MAC_NUM];
 658         struct mutex            mutex;
 659         int                     total;
 660         int                     max;
 661 };
 662
 663 #define MLX4_MAX_VLAN_NUM       128
 664 #define MLX4_VLAN_TABLE_SIZE    (MLX4_MAX_VLAN_NUM << 2)
 665
 666 struct mlx4_vlan_table {
 667         __be32                  entries[MLX4_MAX_VLAN_NUM];
 668         int                     refs[MLX4_MAX_VLAN_NUM];
 669         struct mutex            mutex;
 670         int                     total;
 671         int                     max;
 672 };
 673
 674 #define SET_PORT_GEN_ALL_VALID          0x7
 675 #define SET_PORT_PROMISC_SHIFT          31
 676 #define SET_PORT_MC_PROMISC_SHIFT       30
 677
 678 enum {
 679         MCAST_DIRECT_ONLY       = 0,
 680         MCAST_DIRECT            = 1,
 681         MCAST_DEFAULT           = 2
 682 };
 683
 684
 685 struct mlx4_set_port_general_context {
 686         u8 reserved[3];
 687         u8 flags;
 688         u16 reserved2;
 689         __be16 mtu;
 690         u8 pptx;
 691         u8 pfctx;
 692         u16 reserved3;
 693         u8 pprx;
 694         u8 pfcrx;
 695         u16 reserved4;
 696 };
 697
 698 struct mlx4_set_port_rqp_calc_context {
 699         __be32 base_qpn;
 700         u8 rererved;
 701         u8 n_mac;
 702         u8 n_vlan;
 703         u8 n_prio;
 704         u8 reserved2[3];
 705         u8 mac_miss;
 706         u8 intra_no_vlan;
 707         u8 no_vlan;
 708         u8 intra_vlan_miss;
 709         u8 vlan_miss;
 710         u8 reserved3[3];
 711         u8 no_vlan_prio;
 712         __be32 promisc;
 713         __be32 mcast;
 714 };
 715
 716 struct mlx4_mac_entry {
 717         u64 mac;
 718         u64 reg_id;
 719 };
 720
 721 struct mlx4_port_info {
 722         struct mlx4_dev        *dev;
 723         int                     port;
 724         char                    dev_name[16];
 725         struct device_attribute port_attr;
 726         enum mlx4_port_type     tmp_type;
 727         char                    dev_mtu_name[16];
 728         struct device_attribute port_mtu_attr;
 729         struct mlx4_mac_table   mac_table;
 730         struct radix_tree_root  mac_tree;
 731         struct mlx4_vlan_table  vlan_table;
 732         int                     base_qpn;
 733 };
 734
 735 struct mlx4_sense {
 736         struct mlx4_dev         *dev;
 737         u8                      do_sense_port[MLX4_MAX_PORTS + 1];
 738         u8                      sense_allowed[MLX4_MAX_PORTS + 1];
 739         struct delayed_work     sense_poll;
 740 };
 741
 742 struct mlx4_msix_ctl {
 743         u64             pool_bm;
 744         struct mutex    pool_lock;
 745 };
 746
 747 struct mlx4_steer {
 748         struct list_head promisc_qps[MLX4_NUM_STEERS];
 749         struct list_head steer_entries[MLX4_NUM_STEERS];
 750 };
 751
 752 struct mlx4_priv {
 753         struct mlx4_dev         dev;
 754
 755         struct list_head        dev_list;
 756         struct list_head        ctx_list;
 757         spinlock_t              ctx_lock;
 758
 759         struct list_head        pgdir_list;
 760         struct mutex            pgdir_mutex;
 761
 762         struct mlx4_fw          fw;
 763         struct mlx4_cmd         cmd;
 764         struct mlx4_mfunc       mfunc;
 765
 766         struct mlx4_bitmap      pd_bitmap;
 767         struct mlx4_bitmap      xrcd_bitmap;
 768         struct mlx4_uar_table   uar_table;
 769         struct mlx4_mr_table    mr_table;
 770         struct mlx4_cq_table    cq_table;
 771         struct mlx4_eq_table    eq_table;
 772         struct mlx4_srq_table   srq_table;
 773         struct mlx4_qp_table    qp_table;
 774         struct mlx4_mcg_table   mcg_table;
 775         struct mlx4_bitmap      counters_bitmap;
 776
 777         struct mlx4_catas_err   catas_err;
 778
 779         void __iomem           *clr_base;
 780
 781         struct mlx4_uar         driver_uar;
 782         void __iomem           *kar;
 783         struct mlx4_port_info   port[MLX4_MAX_PORTS + 1];
 784         struct mlx4_sense       sense;
 785         struct mutex            port_mutex;
 786         struct mlx4_msix_ctl    msix_ctl;
 787         struct mlx4_steer       *steer;
 788         struct list_head        bf_list;
 789         struct mutex            bf_mutex;
 790         struct io_mapping       *bf_mapping;
 791         int                     reserved_mtts;
 792         int                     fs_hash_mode;
 793 };
 794
 795 static inline struct mlx4_priv *mlx4_priv(struct mlx4_dev *dev)
 796 {
 797         return container_of(dev, struct mlx4_priv, dev);
 798 }
 799
 800 #define MLX4_SENSE_RANGE        (HZ * 3)
 801
 802 extern struct workqueue_struct *mlx4_wq;
 803
 804 u32 mlx4_bitmap_alloc(struct mlx4_bitmap *bitmap);
 805 void mlx4_bitmap_free(struct mlx4_bitmap *bitmap, u32 obj);
 806 u32 mlx4_bitmap_alloc_range(struct mlx4_bitmap *bitmap, int cnt, int align);
 807 void mlx4_bitmap_free_range(struct mlx4_bitmap *bitmap, u32 obj, int cnt);
 808 u32 mlx4_bitmap_avail(struct mlx4_bitmap *bitmap);
 809 int mlx4_bitmap_init(struct mlx4_bitmap *bitmap, u32 num, u32 mask,
 810                      u32 reserved_bot, u32 resetrved_top);
 811 void mlx4_bitmap_cleanup(struct mlx4_bitmap *bitmap);
 812
 813 int mlx4_reset(struct mlx4_dev *dev);
 814
 815 int mlx4_alloc_eq_table(struct mlx4_dev *dev);
 816 void mlx4_free_eq_table(struct mlx4_dev *dev);
 817
 818 int mlx4_init_pd_table(struct mlx4_dev *dev);
 819 int mlx4_init_xrcd_table(struct mlx4_dev *dev);
 820 int mlx4_init_uar_table(struct mlx4_dev *dev);
 821 int mlx4_init_mr_table(struct mlx4_dev *dev);
 822 int mlx4_init_eq_table(struct mlx4_dev *dev);
 823 int mlx4_init_cq_table(struct mlx4_dev *dev);
 824 int mlx4_init_qp_table(struct mlx4_dev *dev);
 825 int mlx4_init_srq_table(struct mlx4_dev *dev);
 826 int mlx4_init_mcg_table(struct mlx4_dev *dev);
 827
 828 void mlx4_cleanup_pd_table(struct mlx4_dev *dev);
 829 void mlx4_cleanup_xrcd_table(struct mlx4_dev *dev);
 830 void mlx4_cleanup_uar_table(struct mlx4_dev *dev);
 831 void mlx4_cleanup_mr_table(struct mlx4_dev *dev);
 832 void mlx4_cleanup_eq_table(struct mlx4_dev *dev);
 833 void mlx4_cleanup_cq_table(struct mlx4_dev *dev);
 834 void mlx4_cleanup_qp_table(struct mlx4_dev *dev);
 835 void mlx4_cleanup_srq_table(struct mlx4_dev *dev);
 836 void mlx4_cleanup_mcg_table(struct mlx4_dev *dev);
 837 int __mlx4_qp_alloc_icm(struct mlx4_dev *dev, int qpn);
 838 void __mlx4_qp_free_icm(struct mlx4_dev *dev, int qpn);
 839 int __mlx4_cq_alloc_icm(struct mlx4_dev *dev, int *cqn);
 840 void __mlx4_cq_free_icm(struct mlx4_dev *dev, int cqn);
 841 int __mlx4_srq_alloc_icm(struct mlx4_dev *dev, int *srqn);
 842 void __mlx4_srq_free_icm(struct mlx4_dev *dev, int srqn);
 843 int __mlx4_mr_reserve(struct mlx4_dev *dev);
 844 void __mlx4_mr_release(struct mlx4_dev *dev, u32 index);
 845 int __mlx4_mr_alloc_icm(struct mlx4_dev *dev, u32 index);
 846 void __mlx4_mr_free_icm(struct mlx4_dev *dev, u32 index);
 847 u32 __mlx4_alloc_mtt_range(struct mlx4_dev *dev, int order);
 848 void __mlx4_free_mtt_range(struct mlx4_dev *dev, u32 first_seg, int order);
 849
 850 int mlx4_WRITE_MTT_wrapper(struct mlx4_dev *dev, int slave,
 851                            struct mlx4_vhcr *vhcr,
 852                            struct mlx4_cmd_mailbox *inbox,
 853                            struct mlx4_cmd_mailbox *outbox,
 854                            struct mlx4_cmd_info *cmd);
 855 int mlx4_SYNC_TPT_wrapper(struct mlx4_dev *dev, int slave,
 856                            struct mlx4_vhcr *vhcr,
 857                            struct mlx4_cmd_mailbox *inbox,
 858                            struct mlx4_cmd_mailbox *outbox,
 859                            struct mlx4_cmd_info *cmd);
 860 int mlx4_SW2HW_MPT_wrapper(struct mlx4_dev *dev, int slave,
 861                            struct mlx4_vhcr *vhcr,
 862                            struct mlx4_cmd_mailbox *inbox,
 863                            struct mlx4_cmd_mailbox *outbox,
 864                            struct mlx4_cmd_info *cmd);
 865 int mlx4_HW2SW_MPT_wrapper(struct mlx4_dev *dev, int slave,
 866                            struct mlx4_vhcr *vhcr,
 867                            struct mlx4_cmd_mailbox *inbox,
 868                            struct mlx4_cmd_mailbox *outbox,
 869                            struct mlx4_cmd_info *cmd);
 870 int mlx4_QUERY_MPT_wrapper(struct mlx4_dev *dev, int slave,
 871                            struct mlx4_vhcr *vhcr,
 872                            struct mlx4_cmd_mailbox *inbox,
 873                            struct mlx4_cmd_mailbox *outbox,
 874                            struct mlx4_cmd_info *cmd);
 875 int mlx4_SW2HW_EQ_wrapper(struct mlx4_dev *dev, int slave,
 876                           struct mlx4_vhcr *vhcr,
 877                           struct mlx4_cmd_mailbox *inbox,
 878                           struct mlx4_cmd_mailbox *outbox,
 879                           struct mlx4_cmd_info *cmd);
 880 int mlx4_DMA_wrapper(struct mlx4_dev *dev, int slave,
 881                      struct mlx4_vhcr *vhcr,
 882                      struct mlx4_cmd_mailbox *inbox,
 883                      struct mlx4_cmd_mailbox *outbox,
 884                      struct mlx4_cmd_info *cmd);
 885 int __mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align,
 886                             int *base);
 887 void __mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt);
 888 int __mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac);
 889 void __mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac);
 890 int __mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac);
 891 int __mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
 892                      int start_index, int npages, u64 *page_list);
 893 int __mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx);
 894 void __mlx4_counter_free(struct mlx4_dev *dev, u32 idx);
 895 int __mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn);
 896 void __mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn);
 897
 898 void mlx4_start_catas_poll(struct mlx4_dev *dev);
 899 void mlx4_stop_catas_poll(struct mlx4_dev *dev);
 900 void mlx4_catas_init(void);
 901 int mlx4_restart_one(struct pci_dev *pdev);
 902 int mlx4_register_device(struct mlx4_dev *dev);
 903 void mlx4_unregister_device(struct mlx4_dev *dev);
 904 void mlx4_dispatch_event(struct mlx4_dev *dev, enum mlx4_dev_event type, int port);
 905
 906 struct mlx4_dev_cap;
 907 struct mlx4_init_hca_param;
 908
 909 u64 mlx4_make_profile(struct mlx4_dev *dev,
 910                       struct mlx4_profile *request,
 911                       struct mlx4_dev_cap *dev_cap,
 912                       struct mlx4_init_hca_param *init_hca);
 913 void mlx4_master_comm_channel(struct work_struct *work);
 914 void mlx4_gen_slave_eqe(struct work_struct *work);
 915 void mlx4_master_handle_slave_flr(struct work_struct *work);
 916
 917 int mlx4_ALLOC_RES_wrapper(struct mlx4_dev *dev, int slave,
 918                            struct mlx4_vhcr *vhcr,
 919                            struct mlx4_cmd_mailbox *inbox,
 920                            struct mlx4_cmd_mailbox *outbox,
 921                            struct mlx4_cmd_info *cmd);
 922 int mlx4_FREE_RES_wrapper(struct mlx4_dev *dev, int slave,
 923                           struct mlx4_vhcr *vhcr,
 924                           struct mlx4_cmd_mailbox *inbox,
 925                           struct mlx4_cmd_mailbox *outbox,
 926                           struct mlx4_cmd_info *cmd);
 927 int mlx4_MAP_EQ_wrapper(struct mlx4_dev *dev, int slave,
 928                         struct mlx4_vhcr *vhcr, struct mlx4_cmd_mailbox *inbox,
 929                         struct mlx4_cmd_mailbox *outbox,
 930                         struct mlx4_cmd_info *cmd);
 931 int mlx4_COMM_INT_wrapper(struct mlx4_dev *dev, int slave,
 932                           struct mlx4_vhcr *vhcr,
 933                           struct mlx4_cmd_mailbox *inbox,
 934                           struct mlx4_cmd_mailbox *outbox,
 935                           struct mlx4_cmd_info *cmd);
 936 int mlx4_HW2SW_EQ_wrapper(struct mlx4_dev *dev, int slave,
 937                             struct mlx4_vhcr *vhcr,
 938                             struct mlx4_cmd_mailbox *inbox,
 939                             struct mlx4_cmd_mailbox *outbox,
 940                           struct mlx4_cmd_info *cmd);
 941 int mlx4_QUERY_EQ_wrapper(struct mlx4_dev *dev, int slave,
 942                           struct mlx4_vhcr *vhcr,
 943                           struct mlx4_cmd_mailbox *inbox,
 944                           struct mlx4_cmd_mailbox *outbox,
 945                           struct mlx4_cmd_info *cmd);
 946 int mlx4_SW2HW_CQ_wrapper(struct mlx4_dev *dev, int slave,
 947                           struct mlx4_vhcr *vhcr,
 948                           struct mlx4_cmd_mailbox *inbox,
 949                           struct mlx4_cmd_mailbox *outbox,
 950                           struct mlx4_cmd_info *cmd);
 951 int mlx4_HW2SW_CQ_wrapper(struct mlx4_dev *dev, int slave,
 952                           struct mlx4_vhcr *vhcr,
 953                           struct mlx4_cmd_mailbox *inbox,
 954                           struct mlx4_cmd_mailbox *outbox,
 955                           struct mlx4_cmd_info *cmd);
 956 int mlx4_QUERY_CQ_wrapper(struct mlx4_dev *dev, int slave,
 957                           struct mlx4_vhcr *vhcr,
 958                           struct mlx4_cmd_mailbox *inbox,
 959                           struct mlx4_cmd_mailbox *outbox,
 960                           struct mlx4_cmd_info *cmd);
 961 int mlx4_MODIFY_CQ_wrapper(struct mlx4_dev *dev, int slave,
 962                           struct mlx4_vhcr *vhcr,
 963                           struct mlx4_cmd_mailbox *inbox,
 964                           struct mlx4_cmd_mailbox *outbox,
 965                            struct mlx4_cmd_info *cmd);
 966 int mlx4_SW2HW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
 967                            struct mlx4_vhcr *vhcr,
 968                            struct mlx4_cmd_mailbox *inbox,
 969                            struct mlx4_cmd_mailbox *outbox,
 970                            struct mlx4_cmd_info *cmd);
 971 int mlx4_HW2SW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
 972                            struct mlx4_vhcr *vhcr,
 973                            struct mlx4_cmd_mailbox *inbox,
 974                            struct mlx4_cmd_mailbox *outbox,
 975                            struct mlx4_cmd_info *cmd);
 976 int mlx4_QUERY_SRQ_wrapper(struct mlx4_dev *dev, int slave,
 977                            struct mlx4_vhcr *vhcr,
 978                            struct mlx4_cmd_mailbox *inbox,
 979                            struct mlx4_cmd_mailbox *outbox,
 980                            struct mlx4_cmd_info *cmd);
 981 int mlx4_ARM_SRQ_wrapper(struct mlx4_dev *dev, int slave,
 982                          struct mlx4_vhcr *vhcr,
 983                          struct mlx4_cmd_mailbox *inbox,
 984                          struct mlx4_cmd_mailbox *outbox,
 985                          struct mlx4_cmd_info *cmd);
 986 int mlx4_GEN_QP_wrapper(struct mlx4_dev *dev, int slave,
 987                         struct mlx4_vhcr *vhcr,
 988                         struct mlx4_cmd_mailbox *inbox,
 989                         struct mlx4_cmd_mailbox *outbox,
 990                         struct mlx4_cmd_info *cmd);
 991 int mlx4_RST2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
 992                              struct mlx4_vhcr *vhcr,
 993                              struct mlx4_cmd_mailbox *inbox,
 994                              struct mlx4_cmd_mailbox *outbox,
 995                              struct mlx4_cmd_info *cmd);
 996 int mlx4_INIT2RTR_QP_wrapper(struct mlx4_dev *dev, int slave,
 997                              struct mlx4_vhcr *vhcr,
 998                              struct mlx4_cmd_mailbox *inbox,
 999                              struct mlx4_cmd_mailbox *outbox,
1000                              struct mlx4_cmd_info *cmd);
1001 int mlx4_2RST_QP_wrapper(struct mlx4_dev *dev, int slave,
1002                          struct mlx4_vhcr *vhcr,
1003                          struct mlx4_cmd_mailbox *inbox,
1004                          struct mlx4_cmd_mailbox *outbox,
1005                          struct mlx4_cmd_info *cmd);
1006
1007 int mlx4_GEN_EQE(struct mlx4_dev *dev, int slave, struct mlx4_eqe *eqe);
1008
1009 int mlx4_cmd_init(struct mlx4_dev *dev);
1010 void mlx4_cmd_cleanup(struct mlx4_dev *dev);
1011 int mlx4_multi_func_init(struct mlx4_dev *dev);
1012 void mlx4_multi_func_cleanup(struct mlx4_dev *dev);
1013 void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param);
1014 int mlx4_cmd_use_events(struct mlx4_dev *dev);
1015 void mlx4_cmd_use_polling(struct mlx4_dev *dev);
1016
1017 int mlx4_comm_cmd(struct mlx4_dev *dev, u8 cmd, u16 param,
1018                   unsigned long timeout);
1019
1020 void mlx4_cq_completion(struct mlx4_dev *dev, u32 cqn);
1021 void mlx4_cq_event(struct mlx4_dev *dev, u32 cqn, int event_type);
1022
1023 void mlx4_qp_event(struct mlx4_dev *dev, u32 qpn, int event_type);
1024
1025 void mlx4_srq_event(struct mlx4_dev *dev, u32 srqn, int event_type);
1026
1027 void mlx4_handle_catas_err(struct mlx4_dev *dev);
1028
1029 int mlx4_SENSE_PORT(struct mlx4_dev *dev, int port,
1030                     enum mlx4_port_type *type);
1031 void mlx4_do_sense_ports(struct mlx4_dev *dev,
1032                          enum mlx4_port_type *stype,
1033                          enum mlx4_port_type *defaults);
1034 void mlx4_start_sense(struct mlx4_dev *dev);
1035 void mlx4_stop_sense(struct mlx4_dev *dev);
1036 void mlx4_sense_init(struct mlx4_dev *dev);
1037 int mlx4_check_port_params(struct mlx4_dev *dev,
1038                            enum mlx4_port_type *port_type);
1039 int mlx4_change_port_types(struct mlx4_dev *dev,
1040                            enum mlx4_port_type *port_types);
1041
1042 void mlx4_init_mac_table(struct mlx4_dev *dev, struct mlx4_mac_table *table);
1043 void mlx4_init_vlan_table(struct mlx4_dev *dev, struct mlx4_vlan_table *table);
1044
1045 int mlx4_SET_PORT(struct mlx4_dev *dev, u8 port);
1046 /* resource tracker functions*/
1047 int mlx4_get_slave_from_resource_id(struct mlx4_dev *dev,
1048                                     enum mlx4_resource resource_type,
1049                                     u64 resource_id, int *slave);
1050 void mlx4_delete_all_resources_for_slave(struct mlx4_dev *dev, int slave_id);
1051 int mlx4_init_resource_tracker(struct mlx4_dev *dev);
1052
1053 void mlx4_free_resource_tracker(struct mlx4_dev *dev,
1054                                 enum mlx4_res_tracker_free_type type);
1055
1056 int mlx4_QUERY_FW_wrapper(struct mlx4_dev *dev, int slave,
1057                           struct mlx4_vhcr *vhcr,
1058                           struct mlx4_cmd_mailbox *inbox,
1059                           struct mlx4_cmd_mailbox *outbox,
1060                           struct mlx4_cmd_info *cmd);
1061 int mlx4_SET_PORT_wrapper(struct mlx4_dev *dev, int slave,
1062                           struct mlx4_vhcr *vhcr,
1063                           struct mlx4_cmd_mailbox *inbox,
1064                           struct mlx4_cmd_mailbox *outbox,
1065                           struct mlx4_cmd_info *cmd);
1066 int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave,
1067                            struct mlx4_vhcr *vhcr,
1068                            struct mlx4_cmd_mailbox *inbox,
1069                            struct mlx4_cmd_mailbox *outbox,
1070                            struct mlx4_cmd_info *cmd);
1071 int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave,
1072                             struct mlx4_vhcr *vhcr,
1073                             struct mlx4_cmd_mailbox *inbox,
1074                             struct mlx4_cmd_mailbox *outbox,
1075                             struct mlx4_cmd_info *cmd);
1076 int mlx4_QUERY_DEV_CAP_wrapper(struct mlx4_dev *dev, int slave,
1077                                struct mlx4_vhcr *vhcr,
1078                                struct mlx4_cmd_mailbox *inbox,
1079                                struct mlx4_cmd_mailbox *outbox,
1080                                struct mlx4_cmd_info *cmd);
1081 int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave,
1082                             struct mlx4_vhcr *vhcr,
1083                             struct mlx4_cmd_mailbox *inbox,
1084                             struct mlx4_cmd_mailbox *outbox,
1085                             struct mlx4_cmd_info *cmd);
1086 int mlx4_get_port_ib_caps(struct mlx4_dev *dev, u8 port, __be32 *caps);
1087
1088
1089 int mlx4_QP_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
1090                            struct mlx4_vhcr *vhcr,
1091                            struct mlx4_cmd_mailbox *inbox,
1092                            struct mlx4_cmd_mailbox *outbox,
1093                            struct mlx4_cmd_info *cmd);
1094
1095 int mlx4_PROMISC_wrapper(struct mlx4_dev *dev, int slave,
1096                          struct mlx4_vhcr *vhcr,
1097                          struct mlx4_cmd_mailbox *inbox,
1098                          struct mlx4_cmd_mailbox *outbox,
1099                          struct mlx4_cmd_info *cmd);
1100 int mlx4_qp_detach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1101                           enum mlx4_protocol prot, enum mlx4_steer_type steer);
1102 int mlx4_qp_attach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1103                           int block_mcast_loopback, enum mlx4_protocol prot,
1104                           enum mlx4_steer_type steer);
1105 int mlx4_SET_MCAST_FLTR_wrapper(struct mlx4_dev *dev, int slave,
1106                                 struct mlx4_vhcr *vhcr,
1107                                 struct mlx4_cmd_mailbox *inbox,
1108                                 struct mlx4_cmd_mailbox *outbox,
1109                                 struct mlx4_cmd_info *cmd);
1110 int mlx4_SET_VLAN_FLTR_wrapper(struct mlx4_dev *dev, int slave,
1111                                struct mlx4_vhcr *vhcr,
1112                                struct mlx4_cmd_mailbox *inbox,
1113                                struct mlx4_cmd_mailbox *outbox,
1114                                struct mlx4_cmd_info *cmd);
1115 int mlx4_common_set_vlan_fltr(struct mlx4_dev *dev, int function,
1116                                      int port, void *buf);
1117 int mlx4_common_dump_eth_stats(struct mlx4_dev *dev, int slave, u32 in_mod,
1118                                 struct mlx4_cmd_mailbox *outbox);
1119 int mlx4_DUMP_ETH_STATS_wrapper(struct mlx4_dev *dev, int slave,
1120                                    struct mlx4_vhcr *vhcr,
1121                                    struct mlx4_cmd_mailbox *inbox,
1122                                    struct mlx4_cmd_mailbox *outbox,
1123                                 struct mlx4_cmd_info *cmd);
1124 int mlx4_PKEY_TABLE_wrapper(struct mlx4_dev *dev, int slave,
1125                             struct mlx4_vhcr *vhcr,
1126                             struct mlx4_cmd_mailbox *inbox,
1127                             struct mlx4_cmd_mailbox *outbox,
1128                             struct mlx4_cmd_info *cmd);
1129 int mlx4_QUERY_IF_STAT_wrapper(struct mlx4_dev *dev, int slave,
1130                                struct mlx4_vhcr *vhcr,
1131                                struct mlx4_cmd_mailbox *inbox,
1132                                struct mlx4_cmd_mailbox *outbox,
1133                                struct mlx4_cmd_info *cmd);
1134 int mlx4_QP_FLOW_STEERING_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
1135                                          struct mlx4_vhcr *vhcr,
1136                                          struct mlx4_cmd_mailbox *inbox,
1137                                          struct mlx4_cmd_mailbox *outbox,
1138                                          struct mlx4_cmd_info *cmd);
1139 int mlx4_QP_FLOW_STEERING_DETACH_wrapper(struct mlx4_dev *dev, int slave,
1140                                          struct mlx4_vhcr *vhcr,
1141                                          struct mlx4_cmd_mailbox *inbox,
1142                                          struct mlx4_cmd_mailbox *outbox,
1143                                          struct mlx4_cmd_info *cmd);
1144
1145 int mlx4_get_mgm_entry_size(struct mlx4_dev *dev);
1146 int mlx4_get_qp_per_mgm(struct mlx4_dev *dev);
1147
1148 static inline void set_param_l(u64 *arg, u32 val)
1149 {
1150         *((u32 *)arg) = val;
1151 }
1152
1153 static inline void set_param_h(u64 *arg, u32 val)
1154 {
1155         *arg = (*arg & 0xffffffff) | ((u64) val << 32);
1156 }
1157
1158 static inline u32 get_param_l(u64 *arg)
1159 {
1160         return (u32) (*arg & 0xffffffff);
1161 }
1162
1163 static inline u32 get_param_h(u64 *arg)
1164 {
1165         return (u32)(*arg >> 32);
1166 }
1167
1168 static inline spinlock_t *mlx4_tlock(struct mlx4_dev *dev)
1169 {
1170         return &mlx4_priv(dev)->mfunc.master.res_tracker.lock;
1171 }
1172
1173 #define NOT_MASKED_PD_BITS 17
1174
1175 #endif /* MLX4_H */