drivers/net/ethernet/mellanox/mlx4/mlx4.h

   1 /*
   2  * Copyright (c) 2004, 2005 Topspin Communications.  All rights reserved.
   3  * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
   4  * Copyright (c) 2005, 2006, 2007 Cisco Systems.  All rights reserved.
   5  * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
   6  * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
   7  *
   8  * This software is available to you under a choice of one of two
   9  * licenses.  You may choose to be licensed under the terms of the GNU
  10  * General Public License (GPL) Version 2, available from the file
  11  * COPYING in the main directory of this source tree, or the
  12  * OpenIB.org BSD license below:
  13  *
  14  *     Redistribution and use in source and binary forms, with or
  15  *     without modification, are permitted provided that the following
  16  *     conditions are met:
  17  *
  18  *      - Redistributions of source code must retain the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer.
  21  *
  22  *      - Redistributions in binary form must reproduce the above
  23  *        copyright notice, this list of conditions and the following
  24  *        disclaimer in the documentation and/or other materials
  25  *        provided with the distribution.
  26  *
  27  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  28  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  29  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  30  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  31  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  32  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  33  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  34  * SOFTWARE.
  35  */
  36
  37 #ifndef MLX4_H
  38 #define MLX4_H
  39
  40 #include <linux/mutex.h>
  41 #include <linux/radix-tree.h>
  42 #include <linux/rbtree.h>
  43 #include <linux/timer.h>
  44 #include <linux/semaphore.h>
  45 #include <linux/workqueue.h>
  46
  47 #include <linux/mlx4/device.h>
  48 #include <linux/mlx4/driver.h>
  49 #include <linux/mlx4/doorbell.h>
  50 #include <linux/mlx4/cmd.h>
  51
  52 #define DRV_NAME        "mlx4_core"
  53 #define PFX             DRV_NAME ": "
  54 #define DRV_VERSION     "1.1"
  55 #define DRV_RELDATE     "Dec, 2011"
  56
  57 #define MLX4_NUM_UP             8
  58 #define MLX4_NUM_TC             8
  59 #define MLX4_RATELIMIT_UNITS 3 /* 100 Mbps */
  60 #define MLX4_RATELIMIT_DEFAULT 0xffff
  61
  62 struct mlx4_set_port_prio2tc_context {
  63         u8 prio2tc[4];
  64 };
  65
  66 struct mlx4_port_scheduler_tc_cfg_be {
  67         __be16 pg;
  68         __be16 bw_precentage;
  69         __be16 max_bw_units; /* 3-100Mbps, 4-1Gbps, other values - reserved */
  70         __be16 max_bw_value;
  71 };
  72
  73 struct mlx4_set_port_scheduler_context {
  74         struct mlx4_port_scheduler_tc_cfg_be tc[MLX4_NUM_TC];
  75 };
  76
  77 enum {
  78         MLX4_HCR_BASE           = 0x80680,
  79         MLX4_HCR_SIZE           = 0x0001c,
  80         MLX4_CLR_INT_SIZE       = 0x00008,
  81         MLX4_SLAVE_COMM_BASE    = 0x0,
  82         MLX4_COMM_PAGESIZE      = 0x1000
  83 };
  84
  85 enum {
  86         MLX4_MAX_MGM_ENTRY_SIZE = 0x1000,
  87         MLX4_MAX_QP_PER_MGM     = 4 * (MLX4_MAX_MGM_ENTRY_SIZE / 16 - 2),
  88         MLX4_MTT_ENTRY_PER_SEG  = 8,
  89 };
  90
  91 enum {
  92         MLX4_NUM_PDS            = 1 << 15
  93 };
  94
  95 enum {
  96         MLX4_CMPT_TYPE_QP       = 0,
  97         MLX4_CMPT_TYPE_SRQ      = 1,
  98         MLX4_CMPT_TYPE_CQ       = 2,
  99         MLX4_CMPT_TYPE_EQ       = 3,
 100         MLX4_CMPT_NUM_TYPE
 101 };
 102
 103 enum {
 104         MLX4_CMPT_SHIFT         = 24,
 105         MLX4_NUM_CMPTS          = MLX4_CMPT_NUM_TYPE << MLX4_CMPT_SHIFT
 106 };
 107
 108 enum mlx4_mr_state {
 109         MLX4_MR_DISABLED = 0,
 110         MLX4_MR_EN_HW,
 111         MLX4_MR_EN_SW
 112 };
 113
 114 #define MLX4_COMM_TIME          10000
 115 enum {
 116         MLX4_COMM_CMD_RESET,
 117         MLX4_COMM_CMD_VHCR0,
 118         MLX4_COMM_CMD_VHCR1,
 119         MLX4_COMM_CMD_VHCR2,
 120         MLX4_COMM_CMD_VHCR_EN,
 121         MLX4_COMM_CMD_VHCR_POST,
 122         MLX4_COMM_CMD_FLR = 254
 123 };
 124
 125 /*The flag indicates that the slave should delay the RESET cmd*/
 126 #define MLX4_DELAY_RESET_SLAVE 0xbbbbbbb
 127 /*indicates how many retries will be done if we are in the middle of FLR*/
 128 #define NUM_OF_RESET_RETRIES    10
 129 #define SLEEP_TIME_IN_RESET     (2 * 1000)
 130 enum mlx4_resource {
 131         RES_QP,
 132         RES_CQ,
 133         RES_SRQ,
 134         RES_XRCD,
 135         RES_MPT,
 136         RES_MTT,
 137         RES_MAC,
 138         RES_VLAN,
 139         RES_EQ,
 140         RES_COUNTER,
 141         MLX4_NUM_OF_RESOURCE_TYPE
 142 };
 143
 144 enum mlx4_alloc_mode {
 145         RES_OP_RESERVE,
 146         RES_OP_RESERVE_AND_MAP,
 147         RES_OP_MAP_ICM,
 148 };
 149
 150 enum mlx4_res_tracker_free_type {
 151         RES_TR_FREE_ALL,
 152         RES_TR_FREE_SLAVES_ONLY,
 153         RES_TR_FREE_STRUCTS_ONLY,
 154 };
 155
 156 /*
 157  *Virtual HCR structures.
 158  * mlx4_vhcr is the sw representation, in machine endianess
 159  *
 160  * mlx4_vhcr_cmd is the formalized structure, the one that is passed
 161  * to FW to go through communication channel.
 162  * It is big endian, and has the same structure as the physical HCR
 163  * used by command interface
 164  */
 165 struct mlx4_vhcr {
 166         u64     in_param;
 167         u64     out_param;
 168         u32     in_modifier;
 169         u32     errno;
 170         u16     op;
 171         u16     token;
 172         u8      op_modifier;
 173         u8      e_bit;
 174 };
 175
 176 struct mlx4_vhcr_cmd {
 177         __be64 in_param;
 178         __be32 in_modifier;
 179         __be64 out_param;
 180         __be16 token;
 181         u16 reserved;
 182         u8 status;
 183         u8 flags;
 184         __be16 opcode;
 185 };
 186
 187 struct mlx4_cmd_info {
 188         u16 opcode;
 189         bool has_inbox;
 190         bool has_outbox;
 191         bool out_is_imm;
 192         bool encode_slave_id;
 193         int (*verify)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr,
 194                       struct mlx4_cmd_mailbox *inbox);
 195         int (*wrapper)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr,
 196                        struct mlx4_cmd_mailbox *inbox,
 197                        struct mlx4_cmd_mailbox *outbox,
 198                        struct mlx4_cmd_info *cmd);
 199 };
 200
 201 #ifdef CONFIG_MLX4_DEBUG
 202 extern int mlx4_debug_level;
 203 #else /* CONFIG_MLX4_DEBUG */
 204 #define mlx4_debug_level        (0)
 205 #endif /* CONFIG_MLX4_DEBUG */
 206
 207 #define mlx4_dbg(mdev, format, arg...)                                  \
 208 do {                                                                    \
 209         if (mlx4_debug_level)                                           \
 210                 dev_printk(KERN_DEBUG, &mdev->pdev->dev, format, ##arg); \
 211 } while (0)
 212
 213 #define mlx4_err(mdev, format, arg...) \
 214         dev_err(&mdev->pdev->dev, format, ##arg)
 215 #define mlx4_info(mdev, format, arg...) \
 216         dev_info(&mdev->pdev->dev, format, ##arg)
 217 #define mlx4_warn(mdev, format, arg...) \
 218         dev_warn(&mdev->pdev->dev, format, ##arg)
 219
 220 extern int mlx4_log_num_mgm_entry_size;
 221 extern int log_mtts_per_seg;
 222
 223 #define MLX4_MAX_NUM_SLAVES     (MLX4_MAX_NUM_PF + MLX4_MAX_NUM_VF)
 224 #define ALL_SLAVES 0xff
 225
 226 struct mlx4_bitmap {
 227         u32                     last;
 228         u32                     top;
 229         u32                     max;
 230         u32                     reserved_top;
 231         u32                     mask;
 232         u32                     avail;
 233         spinlock_t              lock;
 234         unsigned long          *table;
 235 };
 236
 237 struct mlx4_buddy {
 238         unsigned long         **bits;
 239         unsigned int           *num_free;
 240         int                     max_order;
 241         spinlock_t              lock;
 242 };
 243
 244 struct mlx4_icm;
 245
 246 struct mlx4_icm_table {
 247         u64                     virt;
 248         int                     num_icm;
 249         int                     num_obj;
 250         int                     obj_size;
 251         int                     lowmem;
 252         int                     coherent;
 253         struct mutex            mutex;
 254         struct mlx4_icm       **icm;
 255 };
 256
 257 /*
 258  * Must be packed because mtt_seg is 64 bits but only aligned to 32 bits.
 259  */
 260 struct mlx4_mpt_entry {
 261         __be32 flags;
 262         __be32 qpn;
 263         __be32 key;
 264         __be32 pd_flags;
 265         __be64 start;
 266         __be64 length;
 267         __be32 lkey;
 268         __be32 win_cnt;
 269         u8      reserved1[3];
 270         u8      mtt_rep;
 271         __be64 mtt_addr;
 272         __be32 mtt_sz;
 273         __be32 entity_size;
 274         __be32 first_byte_offset;
 275 } __packed;
 276
 277 /*
 278  * Must be packed because start is 64 bits but only aligned to 32 bits.
 279  */
 280 struct mlx4_eq_context {
 281         __be32                  flags;
 282         u16                     reserved1[3];
 283         __be16                  page_offset;
 284         u8                      log_eq_size;
 285         u8                      reserved2[4];
 286         u8                      eq_period;
 287         u8                      reserved3;
 288         u8                      eq_max_count;
 289         u8                      reserved4[3];
 290         u8                      intr;
 291         u8                      log_page_size;
 292         u8                      reserved5[2];
 293         u8                      mtt_base_addr_h;
 294         __be32                  mtt_base_addr_l;
 295         u32                     reserved6[2];
 296         __be32                  consumer_index;
 297         __be32                  producer_index;
 298         u32                     reserved7[4];
 299 };
 300
 301 struct mlx4_cq_context {
 302         __be32                  flags;
 303         u16                     reserved1[3];
 304         __be16                  page_offset;
 305         __be32                  logsize_usrpage;
 306         __be16                  cq_period;
 307         __be16                  cq_max_count;
 308         u8                      reserved2[3];
 309         u8                      comp_eqn;
 310         u8                      log_page_size;
 311         u8                      reserved3[2];
 312         u8                      mtt_base_addr_h;
 313         __be32                  mtt_base_addr_l;
 314         __be32                  last_notified_index;
 315         __be32                  solicit_producer_index;
 316         __be32                  consumer_index;
 317         __be32                  producer_index;
 318         u32                     reserved4[2];
 319         __be64                  db_rec_addr;
 320 };
 321
 322 struct mlx4_srq_context {
 323         __be32                  state_logsize_srqn;
 324         u8                      logstride;
 325         u8                      reserved1;
 326         __be16                  xrcd;
 327         __be32                  pg_offset_cqn;
 328         u32                     reserved2;
 329         u8                      log_page_size;
 330         u8                      reserved3[2];
 331         u8                      mtt_base_addr_h;
 332         __be32                  mtt_base_addr_l;
 333         __be32                  pd;
 334         __be16                  limit_watermark;
 335         __be16                  wqe_cnt;
 336         u16                     reserved4;
 337         __be16                  wqe_counter;
 338         u32                     reserved5;
 339         __be64                  db_rec_addr;
 340 };
 341
 342 struct mlx4_eqe {
 343         u8                      reserved1;
 344         u8                      type;
 345         u8                      reserved2;
 346         u8                      subtype;
 347         union {
 348                 u32             raw[6];
 349                 struct {
 350                         __be32  cqn;
 351                 } __packed comp;
 352                 struct {
 353                         u16     reserved1;
 354                         __be16  token;
 355                         u32     reserved2;
 356                         u8      reserved3[3];
 357                         u8      status;
 358                         __be64  out_param;
 359                 } __packed cmd;
 360                 struct {
 361                         __be32  qpn;
 362                 } __packed qp;
 363                 struct {
 364                         __be32  srqn;
 365                 } __packed srq;
 366                 struct {
 367                         __be32  cqn;
 368                         u32     reserved1;
 369                         u8      reserved2[3];
 370                         u8      syndrome;
 371                 } __packed cq_err;
 372                 struct {
 373                         u32     reserved1[2];
 374                         __be32  port;
 375                 } __packed port_change;
 376                 struct {
 377                         #define COMM_CHANNEL_BIT_ARRAY_SIZE     4
 378                         u32 reserved;
 379                         u32 bit_vec[COMM_CHANNEL_BIT_ARRAY_SIZE];
 380                 } __packed comm_channel_arm;
 381                 struct {
 382                         u8      port;
 383                         u8      reserved[3];
 384                         __be64  mac;
 385                 } __packed mac_update;
 386                 struct {
 387                         u8      port;
 388                 } __packed sw_event;
 389                 struct {
 390                         __be32  slave_id;
 391                 } __packed flr_event;
 392                 struct {
 393                         __be16  current_temperature;
 394                         __be16  warning_threshold;
 395                 } __packed warming;
 396         }                       event;
 397         u8                      slave_id;
 398         u8                      reserved3[2];
 399         u8                      owner;
 400 } __packed;
 401
 402 struct mlx4_eq {
 403         struct mlx4_dev        *dev;
 404         void __iomem           *doorbell;
 405         int                     eqn;
 406         u32                     cons_index;
 407         u16                     irq;
 408         u16                     have_irq;
 409         int                     nent;
 410         struct mlx4_buf_list   *page_list;
 411         struct mlx4_mtt         mtt;
 412 };
 413
 414 struct mlx4_slave_eqe {
 415         u8 type;
 416         u8 port;
 417         u32 param;
 418 };
 419
 420 struct mlx4_slave_event_eq_info {
 421         int eqn;
 422         u16 token;
 423 };
 424
 425 struct mlx4_profile {
 426         int                     num_qp;
 427         int                     rdmarc_per_qp;
 428         int                     num_srq;
 429         int                     num_cq;
 430         int                     num_mcg;
 431         int                     num_mpt;
 432         unsigned                num_mtt;
 433 };
 434
 435 struct mlx4_fw {
 436         u64                     clr_int_base;
 437         u64                     catas_offset;
 438         u64                     comm_base;
 439         struct mlx4_icm        *fw_icm;
 440         struct mlx4_icm        *aux_icm;
 441         u32                     catas_size;
 442         u16                     fw_pages;
 443         u8                      clr_int_bar;
 444         u8                      catas_bar;
 445         u8                      comm_bar;
 446 };
 447
 448 struct mlx4_comm {
 449         u32                     slave_write;
 450         u32                     slave_read;
 451 };
 452
 453 enum {
 454         MLX4_MCAST_CONFIG       = 0,
 455         MLX4_MCAST_DISABLE      = 1,
 456         MLX4_MCAST_ENABLE       = 2,
 457 };
 458
 459 #define VLAN_FLTR_SIZE  128
 460
 461 struct mlx4_vlan_fltr {
 462         __be32 entry[VLAN_FLTR_SIZE];
 463 };
 464
 465 struct mlx4_mcast_entry {
 466         struct list_head list;
 467         u64 addr;
 468 };
 469
 470 struct mlx4_promisc_qp {
 471         struct list_head list;
 472         u32 qpn;
 473 };
 474
 475 struct mlx4_steer_index {
 476         struct list_head list;
 477         unsigned int index;
 478         struct list_head duplicates;
 479 };
 480
 481 #define MLX4_EVENT_TYPES_NUM 64
 482
 483 struct mlx4_slave_state {
 484         u8 comm_toggle;
 485         u8 last_cmd;
 486         u8 init_port_mask;
 487         bool active;
 488         u8 function;
 489         dma_addr_t vhcr_dma;
 490         u16 mtu[MLX4_MAX_PORTS + 1];
 491         __be32 ib_cap_mask[MLX4_MAX_PORTS + 1];
 492         struct mlx4_slave_eqe eq[MLX4_MFUNC_MAX_EQES];
 493         struct list_head mcast_filters[MLX4_MAX_PORTS + 1];
 494         struct mlx4_vlan_fltr *vlan_filter[MLX4_MAX_PORTS + 1];
 495         /* event type to eq number lookup */
 496         struct mlx4_slave_event_eq_info event_eq[MLX4_EVENT_TYPES_NUM];
 497         u16 eq_pi;
 498         u16 eq_ci;
 499         spinlock_t lock;
 500         /*initialized via the kzalloc*/
 501         u8 is_slave_going_down;
 502         u32 cookie;
 503 };
 504
 505 struct slave_list {
 506         struct mutex mutex;
 507         struct list_head res_list[MLX4_NUM_OF_RESOURCE_TYPE];
 508 };
 509
 510 struct mlx4_resource_tracker {
 511         spinlock_t lock;
 512         /* tree for each resources */
 513         struct rb_root res_tree[MLX4_NUM_OF_RESOURCE_TYPE];
 514         /* num_of_slave's lists, one per slave */
 515         struct slave_list *slave_list;
 516 };
 517
 518 #define SLAVE_EVENT_EQ_SIZE     128
 519 struct mlx4_slave_event_eq {
 520         u32 eqn;
 521         u32 cons;
 522         u32 prod;
 523         struct mlx4_eqe event_eqe[SLAVE_EVENT_EQ_SIZE];
 524 };
 525
 526 struct mlx4_master_qp0_state {
 527         int proxy_qp0_active;
 528         int qp0_active;
 529         int port_active;
 530 };
 531
 532 struct mlx4_mfunc_master_ctx {
 533         struct mlx4_slave_state *slave_state;
 534         struct mlx4_master_qp0_state qp0_state[MLX4_MAX_PORTS + 1];
 535         int                     init_port_ref[MLX4_MAX_PORTS + 1];
 536         u16                     max_mtu[MLX4_MAX_PORTS + 1];
 537         int                     disable_mcast_ref[MLX4_MAX_PORTS + 1];
 538         struct mlx4_resource_tracker res_tracker;
 539         struct workqueue_struct *comm_wq;
 540         struct work_struct      comm_work;
 541         struct work_struct      slave_event_work;
 542         struct work_struct      slave_flr_event_work;
 543         spinlock_t              slave_state_lock;
 544         __be32                  comm_arm_bit_vector[4];
 545         struct mlx4_eqe         cmd_eqe;
 546         struct mlx4_slave_event_eq slave_eq;
 547         struct mutex            gen_eqe_mutex[MLX4_MFUNC_MAX];
 548 };
 549
 550 struct mlx4_mfunc {
 551         struct mlx4_comm __iomem       *comm;
 552         struct mlx4_vhcr_cmd           *vhcr;
 553         dma_addr_t                      vhcr_dma;
 554
 555         struct mlx4_mfunc_master_ctx    master;
 556 };
 557
 558 struct mlx4_cmd {
 559         struct pci_pool        *pool;
 560         void __iomem           *hcr;
 561         struct mutex            hcr_mutex;
 562         struct semaphore        poll_sem;
 563         struct semaphore        event_sem;
 564         struct semaphore        slave_sem;
 565         int                     max_cmds;
 566         spinlock_t              context_lock;
 567         int                     free_head;
 568         struct mlx4_cmd_context *context;
 569         u16                     token_mask;
 570         u8                      use_events;
 571         u8                      toggle;
 572         u8                      comm_toggle;
 573 };
 574
 575 struct mlx4_uar_table {
 576         struct mlx4_bitmap      bitmap;
 577 };
 578
 579 struct mlx4_mr_table {
 580         struct mlx4_bitmap      mpt_bitmap;
 581         struct mlx4_buddy       mtt_buddy;
 582         u64                     mtt_base;
 583         u64                     mpt_base;
 584         struct mlx4_icm_table   mtt_table;
 585         struct mlx4_icm_table   dmpt_table;
 586 };
 587
 588 struct mlx4_cq_table {
 589         struct mlx4_bitmap      bitmap;
 590         spinlock_t              lock;
 591         struct radix_tree_root  tree;
 592         struct mlx4_icm_table   table;
 593         struct mlx4_icm_table   cmpt_table;
 594 };
 595
 596 struct mlx4_eq_table {
 597         struct mlx4_bitmap      bitmap;
 598         char                   *irq_names;
 599         void __iomem           *clr_int;
 600         void __iomem          **uar_map;
 601         u32                     clr_mask;
 602         struct mlx4_eq         *eq;
 603         struct mlx4_icm_table   table;
 604         struct mlx4_icm_table   cmpt_table;
 605         int                     have_irq;
 606         u8                      inta_pin;
 607 };
 608
 609 struct mlx4_srq_table {
 610         struct mlx4_bitmap      bitmap;
 611         spinlock_t              lock;
 612         struct radix_tree_root  tree;
 613         struct mlx4_icm_table   table;
 614         struct mlx4_icm_table   cmpt_table;
 615 };
 616
 617 struct mlx4_qp_table {
 618         struct mlx4_bitmap      bitmap;
 619         u32                     rdmarc_base;
 620         int                     rdmarc_shift;
 621         spinlock_t              lock;
 622         struct mlx4_icm_table   qp_table;
 623         struct mlx4_icm_table   auxc_table;
 624         struct mlx4_icm_table   altc_table;
 625         struct mlx4_icm_table   rdmarc_table;
 626         struct mlx4_icm_table   cmpt_table;
 627 };
 628
 629 struct mlx4_mcg_table {
 630         struct mutex            mutex;
 631         struct mlx4_bitmap      bitmap;
 632         struct mlx4_icm_table   table;
 633 };
 634
 635 struct mlx4_catas_err {
 636         u32 __iomem            *map;
 637         struct timer_list       timer;
 638         struct list_head        list;
 639 };
 640
 641 #define MLX4_MAX_MAC_NUM        128
 642 #define MLX4_MAC_TABLE_SIZE     (MLX4_MAX_MAC_NUM << 3)
 643
 644 struct mlx4_mac_table {
 645         __be64                  entries[MLX4_MAX_MAC_NUM];
 646         int                     refs[MLX4_MAX_MAC_NUM];
 647         struct mutex            mutex;
 648         int                     total;
 649         int                     max;
 650 };
 651
 652 #define MLX4_MAX_VLAN_NUM       128
 653 #define MLX4_VLAN_TABLE_SIZE    (MLX4_MAX_VLAN_NUM << 2)
 654
 655 struct mlx4_vlan_table {
 656         __be32                  entries[MLX4_MAX_VLAN_NUM];
 657         int                     refs[MLX4_MAX_VLAN_NUM];
 658         struct mutex            mutex;
 659         int                     total;
 660         int                     max;
 661 };
 662
 663 #define SET_PORT_GEN_ALL_VALID          0x7
 664 #define SET_PORT_PROMISC_SHIFT          31
 665 #define SET_PORT_MC_PROMISC_SHIFT       30
 666
 667 enum {
 668         MCAST_DIRECT_ONLY       = 0,
 669         MCAST_DIRECT            = 1,
 670         MCAST_DEFAULT           = 2
 671 };
 672
 673
 674 struct mlx4_set_port_general_context {
 675         u8 reserved[3];
 676         u8 flags;
 677         u16 reserved2;
 678         __be16 mtu;
 679         u8 pptx;
 680         u8 pfctx;
 681         u16 reserved3;
 682         u8 pprx;
 683         u8 pfcrx;
 684         u16 reserved4;
 685 };
 686
 687 struct mlx4_set_port_rqp_calc_context {
 688         __be32 base_qpn;
 689         u8 rererved;
 690         u8 n_mac;
 691         u8 n_vlan;
 692         u8 n_prio;
 693         u8 reserved2[3];
 694         u8 mac_miss;
 695         u8 intra_no_vlan;
 696         u8 no_vlan;
 697         u8 intra_vlan_miss;
 698         u8 vlan_miss;
 699         u8 reserved3[3];
 700         u8 no_vlan_prio;
 701         __be32 promisc;
 702         __be32 mcast;
 703 };
 704
 705 struct mlx4_mac_entry {
 706         u64 mac;
 707 };
 708
 709 struct mlx4_port_info {
 710         struct mlx4_dev        *dev;
 711         int                     port;
 712         char                    dev_name[16];
 713         struct device_attribute port_attr;
 714         enum mlx4_port_type     tmp_type;
 715         char                    dev_mtu_name[16];
 716         struct device_attribute port_mtu_attr;
 717         struct mlx4_mac_table   mac_table;
 718         struct radix_tree_root  mac_tree;
 719         struct mlx4_vlan_table  vlan_table;
 720         int                     base_qpn;
 721 };
 722
 723 struct mlx4_sense {
 724         struct mlx4_dev         *dev;
 725         u8                      do_sense_port[MLX4_MAX_PORTS + 1];
 726         u8                      sense_allowed[MLX4_MAX_PORTS + 1];
 727         struct delayed_work     sense_poll;
 728 };
 729
 730 struct mlx4_msix_ctl {
 731         u64             pool_bm;
 732         struct mutex    pool_lock;
 733 };
 734
 735 struct mlx4_steer {
 736         struct list_head promisc_qps[MLX4_NUM_STEERS];
 737         struct list_head steer_entries[MLX4_NUM_STEERS];
 738 };
 739
 740 struct mlx4_priv {
 741         struct mlx4_dev         dev;
 742
 743         struct list_head        dev_list;
 744         struct list_head        ctx_list;
 745         spinlock_t              ctx_lock;
 746
 747         struct list_head        pgdir_list;
 748         struct mutex            pgdir_mutex;
 749
 750         struct mlx4_fw          fw;
 751         struct mlx4_cmd         cmd;
 752         struct mlx4_mfunc       mfunc;
 753
 754         struct mlx4_bitmap      pd_bitmap;
 755         struct mlx4_bitmap      xrcd_bitmap;
 756         struct mlx4_uar_table   uar_table;
 757         struct mlx4_mr_table    mr_table;
 758         struct mlx4_cq_table    cq_table;
 759         struct mlx4_eq_table    eq_table;
 760         struct mlx4_srq_table   srq_table;
 761         struct mlx4_qp_table    qp_table;
 762         struct mlx4_mcg_table   mcg_table;
 763         struct mlx4_bitmap      counters_bitmap;
 764
 765         struct mlx4_catas_err   catas_err;
 766
 767         void __iomem           *clr_base;
 768
 769         struct mlx4_uar         driver_uar;
 770         void __iomem           *kar;
 771         struct mlx4_port_info   port[MLX4_MAX_PORTS + 1];
 772         struct mlx4_sense       sense;
 773         struct mutex            port_mutex;
 774         struct mlx4_msix_ctl    msix_ctl;
 775         struct mlx4_steer       *steer;
 776         struct list_head        bf_list;
 777         struct mutex            bf_mutex;
 778         struct io_mapping       *bf_mapping;
 779         int                     reserved_mtts;
 780 };
 781
 782 static inline struct mlx4_priv *mlx4_priv(struct mlx4_dev *dev)
 783 {
 784         return container_of(dev, struct mlx4_priv, dev);
 785 }
 786
 787 #define MLX4_SENSE_RANGE        (HZ * 3)
 788
 789 extern struct workqueue_struct *mlx4_wq;
 790
 791 u32 mlx4_bitmap_alloc(struct mlx4_bitmap *bitmap);
 792 void mlx4_bitmap_free(struct mlx4_bitmap *bitmap, u32 obj);
 793 u32 mlx4_bitmap_alloc_range(struct mlx4_bitmap *bitmap, int cnt, int align);
 794 void mlx4_bitmap_free_range(struct mlx4_bitmap *bitmap, u32 obj, int cnt);
 795 u32 mlx4_bitmap_avail(struct mlx4_bitmap *bitmap);
 796 int mlx4_bitmap_init(struct mlx4_bitmap *bitmap, u32 num, u32 mask,
 797                      u32 reserved_bot, u32 resetrved_top);
 798 void mlx4_bitmap_cleanup(struct mlx4_bitmap *bitmap);
 799
 800 int mlx4_reset(struct mlx4_dev *dev);
 801
 802 int mlx4_alloc_eq_table(struct mlx4_dev *dev);
 803 void mlx4_free_eq_table(struct mlx4_dev *dev);
 804
 805 int mlx4_init_pd_table(struct mlx4_dev *dev);
 806 int mlx4_init_xrcd_table(struct mlx4_dev *dev);
 807 int mlx4_init_uar_table(struct mlx4_dev *dev);
 808 int mlx4_init_mr_table(struct mlx4_dev *dev);
 809 int mlx4_init_eq_table(struct mlx4_dev *dev);
 810 int mlx4_init_cq_table(struct mlx4_dev *dev);
 811 int mlx4_init_qp_table(struct mlx4_dev *dev);
 812 int mlx4_init_srq_table(struct mlx4_dev *dev);
 813 int mlx4_init_mcg_table(struct mlx4_dev *dev);
 814
 815 void mlx4_cleanup_pd_table(struct mlx4_dev *dev);
 816 void mlx4_cleanup_xrcd_table(struct mlx4_dev *dev);
 817 void mlx4_cleanup_uar_table(struct mlx4_dev *dev);
 818 void mlx4_cleanup_mr_table(struct mlx4_dev *dev);
 819 void mlx4_cleanup_eq_table(struct mlx4_dev *dev);
 820 void mlx4_cleanup_cq_table(struct mlx4_dev *dev);
 821 void mlx4_cleanup_qp_table(struct mlx4_dev *dev);
 822 void mlx4_cleanup_srq_table(struct mlx4_dev *dev);
 823 void mlx4_cleanup_mcg_table(struct mlx4_dev *dev);
 824 int __mlx4_qp_alloc_icm(struct mlx4_dev *dev, int qpn);
 825 void __mlx4_qp_free_icm(struct mlx4_dev *dev, int qpn);
 826 int __mlx4_cq_alloc_icm(struct mlx4_dev *dev, int *cqn);
 827 void __mlx4_cq_free_icm(struct mlx4_dev *dev, int cqn);
 828 int __mlx4_srq_alloc_icm(struct mlx4_dev *dev, int *srqn);
 829 void __mlx4_srq_free_icm(struct mlx4_dev *dev, int srqn);
 830 int __mlx4_mr_reserve(struct mlx4_dev *dev);
 831 void __mlx4_mr_release(struct mlx4_dev *dev, u32 index);
 832 int __mlx4_mr_alloc_icm(struct mlx4_dev *dev, u32 index);
 833 void __mlx4_mr_free_icm(struct mlx4_dev *dev, u32 index);
 834 u32 __mlx4_alloc_mtt_range(struct mlx4_dev *dev, int order);
 835 void __mlx4_free_mtt_range(struct mlx4_dev *dev, u32 first_seg, int order);
 836
 837 int mlx4_WRITE_MTT_wrapper(struct mlx4_dev *dev, int slave,
 838                            struct mlx4_vhcr *vhcr,
 839                            struct mlx4_cmd_mailbox *inbox,
 840                            struct mlx4_cmd_mailbox *outbox,
 841                            struct mlx4_cmd_info *cmd);
 842 int mlx4_SYNC_TPT_wrapper(struct mlx4_dev *dev, int slave,
 843                            struct mlx4_vhcr *vhcr,
 844                            struct mlx4_cmd_mailbox *inbox,
 845                            struct mlx4_cmd_mailbox *outbox,
 846                            struct mlx4_cmd_info *cmd);
 847 int mlx4_SW2HW_MPT_wrapper(struct mlx4_dev *dev, int slave,
 848                            struct mlx4_vhcr *vhcr,
 849                            struct mlx4_cmd_mailbox *inbox,
 850                            struct mlx4_cmd_mailbox *outbox,
 851                            struct mlx4_cmd_info *cmd);
 852 int mlx4_HW2SW_MPT_wrapper(struct mlx4_dev *dev, int slave,
 853                            struct mlx4_vhcr *vhcr,
 854                            struct mlx4_cmd_mailbox *inbox,
 855                            struct mlx4_cmd_mailbox *outbox,
 856                            struct mlx4_cmd_info *cmd);
 857 int mlx4_QUERY_MPT_wrapper(struct mlx4_dev *dev, int slave,
 858                            struct mlx4_vhcr *vhcr,
 859                            struct mlx4_cmd_mailbox *inbox,
 860                            struct mlx4_cmd_mailbox *outbox,
 861                            struct mlx4_cmd_info *cmd);
 862 int mlx4_SW2HW_EQ_wrapper(struct mlx4_dev *dev, int slave,
 863                           struct mlx4_vhcr *vhcr,
 864                           struct mlx4_cmd_mailbox *inbox,
 865                           struct mlx4_cmd_mailbox *outbox,
 866                           struct mlx4_cmd_info *cmd);
 867 int mlx4_DMA_wrapper(struct mlx4_dev *dev, int slave,
 868                      struct mlx4_vhcr *vhcr,
 869                      struct mlx4_cmd_mailbox *inbox,
 870                      struct mlx4_cmd_mailbox *outbox,
 871                      struct mlx4_cmd_info *cmd);
 872 int __mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align,
 873                             int *base);
 874 void __mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt);
 875 int __mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac);
 876 void __mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac);
 877 int __mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac);
 878 int __mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
 879                      int start_index, int npages, u64 *page_list);
 880 int __mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx);
 881 void __mlx4_counter_free(struct mlx4_dev *dev, u32 idx);
 882 int __mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn);
 883 void __mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn);
 884
 885 void mlx4_start_catas_poll(struct mlx4_dev *dev);
 886 void mlx4_stop_catas_poll(struct mlx4_dev *dev);
 887 void mlx4_catas_init(void);
 888 int mlx4_restart_one(struct pci_dev *pdev);
 889 int mlx4_register_device(struct mlx4_dev *dev);
 890 void mlx4_unregister_device(struct mlx4_dev *dev);
 891 void mlx4_dispatch_event(struct mlx4_dev *dev, enum mlx4_dev_event type, int port);
 892
 893 struct mlx4_dev_cap;
 894 struct mlx4_init_hca_param;
 895
 896 u64 mlx4_make_profile(struct mlx4_dev *dev,
 897                       struct mlx4_profile *request,
 898                       struct mlx4_dev_cap *dev_cap,
 899                       struct mlx4_init_hca_param *init_hca);
 900 void mlx4_master_comm_channel(struct work_struct *work);
 901 void mlx4_gen_slave_eqe(struct work_struct *work);
 902 void mlx4_master_handle_slave_flr(struct work_struct *work);
 903
 904 int mlx4_ALLOC_RES_wrapper(struct mlx4_dev *dev, int slave,
 905                            struct mlx4_vhcr *vhcr,
 906                            struct mlx4_cmd_mailbox *inbox,
 907                            struct mlx4_cmd_mailbox *outbox,
 908                            struct mlx4_cmd_info *cmd);
 909 int mlx4_FREE_RES_wrapper(struct mlx4_dev *dev, int slave,
 910                           struct mlx4_vhcr *vhcr,
 911                           struct mlx4_cmd_mailbox *inbox,
 912                           struct mlx4_cmd_mailbox *outbox,
 913                           struct mlx4_cmd_info *cmd);
 914 int mlx4_MAP_EQ_wrapper(struct mlx4_dev *dev, int slave,
 915                         struct mlx4_vhcr *vhcr, struct mlx4_cmd_mailbox *inbox,
 916                         struct mlx4_cmd_mailbox *outbox,
 917                         struct mlx4_cmd_info *cmd);
 918 int mlx4_COMM_INT_wrapper(struct mlx4_dev *dev, int slave,
 919                           struct mlx4_vhcr *vhcr,
 920                           struct mlx4_cmd_mailbox *inbox,
 921                           struct mlx4_cmd_mailbox *outbox,
 922                           struct mlx4_cmd_info *cmd);
 923 int mlx4_HW2SW_EQ_wrapper(struct mlx4_dev *dev, int slave,
 924                             struct mlx4_vhcr *vhcr,
 925                             struct mlx4_cmd_mailbox *inbox,
 926                             struct mlx4_cmd_mailbox *outbox,
 927                           struct mlx4_cmd_info *cmd);
 928 int mlx4_QUERY_EQ_wrapper(struct mlx4_dev *dev, int slave,
 929                           struct mlx4_vhcr *vhcr,
 930                           struct mlx4_cmd_mailbox *inbox,
 931                           struct mlx4_cmd_mailbox *outbox,
 932                           struct mlx4_cmd_info *cmd);
 933 int mlx4_SW2HW_CQ_wrapper(struct mlx4_dev *dev, int slave,
 934                           struct mlx4_vhcr *vhcr,
 935                           struct mlx4_cmd_mailbox *inbox,
 936                           struct mlx4_cmd_mailbox *outbox,
 937                           struct mlx4_cmd_info *cmd);
 938 int mlx4_HW2SW_CQ_wrapper(struct mlx4_dev *dev, int slave,
 939                           struct mlx4_vhcr *vhcr,
 940                           struct mlx4_cmd_mailbox *inbox,
 941                           struct mlx4_cmd_mailbox *outbox,
 942                           struct mlx4_cmd_info *cmd);
 943 int mlx4_QUERY_CQ_wrapper(struct mlx4_dev *dev, int slave,
 944                           struct mlx4_vhcr *vhcr,
 945                           struct mlx4_cmd_mailbox *inbox,
 946                           struct mlx4_cmd_mailbox *outbox,
 947                           struct mlx4_cmd_info *cmd);
 948 int mlx4_MODIFY_CQ_wrapper(struct mlx4_dev *dev, int slave,
 949                           struct mlx4_vhcr *vhcr,
 950                           struct mlx4_cmd_mailbox *inbox,
 951                           struct mlx4_cmd_mailbox *outbox,
 952                            struct mlx4_cmd_info *cmd);
 953 int mlx4_SW2HW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
 954                            struct mlx4_vhcr *vhcr,
 955                            struct mlx4_cmd_mailbox *inbox,
 956                            struct mlx4_cmd_mailbox *outbox,
 957                            struct mlx4_cmd_info *cmd);
 958 int mlx4_HW2SW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
 959                            struct mlx4_vhcr *vhcr,
 960                            struct mlx4_cmd_mailbox *inbox,
 961                            struct mlx4_cmd_mailbox *outbox,
 962                            struct mlx4_cmd_info *cmd);
 963 int mlx4_QUERY_SRQ_wrapper(struct mlx4_dev *dev, int slave,
 964                            struct mlx4_vhcr *vhcr,
 965                            struct mlx4_cmd_mailbox *inbox,
 966                            struct mlx4_cmd_mailbox *outbox,
 967                            struct mlx4_cmd_info *cmd);
 968 int mlx4_ARM_SRQ_wrapper(struct mlx4_dev *dev, int slave,
 969                          struct mlx4_vhcr *vhcr,
 970                          struct mlx4_cmd_mailbox *inbox,
 971                          struct mlx4_cmd_mailbox *outbox,
 972                          struct mlx4_cmd_info *cmd);
 973 int mlx4_GEN_QP_wrapper(struct mlx4_dev *dev, int slave,
 974                         struct mlx4_vhcr *vhcr,
 975                         struct mlx4_cmd_mailbox *inbox,
 976                         struct mlx4_cmd_mailbox *outbox,
 977                         struct mlx4_cmd_info *cmd);
 978 int mlx4_RST2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
 979                              struct mlx4_vhcr *vhcr,
 980                              struct mlx4_cmd_mailbox *inbox,
 981                              struct mlx4_cmd_mailbox *outbox,
 982                              struct mlx4_cmd_info *cmd);
 983 int mlx4_INIT2RTR_QP_wrapper(struct mlx4_dev *dev, int slave,
 984                              struct mlx4_vhcr *vhcr,
 985                              struct mlx4_cmd_mailbox *inbox,
 986                              struct mlx4_cmd_mailbox *outbox,
 987                              struct mlx4_cmd_info *cmd);
 988 int mlx4_2RST_QP_wrapper(struct mlx4_dev *dev, int slave,
 989                          struct mlx4_vhcr *vhcr,
 990                          struct mlx4_cmd_mailbox *inbox,
 991                          struct mlx4_cmd_mailbox *outbox,
 992                          struct mlx4_cmd_info *cmd);
 993
 994 int mlx4_GEN_EQE(struct mlx4_dev *dev, int slave, struct mlx4_eqe *eqe);
 995
 996 int mlx4_cmd_init(struct mlx4_dev *dev);
 997 void mlx4_cmd_cleanup(struct mlx4_dev *dev);
 998 int mlx4_multi_func_init(struct mlx4_dev *dev);
 999 void mlx4_multi_func_cleanup(struct mlx4_dev *dev);
1000 void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param);
1001 int mlx4_cmd_use_events(struct mlx4_dev *dev);
1002 void mlx4_cmd_use_polling(struct mlx4_dev *dev);
1003
1004 int mlx4_comm_cmd(struct mlx4_dev *dev, u8 cmd, u16 param,
1005                   unsigned long timeout);
1006
1007 void mlx4_cq_completion(struct mlx4_dev *dev, u32 cqn);
1008 void mlx4_cq_event(struct mlx4_dev *dev, u32 cqn, int event_type);
1009
1010 void mlx4_qp_event(struct mlx4_dev *dev, u32 qpn, int event_type);
1011
1012 void mlx4_srq_event(struct mlx4_dev *dev, u32 srqn, int event_type);
1013
1014 void mlx4_handle_catas_err(struct mlx4_dev *dev);
1015
1016 int mlx4_SENSE_PORT(struct mlx4_dev *dev, int port,
1017                     enum mlx4_port_type *type);
1018 void mlx4_do_sense_ports(struct mlx4_dev *dev,
1019                          enum mlx4_port_type *stype,
1020                          enum mlx4_port_type *defaults);
1021 void mlx4_start_sense(struct mlx4_dev *dev);
1022 void mlx4_stop_sense(struct mlx4_dev *dev);
1023 void mlx4_sense_init(struct mlx4_dev *dev);
1024 int mlx4_check_port_params(struct mlx4_dev *dev,
1025                            enum mlx4_port_type *port_type);
1026 int mlx4_change_port_types(struct mlx4_dev *dev,
1027                            enum mlx4_port_type *port_types);
1028
1029 void mlx4_init_mac_table(struct mlx4_dev *dev, struct mlx4_mac_table *table);
1030 void mlx4_init_vlan_table(struct mlx4_dev *dev, struct mlx4_vlan_table *table);
1031
1032 int mlx4_SET_PORT(struct mlx4_dev *dev, u8 port);
1033 /* resource tracker functions*/
1034 int mlx4_get_slave_from_resource_id(struct mlx4_dev *dev,
1035                                     enum mlx4_resource resource_type,
1036                                     int resource_id, int *slave);
1037 void mlx4_delete_all_resources_for_slave(struct mlx4_dev *dev, int slave_id);
1038 int mlx4_init_resource_tracker(struct mlx4_dev *dev);
1039
1040 void mlx4_free_resource_tracker(struct mlx4_dev *dev,
1041                                 enum mlx4_res_tracker_free_type type);
1042
1043 int mlx4_QUERY_FW_wrapper(struct mlx4_dev *dev, int slave,
1044                           struct mlx4_vhcr *vhcr,
1045                           struct mlx4_cmd_mailbox *inbox,
1046                           struct mlx4_cmd_mailbox *outbox,
1047                           struct mlx4_cmd_info *cmd);
1048 int mlx4_SET_PORT_wrapper(struct mlx4_dev *dev, int slave,
1049                           struct mlx4_vhcr *vhcr,
1050                           struct mlx4_cmd_mailbox *inbox,
1051                           struct mlx4_cmd_mailbox *outbox,
1052                           struct mlx4_cmd_info *cmd);
1053 int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave,
1054                            struct mlx4_vhcr *vhcr,
1055                            struct mlx4_cmd_mailbox *inbox,
1056                            struct mlx4_cmd_mailbox *outbox,
1057                            struct mlx4_cmd_info *cmd);
1058 int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave,
1059                             struct mlx4_vhcr *vhcr,
1060                             struct mlx4_cmd_mailbox *inbox,
1061                             struct mlx4_cmd_mailbox *outbox,
1062                             struct mlx4_cmd_info *cmd);
1063 int mlx4_QUERY_DEV_CAP_wrapper(struct mlx4_dev *dev, int slave,
1064                                struct mlx4_vhcr *vhcr,
1065                                struct mlx4_cmd_mailbox *inbox,
1066                                struct mlx4_cmd_mailbox *outbox,
1067                                struct mlx4_cmd_info *cmd);
1068 int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave,
1069                             struct mlx4_vhcr *vhcr,
1070                             struct mlx4_cmd_mailbox *inbox,
1071                             struct mlx4_cmd_mailbox *outbox,
1072                             struct mlx4_cmd_info *cmd);
1073 int mlx4_get_port_ib_caps(struct mlx4_dev *dev, u8 port, __be32 *caps);
1074
1075
1076 int mlx4_QP_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
1077                            struct mlx4_vhcr *vhcr,
1078                            struct mlx4_cmd_mailbox *inbox,
1079                            struct mlx4_cmd_mailbox *outbox,
1080                            struct mlx4_cmd_info *cmd);
1081
1082 int mlx4_PROMISC_wrapper(struct mlx4_dev *dev, int slave,
1083                          struct mlx4_vhcr *vhcr,
1084                          struct mlx4_cmd_mailbox *inbox,
1085                          struct mlx4_cmd_mailbox *outbox,
1086                          struct mlx4_cmd_info *cmd);
1087 int mlx4_qp_detach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1088                           enum mlx4_protocol prot, enum mlx4_steer_type steer);
1089 int mlx4_qp_attach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1090                           int block_mcast_loopback, enum mlx4_protocol prot,
1091                           enum mlx4_steer_type steer);
1092 int mlx4_SET_MCAST_FLTR_wrapper(struct mlx4_dev *dev, int slave,
1093                                 struct mlx4_vhcr *vhcr,
1094                                 struct mlx4_cmd_mailbox *inbox,
1095                                 struct mlx4_cmd_mailbox *outbox,
1096                                 struct mlx4_cmd_info *cmd);
1097 int mlx4_SET_VLAN_FLTR_wrapper(struct mlx4_dev *dev, int slave,
1098                                struct mlx4_vhcr *vhcr,
1099                                struct mlx4_cmd_mailbox *inbox,
1100                                struct mlx4_cmd_mailbox *outbox,
1101                                struct mlx4_cmd_info *cmd);
1102 int mlx4_common_set_vlan_fltr(struct mlx4_dev *dev, int function,
1103                                      int port, void *buf);
1104 int mlx4_common_dump_eth_stats(struct mlx4_dev *dev, int slave, u32 in_mod,
1105                                 struct mlx4_cmd_mailbox *outbox);
1106 int mlx4_DUMP_ETH_STATS_wrapper(struct mlx4_dev *dev, int slave,
1107                                    struct mlx4_vhcr *vhcr,
1108                                    struct mlx4_cmd_mailbox *inbox,
1109                                    struct mlx4_cmd_mailbox *outbox,
1110                                 struct mlx4_cmd_info *cmd);
1111 int mlx4_PKEY_TABLE_wrapper(struct mlx4_dev *dev, int slave,
1112                             struct mlx4_vhcr *vhcr,
1113                             struct mlx4_cmd_mailbox *inbox,
1114                             struct mlx4_cmd_mailbox *outbox,
1115                             struct mlx4_cmd_info *cmd);
1116 int mlx4_QUERY_IF_STAT_wrapper(struct mlx4_dev *dev, int slave,
1117                                struct mlx4_vhcr *vhcr,
1118                                struct mlx4_cmd_mailbox *inbox,
1119                                struct mlx4_cmd_mailbox *outbox,
1120                                struct mlx4_cmd_info *cmd);
1121
1122 int mlx4_get_mgm_entry_size(struct mlx4_dev *dev);
1123 int mlx4_get_qp_per_mgm(struct mlx4_dev *dev);
1124
1125 static inline void set_param_l(u64 *arg, u32 val)
1126 {
1127         *((u32 *)arg) = val;
1128 }
1129
1130 static inline void set_param_h(u64 *arg, u32 val)
1131 {
1132         *arg = (*arg & 0xffffffff) | ((u64) val << 32);
1133 }
1134
1135 static inline u32 get_param_l(u64 *arg)
1136 {
1137         return (u32) (*arg & 0xffffffff);
1138 }
1139
1140 static inline u32 get_param_h(u64 *arg)
1141 {
1142         return (u32)(*arg >> 32);
1143 }
1144
1145 static inline spinlock_t *mlx4_tlock(struct mlx4_dev *dev)
1146 {
1147         return &mlx4_priv(dev)->mfunc.master.res_tracker.lock;
1148 }
1149
1150 #define NOT_MASKED_PD_BITS 17
1151
1152 #endif /* MLX4_H */