drivers/net/ethernet/mellanox/mlx4/mlx4.h

   1 /*
   2  * Copyright (c) 2004, 2005 Topspin Communications.  All rights reserved.
   3  * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
   4  * Copyright (c) 2005, 2006, 2007 Cisco Systems.  All rights reserved.
   5  * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
   6  * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
   7  *
   8  * This software is available to you under a choice of one of two
   9  * licenses.  You may choose to be licensed under the terms of the GNU
  10  * General Public License (GPL) Version 2, available from the file
  11  * COPYING in the main directory of this source tree, or the
  12  * OpenIB.org BSD license below:
  13  *
  14  *     Redistribution and use in source and binary forms, with or
  15  *     without modification, are permitted provided that the following
  16  *     conditions are met:
  17  *
  18  *      - Redistributions of source code must retain the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer.
  21  *
  22  *      - Redistributions in binary form must reproduce the above
  23  *        copyright notice, this list of conditions and the following
  24  *        disclaimer in the documentation and/or other materials
  25  *        provided with the distribution.
  26  *
  27  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  28  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  29  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  30  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  31  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  32  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  33  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  34  * SOFTWARE.
  35  */
  36
  37 #ifndef MLX4_H
  38 #define MLX4_H
  39
  40 #include <linux/mutex.h>
  41 #include <linux/radix-tree.h>
  42 #include <linux/rbtree.h>
  43 #include <linux/timer.h>
  44 #include <linux/semaphore.h>
  45 #include <linux/workqueue.h>
  46
  47 #include <linux/mlx4/device.h>
  48 #include <linux/mlx4/driver.h>
  49 #include <linux/mlx4/doorbell.h>
  50 #include <linux/mlx4/cmd.h>
  51
  52 #define DRV_NAME        "mlx4_core"
  53 #define PFX             DRV_NAME ": "
  54 #define DRV_VERSION     "2.2-1"
  55 #define DRV_RELDATE     "Feb, 2014"
  56
  57 #define MLX4_FS_UDP_UC_EN               (1 << 1)
  58 #define MLX4_FS_TCP_UC_EN               (1 << 2)
  59 #define MLX4_FS_NUM_OF_L2_ADDR          8
  60 #define MLX4_FS_MGM_LOG_ENTRY_SIZE      7
  61 #define MLX4_FS_NUM_MCG                 (1 << 17)
  62
  63 #define INIT_HCA_TPT_MW_ENABLE          (1 << 7)
  64
  65 struct mlx4_set_port_prio2tc_context {
  66         u8 prio2tc[4];
  67 };
  68
  69 struct mlx4_port_scheduler_tc_cfg_be {
  70         __be16 pg;
  71         __be16 bw_precentage;
  72         __be16 max_bw_units; /* 3-100Mbps, 4-1Gbps, other values - reserved */
  73         __be16 max_bw_value;
  74 };
  75
  76 struct mlx4_set_port_scheduler_context {
  77         struct mlx4_port_scheduler_tc_cfg_be tc[MLX4_NUM_TC];
  78 };
  79
  80 enum {
  81         MLX4_HCR_BASE           = 0x80680,
  82         MLX4_HCR_SIZE           = 0x0001c,
  83         MLX4_CLR_INT_SIZE       = 0x00008,
  84         MLX4_SLAVE_COMM_BASE    = 0x0,
  85         MLX4_COMM_PAGESIZE      = 0x1000,
  86         MLX4_CLOCK_SIZE         = 0x00008
  87 };
  88
  89 enum {
  90         MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE = 10,
  91         MLX4_MIN_MGM_LOG_ENTRY_SIZE = 7,
  92         MLX4_MAX_MGM_LOG_ENTRY_SIZE = 12,
  93         MLX4_MAX_QP_PER_MGM = 4 * ((1 << MLX4_MAX_MGM_LOG_ENTRY_SIZE) / 16 - 2),
  94         MLX4_MTT_ENTRY_PER_SEG  = 8,
  95 };
  96
  97 enum {
  98         MLX4_NUM_PDS            = 1 << 15
  99 };
 100
 101 enum {
 102         MLX4_CMPT_TYPE_QP       = 0,
 103         MLX4_CMPT_TYPE_SRQ      = 1,
 104         MLX4_CMPT_TYPE_CQ       = 2,
 105         MLX4_CMPT_TYPE_EQ       = 3,
 106         MLX4_CMPT_NUM_TYPE
 107 };
 108
 109 enum {
 110         MLX4_CMPT_SHIFT         = 24,
 111         MLX4_NUM_CMPTS          = MLX4_CMPT_NUM_TYPE << MLX4_CMPT_SHIFT
 112 };
 113
 114 enum mlx4_mpt_state {
 115         MLX4_MPT_DISABLED = 0,
 116         MLX4_MPT_EN_HW,
 117         MLX4_MPT_EN_SW
 118 };
 119
 120 #define MLX4_COMM_TIME          10000
 121 enum {
 122         MLX4_COMM_CMD_RESET,
 123         MLX4_COMM_CMD_VHCR0,
 124         MLX4_COMM_CMD_VHCR1,
 125         MLX4_COMM_CMD_VHCR2,
 126         MLX4_COMM_CMD_VHCR_EN,
 127         MLX4_COMM_CMD_VHCR_POST,
 128         MLX4_COMM_CMD_FLR = 254
 129 };
 130
 131 enum {
 132         MLX4_VF_SMI_DISABLED,
 133         MLX4_VF_SMI_ENABLED
 134 };
 135
 136 /*The flag indicates that the slave should delay the RESET cmd*/
 137 #define MLX4_DELAY_RESET_SLAVE 0xbbbbbbb
 138 /*indicates how many retries will be done if we are in the middle of FLR*/
 139 #define NUM_OF_RESET_RETRIES    10
 140 #define SLEEP_TIME_IN_RESET     (2 * 1000)
 141 enum mlx4_resource {
 142         RES_QP,
 143         RES_CQ,
 144         RES_SRQ,
 145         RES_XRCD,
 146         RES_MPT,
 147         RES_MTT,
 148         RES_MAC,
 149         RES_VLAN,
 150         RES_EQ,
 151         RES_COUNTER,
 152         RES_FS_RULE,
 153         MLX4_NUM_OF_RESOURCE_TYPE
 154 };
 155
 156 enum mlx4_alloc_mode {
 157         RES_OP_RESERVE,
 158         RES_OP_RESERVE_AND_MAP,
 159         RES_OP_MAP_ICM,
 160 };
 161
 162 enum mlx4_res_tracker_free_type {
 163         RES_TR_FREE_ALL,
 164         RES_TR_FREE_SLAVES_ONLY,
 165         RES_TR_FREE_STRUCTS_ONLY,
 166 };
 167
 168 /*
 169  *Virtual HCR structures.
 170  * mlx4_vhcr is the sw representation, in machine endianess
 171  *
 172  * mlx4_vhcr_cmd is the formalized structure, the one that is passed
 173  * to FW to go through communication channel.
 174  * It is big endian, and has the same structure as the physical HCR
 175  * used by command interface
 176  */
 177 struct mlx4_vhcr {
 178         u64     in_param;
 179         u64     out_param;
 180         u32     in_modifier;
 181         u32     errno;
 182         u16     op;
 183         u16     token;
 184         u8      op_modifier;
 185         u8      e_bit;
 186 };
 187
 188 struct mlx4_vhcr_cmd {
 189         __be64 in_param;
 190         __be32 in_modifier;
 191         __be64 out_param;
 192         __be16 token;
 193         u16 reserved;
 194         u8 status;
 195         u8 flags;
 196         __be16 opcode;
 197 };
 198
 199 struct mlx4_cmd_info {
 200         u16 opcode;
 201         bool has_inbox;
 202         bool has_outbox;
 203         bool out_is_imm;
 204         bool encode_slave_id;
 205         int (*verify)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr,
 206                       struct mlx4_cmd_mailbox *inbox);
 207         int (*wrapper)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr,
 208                        struct mlx4_cmd_mailbox *inbox,
 209                        struct mlx4_cmd_mailbox *outbox,
 210                        struct mlx4_cmd_info *cmd);
 211 };
 212
 213 #ifdef CONFIG_MLX4_DEBUG
 214 extern int mlx4_debug_level;
 215 #else /* CONFIG_MLX4_DEBUG */
 216 #define mlx4_debug_level        (0)
 217 #endif /* CONFIG_MLX4_DEBUG */
 218
 219 #define mlx4_dbg(mdev, format, ...)                                     \
 220 do {                                                                    \
 221         if (mlx4_debug_level)                                           \
 222                 dev_printk(KERN_DEBUG, &(mdev)->pdev->dev, format,      \
 223                            ##__VA_ARGS__);                              \
 224 } while (0)
 225
 226 #define mlx4_err(mdev, format, ...)                                     \
 227         dev_err(&(mdev)->pdev->dev, format, ##__VA_ARGS__)
 228 #define mlx4_info(mdev, format, ...)                                    \
 229         dev_info(&(mdev)->pdev->dev, format, ##__VA_ARGS__)
 230 #define mlx4_warn(mdev, format, ...)                                    \
 231         dev_warn(&(mdev)->pdev->dev, format, ##__VA_ARGS__)
 232
 233 extern int mlx4_log_num_mgm_entry_size;
 234 extern int log_mtts_per_seg;
 235
 236 #define MLX4_MAX_NUM_SLAVES     (MLX4_MAX_NUM_PF + MLX4_MAX_NUM_VF)
 237 #define ALL_SLAVES 0xff
 238
 239 struct mlx4_bitmap {
 240         u32                     last;
 241         u32                     top;
 242         u32                     max;
 243         u32                     reserved_top;
 244         u32                     mask;
 245         u32                     avail;
 246         spinlock_t              lock;
 247         unsigned long          *table;
 248 };
 249
 250 struct mlx4_buddy {
 251         unsigned long         **bits;
 252         unsigned int           *num_free;
 253         u32                     max_order;
 254         spinlock_t              lock;
 255 };
 256
 257 struct mlx4_icm;
 258
 259 struct mlx4_icm_table {
 260         u64                     virt;
 261         int                     num_icm;
 262         u32                     num_obj;
 263         int                     obj_size;
 264         int                     lowmem;
 265         int                     coherent;
 266         struct mutex            mutex;
 267         struct mlx4_icm       **icm;
 268 };
 269
 270 #define MLX4_MPT_FLAG_SW_OWNS       (0xfUL << 28)
 271 #define MLX4_MPT_FLAG_FREE          (0x3UL << 28)
 272 #define MLX4_MPT_FLAG_MIO           (1 << 17)
 273 #define MLX4_MPT_FLAG_BIND_ENABLE   (1 << 15)
 274 #define MLX4_MPT_FLAG_PHYSICAL      (1 <<  9)
 275 #define MLX4_MPT_FLAG_REGION        (1 <<  8)
 276
 277 #define MLX4_MPT_PD_MASK            (0x1FFFFUL)
 278 #define MLX4_MPT_PD_VF_MASK         (0xFE0000UL)
 279 #define MLX4_MPT_PD_FLAG_FAST_REG   (1 << 27)
 280 #define MLX4_MPT_PD_FLAG_RAE        (1 << 28)
 281 #define MLX4_MPT_PD_FLAG_EN_INV     (3 << 24)
 282
 283 #define MLX4_MPT_QP_FLAG_BOUND_QP   (1 << 7)
 284
 285 #define MLX4_MPT_STATUS_SW              0xF0
 286 #define MLX4_MPT_STATUS_HW              0x00
 287
 288 #define MLX4_CQE_SIZE_MASK_STRIDE       0x3
 289 #define MLX4_EQE_SIZE_MASK_STRIDE       0x30
 290
 291 /*
 292  * Must be packed because mtt_seg is 64 bits but only aligned to 32 bits.
 293  */
 294 struct mlx4_mpt_entry {
 295         __be32 flags;
 296         __be32 qpn;
 297         __be32 key;
 298         __be32 pd_flags;
 299         __be64 start;
 300         __be64 length;
 301         __be32 lkey;
 302         __be32 win_cnt;
 303         u8      reserved1[3];
 304         u8      mtt_rep;
 305         __be64 mtt_addr;
 306         __be32 mtt_sz;
 307         __be32 entity_size;
 308         __be32 first_byte_offset;
 309 } __packed;
 310
 311 /*
 312  * Must be packed because start is 64 bits but only aligned to 32 bits.
 313  */
 314 struct mlx4_eq_context {
 315         __be32                  flags;
 316         u16                     reserved1[3];
 317         __be16                  page_offset;
 318         u8                      log_eq_size;
 319         u8                      reserved2[4];
 320         u8                      eq_period;
 321         u8                      reserved3;
 322         u8                      eq_max_count;
 323         u8                      reserved4[3];
 324         u8                      intr;
 325         u8                      log_page_size;
 326         u8                      reserved5[2];
 327         u8                      mtt_base_addr_h;
 328         __be32                  mtt_base_addr_l;
 329         u32                     reserved6[2];
 330         __be32                  consumer_index;
 331         __be32                  producer_index;
 332         u32                     reserved7[4];
 333 };
 334
 335 struct mlx4_cq_context {
 336         __be32                  flags;
 337         u16                     reserved1[3];
 338         __be16                  page_offset;
 339         __be32                  logsize_usrpage;
 340         __be16                  cq_period;
 341         __be16                  cq_max_count;
 342         u8                      reserved2[3];
 343         u8                      comp_eqn;
 344         u8                      log_page_size;
 345         u8                      reserved3[2];
 346         u8                      mtt_base_addr_h;
 347         __be32                  mtt_base_addr_l;
 348         __be32                  last_notified_index;
 349         __be32                  solicit_producer_index;
 350         __be32                  consumer_index;
 351         __be32                  producer_index;
 352         u32                     reserved4[2];
 353         __be64                  db_rec_addr;
 354 };
 355
 356 struct mlx4_srq_context {
 357         __be32                  state_logsize_srqn;
 358         u8                      logstride;
 359         u8                      reserved1;
 360         __be16                  xrcd;
 361         __be32                  pg_offset_cqn;
 362         u32                     reserved2;
 363         u8                      log_page_size;
 364         u8                      reserved3[2];
 365         u8                      mtt_base_addr_h;
 366         __be32                  mtt_base_addr_l;
 367         __be32                  pd;
 368         __be16                  limit_watermark;
 369         __be16                  wqe_cnt;
 370         u16                     reserved4;
 371         __be16                  wqe_counter;
 372         u32                     reserved5;
 373         __be64                  db_rec_addr;
 374 };
 375
 376 struct mlx4_eq {
 377         struct mlx4_dev        *dev;
 378         void __iomem           *doorbell;
 379         int                     eqn;
 380         u32                     cons_index;
 381         u16                     irq;
 382         u16                     have_irq;
 383         int                     nent;
 384         struct mlx4_buf_list   *page_list;
 385         struct mlx4_mtt         mtt;
 386 };
 387
 388 struct mlx4_slave_eqe {
 389         u8 type;
 390         u8 port;
 391         u32 param;
 392 };
 393
 394 struct mlx4_slave_event_eq_info {
 395         int eqn;
 396         u16 token;
 397 };
 398
 399 struct mlx4_profile {
 400         int                     num_qp;
 401         int                     rdmarc_per_qp;
 402         int                     num_srq;
 403         int                     num_cq;
 404         int                     num_mcg;
 405         int                     num_mpt;
 406         unsigned                num_mtt;
 407 };
 408
 409 struct mlx4_fw {
 410         u64                     clr_int_base;
 411         u64                     catas_offset;
 412         u64                     comm_base;
 413         u64                     clock_offset;
 414         struct mlx4_icm        *fw_icm;
 415         struct mlx4_icm        *aux_icm;
 416         u32                     catas_size;
 417         u16                     fw_pages;
 418         u8                      clr_int_bar;
 419         u8                      catas_bar;
 420         u8                      comm_bar;
 421         u8                      clock_bar;
 422 };
 423
 424 struct mlx4_comm {
 425         u32                     slave_write;
 426         u32                     slave_read;
 427 };
 428
 429 enum {
 430         MLX4_MCAST_CONFIG       = 0,
 431         MLX4_MCAST_DISABLE      = 1,
 432         MLX4_MCAST_ENABLE       = 2,
 433 };
 434
 435 #define VLAN_FLTR_SIZE  128
 436
 437 struct mlx4_vlan_fltr {
 438         __be32 entry[VLAN_FLTR_SIZE];
 439 };
 440
 441 struct mlx4_mcast_entry {
 442         struct list_head list;
 443         u64 addr;
 444 };
 445
 446 struct mlx4_promisc_qp {
 447         struct list_head list;
 448         u32 qpn;
 449 };
 450
 451 struct mlx4_steer_index {
 452         struct list_head list;
 453         unsigned int index;
 454         struct list_head duplicates;
 455 };
 456
 457 #define MLX4_EVENT_TYPES_NUM 64
 458
 459 struct mlx4_slave_state {
 460         u8 comm_toggle;
 461         u8 last_cmd;
 462         u8 init_port_mask;
 463         bool active;
 464         bool old_vlan_api;
 465         u8 function;
 466         dma_addr_t vhcr_dma;
 467         u16 mtu[MLX4_MAX_PORTS + 1];
 468         __be32 ib_cap_mask[MLX4_MAX_PORTS + 1];
 469         struct mlx4_slave_eqe eq[MLX4_MFUNC_MAX_EQES];
 470         struct list_head mcast_filters[MLX4_MAX_PORTS + 1];
 471         struct mlx4_vlan_fltr *vlan_filter[MLX4_MAX_PORTS + 1];
 472         /* event type to eq number lookup */
 473         struct mlx4_slave_event_eq_info event_eq[MLX4_EVENT_TYPES_NUM];
 474         u16 eq_pi;
 475         u16 eq_ci;
 476         spinlock_t lock;
 477         /*initialized via the kzalloc*/
 478         u8 is_slave_going_down;
 479         u32 cookie;
 480         enum slave_port_state port_state[MLX4_MAX_PORTS + 1];
 481 };
 482
 483 #define MLX4_VGT 4095
 484 #define NO_INDX  (-1)
 485
 486 struct mlx4_vport_state {
 487         u64 mac;
 488         u16 default_vlan;
 489         u8  default_qos;
 490         u32 tx_rate;
 491         bool spoofchk;
 492         u32 link_state;
 493 };
 494
 495 struct mlx4_vf_admin_state {
 496         struct mlx4_vport_state vport[MLX4_MAX_PORTS + 1];
 497         u8 enable_smi[MLX4_MAX_PORTS + 1];
 498 };
 499
 500 struct mlx4_vport_oper_state {
 501         struct mlx4_vport_state state;
 502         int mac_idx;
 503         int vlan_idx;
 504 };
 505
 506 struct mlx4_vf_oper_state {
 507         struct mlx4_vport_oper_state vport[MLX4_MAX_PORTS + 1];
 508         u8 smi_enabled[MLX4_MAX_PORTS + 1];
 509 };
 510
 511 struct slave_list {
 512         struct mutex mutex;
 513         struct list_head res_list[MLX4_NUM_OF_RESOURCE_TYPE];
 514 };
 515
 516 struct resource_allocator {
 517         spinlock_t alloc_lock; /* protect quotas */
 518         union {
 519                 int res_reserved;
 520                 int res_port_rsvd[MLX4_MAX_PORTS];
 521         };
 522         union {
 523                 int res_free;
 524                 int res_port_free[MLX4_MAX_PORTS];
 525         };
 526         int *quota;
 527         int *allocated;
 528         int *guaranteed;
 529 };
 530
 531 struct mlx4_resource_tracker {
 532         spinlock_t lock;
 533         /* tree for each resources */
 534         struct rb_root res_tree[MLX4_NUM_OF_RESOURCE_TYPE];
 535         /* num_of_slave's lists, one per slave */
 536         struct slave_list *slave_list;
 537         struct resource_allocator res_alloc[MLX4_NUM_OF_RESOURCE_TYPE];
 538 };
 539
 540 #define SLAVE_EVENT_EQ_SIZE     128
 541 struct mlx4_slave_event_eq {
 542         u32 eqn;
 543         u32 cons;
 544         u32 prod;
 545         spinlock_t event_lock;
 546         struct mlx4_eqe event_eqe[SLAVE_EVENT_EQ_SIZE];
 547 };
 548
 549 struct mlx4_master_qp0_state {
 550         int proxy_qp0_active;
 551         int qp0_active;
 552         int port_active;
 553 };
 554
 555 struct mlx4_mfunc_master_ctx {
 556         struct mlx4_slave_state *slave_state;
 557         struct mlx4_vf_admin_state *vf_admin;
 558         struct mlx4_vf_oper_state *vf_oper;
 559         struct mlx4_master_qp0_state qp0_state[MLX4_MAX_PORTS + 1];
 560         int                     init_port_ref[MLX4_MAX_PORTS + 1];
 561         u16                     max_mtu[MLX4_MAX_PORTS + 1];
 562         int                     disable_mcast_ref[MLX4_MAX_PORTS + 1];
 563         struct mlx4_resource_tracker res_tracker;
 564         struct workqueue_struct *comm_wq;
 565         struct work_struct      comm_work;
 566         struct work_struct      slave_event_work;
 567         struct work_struct      slave_flr_event_work;
 568         spinlock_t              slave_state_lock;
 569         __be32                  comm_arm_bit_vector[4];
 570         struct mlx4_eqe         cmd_eqe;
 571         struct mlx4_slave_event_eq slave_eq;
 572         struct mutex            gen_eqe_mutex[MLX4_MFUNC_MAX];
 573 };
 574
 575 struct mlx4_mfunc {
 576         struct mlx4_comm __iomem       *comm;
 577         struct mlx4_vhcr_cmd           *vhcr;
 578         dma_addr_t                      vhcr_dma;
 579
 580         struct mlx4_mfunc_master_ctx    master;
 581 };
 582
 583 #define MGM_QPN_MASK       0x00FFFFFF
 584 #define MGM_BLCK_LB_BIT    30
 585
 586 struct mlx4_mgm {
 587         __be32                  next_gid_index;
 588         __be32                  members_count;
 589         u32                     reserved[2];
 590         u8                      gid[16];
 591         __be32                  qp[MLX4_MAX_QP_PER_MGM];
 592 };
 593
 594 struct mlx4_cmd {
 595         struct pci_pool        *pool;
 596         void __iomem           *hcr;
 597         struct mutex            hcr_mutex;
 598         struct mutex            slave_cmd_mutex;
 599         struct semaphore        poll_sem;
 600         struct semaphore        event_sem;
 601         int                     max_cmds;
 602         spinlock_t              context_lock;
 603         int                     free_head;
 604         struct mlx4_cmd_context *context;
 605         u16                     token_mask;
 606         u8                      use_events;
 607         u8                      toggle;
 608         u8                      comm_toggle;
 609 };
 610
 611 enum {
 612         MLX4_VF_IMMED_VLAN_FLAG_VLAN = 1 << 0,
 613         MLX4_VF_IMMED_VLAN_FLAG_QOS = 1 << 1,
 614         MLX4_VF_IMMED_VLAN_FLAG_LINK_DISABLE = 1 << 2,
 615 };
 616 struct mlx4_vf_immed_vlan_work {
 617         struct work_struct      work;
 618         struct mlx4_priv        *priv;
 619         int                     flags;
 620         int                     slave;
 621         int                     vlan_ix;
 622         int                     orig_vlan_ix;
 623         u8                      port;
 624         u8                      qos;
 625         u16                     vlan_id;
 626         u16                     orig_vlan_id;
 627 };
 628
 629
 630 struct mlx4_uar_table {
 631         struct mlx4_bitmap      bitmap;
 632 };
 633
 634 struct mlx4_mr_table {
 635         struct mlx4_bitmap      mpt_bitmap;
 636         struct mlx4_buddy       mtt_buddy;
 637         u64                     mtt_base;
 638         u64                     mpt_base;
 639         struct mlx4_icm_table   mtt_table;
 640         struct mlx4_icm_table   dmpt_table;
 641 };
 642
 643 struct mlx4_cq_table {
 644         struct mlx4_bitmap      bitmap;
 645         spinlock_t              lock;
 646         struct radix_tree_root  tree;
 647         struct mlx4_icm_table   table;
 648         struct mlx4_icm_table   cmpt_table;
 649 };
 650
 651 struct mlx4_eq_table {
 652         struct mlx4_bitmap      bitmap;
 653         char                   *irq_names;
 654         void __iomem           *clr_int;
 655         void __iomem          **uar_map;
 656         u32                     clr_mask;
 657         struct mlx4_eq         *eq;
 658         struct mlx4_icm_table   table;
 659         struct mlx4_icm_table   cmpt_table;
 660         int                     have_irq;
 661         u8                      inta_pin;
 662 };
 663
 664 struct mlx4_srq_table {
 665         struct mlx4_bitmap      bitmap;
 666         spinlock_t              lock;
 667         struct radix_tree_root  tree;
 668         struct mlx4_icm_table   table;
 669         struct mlx4_icm_table   cmpt_table;
 670 };
 671
 672 struct mlx4_qp_table {
 673         struct mlx4_bitmap      bitmap;
 674         u32                     rdmarc_base;
 675         int                     rdmarc_shift;
 676         spinlock_t              lock;
 677         struct mlx4_icm_table   qp_table;
 678         struct mlx4_icm_table   auxc_table;
 679         struct mlx4_icm_table   altc_table;
 680         struct mlx4_icm_table   rdmarc_table;
 681         struct mlx4_icm_table   cmpt_table;
 682 };
 683
 684 struct mlx4_mcg_table {
 685         struct mutex            mutex;
 686         struct mlx4_bitmap      bitmap;
 687         struct mlx4_icm_table   table;
 688 };
 689
 690 struct mlx4_catas_err {
 691         u32 __iomem            *map;
 692         struct timer_list       timer;
 693         struct list_head        list;
 694 };
 695
 696 #define MLX4_MAX_MAC_NUM        128
 697 #define MLX4_MAC_TABLE_SIZE     (MLX4_MAX_MAC_NUM << 3)
 698
 699 struct mlx4_mac_table {
 700         __be64                  entries[MLX4_MAX_MAC_NUM];
 701         int                     refs[MLX4_MAX_MAC_NUM];
 702         struct mutex            mutex;
 703         int                     total;
 704         int                     max;
 705 };
 706
 707 #define MLX4_ROCE_GID_ENTRY_SIZE        16
 708
 709 struct mlx4_roce_gid_entry {
 710         u8 raw[MLX4_ROCE_GID_ENTRY_SIZE];
 711 };
 712
 713 struct mlx4_roce_gid_table {
 714         struct mlx4_roce_gid_entry      roce_gids[MLX4_ROCE_MAX_GIDS];
 715         struct mutex                    mutex;
 716 };
 717
 718 #define MLX4_MAX_VLAN_NUM       128
 719 #define MLX4_VLAN_TABLE_SIZE    (MLX4_MAX_VLAN_NUM << 2)
 720
 721 struct mlx4_vlan_table {
 722         __be32                  entries[MLX4_MAX_VLAN_NUM];
 723         int                     refs[MLX4_MAX_VLAN_NUM];
 724         struct mutex            mutex;
 725         int                     total;
 726         int                     max;
 727 };
 728
 729 #define SET_PORT_GEN_ALL_VALID          0x7
 730 #define SET_PORT_PROMISC_SHIFT          31
 731 #define SET_PORT_MC_PROMISC_SHIFT       30
 732
 733 enum {
 734         MCAST_DIRECT_ONLY       = 0,
 735         MCAST_DIRECT            = 1,
 736         MCAST_DEFAULT           = 2
 737 };
 738
 739
 740 struct mlx4_set_port_general_context {
 741         u8 reserved[3];
 742         u8 flags;
 743         u16 reserved2;
 744         __be16 mtu;
 745         u8 pptx;
 746         u8 pfctx;
 747         u16 reserved3;
 748         u8 pprx;
 749         u8 pfcrx;
 750         u16 reserved4;
 751 };
 752
 753 struct mlx4_set_port_rqp_calc_context {
 754         __be32 base_qpn;
 755         u8 rererved;
 756         u8 n_mac;
 757         u8 n_vlan;
 758         u8 n_prio;
 759         u8 reserved2[3];
 760         u8 mac_miss;
 761         u8 intra_no_vlan;
 762         u8 no_vlan;
 763         u8 intra_vlan_miss;
 764         u8 vlan_miss;
 765         u8 reserved3[3];
 766         u8 no_vlan_prio;
 767         __be32 promisc;
 768         __be32 mcast;
 769 };
 770
 771 struct mlx4_port_info {
 772         struct mlx4_dev        *dev;
 773         int                     port;
 774         char                    dev_name[16];
 775         struct device_attribute port_attr;
 776         enum mlx4_port_type     tmp_type;
 777         char                    dev_mtu_name[16];
 778         struct device_attribute port_mtu_attr;
 779         struct mlx4_mac_table   mac_table;
 780         struct mlx4_vlan_table  vlan_table;
 781         struct mlx4_roce_gid_table gid_table;
 782         int                     base_qpn;
 783 };
 784
 785 struct mlx4_sense {
 786         struct mlx4_dev         *dev;
 787         u8                      do_sense_port[MLX4_MAX_PORTS + 1];
 788         u8                      sense_allowed[MLX4_MAX_PORTS + 1];
 789         struct delayed_work     sense_poll;
 790 };
 791
 792 struct mlx4_msix_ctl {
 793         u64             pool_bm;
 794         struct mutex    pool_lock;
 795 };
 796
 797 struct mlx4_steer {
 798         struct list_head promisc_qps[MLX4_NUM_STEERS];
 799         struct list_head steer_entries[MLX4_NUM_STEERS];
 800 };
 801
 802 enum {
 803         MLX4_PCI_DEV_IS_VF              = 1 << 0,
 804         MLX4_PCI_DEV_FORCE_SENSE_PORT   = 1 << 1,
 805 };
 806
 807 enum {
 808         MLX4_NO_RR      = 0,
 809         MLX4_USE_RR     = 1,
 810 };
 811
 812 struct mlx4_priv {
 813         struct mlx4_dev         dev;
 814
 815         struct list_head        dev_list;
 816         struct list_head        ctx_list;
 817         spinlock_t              ctx_lock;
 818
 819         int                     pci_dev_data;
 820         int                     removed;
 821
 822         struct list_head        pgdir_list;
 823         struct mutex            pgdir_mutex;
 824
 825         struct mlx4_fw          fw;
 826         struct mlx4_cmd         cmd;
 827         struct mlx4_mfunc       mfunc;
 828
 829         struct mlx4_bitmap      pd_bitmap;
 830         struct mlx4_bitmap      xrcd_bitmap;
 831         struct mlx4_uar_table   uar_table;
 832         struct mlx4_mr_table    mr_table;
 833         struct mlx4_cq_table    cq_table;
 834         struct mlx4_eq_table    eq_table;
 835         struct mlx4_srq_table   srq_table;
 836         struct mlx4_qp_table    qp_table;
 837         struct mlx4_mcg_table   mcg_table;
 838         struct mlx4_bitmap      counters_bitmap;
 839
 840         struct mlx4_catas_err   catas_err;
 841
 842         void __iomem           *clr_base;
 843
 844         struct mlx4_uar         driver_uar;
 845         void __iomem           *kar;
 846         struct mlx4_port_info   port[MLX4_MAX_PORTS + 1];
 847         struct mlx4_sense       sense;
 848         struct mutex            port_mutex;
 849         struct mlx4_msix_ctl    msix_ctl;
 850         struct mlx4_steer       *steer;
 851         struct list_head        bf_list;
 852         struct mutex            bf_mutex;
 853         struct io_mapping       *bf_mapping;
 854         void __iomem            *clock_mapping;
 855         int                     reserved_mtts;
 856         int                     fs_hash_mode;
 857         u8 virt2phys_pkey[MLX4_MFUNC_MAX][MLX4_MAX_PORTS][MLX4_MAX_PORT_PKEYS];
 858         __be64                  slave_node_guids[MLX4_MFUNC_MAX];
 859
 860         atomic_t                opreq_count;
 861         struct work_struct      opreq_task;
 862 };
 863
 864 static inline struct mlx4_priv *mlx4_priv(struct mlx4_dev *dev)
 865 {
 866         return container_of(dev, struct mlx4_priv, dev);
 867 }
 868
 869 #define MLX4_SENSE_RANGE        (HZ * 3)
 870
 871 extern struct workqueue_struct *mlx4_wq;
 872
 873 u32 mlx4_bitmap_alloc(struct mlx4_bitmap *bitmap);
 874 void mlx4_bitmap_free(struct mlx4_bitmap *bitmap, u32 obj, int use_rr);
 875 u32 mlx4_bitmap_alloc_range(struct mlx4_bitmap *bitmap, int cnt, int align);
 876 void mlx4_bitmap_free_range(struct mlx4_bitmap *bitmap, u32 obj, int cnt,
 877                             int use_rr);
 878 u32 mlx4_bitmap_avail(struct mlx4_bitmap *bitmap);
 879 int mlx4_bitmap_init(struct mlx4_bitmap *bitmap, u32 num, u32 mask,
 880                      u32 reserved_bot, u32 resetrved_top);
 881 void mlx4_bitmap_cleanup(struct mlx4_bitmap *bitmap);
 882
 883 int mlx4_reset(struct mlx4_dev *dev);
 884
 885 int mlx4_alloc_eq_table(struct mlx4_dev *dev);
 886 void mlx4_free_eq_table(struct mlx4_dev *dev);
 887
 888 int mlx4_init_pd_table(struct mlx4_dev *dev);
 889 int mlx4_init_xrcd_table(struct mlx4_dev *dev);
 890 int mlx4_init_uar_table(struct mlx4_dev *dev);
 891 int mlx4_init_mr_table(struct mlx4_dev *dev);
 892 int mlx4_init_eq_table(struct mlx4_dev *dev);
 893 int mlx4_init_cq_table(struct mlx4_dev *dev);
 894 int mlx4_init_qp_table(struct mlx4_dev *dev);
 895 int mlx4_init_srq_table(struct mlx4_dev *dev);
 896 int mlx4_init_mcg_table(struct mlx4_dev *dev);
 897
 898 void mlx4_cleanup_pd_table(struct mlx4_dev *dev);
 899 void mlx4_cleanup_xrcd_table(struct mlx4_dev *dev);
 900 void mlx4_cleanup_uar_table(struct mlx4_dev *dev);
 901 void mlx4_cleanup_mr_table(struct mlx4_dev *dev);
 902 void mlx4_cleanup_eq_table(struct mlx4_dev *dev);
 903 void mlx4_cleanup_cq_table(struct mlx4_dev *dev);
 904 void mlx4_cleanup_qp_table(struct mlx4_dev *dev);
 905 void mlx4_cleanup_srq_table(struct mlx4_dev *dev);
 906 void mlx4_cleanup_mcg_table(struct mlx4_dev *dev);
 907 int __mlx4_qp_alloc_icm(struct mlx4_dev *dev, int qpn, gfp_t gfp);
 908 void __mlx4_qp_free_icm(struct mlx4_dev *dev, int qpn);
 909 int __mlx4_cq_alloc_icm(struct mlx4_dev *dev, int *cqn);
 910 void __mlx4_cq_free_icm(struct mlx4_dev *dev, int cqn);
 911 int __mlx4_srq_alloc_icm(struct mlx4_dev *dev, int *srqn);
 912 void __mlx4_srq_free_icm(struct mlx4_dev *dev, int srqn);
 913 int __mlx4_mpt_reserve(struct mlx4_dev *dev);
 914 void __mlx4_mpt_release(struct mlx4_dev *dev, u32 index);
 915 int __mlx4_mpt_alloc_icm(struct mlx4_dev *dev, u32 index, gfp_t gfp);
 916 void __mlx4_mpt_free_icm(struct mlx4_dev *dev, u32 index);
 917 u32 __mlx4_alloc_mtt_range(struct mlx4_dev *dev, int order);
 918 void __mlx4_free_mtt_range(struct mlx4_dev *dev, u32 first_seg, int order);
 919
 920 int mlx4_WRITE_MTT_wrapper(struct mlx4_dev *dev, int slave,
 921                            struct mlx4_vhcr *vhcr,
 922                            struct mlx4_cmd_mailbox *inbox,
 923                            struct mlx4_cmd_mailbox *outbox,
 924                            struct mlx4_cmd_info *cmd);
 925 int mlx4_SYNC_TPT_wrapper(struct mlx4_dev *dev, int slave,
 926                            struct mlx4_vhcr *vhcr,
 927                            struct mlx4_cmd_mailbox *inbox,
 928                            struct mlx4_cmd_mailbox *outbox,
 929                            struct mlx4_cmd_info *cmd);
 930 int mlx4_SW2HW_MPT_wrapper(struct mlx4_dev *dev, int slave,
 931                            struct mlx4_vhcr *vhcr,
 932                            struct mlx4_cmd_mailbox *inbox,
 933                            struct mlx4_cmd_mailbox *outbox,
 934                            struct mlx4_cmd_info *cmd);
 935 int mlx4_HW2SW_MPT_wrapper(struct mlx4_dev *dev, int slave,
 936                            struct mlx4_vhcr *vhcr,
 937                            struct mlx4_cmd_mailbox *inbox,
 938                            struct mlx4_cmd_mailbox *outbox,
 939                            struct mlx4_cmd_info *cmd);
 940 int mlx4_QUERY_MPT_wrapper(struct mlx4_dev *dev, int slave,
 941                            struct mlx4_vhcr *vhcr,
 942                            struct mlx4_cmd_mailbox *inbox,
 943                            struct mlx4_cmd_mailbox *outbox,
 944                            struct mlx4_cmd_info *cmd);
 945 int mlx4_SW2HW_EQ_wrapper(struct mlx4_dev *dev, int slave,
 946                           struct mlx4_vhcr *vhcr,
 947                           struct mlx4_cmd_mailbox *inbox,
 948                           struct mlx4_cmd_mailbox *outbox,
 949                           struct mlx4_cmd_info *cmd);
 950 int mlx4_DMA_wrapper(struct mlx4_dev *dev, int slave,
 951                      struct mlx4_vhcr *vhcr,
 952                      struct mlx4_cmd_mailbox *inbox,
 953                      struct mlx4_cmd_mailbox *outbox,
 954                      struct mlx4_cmd_info *cmd);
 955 int __mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align,
 956                             int *base);
 957 void __mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt);
 958 int __mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac);
 959 void __mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac);
 960 int __mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
 961                      int start_index, int npages, u64 *page_list);
 962 int __mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx);
 963 void __mlx4_counter_free(struct mlx4_dev *dev, u32 idx);
 964 int __mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn);
 965 void __mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn);
 966
 967 void mlx4_start_catas_poll(struct mlx4_dev *dev);
 968 void mlx4_stop_catas_poll(struct mlx4_dev *dev);
 969 void mlx4_catas_init(void);
 970 int mlx4_restart_one(struct pci_dev *pdev);
 971 int mlx4_register_device(struct mlx4_dev *dev);
 972 void mlx4_unregister_device(struct mlx4_dev *dev);
 973 void mlx4_dispatch_event(struct mlx4_dev *dev, enum mlx4_dev_event type,
 974                          unsigned long param);
 975
 976 struct mlx4_dev_cap;
 977 struct mlx4_init_hca_param;
 978
 979 u64 mlx4_make_profile(struct mlx4_dev *dev,
 980                       struct mlx4_profile *request,
 981                       struct mlx4_dev_cap *dev_cap,
 982                       struct mlx4_init_hca_param *init_hca);
 983 void mlx4_master_comm_channel(struct work_struct *work);
 984 void mlx4_gen_slave_eqe(struct work_struct *work);
 985 void mlx4_master_handle_slave_flr(struct work_struct *work);
 986
 987 int mlx4_ALLOC_RES_wrapper(struct mlx4_dev *dev, int slave,
 988                            struct mlx4_vhcr *vhcr,
 989                            struct mlx4_cmd_mailbox *inbox,
 990                            struct mlx4_cmd_mailbox *outbox,
 991                            struct mlx4_cmd_info *cmd);
 992 int mlx4_FREE_RES_wrapper(struct mlx4_dev *dev, int slave,
 993                           struct mlx4_vhcr *vhcr,
 994                           struct mlx4_cmd_mailbox *inbox,
 995                           struct mlx4_cmd_mailbox *outbox,
 996                           struct mlx4_cmd_info *cmd);
 997 int mlx4_MAP_EQ_wrapper(struct mlx4_dev *dev, int slave,
 998                         struct mlx4_vhcr *vhcr, struct mlx4_cmd_mailbox *inbox,
 999                         struct mlx4_cmd_mailbox *outbox,
1000                         struct mlx4_cmd_info *cmd);
1001 int mlx4_COMM_INT_wrapper(struct mlx4_dev *dev, int slave,
1002                           struct mlx4_vhcr *vhcr,
1003                           struct mlx4_cmd_mailbox *inbox,
1004                           struct mlx4_cmd_mailbox *outbox,
1005                           struct mlx4_cmd_info *cmd);
1006 int mlx4_HW2SW_EQ_wrapper(struct mlx4_dev *dev, int slave,
1007                             struct mlx4_vhcr *vhcr,
1008                             struct mlx4_cmd_mailbox *inbox,
1009                             struct mlx4_cmd_mailbox *outbox,
1010                           struct mlx4_cmd_info *cmd);
1011 int mlx4_QUERY_EQ_wrapper(struct mlx4_dev *dev, int slave,
1012                           struct mlx4_vhcr *vhcr,
1013                           struct mlx4_cmd_mailbox *inbox,
1014                           struct mlx4_cmd_mailbox *outbox,
1015                           struct mlx4_cmd_info *cmd);
1016 int mlx4_SW2HW_CQ_wrapper(struct mlx4_dev *dev, int slave,
1017                           struct mlx4_vhcr *vhcr,
1018                           struct mlx4_cmd_mailbox *inbox,
1019                           struct mlx4_cmd_mailbox *outbox,
1020                           struct mlx4_cmd_info *cmd);
1021 int mlx4_HW2SW_CQ_wrapper(struct mlx4_dev *dev, int slave,
1022                           struct mlx4_vhcr *vhcr,
1023                           struct mlx4_cmd_mailbox *inbox,
1024                           struct mlx4_cmd_mailbox *outbox,
1025                           struct mlx4_cmd_info *cmd);
1026 int mlx4_QUERY_CQ_wrapper(struct mlx4_dev *dev, int slave,
1027                           struct mlx4_vhcr *vhcr,
1028                           struct mlx4_cmd_mailbox *inbox,
1029                           struct mlx4_cmd_mailbox *outbox,
1030                           struct mlx4_cmd_info *cmd);
1031 int mlx4_MODIFY_CQ_wrapper(struct mlx4_dev *dev, int slave,
1032                           struct mlx4_vhcr *vhcr,
1033                           struct mlx4_cmd_mailbox *inbox,
1034                           struct mlx4_cmd_mailbox *outbox,
1035                            struct mlx4_cmd_info *cmd);
1036 int mlx4_SW2HW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
1037                            struct mlx4_vhcr *vhcr,
1038                            struct mlx4_cmd_mailbox *inbox,
1039                            struct mlx4_cmd_mailbox *outbox,
1040                            struct mlx4_cmd_info *cmd);
1041 int mlx4_HW2SW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
1042                            struct mlx4_vhcr *vhcr,
1043                            struct mlx4_cmd_mailbox *inbox,
1044                            struct mlx4_cmd_mailbox *outbox,
1045                            struct mlx4_cmd_info *cmd);
1046 int mlx4_QUERY_SRQ_wrapper(struct mlx4_dev *dev, int slave,
1047                            struct mlx4_vhcr *vhcr,
1048                            struct mlx4_cmd_mailbox *inbox,
1049                            struct mlx4_cmd_mailbox *outbox,
1050                            struct mlx4_cmd_info *cmd);
1051 int mlx4_ARM_SRQ_wrapper(struct mlx4_dev *dev, int slave,
1052                          struct mlx4_vhcr *vhcr,
1053                          struct mlx4_cmd_mailbox *inbox,
1054                          struct mlx4_cmd_mailbox *outbox,
1055                          struct mlx4_cmd_info *cmd);
1056 int mlx4_GEN_QP_wrapper(struct mlx4_dev *dev, int slave,
1057                         struct mlx4_vhcr *vhcr,
1058                         struct mlx4_cmd_mailbox *inbox,
1059                         struct mlx4_cmd_mailbox *outbox,
1060                         struct mlx4_cmd_info *cmd);
1061 int mlx4_RST2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
1062                              struct mlx4_vhcr *vhcr,
1063                              struct mlx4_cmd_mailbox *inbox,
1064                              struct mlx4_cmd_mailbox *outbox,
1065                              struct mlx4_cmd_info *cmd);
1066 int mlx4_INIT2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
1067                               struct mlx4_vhcr *vhcr,
1068                               struct mlx4_cmd_mailbox *inbox,
1069                               struct mlx4_cmd_mailbox *outbox,
1070                               struct mlx4_cmd_info *cmd);
1071 int mlx4_INIT2RTR_QP_wrapper(struct mlx4_dev *dev, int slave,
1072                              struct mlx4_vhcr *vhcr,
1073                              struct mlx4_cmd_mailbox *inbox,
1074                              struct mlx4_cmd_mailbox *outbox,
1075                              struct mlx4_cmd_info *cmd);
1076 int mlx4_RTR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
1077                             struct mlx4_vhcr *vhcr,
1078                             struct mlx4_cmd_mailbox *inbox,
1079                             struct mlx4_cmd_mailbox *outbox,
1080                             struct mlx4_cmd_info *cmd);
1081 int mlx4_RTS2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
1082                             struct mlx4_vhcr *vhcr,
1083                             struct mlx4_cmd_mailbox *inbox,
1084                             struct mlx4_cmd_mailbox *outbox,
1085                             struct mlx4_cmd_info *cmd);
1086 int mlx4_SQERR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
1087                               struct mlx4_vhcr *vhcr,
1088                               struct mlx4_cmd_mailbox *inbox,
1089                               struct mlx4_cmd_mailbox *outbox,
1090                               struct mlx4_cmd_info *cmd);
1091 int mlx4_2ERR_QP_wrapper(struct mlx4_dev *dev, int slave,
1092                          struct mlx4_vhcr *vhcr,
1093                          struct mlx4_cmd_mailbox *inbox,
1094                          struct mlx4_cmd_mailbox *outbox,
1095                          struct mlx4_cmd_info *cmd);
1096 int mlx4_RTS2SQD_QP_wrapper(struct mlx4_dev *dev, int slave,
1097                             struct mlx4_vhcr *vhcr,
1098                             struct mlx4_cmd_mailbox *inbox,
1099                             struct mlx4_cmd_mailbox *outbox,
1100                             struct mlx4_cmd_info *cmd);
1101 int mlx4_SQD2SQD_QP_wrapper(struct mlx4_dev *dev, int slave,
1102                             struct mlx4_vhcr *vhcr,
1103                             struct mlx4_cmd_mailbox *inbox,
1104                             struct mlx4_cmd_mailbox *outbox,
1105                             struct mlx4_cmd_info *cmd);
1106 int mlx4_SQD2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
1107                             struct mlx4_vhcr *vhcr,
1108                             struct mlx4_cmd_mailbox *inbox,
1109                             struct mlx4_cmd_mailbox *outbox,
1110                             struct mlx4_cmd_info *cmd);
1111 int mlx4_2RST_QP_wrapper(struct mlx4_dev *dev, int slave,
1112                          struct mlx4_vhcr *vhcr,
1113                          struct mlx4_cmd_mailbox *inbox,
1114                          struct mlx4_cmd_mailbox *outbox,
1115                          struct mlx4_cmd_info *cmd);
1116 int mlx4_QUERY_QP_wrapper(struct mlx4_dev *dev, int slave,
1117                           struct mlx4_vhcr *vhcr,
1118                           struct mlx4_cmd_mailbox *inbox,
1119                           struct mlx4_cmd_mailbox *outbox,
1120                           struct mlx4_cmd_info *cmd);
1121
1122 int mlx4_GEN_EQE(struct mlx4_dev *dev, int slave, struct mlx4_eqe *eqe);
1123
1124 int mlx4_cmd_init(struct mlx4_dev *dev);
1125 void mlx4_cmd_cleanup(struct mlx4_dev *dev);
1126 int mlx4_multi_func_init(struct mlx4_dev *dev);
1127 void mlx4_multi_func_cleanup(struct mlx4_dev *dev);
1128 void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param);
1129 int mlx4_cmd_use_events(struct mlx4_dev *dev);
1130 void mlx4_cmd_use_polling(struct mlx4_dev *dev);
1131
1132 int mlx4_comm_cmd(struct mlx4_dev *dev, u8 cmd, u16 param,
1133                   unsigned long timeout);
1134
1135 void mlx4_cq_completion(struct mlx4_dev *dev, u32 cqn);
1136 void mlx4_cq_event(struct mlx4_dev *dev, u32 cqn, int event_type);
1137
1138 void mlx4_qp_event(struct mlx4_dev *dev, u32 qpn, int event_type);
1139
1140 void mlx4_srq_event(struct mlx4_dev *dev, u32 srqn, int event_type);
1141
1142 void mlx4_handle_catas_err(struct mlx4_dev *dev);
1143
1144 int mlx4_SENSE_PORT(struct mlx4_dev *dev, int port,
1145                     enum mlx4_port_type *type);
1146 void mlx4_do_sense_ports(struct mlx4_dev *dev,
1147                          enum mlx4_port_type *stype,
1148                          enum mlx4_port_type *defaults);
1149 void mlx4_start_sense(struct mlx4_dev *dev);
1150 void mlx4_stop_sense(struct mlx4_dev *dev);
1151 void mlx4_sense_init(struct mlx4_dev *dev);
1152 int mlx4_check_port_params(struct mlx4_dev *dev,
1153                            enum mlx4_port_type *port_type);
1154 int mlx4_change_port_types(struct mlx4_dev *dev,
1155                            enum mlx4_port_type *port_types);
1156
1157 void mlx4_init_mac_table(struct mlx4_dev *dev, struct mlx4_mac_table *table);
1158 void mlx4_init_vlan_table(struct mlx4_dev *dev, struct mlx4_vlan_table *table);
1159 void mlx4_init_roce_gid_table(struct mlx4_dev *dev,
1160                               struct mlx4_roce_gid_table *table);
1161 void __mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, u16 vlan);
1162 int __mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index);
1163
1164 int mlx4_SET_PORT(struct mlx4_dev *dev, u8 port, int pkey_tbl_sz);
1165 /* resource tracker functions*/
1166 int mlx4_get_slave_from_resource_id(struct mlx4_dev *dev,
1167                                     enum mlx4_resource resource_type,
1168                                     u64 resource_id, int *slave);
1169 void mlx4_delete_all_resources_for_slave(struct mlx4_dev *dev, int slave_id);
1170 void mlx4_reset_roce_gids(struct mlx4_dev *dev, int slave);
1171 int mlx4_init_resource_tracker(struct mlx4_dev *dev);
1172
1173 void mlx4_free_resource_tracker(struct mlx4_dev *dev,
1174                                 enum mlx4_res_tracker_free_type type);
1175
1176 int mlx4_QUERY_FW_wrapper(struct mlx4_dev *dev, int slave,
1177                           struct mlx4_vhcr *vhcr,
1178                           struct mlx4_cmd_mailbox *inbox,
1179                           struct mlx4_cmd_mailbox *outbox,
1180                           struct mlx4_cmd_info *cmd);
1181 int mlx4_SET_PORT_wrapper(struct mlx4_dev *dev, int slave,
1182                           struct mlx4_vhcr *vhcr,
1183                           struct mlx4_cmd_mailbox *inbox,
1184                           struct mlx4_cmd_mailbox *outbox,
1185                           struct mlx4_cmd_info *cmd);
1186 int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave,
1187                            struct mlx4_vhcr *vhcr,
1188                            struct mlx4_cmd_mailbox *inbox,
1189                            struct mlx4_cmd_mailbox *outbox,
1190                            struct mlx4_cmd_info *cmd);
1191 int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave,
1192                             struct mlx4_vhcr *vhcr,
1193                             struct mlx4_cmd_mailbox *inbox,
1194                             struct mlx4_cmd_mailbox *outbox,
1195                             struct mlx4_cmd_info *cmd);
1196 int mlx4_QUERY_DEV_CAP_wrapper(struct mlx4_dev *dev, int slave,
1197                                struct mlx4_vhcr *vhcr,
1198                                struct mlx4_cmd_mailbox *inbox,
1199                                struct mlx4_cmd_mailbox *outbox,
1200                                struct mlx4_cmd_info *cmd);
1201 int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave,
1202                             struct mlx4_vhcr *vhcr,
1203                             struct mlx4_cmd_mailbox *inbox,
1204                             struct mlx4_cmd_mailbox *outbox,
1205                             struct mlx4_cmd_info *cmd);
1206 int mlx4_get_port_ib_caps(struct mlx4_dev *dev, u8 port, __be32 *caps);
1207
1208 int mlx4_get_slave_pkey_gid_tbl_len(struct mlx4_dev *dev, u8 port,
1209                                     int *gid_tbl_len, int *pkey_tbl_len);
1210
1211 int mlx4_QP_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
1212                            struct mlx4_vhcr *vhcr,
1213                            struct mlx4_cmd_mailbox *inbox,
1214                            struct mlx4_cmd_mailbox *outbox,
1215                            struct mlx4_cmd_info *cmd);
1216
1217 int mlx4_UPDATE_QP_wrapper(struct mlx4_dev *dev, int slave,
1218                            struct mlx4_vhcr *vhcr,
1219                            struct mlx4_cmd_mailbox *inbox,
1220                            struct mlx4_cmd_mailbox *outbox,
1221                            struct mlx4_cmd_info *cmd);
1222
1223 int mlx4_PROMISC_wrapper(struct mlx4_dev *dev, int slave,
1224                          struct mlx4_vhcr *vhcr,
1225                          struct mlx4_cmd_mailbox *inbox,
1226                          struct mlx4_cmd_mailbox *outbox,
1227                          struct mlx4_cmd_info *cmd);
1228 int mlx4_qp_detach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1229                           enum mlx4_protocol prot, enum mlx4_steer_type steer);
1230 int mlx4_qp_attach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1231                           int block_mcast_loopback, enum mlx4_protocol prot,
1232                           enum mlx4_steer_type steer);
1233 int mlx4_trans_to_dmfs_attach(struct mlx4_dev *dev, struct mlx4_qp *qp,
1234                               u8 gid[16], u8 port,
1235                               int block_mcast_loopback,
1236                               enum mlx4_protocol prot, u64 *reg_id);
1237 int mlx4_SET_MCAST_FLTR_wrapper(struct mlx4_dev *dev, int slave,
1238                                 struct mlx4_vhcr *vhcr,
1239                                 struct mlx4_cmd_mailbox *inbox,
1240                                 struct mlx4_cmd_mailbox *outbox,
1241                                 struct mlx4_cmd_info *cmd);
1242 int mlx4_SET_VLAN_FLTR_wrapper(struct mlx4_dev *dev, int slave,
1243                                struct mlx4_vhcr *vhcr,
1244                                struct mlx4_cmd_mailbox *inbox,
1245                                struct mlx4_cmd_mailbox *outbox,
1246                                struct mlx4_cmd_info *cmd);
1247 int mlx4_common_set_vlan_fltr(struct mlx4_dev *dev, int function,
1248                                      int port, void *buf);
1249 int mlx4_common_dump_eth_stats(struct mlx4_dev *dev, int slave, u32 in_mod,
1250                                 struct mlx4_cmd_mailbox *outbox);
1251 int mlx4_DUMP_ETH_STATS_wrapper(struct mlx4_dev *dev, int slave,
1252                                    struct mlx4_vhcr *vhcr,
1253                                    struct mlx4_cmd_mailbox *inbox,
1254                                    struct mlx4_cmd_mailbox *outbox,
1255                                 struct mlx4_cmd_info *cmd);
1256 int mlx4_PKEY_TABLE_wrapper(struct mlx4_dev *dev, int slave,
1257                             struct mlx4_vhcr *vhcr,
1258                             struct mlx4_cmd_mailbox *inbox,
1259                             struct mlx4_cmd_mailbox *outbox,
1260                             struct mlx4_cmd_info *cmd);
1261 int mlx4_QUERY_IF_STAT_wrapper(struct mlx4_dev *dev, int slave,
1262                                struct mlx4_vhcr *vhcr,
1263                                struct mlx4_cmd_mailbox *inbox,
1264                                struct mlx4_cmd_mailbox *outbox,
1265                                struct mlx4_cmd_info *cmd);
1266 int mlx4_QP_FLOW_STEERING_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
1267                                          struct mlx4_vhcr *vhcr,
1268                                          struct mlx4_cmd_mailbox *inbox,
1269                                          struct mlx4_cmd_mailbox *outbox,
1270                                          struct mlx4_cmd_info *cmd);
1271 int mlx4_QP_FLOW_STEERING_DETACH_wrapper(struct mlx4_dev *dev, int slave,
1272                                          struct mlx4_vhcr *vhcr,
1273                                          struct mlx4_cmd_mailbox *inbox,
1274                                          struct mlx4_cmd_mailbox *outbox,
1275                                          struct mlx4_cmd_info *cmd);
1276
1277 int mlx4_get_mgm_entry_size(struct mlx4_dev *dev);
1278 int mlx4_get_qp_per_mgm(struct mlx4_dev *dev);
1279
1280 static inline void set_param_l(u64 *arg, u32 val)
1281 {
1282         *arg = (*arg & 0xffffffff00000000ULL) | (u64) val;
1283 }
1284
1285 static inline void set_param_h(u64 *arg, u32 val)
1286 {
1287         *arg = (*arg & 0xffffffff) | ((u64) val << 32);
1288 }
1289
1290 static inline u32 get_param_l(u64 *arg)
1291 {
1292         return (u32) (*arg & 0xffffffff);
1293 }
1294
1295 static inline u32 get_param_h(u64 *arg)
1296 {
1297         return (u32)(*arg >> 32);
1298 }
1299
1300 static inline spinlock_t *mlx4_tlock(struct mlx4_dev *dev)
1301 {
1302         return &mlx4_priv(dev)->mfunc.master.res_tracker.lock;
1303 }
1304
1305 #define NOT_MASKED_PD_BITS 17
1306
1307 void mlx4_vf_immed_vlan_work_handler(struct work_struct *_work);
1308
1309 void mlx4_init_quotas(struct mlx4_dev *dev);
1310
1311 int mlx4_get_slave_num_gids(struct mlx4_dev *dev, int slave, int port);
1312 /* Returns the VF index of slave */
1313 int mlx4_get_vf_indx(struct mlx4_dev *dev, int slave);
1314 int mlx4_config_mad_demux(struct mlx4_dev *dev);
1315
1316 #endif /* MLX4_H */