drivers/net/ethernet/mellanox/mlx4/mlx4.h

   1 /*
   2  * Copyright (c) 2004, 2005 Topspin Communications.  All rights reserved.
   3  * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
   4  * Copyright (c) 2005, 2006, 2007 Cisco Systems.  All rights reserved.
   5  * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
   6  * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
   7  *
   8  * This software is available to you under a choice of one of two
   9  * licenses.  You may choose to be licensed under the terms of the GNU
  10  * General Public License (GPL) Version 2, available from the file
  11  * COPYING in the main directory of this source tree, or the
  12  * OpenIB.org BSD license below:
  13  *
  14  *     Redistribution and use in source and binary forms, with or
  15  *     without modification, are permitted provided that the following
  16  *     conditions are met:
  17  *
  18  *      - Redistributions of source code must retain the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer.
  21  *
  22  *      - Redistributions in binary form must reproduce the above
  23  *        copyright notice, this list of conditions and the following
  24  *        disclaimer in the documentation and/or other materials
  25  *        provided with the distribution.
  26  *
  27  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  28  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  29  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  30  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  31  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  32  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  33  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  34  * SOFTWARE.
  35  */
  36
  37 #ifndef MLX4_H
  38 #define MLX4_H
  39
  40 #include <linux/mutex.h>
  41 #include <linux/radix-tree.h>
  42 #include <linux/rbtree.h>
  43 #include <linux/timer.h>
  44 #include <linux/semaphore.h>
  45 #include <linux/workqueue.h>
  46 #include <linux/interrupt.h>
  47 #include <linux/spinlock.h>
  48
  49 #include <linux/mlx4/device.h>
  50 #include <linux/mlx4/driver.h>
  51 #include <linux/mlx4/doorbell.h>
  52 #include <linux/mlx4/cmd.h>
  53
  54 #define DRV_NAME        "mlx4_core"
  55 #define PFX             DRV_NAME ": "
  56 #define DRV_VERSION     "2.2-1"
  57 #define DRV_RELDATE     "Feb, 2014"
  58
  59 #define MLX4_FS_UDP_UC_EN               (1 << 1)
  60 #define MLX4_FS_TCP_UC_EN               (1 << 2)
  61 #define MLX4_FS_NUM_OF_L2_ADDR          8
  62 #define MLX4_FS_MGM_LOG_ENTRY_SIZE      7
  63 #define MLX4_FS_NUM_MCG                 (1 << 17)
  64
  65 #define INIT_HCA_TPT_MW_ENABLE          (1 << 7)
  66
  67 struct mlx4_set_port_prio2tc_context {
  68         u8 prio2tc[4];
  69 };
  70
  71 struct mlx4_port_scheduler_tc_cfg_be {
  72         __be16 pg;
  73         __be16 bw_precentage;
  74         __be16 max_bw_units; /* 3-100Mbps, 4-1Gbps, other values - reserved */
  75         __be16 max_bw_value;
  76 };
  77
  78 struct mlx4_set_port_scheduler_context {
  79         struct mlx4_port_scheduler_tc_cfg_be tc[MLX4_NUM_TC];
  80 };
  81
  82 enum {
  83         MLX4_HCR_BASE           = 0x80680,
  84         MLX4_HCR_SIZE           = 0x0001c,
  85         MLX4_CLR_INT_SIZE       = 0x00008,
  86         MLX4_SLAVE_COMM_BASE    = 0x0,
  87         MLX4_COMM_PAGESIZE      = 0x1000,
  88         MLX4_CLOCK_SIZE         = 0x00008,
  89         MLX4_COMM_CHAN_CAPS     = 0x8,
  90         MLX4_COMM_CHAN_FLAGS    = 0xc
  91 };
  92
  93 enum {
  94         MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE = 10,
  95         MLX4_MIN_MGM_LOG_ENTRY_SIZE = 7,
  96         MLX4_MAX_MGM_LOG_ENTRY_SIZE = 12,
  97         MLX4_MAX_QP_PER_MGM = 4 * ((1 << MLX4_MAX_MGM_LOG_ENTRY_SIZE) / 16 - 2),
  98         MLX4_MTT_ENTRY_PER_SEG  = 8,
  99 };
 100
 101 enum {
 102         MLX4_NUM_PDS            = 1 << 15
 103 };
 104
 105 enum {
 106         MLX4_CMPT_TYPE_QP       = 0,
 107         MLX4_CMPT_TYPE_SRQ      = 1,
 108         MLX4_CMPT_TYPE_CQ       = 2,
 109         MLX4_CMPT_TYPE_EQ       = 3,
 110         MLX4_CMPT_NUM_TYPE
 111 };
 112
 113 enum {
 114         MLX4_CMPT_SHIFT         = 24,
 115         MLX4_NUM_CMPTS          = MLX4_CMPT_NUM_TYPE << MLX4_CMPT_SHIFT
 116 };
 117
 118 enum mlx4_mpt_state {
 119         MLX4_MPT_DISABLED = 0,
 120         MLX4_MPT_EN_HW,
 121         MLX4_MPT_EN_SW
 122 };
 123
 124 #define MLX4_COMM_TIME          10000
 125 #define MLX4_COMM_OFFLINE_TIME_OUT 30000
 126 #define MLX4_COMM_CMD_NA_OP    0x0
 127
 128
 129 enum {
 130         MLX4_COMM_CMD_RESET,
 131         MLX4_COMM_CMD_VHCR0,
 132         MLX4_COMM_CMD_VHCR1,
 133         MLX4_COMM_CMD_VHCR2,
 134         MLX4_COMM_CMD_VHCR_EN,
 135         MLX4_COMM_CMD_VHCR_POST,
 136         MLX4_COMM_CMD_FLR = 254
 137 };
 138
 139 enum {
 140         MLX4_VF_SMI_DISABLED,
 141         MLX4_VF_SMI_ENABLED
 142 };
 143
 144 /*The flag indicates that the slave should delay the RESET cmd*/
 145 #define MLX4_DELAY_RESET_SLAVE 0xbbbbbbb
 146 /*indicates how many retries will be done if we are in the middle of FLR*/
 147 #define NUM_OF_RESET_RETRIES    10
 148 #define SLEEP_TIME_IN_RESET     (2 * 1000)
 149 enum mlx4_resource {
 150         RES_QP,
 151         RES_CQ,
 152         RES_SRQ,
 153         RES_XRCD,
 154         RES_MPT,
 155         RES_MTT,
 156         RES_MAC,
 157         RES_VLAN,
 158         RES_EQ,
 159         RES_COUNTER,
 160         RES_FS_RULE,
 161         MLX4_NUM_OF_RESOURCE_TYPE
 162 };
 163
 164 enum mlx4_alloc_mode {
 165         RES_OP_RESERVE,
 166         RES_OP_RESERVE_AND_MAP,
 167         RES_OP_MAP_ICM,
 168 };
 169
 170 enum mlx4_res_tracker_free_type {
 171         RES_TR_FREE_ALL,
 172         RES_TR_FREE_SLAVES_ONLY,
 173         RES_TR_FREE_STRUCTS_ONLY,
 174 };
 175
 176 /*
 177  *Virtual HCR structures.
 178  * mlx4_vhcr is the sw representation, in machine endianess
 179  *
 180  * mlx4_vhcr_cmd is the formalized structure, the one that is passed
 181  * to FW to go through communication channel.
 182  * It is big endian, and has the same structure as the physical HCR
 183  * used by command interface
 184  */
 185 struct mlx4_vhcr {
 186         u64     in_param;
 187         u64     out_param;
 188         u32     in_modifier;
 189         u32     errno;
 190         u16     op;
 191         u16     token;
 192         u8      op_modifier;
 193         u8      e_bit;
 194 };
 195
 196 struct mlx4_vhcr_cmd {
 197         __be64 in_param;
 198         __be32 in_modifier;
 199         __be64 out_param;
 200         __be16 token;
 201         u16 reserved;
 202         u8 status;
 203         u8 flags;
 204         __be16 opcode;
 205 };
 206
 207 struct mlx4_cmd_info {
 208         u16 opcode;
 209         bool has_inbox;
 210         bool has_outbox;
 211         bool out_is_imm;
 212         bool encode_slave_id;
 213         int (*verify)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr,
 214                       struct mlx4_cmd_mailbox *inbox);
 215         int (*wrapper)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr,
 216                        struct mlx4_cmd_mailbox *inbox,
 217                        struct mlx4_cmd_mailbox *outbox,
 218                        struct mlx4_cmd_info *cmd);
 219 };
 220
 221 #ifdef CONFIG_MLX4_DEBUG
 222 extern int mlx4_debug_level;
 223 #else /* CONFIG_MLX4_DEBUG */
 224 #define mlx4_debug_level        (0)
 225 #endif /* CONFIG_MLX4_DEBUG */
 226
 227 #define mlx4_dbg(mdev, format, ...)                                     \
 228 do {                                                                    \
 229         if (mlx4_debug_level)                                           \
 230                 dev_printk(KERN_DEBUG,                                  \
 231                            &(mdev)->persist->pdev->dev, format,         \
 232                            ##__VA_ARGS__);                              \
 233 } while (0)
 234
 235 #define mlx4_err(mdev, format, ...)                                     \
 236         dev_err(&(mdev)->persist->pdev->dev, format, ##__VA_ARGS__)
 237 #define mlx4_info(mdev, format, ...)                                    \
 238         dev_info(&(mdev)->persist->pdev->dev, format, ##__VA_ARGS__)
 239 #define mlx4_warn(mdev, format, ...)                                    \
 240         dev_warn(&(mdev)->persist->pdev->dev, format, ##__VA_ARGS__)
 241
 242 extern int mlx4_log_num_mgm_entry_size;
 243 extern int log_mtts_per_seg;
 244 extern int mlx4_internal_err_reset;
 245
 246 #define MLX4_MAX_NUM_SLAVES     (MLX4_MAX_NUM_PF + MLX4_MAX_NUM_VF)
 247 #define ALL_SLAVES 0xff
 248
 249 struct mlx4_bitmap {
 250         u32                     last;
 251         u32                     top;
 252         u32                     max;
 253         u32                     reserved_top;
 254         u32                     mask;
 255         u32                     avail;
 256         u32                     effective_len;
 257         spinlock_t              lock;
 258         unsigned long          *table;
 259 };
 260
 261 struct mlx4_buddy {
 262         unsigned long         **bits;
 263         unsigned int           *num_free;
 264         u32                     max_order;
 265         spinlock_t              lock;
 266 };
 267
 268 struct mlx4_icm;
 269
 270 struct mlx4_icm_table {
 271         u64                     virt;
 272         int                     num_icm;
 273         u32                     num_obj;
 274         int                     obj_size;
 275         int                     lowmem;
 276         int                     coherent;
 277         struct mutex            mutex;
 278         struct mlx4_icm       **icm;
 279 };
 280
 281 #define MLX4_MPT_FLAG_SW_OWNS       (0xfUL << 28)
 282 #define MLX4_MPT_FLAG_FREE          (0x3UL << 28)
 283 #define MLX4_MPT_FLAG_MIO           (1 << 17)
 284 #define MLX4_MPT_FLAG_BIND_ENABLE   (1 << 15)
 285 #define MLX4_MPT_FLAG_PHYSICAL      (1 <<  9)
 286 #define MLX4_MPT_FLAG_REGION        (1 <<  8)
 287
 288 #define MLX4_MPT_PD_MASK            (0x1FFFFUL)
 289 #define MLX4_MPT_PD_VF_MASK         (0xFE0000UL)
 290 #define MLX4_MPT_PD_FLAG_FAST_REG   (1 << 27)
 291 #define MLX4_MPT_PD_FLAG_RAE        (1 << 28)
 292 #define MLX4_MPT_PD_FLAG_EN_INV     (3 << 24)
 293
 294 #define MLX4_MPT_QP_FLAG_BOUND_QP   (1 << 7)
 295
 296 #define MLX4_MPT_STATUS_SW              0xF0
 297 #define MLX4_MPT_STATUS_HW              0x00
 298
 299 #define MLX4_CQE_SIZE_MASK_STRIDE       0x3
 300 #define MLX4_EQE_SIZE_MASK_STRIDE       0x30
 301
 302 /*
 303  * Must be packed because mtt_seg is 64 bits but only aligned to 32 bits.
 304  */
 305 struct mlx4_mpt_entry {
 306         __be32 flags;
 307         __be32 qpn;
 308         __be32 key;
 309         __be32 pd_flags;
 310         __be64 start;
 311         __be64 length;
 312         __be32 lkey;
 313         __be32 win_cnt;
 314         u8      reserved1[3];
 315         u8      mtt_rep;
 316         __be64 mtt_addr;
 317         __be32 mtt_sz;
 318         __be32 entity_size;
 319         __be32 first_byte_offset;
 320 } __packed;
 321
 322 /*
 323  * Must be packed because start is 64 bits but only aligned to 32 bits.
 324  */
 325 struct mlx4_eq_context {
 326         __be32                  flags;
 327         u16                     reserved1[3];
 328         __be16                  page_offset;
 329         u8                      log_eq_size;
 330         u8                      reserved2[4];
 331         u8                      eq_period;
 332         u8                      reserved3;
 333         u8                      eq_max_count;
 334         u8                      reserved4[3];
 335         u8                      intr;
 336         u8                      log_page_size;
 337         u8                      reserved5[2];
 338         u8                      mtt_base_addr_h;
 339         __be32                  mtt_base_addr_l;
 340         u32                     reserved6[2];
 341         __be32                  consumer_index;
 342         __be32                  producer_index;
 343         u32                     reserved7[4];
 344 };
 345
 346 struct mlx4_cq_context {
 347         __be32                  flags;
 348         u16                     reserved1[3];
 349         __be16                  page_offset;
 350         __be32                  logsize_usrpage;
 351         __be16                  cq_period;
 352         __be16                  cq_max_count;
 353         u8                      reserved2[3];
 354         u8                      comp_eqn;
 355         u8                      log_page_size;
 356         u8                      reserved3[2];
 357         u8                      mtt_base_addr_h;
 358         __be32                  mtt_base_addr_l;
 359         __be32                  last_notified_index;
 360         __be32                  solicit_producer_index;
 361         __be32                  consumer_index;
 362         __be32                  producer_index;
 363         u32                     reserved4[2];
 364         __be64                  db_rec_addr;
 365 };
 366
 367 struct mlx4_srq_context {
 368         __be32                  state_logsize_srqn;
 369         u8                      logstride;
 370         u8                      reserved1;
 371         __be16                  xrcd;
 372         __be32                  pg_offset_cqn;
 373         u32                     reserved2;
 374         u8                      log_page_size;
 375         u8                      reserved3[2];
 376         u8                      mtt_base_addr_h;
 377         __be32                  mtt_base_addr_l;
 378         __be32                  pd;
 379         __be16                  limit_watermark;
 380         __be16                  wqe_cnt;
 381         u16                     reserved4;
 382         __be16                  wqe_counter;
 383         u32                     reserved5;
 384         __be64                  db_rec_addr;
 385 };
 386
 387 struct mlx4_eq_tasklet {
 388         struct list_head list;
 389         struct list_head process_list;
 390         struct tasklet_struct task;
 391         /* lock on completion tasklet list */
 392         spinlock_t lock;
 393 };
 394
 395 struct mlx4_eq {
 396         struct mlx4_dev        *dev;
 397         void __iomem           *doorbell;
 398         int                     eqn;
 399         u32                     cons_index;
 400         u16                     irq;
 401         u16                     have_irq;
 402         int                     nent;
 403         struct mlx4_buf_list   *page_list;
 404         struct mlx4_mtt         mtt;
 405         struct mlx4_eq_tasklet  tasklet_ctx;
 406 };
 407
 408 struct mlx4_slave_eqe {
 409         u8 type;
 410         u8 port;
 411         u32 param;
 412 };
 413
 414 struct mlx4_slave_event_eq_info {
 415         int eqn;
 416         u16 token;
 417 };
 418
 419 struct mlx4_profile {
 420         int                     num_qp;
 421         int                     rdmarc_per_qp;
 422         int                     num_srq;
 423         int                     num_cq;
 424         int                     num_mcg;
 425         int                     num_mpt;
 426         unsigned                num_mtt;
 427 };
 428
 429 struct mlx4_fw {
 430         u64                     clr_int_base;
 431         u64                     catas_offset;
 432         u64                     comm_base;
 433         u64                     clock_offset;
 434         struct mlx4_icm        *fw_icm;
 435         struct mlx4_icm        *aux_icm;
 436         u32                     catas_size;
 437         u16                     fw_pages;
 438         u8                      clr_int_bar;
 439         u8                      catas_bar;
 440         u8                      comm_bar;
 441         u8                      clock_bar;
 442 };
 443
 444 struct mlx4_comm {
 445         u32                     slave_write;
 446         u32                     slave_read;
 447 };
 448
 449 enum {
 450         MLX4_MCAST_CONFIG       = 0,
 451         MLX4_MCAST_DISABLE      = 1,
 452         MLX4_MCAST_ENABLE       = 2,
 453 };
 454
 455 #define VLAN_FLTR_SIZE  128
 456
 457 struct mlx4_vlan_fltr {
 458         __be32 entry[VLAN_FLTR_SIZE];
 459 };
 460
 461 struct mlx4_mcast_entry {
 462         struct list_head list;
 463         u64 addr;
 464 };
 465
 466 struct mlx4_promisc_qp {
 467         struct list_head list;
 468         u32 qpn;
 469 };
 470
 471 struct mlx4_steer_index {
 472         struct list_head list;
 473         unsigned int index;
 474         struct list_head duplicates;
 475 };
 476
 477 #define MLX4_EVENT_TYPES_NUM 64
 478
 479 struct mlx4_slave_state {
 480         u8 comm_toggle;
 481         u8 last_cmd;
 482         u8 init_port_mask;
 483         bool active;
 484         bool old_vlan_api;
 485         u8 function;
 486         dma_addr_t vhcr_dma;
 487         u16 mtu[MLX4_MAX_PORTS + 1];
 488         __be32 ib_cap_mask[MLX4_MAX_PORTS + 1];
 489         struct mlx4_slave_eqe eq[MLX4_MFUNC_MAX_EQES];
 490         struct list_head mcast_filters[MLX4_MAX_PORTS + 1];
 491         struct mlx4_vlan_fltr *vlan_filter[MLX4_MAX_PORTS + 1];
 492         /* event type to eq number lookup */
 493         struct mlx4_slave_event_eq_info event_eq[MLX4_EVENT_TYPES_NUM];
 494         u16 eq_pi;
 495         u16 eq_ci;
 496         spinlock_t lock;
 497         /*initialized via the kzalloc*/
 498         u8 is_slave_going_down;
 499         u32 cookie;
 500         enum slave_port_state port_state[MLX4_MAX_PORTS + 1];
 501 };
 502
 503 #define MLX4_VGT 4095
 504 #define NO_INDX  (-1)
 505
 506 struct mlx4_vport_state {
 507         u64 mac;
 508         u16 default_vlan;
 509         u8  default_qos;
 510         u32 tx_rate;
 511         bool spoofchk;
 512         u32 link_state;
 513 };
 514
 515 struct mlx4_vf_admin_state {
 516         struct mlx4_vport_state vport[MLX4_MAX_PORTS + 1];
 517         u8 enable_smi[MLX4_MAX_PORTS + 1];
 518 };
 519
 520 struct mlx4_vport_oper_state {
 521         struct mlx4_vport_state state;
 522         int mac_idx;
 523         int vlan_idx;
 524 };
 525
 526 struct mlx4_vf_oper_state {
 527         struct mlx4_vport_oper_state vport[MLX4_MAX_PORTS + 1];
 528         u8 smi_enabled[MLX4_MAX_PORTS + 1];
 529 };
 530
 531 struct slave_list {
 532         struct mutex mutex;
 533         struct list_head res_list[MLX4_NUM_OF_RESOURCE_TYPE];
 534 };
 535
 536 struct resource_allocator {
 537         spinlock_t alloc_lock; /* protect quotas */
 538         union {
 539                 int res_reserved;
 540                 int res_port_rsvd[MLX4_MAX_PORTS];
 541         };
 542         union {
 543                 int res_free;
 544                 int res_port_free[MLX4_MAX_PORTS];
 545         };
 546         int *quota;
 547         int *allocated;
 548         int *guaranteed;
 549 };
 550
 551 struct mlx4_resource_tracker {
 552         spinlock_t lock;
 553         /* tree for each resources */
 554         struct rb_root res_tree[MLX4_NUM_OF_RESOURCE_TYPE];
 555         /* num_of_slave's lists, one per slave */
 556         struct slave_list *slave_list;
 557         struct resource_allocator res_alloc[MLX4_NUM_OF_RESOURCE_TYPE];
 558 };
 559
 560 #define SLAVE_EVENT_EQ_SIZE     128
 561 struct mlx4_slave_event_eq {
 562         u32 eqn;
 563         u32 cons;
 564         u32 prod;
 565         spinlock_t event_lock;
 566         struct mlx4_eqe event_eqe[SLAVE_EVENT_EQ_SIZE];
 567 };
 568
 569 struct mlx4_master_qp0_state {
 570         int proxy_qp0_active;
 571         int qp0_active;
 572         int port_active;
 573 };
 574
 575 struct mlx4_mfunc_master_ctx {
 576         struct mlx4_slave_state *slave_state;
 577         struct mlx4_vf_admin_state *vf_admin;
 578         struct mlx4_vf_oper_state *vf_oper;
 579         struct mlx4_master_qp0_state qp0_state[MLX4_MAX_PORTS + 1];
 580         int                     init_port_ref[MLX4_MAX_PORTS + 1];
 581         u16                     max_mtu[MLX4_MAX_PORTS + 1];
 582         int                     disable_mcast_ref[MLX4_MAX_PORTS + 1];
 583         struct mlx4_resource_tracker res_tracker;
 584         struct workqueue_struct *comm_wq;
 585         struct work_struct      comm_work;
 586         struct work_struct      slave_event_work;
 587         struct work_struct      slave_flr_event_work;
 588         spinlock_t              slave_state_lock;
 589         __be32                  comm_arm_bit_vector[4];
 590         struct mlx4_eqe         cmd_eqe;
 591         struct mlx4_slave_event_eq slave_eq;
 592         struct mutex            gen_eqe_mutex[MLX4_MFUNC_MAX];
 593 };
 594
 595 struct mlx4_mfunc {
 596         struct mlx4_comm __iomem       *comm;
 597         struct mlx4_vhcr_cmd           *vhcr;
 598         dma_addr_t                      vhcr_dma;
 599
 600         struct mlx4_mfunc_master_ctx    master;
 601 };
 602
 603 #define MGM_QPN_MASK       0x00FFFFFF
 604 #define MGM_BLCK_LB_BIT    30
 605
 606 struct mlx4_mgm {
 607         __be32                  next_gid_index;
 608         __be32                  members_count;
 609         u32                     reserved[2];
 610         u8                      gid[16];
 611         __be32                  qp[MLX4_MAX_QP_PER_MGM];
 612 };
 613
 614 struct mlx4_cmd {
 615         struct pci_pool        *pool;
 616         void __iomem           *hcr;
 617         struct mutex            slave_cmd_mutex;
 618         struct semaphore        poll_sem;
 619         struct semaphore        event_sem;
 620         int                     max_cmds;
 621         spinlock_t              context_lock;
 622         int                     free_head;
 623         struct mlx4_cmd_context *context;
 624         u16                     token_mask;
 625         u8                      use_events;
 626         u8                      toggle;
 627         u8                      comm_toggle;
 628         u8                      initialized;
 629 };
 630
 631 enum {
 632         MLX4_VF_IMMED_VLAN_FLAG_VLAN = 1 << 0,
 633         MLX4_VF_IMMED_VLAN_FLAG_QOS = 1 << 1,
 634         MLX4_VF_IMMED_VLAN_FLAG_LINK_DISABLE = 1 << 2,
 635 };
 636 struct mlx4_vf_immed_vlan_work {
 637         struct work_struct      work;
 638         struct mlx4_priv        *priv;
 639         int                     flags;
 640         int                     slave;
 641         int                     vlan_ix;
 642         int                     orig_vlan_ix;
 643         u8                      port;
 644         u8                      qos;
 645         u16                     vlan_id;
 646         u16                     orig_vlan_id;
 647 };
 648
 649
 650 struct mlx4_uar_table {
 651         struct mlx4_bitmap      bitmap;
 652 };
 653
 654 struct mlx4_mr_table {
 655         struct mlx4_bitmap      mpt_bitmap;
 656         struct mlx4_buddy       mtt_buddy;
 657         u64                     mtt_base;
 658         u64                     mpt_base;
 659         struct mlx4_icm_table   mtt_table;
 660         struct mlx4_icm_table   dmpt_table;
 661 };
 662
 663 struct mlx4_cq_table {
 664         struct mlx4_bitmap      bitmap;
 665         spinlock_t              lock;
 666         struct radix_tree_root  tree;
 667         struct mlx4_icm_table   table;
 668         struct mlx4_icm_table   cmpt_table;
 669 };
 670
 671 struct mlx4_eq_table {
 672         struct mlx4_bitmap      bitmap;
 673         char                   *irq_names;
 674         void __iomem           *clr_int;
 675         void __iomem          **uar_map;
 676         u32                     clr_mask;
 677         struct mlx4_eq         *eq;
 678         struct mlx4_icm_table   table;
 679         struct mlx4_icm_table   cmpt_table;
 680         int                     have_irq;
 681         u8                      inta_pin;
 682 };
 683
 684 struct mlx4_srq_table {
 685         struct mlx4_bitmap      bitmap;
 686         spinlock_t              lock;
 687         struct radix_tree_root  tree;
 688         struct mlx4_icm_table   table;
 689         struct mlx4_icm_table   cmpt_table;
 690 };
 691
 692 enum mlx4_qp_table_zones {
 693         MLX4_QP_TABLE_ZONE_GENERAL,
 694         MLX4_QP_TABLE_ZONE_RSS,
 695         MLX4_QP_TABLE_ZONE_RAW_ETH,
 696         MLX4_QP_TABLE_ZONE_NUM
 697 };
 698
 699 struct mlx4_qp_table {
 700         struct mlx4_bitmap      *bitmap_gen;
 701         struct mlx4_zone_allocator *zones;
 702         u32                     zones_uids[MLX4_QP_TABLE_ZONE_NUM];
 703         u32                     rdmarc_base;
 704         int                     rdmarc_shift;
 705         spinlock_t              lock;
 706         struct mlx4_icm_table   qp_table;
 707         struct mlx4_icm_table   auxc_table;
 708         struct mlx4_icm_table   altc_table;
 709         struct mlx4_icm_table   rdmarc_table;
 710         struct mlx4_icm_table   cmpt_table;
 711 };
 712
 713 struct mlx4_mcg_table {
 714         struct mutex            mutex;
 715         struct mlx4_bitmap      bitmap;
 716         struct mlx4_icm_table   table;
 717 };
 718
 719 struct mlx4_catas_err {
 720         u32 __iomem            *map;
 721         struct timer_list       timer;
 722         struct list_head        list;
 723 };
 724
 725 #define MLX4_MAX_MAC_NUM        128
 726 #define MLX4_MAC_TABLE_SIZE     (MLX4_MAX_MAC_NUM << 3)
 727
 728 struct mlx4_mac_table {
 729         __be64                  entries[MLX4_MAX_MAC_NUM];
 730         int                     refs[MLX4_MAX_MAC_NUM];
 731         struct mutex            mutex;
 732         int                     total;
 733         int                     max;
 734 };
 735
 736 #define MLX4_ROCE_GID_ENTRY_SIZE        16
 737
 738 struct mlx4_roce_gid_entry {
 739         u8 raw[MLX4_ROCE_GID_ENTRY_SIZE];
 740 };
 741
 742 struct mlx4_roce_gid_table {
 743         struct mlx4_roce_gid_entry      roce_gids[MLX4_ROCE_MAX_GIDS];
 744         struct mutex                    mutex;
 745 };
 746
 747 #define MLX4_MAX_VLAN_NUM       128
 748 #define MLX4_VLAN_TABLE_SIZE    (MLX4_MAX_VLAN_NUM << 2)
 749
 750 struct mlx4_vlan_table {
 751         __be32                  entries[MLX4_MAX_VLAN_NUM];
 752         int                     refs[MLX4_MAX_VLAN_NUM];
 753         struct mutex            mutex;
 754         int                     total;
 755         int                     max;
 756 };
 757
 758 #define SET_PORT_GEN_ALL_VALID          0x7
 759 #define SET_PORT_PROMISC_SHIFT          31
 760 #define SET_PORT_MC_PROMISC_SHIFT       30
 761
 762 enum {
 763         MCAST_DIRECT_ONLY       = 0,
 764         MCAST_DIRECT            = 1,
 765         MCAST_DEFAULT           = 2
 766 };
 767
 768
 769 struct mlx4_set_port_general_context {
 770         u8 reserved[3];
 771         u8 flags;
 772         u16 reserved2;
 773         __be16 mtu;
 774         u8 pptx;
 775         u8 pfctx;
 776         u16 reserved3;
 777         u8 pprx;
 778         u8 pfcrx;
 779         u16 reserved4;
 780 };
 781
 782 struct mlx4_set_port_rqp_calc_context {
 783         __be32 base_qpn;
 784         u8 rererved;
 785         u8 n_mac;
 786         u8 n_vlan;
 787         u8 n_prio;
 788         u8 reserved2[3];
 789         u8 mac_miss;
 790         u8 intra_no_vlan;
 791         u8 no_vlan;
 792         u8 intra_vlan_miss;
 793         u8 vlan_miss;
 794         u8 reserved3[3];
 795         u8 no_vlan_prio;
 796         __be32 promisc;
 797         __be32 mcast;
 798 };
 799
 800 struct mlx4_port_info {
 801         struct mlx4_dev        *dev;
 802         int                     port;
 803         char                    dev_name[16];
 804         struct device_attribute port_attr;
 805         enum mlx4_port_type     tmp_type;
 806         char                    dev_mtu_name[16];
 807         struct device_attribute port_mtu_attr;
 808         struct mlx4_mac_table   mac_table;
 809         struct mlx4_vlan_table  vlan_table;
 810         struct mlx4_roce_gid_table gid_table;
 811         int                     base_qpn;
 812 };
 813
 814 struct mlx4_sense {
 815         struct mlx4_dev         *dev;
 816         u8                      do_sense_port[MLX4_MAX_PORTS + 1];
 817         u8                      sense_allowed[MLX4_MAX_PORTS + 1];
 818         struct delayed_work     sense_poll;
 819 };
 820
 821 struct mlx4_msix_ctl {
 822         u64             pool_bm;
 823         struct mutex    pool_lock;
 824 };
 825
 826 struct mlx4_steer {
 827         struct list_head promisc_qps[MLX4_NUM_STEERS];
 828         struct list_head steer_entries[MLX4_NUM_STEERS];
 829 };
 830
 831 enum {
 832         MLX4_PCI_DEV_IS_VF              = 1 << 0,
 833         MLX4_PCI_DEV_FORCE_SENSE_PORT   = 1 << 1,
 834 };
 835
 836 enum {
 837         MLX4_NO_RR      = 0,
 838         MLX4_USE_RR     = 1,
 839 };
 840
 841 struct mlx4_priv {
 842         struct mlx4_dev         dev;
 843
 844         struct list_head        dev_list;
 845         struct list_head        ctx_list;
 846         spinlock_t              ctx_lock;
 847
 848         int                     pci_dev_data;
 849         int                     removed;
 850
 851         struct list_head        pgdir_list;
 852         struct mutex            pgdir_mutex;
 853
 854         struct mlx4_fw          fw;
 855         struct mlx4_cmd         cmd;
 856         struct mlx4_mfunc       mfunc;
 857
 858         struct mlx4_bitmap      pd_bitmap;
 859         struct mlx4_bitmap      xrcd_bitmap;
 860         struct mlx4_uar_table   uar_table;
 861         struct mlx4_mr_table    mr_table;
 862         struct mlx4_cq_table    cq_table;
 863         struct mlx4_eq_table    eq_table;
 864         struct mlx4_srq_table   srq_table;
 865         struct mlx4_qp_table    qp_table;
 866         struct mlx4_mcg_table   mcg_table;
 867         struct mlx4_bitmap      counters_bitmap;
 868
 869         struct mlx4_catas_err   catas_err;
 870
 871         void __iomem           *clr_base;
 872
 873         struct mlx4_uar         driver_uar;
 874         void __iomem           *kar;
 875         struct mlx4_port_info   port[MLX4_MAX_PORTS + 1];
 876         struct mlx4_sense       sense;
 877         struct mutex            port_mutex;
 878         struct mlx4_msix_ctl    msix_ctl;
 879         struct mlx4_steer       *steer;
 880         struct list_head        bf_list;
 881         struct mutex            bf_mutex;
 882         struct io_mapping       *bf_mapping;
 883         void __iomem            *clock_mapping;
 884         int                     reserved_mtts;
 885         int                     fs_hash_mode;
 886         u8 virt2phys_pkey[MLX4_MFUNC_MAX][MLX4_MAX_PORTS][MLX4_MAX_PORT_PKEYS];
 887         __be64                  slave_node_guids[MLX4_MFUNC_MAX];
 888
 889         atomic_t                opreq_count;
 890         struct work_struct      opreq_task;
 891 };
 892
 893 static inline struct mlx4_priv *mlx4_priv(struct mlx4_dev *dev)
 894 {
 895         return container_of(dev, struct mlx4_priv, dev);
 896 }
 897
 898 #define MLX4_SENSE_RANGE        (HZ * 3)
 899
 900 extern struct workqueue_struct *mlx4_wq;
 901
 902 u32 mlx4_bitmap_alloc(struct mlx4_bitmap *bitmap);
 903 void mlx4_bitmap_free(struct mlx4_bitmap *bitmap, u32 obj, int use_rr);
 904 u32 mlx4_bitmap_alloc_range(struct mlx4_bitmap *bitmap, int cnt,
 905                             int align, u32 skip_mask);
 906 void mlx4_bitmap_free_range(struct mlx4_bitmap *bitmap, u32 obj, int cnt,
 907                             int use_rr);
 908 u32 mlx4_bitmap_avail(struct mlx4_bitmap *bitmap);
 909 int mlx4_bitmap_init(struct mlx4_bitmap *bitmap, u32 num, u32 mask,
 910                      u32 reserved_bot, u32 resetrved_top);
 911 void mlx4_bitmap_cleanup(struct mlx4_bitmap *bitmap);
 912
 913 int mlx4_reset(struct mlx4_dev *dev);
 914
 915 int mlx4_alloc_eq_table(struct mlx4_dev *dev);
 916 void mlx4_free_eq_table(struct mlx4_dev *dev);
 917
 918 int mlx4_init_pd_table(struct mlx4_dev *dev);
 919 int mlx4_init_xrcd_table(struct mlx4_dev *dev);
 920 int mlx4_init_uar_table(struct mlx4_dev *dev);
 921 int mlx4_init_mr_table(struct mlx4_dev *dev);
 922 int mlx4_init_eq_table(struct mlx4_dev *dev);
 923 int mlx4_init_cq_table(struct mlx4_dev *dev);
 924 int mlx4_init_qp_table(struct mlx4_dev *dev);
 925 int mlx4_init_srq_table(struct mlx4_dev *dev);
 926 int mlx4_init_mcg_table(struct mlx4_dev *dev);
 927
 928 void mlx4_cleanup_pd_table(struct mlx4_dev *dev);
 929 void mlx4_cleanup_xrcd_table(struct mlx4_dev *dev);
 930 void mlx4_cleanup_uar_table(struct mlx4_dev *dev);
 931 void mlx4_cleanup_mr_table(struct mlx4_dev *dev);
 932 void mlx4_cleanup_eq_table(struct mlx4_dev *dev);
 933 void mlx4_cleanup_cq_table(struct mlx4_dev *dev);
 934 void mlx4_cleanup_qp_table(struct mlx4_dev *dev);
 935 void mlx4_cleanup_srq_table(struct mlx4_dev *dev);
 936 void mlx4_cleanup_mcg_table(struct mlx4_dev *dev);
 937 int __mlx4_qp_alloc_icm(struct mlx4_dev *dev, int qpn, gfp_t gfp);
 938 void __mlx4_qp_free_icm(struct mlx4_dev *dev, int qpn);
 939 int __mlx4_cq_alloc_icm(struct mlx4_dev *dev, int *cqn);
 940 void __mlx4_cq_free_icm(struct mlx4_dev *dev, int cqn);
 941 int __mlx4_srq_alloc_icm(struct mlx4_dev *dev, int *srqn);
 942 void __mlx4_srq_free_icm(struct mlx4_dev *dev, int srqn);
 943 int __mlx4_mpt_reserve(struct mlx4_dev *dev);
 944 void __mlx4_mpt_release(struct mlx4_dev *dev, u32 index);
 945 int __mlx4_mpt_alloc_icm(struct mlx4_dev *dev, u32 index, gfp_t gfp);
 946 void __mlx4_mpt_free_icm(struct mlx4_dev *dev, u32 index);
 947 u32 __mlx4_alloc_mtt_range(struct mlx4_dev *dev, int order);
 948 void __mlx4_free_mtt_range(struct mlx4_dev *dev, u32 first_seg, int order);
 949
 950 int mlx4_WRITE_MTT_wrapper(struct mlx4_dev *dev, int slave,
 951                            struct mlx4_vhcr *vhcr,
 952                            struct mlx4_cmd_mailbox *inbox,
 953                            struct mlx4_cmd_mailbox *outbox,
 954                            struct mlx4_cmd_info *cmd);
 955 int mlx4_SYNC_TPT_wrapper(struct mlx4_dev *dev, int slave,
 956                            struct mlx4_vhcr *vhcr,
 957                            struct mlx4_cmd_mailbox *inbox,
 958                            struct mlx4_cmd_mailbox *outbox,
 959                            struct mlx4_cmd_info *cmd);
 960 int mlx4_SW2HW_MPT_wrapper(struct mlx4_dev *dev, int slave,
 961                            struct mlx4_vhcr *vhcr,
 962                            struct mlx4_cmd_mailbox *inbox,
 963                            struct mlx4_cmd_mailbox *outbox,
 964                            struct mlx4_cmd_info *cmd);
 965 int mlx4_HW2SW_MPT_wrapper(struct mlx4_dev *dev, int slave,
 966                            struct mlx4_vhcr *vhcr,
 967                            struct mlx4_cmd_mailbox *inbox,
 968                            struct mlx4_cmd_mailbox *outbox,
 969                            struct mlx4_cmd_info *cmd);
 970 int mlx4_QUERY_MPT_wrapper(struct mlx4_dev *dev, int slave,
 971                            struct mlx4_vhcr *vhcr,
 972                            struct mlx4_cmd_mailbox *inbox,
 973                            struct mlx4_cmd_mailbox *outbox,
 974                            struct mlx4_cmd_info *cmd);
 975 int mlx4_SW2HW_EQ_wrapper(struct mlx4_dev *dev, int slave,
 976                           struct mlx4_vhcr *vhcr,
 977                           struct mlx4_cmd_mailbox *inbox,
 978                           struct mlx4_cmd_mailbox *outbox,
 979                           struct mlx4_cmd_info *cmd);
 980 int mlx4_CONFIG_DEV_wrapper(struct mlx4_dev *dev, int slave,
 981                             struct mlx4_vhcr *vhcr,
 982                             struct mlx4_cmd_mailbox *inbox,
 983                             struct mlx4_cmd_mailbox *outbox,
 984                             struct mlx4_cmd_info *cmd);
 985 int mlx4_DMA_wrapper(struct mlx4_dev *dev, int slave,
 986                      struct mlx4_vhcr *vhcr,
 987                      struct mlx4_cmd_mailbox *inbox,
 988                      struct mlx4_cmd_mailbox *outbox,
 989                      struct mlx4_cmd_info *cmd);
 990 int __mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align,
 991                             int *base, u8 flags);
 992 void __mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt);
 993 int __mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac);
 994 void __mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac);
 995 int __mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
 996                      int start_index, int npages, u64 *page_list);
 997 int __mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx);
 998 void __mlx4_counter_free(struct mlx4_dev *dev, u32 idx);
 999 int __mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn);
1000 void __mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn);
1001
1002 void mlx4_start_catas_poll(struct mlx4_dev *dev);
1003 void mlx4_stop_catas_poll(struct mlx4_dev *dev);
1004 int mlx4_catas_init(struct mlx4_dev *dev);
1005 void mlx4_catas_end(struct mlx4_dev *dev);
1006 int mlx4_restart_one(struct pci_dev *pdev);
1007 int mlx4_register_device(struct mlx4_dev *dev);
1008 void mlx4_unregister_device(struct mlx4_dev *dev);
1009 void mlx4_dispatch_event(struct mlx4_dev *dev, enum mlx4_dev_event type,
1010                          unsigned long param);
1011
1012 struct mlx4_dev_cap;
1013 struct mlx4_init_hca_param;
1014
1015 u64 mlx4_make_profile(struct mlx4_dev *dev,
1016                       struct mlx4_profile *request,
1017                       struct mlx4_dev_cap *dev_cap,
1018                       struct mlx4_init_hca_param *init_hca);
1019 void mlx4_master_comm_channel(struct work_struct *work);
1020 void mlx4_gen_slave_eqe(struct work_struct *work);
1021 void mlx4_master_handle_slave_flr(struct work_struct *work);
1022
1023 int mlx4_ALLOC_RES_wrapper(struct mlx4_dev *dev, int slave,
1024                            struct mlx4_vhcr *vhcr,
1025                            struct mlx4_cmd_mailbox *inbox,
1026                            struct mlx4_cmd_mailbox *outbox,
1027                            struct mlx4_cmd_info *cmd);
1028 int mlx4_FREE_RES_wrapper(struct mlx4_dev *dev, int slave,
1029                           struct mlx4_vhcr *vhcr,
1030                           struct mlx4_cmd_mailbox *inbox,
1031                           struct mlx4_cmd_mailbox *outbox,
1032                           struct mlx4_cmd_info *cmd);
1033 int mlx4_MAP_EQ_wrapper(struct mlx4_dev *dev, int slave,
1034                         struct mlx4_vhcr *vhcr, struct mlx4_cmd_mailbox *inbox,
1035                         struct mlx4_cmd_mailbox *outbox,
1036                         struct mlx4_cmd_info *cmd);
1037 int mlx4_COMM_INT_wrapper(struct mlx4_dev *dev, int slave,
1038                           struct mlx4_vhcr *vhcr,
1039                           struct mlx4_cmd_mailbox *inbox,
1040                           struct mlx4_cmd_mailbox *outbox,
1041                           struct mlx4_cmd_info *cmd);
1042 int mlx4_HW2SW_EQ_wrapper(struct mlx4_dev *dev, int slave,
1043                             struct mlx4_vhcr *vhcr,
1044                             struct mlx4_cmd_mailbox *inbox,
1045                             struct mlx4_cmd_mailbox *outbox,
1046                           struct mlx4_cmd_info *cmd);
1047 int mlx4_QUERY_EQ_wrapper(struct mlx4_dev *dev, int slave,
1048                           struct mlx4_vhcr *vhcr,
1049                           struct mlx4_cmd_mailbox *inbox,
1050                           struct mlx4_cmd_mailbox *outbox,
1051                           struct mlx4_cmd_info *cmd);
1052 int mlx4_SW2HW_CQ_wrapper(struct mlx4_dev *dev, int slave,
1053                           struct mlx4_vhcr *vhcr,
1054                           struct mlx4_cmd_mailbox *inbox,
1055                           struct mlx4_cmd_mailbox *outbox,
1056                           struct mlx4_cmd_info *cmd);
1057 int mlx4_HW2SW_CQ_wrapper(struct mlx4_dev *dev, int slave,
1058                           struct mlx4_vhcr *vhcr,
1059                           struct mlx4_cmd_mailbox *inbox,
1060                           struct mlx4_cmd_mailbox *outbox,
1061                           struct mlx4_cmd_info *cmd);
1062 int mlx4_QUERY_CQ_wrapper(struct mlx4_dev *dev, int slave,
1063                           struct mlx4_vhcr *vhcr,
1064                           struct mlx4_cmd_mailbox *inbox,
1065                           struct mlx4_cmd_mailbox *outbox,
1066                           struct mlx4_cmd_info *cmd);
1067 int mlx4_MODIFY_CQ_wrapper(struct mlx4_dev *dev, int slave,
1068                           struct mlx4_vhcr *vhcr,
1069                           struct mlx4_cmd_mailbox *inbox,
1070                           struct mlx4_cmd_mailbox *outbox,
1071                            struct mlx4_cmd_info *cmd);
1072 int mlx4_SW2HW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
1073                            struct mlx4_vhcr *vhcr,
1074                            struct mlx4_cmd_mailbox *inbox,
1075                            struct mlx4_cmd_mailbox *outbox,
1076                            struct mlx4_cmd_info *cmd);
1077 int mlx4_HW2SW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
1078                            struct mlx4_vhcr *vhcr,
1079                            struct mlx4_cmd_mailbox *inbox,
1080                            struct mlx4_cmd_mailbox *outbox,
1081                            struct mlx4_cmd_info *cmd);
1082 int mlx4_QUERY_SRQ_wrapper(struct mlx4_dev *dev, int slave,
1083                            struct mlx4_vhcr *vhcr,
1084                            struct mlx4_cmd_mailbox *inbox,
1085                            struct mlx4_cmd_mailbox *outbox,
1086                            struct mlx4_cmd_info *cmd);
1087 int mlx4_ARM_SRQ_wrapper(struct mlx4_dev *dev, int slave,
1088                          struct mlx4_vhcr *vhcr,
1089                          struct mlx4_cmd_mailbox *inbox,
1090                          struct mlx4_cmd_mailbox *outbox,
1091                          struct mlx4_cmd_info *cmd);
1092 int mlx4_GEN_QP_wrapper(struct mlx4_dev *dev, int slave,
1093                         struct mlx4_vhcr *vhcr,
1094                         struct mlx4_cmd_mailbox *inbox,
1095                         struct mlx4_cmd_mailbox *outbox,
1096                         struct mlx4_cmd_info *cmd);
1097 int mlx4_RST2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
1098                              struct mlx4_vhcr *vhcr,
1099                              struct mlx4_cmd_mailbox *inbox,
1100                              struct mlx4_cmd_mailbox *outbox,
1101                              struct mlx4_cmd_info *cmd);
1102 int mlx4_INIT2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
1103                               struct mlx4_vhcr *vhcr,
1104                               struct mlx4_cmd_mailbox *inbox,
1105                               struct mlx4_cmd_mailbox *outbox,
1106                               struct mlx4_cmd_info *cmd);
1107 int mlx4_INIT2RTR_QP_wrapper(struct mlx4_dev *dev, int slave,
1108                              struct mlx4_vhcr *vhcr,
1109                              struct mlx4_cmd_mailbox *inbox,
1110                              struct mlx4_cmd_mailbox *outbox,
1111                              struct mlx4_cmd_info *cmd);
1112 int mlx4_RTR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
1113                             struct mlx4_vhcr *vhcr,
1114                             struct mlx4_cmd_mailbox *inbox,
1115                             struct mlx4_cmd_mailbox *outbox,
1116                             struct mlx4_cmd_info *cmd);
1117 int mlx4_RTS2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
1118                             struct mlx4_vhcr *vhcr,
1119                             struct mlx4_cmd_mailbox *inbox,
1120                             struct mlx4_cmd_mailbox *outbox,
1121                             struct mlx4_cmd_info *cmd);
1122 int mlx4_SQERR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
1123                               struct mlx4_vhcr *vhcr,
1124                               struct mlx4_cmd_mailbox *inbox,
1125                               struct mlx4_cmd_mailbox *outbox,
1126                               struct mlx4_cmd_info *cmd);
1127 int mlx4_2ERR_QP_wrapper(struct mlx4_dev *dev, int slave,
1128                          struct mlx4_vhcr *vhcr,
1129                          struct mlx4_cmd_mailbox *inbox,
1130                          struct mlx4_cmd_mailbox *outbox,
1131                          struct mlx4_cmd_info *cmd);
1132 int mlx4_RTS2SQD_QP_wrapper(struct mlx4_dev *dev, int slave,
1133                             struct mlx4_vhcr *vhcr,
1134                             struct mlx4_cmd_mailbox *inbox,
1135                             struct mlx4_cmd_mailbox *outbox,
1136                             struct mlx4_cmd_info *cmd);
1137 int mlx4_SQD2SQD_QP_wrapper(struct mlx4_dev *dev, int slave,
1138                             struct mlx4_vhcr *vhcr,
1139                             struct mlx4_cmd_mailbox *inbox,
1140                             struct mlx4_cmd_mailbox *outbox,
1141                             struct mlx4_cmd_info *cmd);
1142 int mlx4_SQD2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
1143                             struct mlx4_vhcr *vhcr,
1144                             struct mlx4_cmd_mailbox *inbox,
1145                             struct mlx4_cmd_mailbox *outbox,
1146                             struct mlx4_cmd_info *cmd);
1147 int mlx4_2RST_QP_wrapper(struct mlx4_dev *dev, int slave,
1148                          struct mlx4_vhcr *vhcr,
1149                          struct mlx4_cmd_mailbox *inbox,
1150                          struct mlx4_cmd_mailbox *outbox,
1151                          struct mlx4_cmd_info *cmd);
1152 int mlx4_QUERY_QP_wrapper(struct mlx4_dev *dev, int slave,
1153                           struct mlx4_vhcr *vhcr,
1154                           struct mlx4_cmd_mailbox *inbox,
1155                           struct mlx4_cmd_mailbox *outbox,
1156                           struct mlx4_cmd_info *cmd);
1157
1158 int mlx4_GEN_EQE(struct mlx4_dev *dev, int slave, struct mlx4_eqe *eqe);
1159
1160 enum {
1161         MLX4_CMD_CLEANUP_STRUCT = 1UL << 0,
1162         MLX4_CMD_CLEANUP_POOL   = 1UL << 1,
1163         MLX4_CMD_CLEANUP_HCR    = 1UL << 2,
1164         MLX4_CMD_CLEANUP_VHCR   = 1UL << 3,
1165         MLX4_CMD_CLEANUP_ALL    = (MLX4_CMD_CLEANUP_VHCR << 1) - 1
1166 };
1167
1168 int mlx4_cmd_init(struct mlx4_dev *dev);
1169 void mlx4_cmd_cleanup(struct mlx4_dev *dev, int cleanup_mask);
1170 int mlx4_multi_func_init(struct mlx4_dev *dev);
1171 int mlx4_ARM_COMM_CHANNEL(struct mlx4_dev *dev);
1172 void mlx4_multi_func_cleanup(struct mlx4_dev *dev);
1173 void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param);
1174 int mlx4_cmd_use_events(struct mlx4_dev *dev);
1175 void mlx4_cmd_use_polling(struct mlx4_dev *dev);
1176
1177 int mlx4_comm_cmd(struct mlx4_dev *dev, u8 cmd, u16 param,
1178                   u16 op, unsigned long timeout);
1179
1180 void mlx4_cq_tasklet_cb(unsigned long data);
1181 void mlx4_cq_completion(struct mlx4_dev *dev, u32 cqn);
1182 void mlx4_cq_event(struct mlx4_dev *dev, u32 cqn, int event_type);
1183
1184 void mlx4_qp_event(struct mlx4_dev *dev, u32 qpn, int event_type);
1185
1186 void mlx4_srq_event(struct mlx4_dev *dev, u32 srqn, int event_type);
1187
1188 void mlx4_enter_error_state(struct mlx4_dev_persistent *persist);
1189
1190 int mlx4_SENSE_PORT(struct mlx4_dev *dev, int port,
1191                     enum mlx4_port_type *type);
1192 void mlx4_do_sense_ports(struct mlx4_dev *dev,
1193                          enum mlx4_port_type *stype,
1194                          enum mlx4_port_type *defaults);
1195 void mlx4_start_sense(struct mlx4_dev *dev);
1196 void mlx4_stop_sense(struct mlx4_dev *dev);
1197 void mlx4_sense_init(struct mlx4_dev *dev);
1198 int mlx4_check_port_params(struct mlx4_dev *dev,
1199                            enum mlx4_port_type *port_type);
1200 int mlx4_change_port_types(struct mlx4_dev *dev,
1201                            enum mlx4_port_type *port_types);
1202
1203 void mlx4_init_mac_table(struct mlx4_dev *dev, struct mlx4_mac_table *table);
1204 void mlx4_init_vlan_table(struct mlx4_dev *dev, struct mlx4_vlan_table *table);
1205 void mlx4_init_roce_gid_table(struct mlx4_dev *dev,
1206                               struct mlx4_roce_gid_table *table);
1207 void __mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, u16 vlan);
1208 int __mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index);
1209
1210 int mlx4_SET_PORT(struct mlx4_dev *dev, u8 port, int pkey_tbl_sz);
1211 /* resource tracker functions*/
1212 int mlx4_get_slave_from_resource_id(struct mlx4_dev *dev,
1213                                     enum mlx4_resource resource_type,
1214                                     u64 resource_id, int *slave);
1215 void mlx4_delete_all_resources_for_slave(struct mlx4_dev *dev, int slave_id);
1216 void mlx4_reset_roce_gids(struct mlx4_dev *dev, int slave);
1217 int mlx4_init_resource_tracker(struct mlx4_dev *dev);
1218
1219 void mlx4_free_resource_tracker(struct mlx4_dev *dev,
1220                                 enum mlx4_res_tracker_free_type type);
1221
1222 int mlx4_QUERY_FW_wrapper(struct mlx4_dev *dev, int slave,
1223                           struct mlx4_vhcr *vhcr,
1224                           struct mlx4_cmd_mailbox *inbox,
1225                           struct mlx4_cmd_mailbox *outbox,
1226                           struct mlx4_cmd_info *cmd);
1227 int mlx4_SET_PORT_wrapper(struct mlx4_dev *dev, int slave,
1228                           struct mlx4_vhcr *vhcr,
1229                           struct mlx4_cmd_mailbox *inbox,
1230                           struct mlx4_cmd_mailbox *outbox,
1231                           struct mlx4_cmd_info *cmd);
1232 int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave,
1233                            struct mlx4_vhcr *vhcr,
1234                            struct mlx4_cmd_mailbox *inbox,
1235                            struct mlx4_cmd_mailbox *outbox,
1236                            struct mlx4_cmd_info *cmd);
1237 int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave,
1238                             struct mlx4_vhcr *vhcr,
1239                             struct mlx4_cmd_mailbox *inbox,
1240                             struct mlx4_cmd_mailbox *outbox,
1241                             struct mlx4_cmd_info *cmd);
1242 int mlx4_QUERY_DEV_CAP_wrapper(struct mlx4_dev *dev, int slave,
1243                                struct mlx4_vhcr *vhcr,
1244                                struct mlx4_cmd_mailbox *inbox,
1245                                struct mlx4_cmd_mailbox *outbox,
1246                                struct mlx4_cmd_info *cmd);
1247 int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave,
1248                             struct mlx4_vhcr *vhcr,
1249                             struct mlx4_cmd_mailbox *inbox,
1250                             struct mlx4_cmd_mailbox *outbox,
1251                             struct mlx4_cmd_info *cmd);
1252 int mlx4_get_port_ib_caps(struct mlx4_dev *dev, u8 port, __be32 *caps);
1253
1254 int mlx4_get_slave_pkey_gid_tbl_len(struct mlx4_dev *dev, u8 port,
1255                                     int *gid_tbl_len, int *pkey_tbl_len);
1256
1257 int mlx4_QP_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
1258                            struct mlx4_vhcr *vhcr,
1259                            struct mlx4_cmd_mailbox *inbox,
1260                            struct mlx4_cmd_mailbox *outbox,
1261                            struct mlx4_cmd_info *cmd);
1262
1263 int mlx4_UPDATE_QP_wrapper(struct mlx4_dev *dev, int slave,
1264                            struct mlx4_vhcr *vhcr,
1265                            struct mlx4_cmd_mailbox *inbox,
1266                            struct mlx4_cmd_mailbox *outbox,
1267                            struct mlx4_cmd_info *cmd);
1268
1269 int mlx4_PROMISC_wrapper(struct mlx4_dev *dev, int slave,
1270                          struct mlx4_vhcr *vhcr,
1271                          struct mlx4_cmd_mailbox *inbox,
1272                          struct mlx4_cmd_mailbox *outbox,
1273                          struct mlx4_cmd_info *cmd);
1274 int mlx4_qp_detach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1275                           enum mlx4_protocol prot, enum mlx4_steer_type steer);
1276 int mlx4_qp_attach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1277                           int block_mcast_loopback, enum mlx4_protocol prot,
1278                           enum mlx4_steer_type steer);
1279 int mlx4_trans_to_dmfs_attach(struct mlx4_dev *dev, struct mlx4_qp *qp,
1280                               u8 gid[16], u8 port,
1281                               int block_mcast_loopback,
1282                               enum mlx4_protocol prot, u64 *reg_id);
1283 int mlx4_SET_MCAST_FLTR_wrapper(struct mlx4_dev *dev, int slave,
1284                                 struct mlx4_vhcr *vhcr,
1285                                 struct mlx4_cmd_mailbox *inbox,
1286                                 struct mlx4_cmd_mailbox *outbox,
1287                                 struct mlx4_cmd_info *cmd);
1288 int mlx4_SET_VLAN_FLTR_wrapper(struct mlx4_dev *dev, int slave,
1289                                struct mlx4_vhcr *vhcr,
1290                                struct mlx4_cmd_mailbox *inbox,
1291                                struct mlx4_cmd_mailbox *outbox,
1292                                struct mlx4_cmd_info *cmd);
1293 int mlx4_common_set_vlan_fltr(struct mlx4_dev *dev, int function,
1294                                      int port, void *buf);
1295 int mlx4_common_dump_eth_stats(struct mlx4_dev *dev, int slave, u32 in_mod,
1296                                 struct mlx4_cmd_mailbox *outbox);
1297 int mlx4_DUMP_ETH_STATS_wrapper(struct mlx4_dev *dev, int slave,
1298                                    struct mlx4_vhcr *vhcr,
1299                                    struct mlx4_cmd_mailbox *inbox,
1300                                    struct mlx4_cmd_mailbox *outbox,
1301                                 struct mlx4_cmd_info *cmd);
1302 int mlx4_PKEY_TABLE_wrapper(struct mlx4_dev *dev, int slave,
1303                             struct mlx4_vhcr *vhcr,
1304                             struct mlx4_cmd_mailbox *inbox,
1305                             struct mlx4_cmd_mailbox *outbox,
1306                             struct mlx4_cmd_info *cmd);
1307 int mlx4_QUERY_IF_STAT_wrapper(struct mlx4_dev *dev, int slave,
1308                                struct mlx4_vhcr *vhcr,
1309                                struct mlx4_cmd_mailbox *inbox,
1310                                struct mlx4_cmd_mailbox *outbox,
1311                                struct mlx4_cmd_info *cmd);
1312 int mlx4_QP_FLOW_STEERING_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
1313                                          struct mlx4_vhcr *vhcr,
1314                                          struct mlx4_cmd_mailbox *inbox,
1315                                          struct mlx4_cmd_mailbox *outbox,
1316                                          struct mlx4_cmd_info *cmd);
1317 int mlx4_QP_FLOW_STEERING_DETACH_wrapper(struct mlx4_dev *dev, int slave,
1318                                          struct mlx4_vhcr *vhcr,
1319                                          struct mlx4_cmd_mailbox *inbox,
1320                                          struct mlx4_cmd_mailbox *outbox,
1321                                          struct mlx4_cmd_info *cmd);
1322 int mlx4_ACCESS_REG_wrapper(struct mlx4_dev *dev, int slave,
1323                             struct mlx4_vhcr *vhcr,
1324                             struct mlx4_cmd_mailbox *inbox,
1325                             struct mlx4_cmd_mailbox *outbox,
1326                             struct mlx4_cmd_info *cmd);
1327
1328 int mlx4_get_mgm_entry_size(struct mlx4_dev *dev);
1329 int mlx4_get_qp_per_mgm(struct mlx4_dev *dev);
1330
1331 static inline void set_param_l(u64 *arg, u32 val)
1332 {
1333         *arg = (*arg & 0xffffffff00000000ULL) | (u64) val;
1334 }
1335
1336 static inline void set_param_h(u64 *arg, u32 val)
1337 {
1338         *arg = (*arg & 0xffffffff) | ((u64) val << 32);
1339 }
1340
1341 static inline u32 get_param_l(u64 *arg)
1342 {
1343         return (u32) (*arg & 0xffffffff);
1344 }
1345
1346 static inline u32 get_param_h(u64 *arg)
1347 {
1348         return (u32)(*arg >> 32);
1349 }
1350
1351 static inline spinlock_t *mlx4_tlock(struct mlx4_dev *dev)
1352 {
1353         return &mlx4_priv(dev)->mfunc.master.res_tracker.lock;
1354 }
1355
1356 #define NOT_MASKED_PD_BITS 17
1357
1358 void mlx4_vf_immed_vlan_work_handler(struct work_struct *_work);
1359
1360 void mlx4_init_quotas(struct mlx4_dev *dev);
1361
1362 int mlx4_get_slave_num_gids(struct mlx4_dev *dev, int slave, int port);
1363 /* Returns the VF index of slave */
1364 int mlx4_get_vf_indx(struct mlx4_dev *dev, int slave);
1365 int mlx4_config_mad_demux(struct mlx4_dev *dev);
1366
1367 enum mlx4_zone_flags {
1368         MLX4_ZONE_ALLOW_ALLOC_FROM_LOWER_PRIO   = 1UL << 0,
1369         MLX4_ZONE_ALLOW_ALLOC_FROM_EQ_PRIO      = 1UL << 1,
1370         MLX4_ZONE_FALLBACK_TO_HIGHER_PRIO       = 1UL << 2,
1371         MLX4_ZONE_USE_RR                        = 1UL << 3,
1372 };
1373
1374 enum mlx4_zone_alloc_flags {
1375         /* No two objects could overlap between zones. UID
1376          * could be left unused. If this flag is given and
1377          * two overlapped zones are used, an object will be free'd
1378          * from the smallest possible matching zone.
1379          */
1380         MLX4_ZONE_ALLOC_FLAGS_NO_OVERLAP        = 1UL << 0,
1381 };
1382
1383 struct mlx4_zone_allocator;
1384
1385 /* Create a new zone allocator */
1386 struct mlx4_zone_allocator *mlx4_zone_allocator_create(enum mlx4_zone_alloc_flags flags);
1387
1388 /* Attach a mlx4_bitmap <bitmap> of priority <priority> to the zone allocator
1389  * <zone_alloc>. Allocating an object from this zone adds an offset <offset>.
1390  * Similarly, when searching for an object to free, this offset it taken into
1391  * account. The use_rr mlx4_ib parameter for allocating objects from this <bitmap>
1392  * is given through the MLX4_ZONE_USE_RR flag in <flags>.
1393  * When an allocation fails, <zone_alloc> tries to allocate from other zones
1394  * according to the policy set by <flags>. <puid> is the unique identifier
1395  * received to this zone.
1396  */
1397 int mlx4_zone_add_one(struct mlx4_zone_allocator *zone_alloc,
1398                       struct mlx4_bitmap *bitmap,
1399                       u32 flags,
1400                       int priority,
1401                       int offset,
1402                       u32 *puid);
1403
1404 /* Remove bitmap indicated by <uid> from <zone_alloc> */
1405 int mlx4_zone_remove_one(struct mlx4_zone_allocator *zone_alloc, u32 uid);
1406
1407 /* Delete the zone allocator <zone_alloc. This function doesn't destroy
1408  * the attached bitmaps.
1409  */
1410 void mlx4_zone_allocator_destroy(struct mlx4_zone_allocator *zone_alloc);
1411
1412 /* Allocate <count> objects with align <align> and skip_mask <skip_mask>
1413  * from the mlx4_bitmap whose uid is <uid>. The bitmap which we actually
1414  * allocated from is returned in <puid>. If the allocation fails, a negative
1415  * number is returned. Otherwise, the offset of the first object is returned.
1416  */
1417 u32 mlx4_zone_alloc_entries(struct mlx4_zone_allocator *zones, u32 uid, int count,
1418                             int align, u32 skip_mask, u32 *puid);
1419
1420 /* Free <count> objects, start from <obj> of the uid <uid> from zone_allocator
1421  * <zones>.
1422  */
1423 u32 mlx4_zone_free_entries(struct mlx4_zone_allocator *zones,
1424                            u32 uid, u32 obj, u32 count);
1425
1426 /* If <zones> was allocated with MLX4_ZONE_ALLOC_FLAGS_NO_OVERLAP, instead of
1427  * specifying the uid when freeing an object, zone allocator could figure it by
1428  * itself. Other parameters are similar to mlx4_zone_free.
1429  */
1430 u32 mlx4_zone_free_entries_unique(struct mlx4_zone_allocator *zones, u32 obj, u32 count);
1431
1432 /* Returns a pointer to mlx4_bitmap that was attached to <zones> with <uid> */
1433 struct mlx4_bitmap *mlx4_zone_get_bitmap(struct mlx4_zone_allocator *zones, u32 uid);
1434
1435 #endif /* MLX4_H */