drivers/net/ethernet/mellanox/mlx4/mlx4.h

   1 /*
   2  * Copyright (c) 2004, 2005 Topspin Communications.  All rights reserved.
   3  * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
   4  * Copyright (c) 2005, 2006, 2007 Cisco Systems.  All rights reserved.
   5  * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
   6  * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
   7  *
   8  * This software is available to you under a choice of one of two
   9  * licenses.  You may choose to be licensed under the terms of the GNU
  10  * General Public License (GPL) Version 2, available from the file
  11  * COPYING in the main directory of this source tree, or the
  12  * OpenIB.org BSD license below:
  13  *
  14  *     Redistribution and use in source and binary forms, with or
  15  *     without modification, are permitted provided that the following
  16  *     conditions are met:
  17  *
  18  *      - Redistributions of source code must retain the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer.
  21  *
  22  *      - Redistributions in binary form must reproduce the above
  23  *        copyright notice, this list of conditions and the following
  24  *        disclaimer in the documentation and/or other materials
  25  *        provided with the distribution.
  26  *
  27  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  28  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  29  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  30  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  31  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  32  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  33  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  34  * SOFTWARE.
  35  */
  36
  37 #ifndef MLX4_H
  38 #define MLX4_H
  39
  40 #include <linux/mutex.h>
  41 #include <linux/radix-tree.h>
  42 #include <linux/rbtree.h>
  43 #include <linux/timer.h>
  44 #include <linux/semaphore.h>
  45 #include <linux/workqueue.h>
  46 #include <linux/interrupt.h>
  47 #include <linux/spinlock.h>
  48
  49 #include <linux/mlx4/device.h>
  50 #include <linux/mlx4/driver.h>
  51 #include <linux/mlx4/doorbell.h>
  52 #include <linux/mlx4/cmd.h>
  53
  54 #define DRV_NAME        "mlx4_core"
  55 #define PFX             DRV_NAME ": "
  56 #define DRV_VERSION     "2.2-1"
  57 #define DRV_RELDATE     "Feb, 2014"
  58
  59 #define MLX4_FS_UDP_UC_EN               (1 << 1)
  60 #define MLX4_FS_TCP_UC_EN               (1 << 2)
  61 #define MLX4_FS_NUM_OF_L2_ADDR          8
  62 #define MLX4_FS_MGM_LOG_ENTRY_SIZE      7
  63 #define MLX4_FS_NUM_MCG                 (1 << 17)
  64
  65 #define INIT_HCA_TPT_MW_ENABLE          (1 << 7)
  66
  67 struct mlx4_set_port_prio2tc_context {
  68         u8 prio2tc[4];
  69 };
  70
  71 struct mlx4_port_scheduler_tc_cfg_be {
  72         __be16 pg;
  73         __be16 bw_precentage;
  74         __be16 max_bw_units; /* 3-100Mbps, 4-1Gbps, other values - reserved */
  75         __be16 max_bw_value;
  76 };
  77
  78 struct mlx4_set_port_scheduler_context {
  79         struct mlx4_port_scheduler_tc_cfg_be tc[MLX4_NUM_TC];
  80 };
  81
  82 enum {
  83         MLX4_HCR_BASE           = 0x80680,
  84         MLX4_HCR_SIZE           = 0x0001c,
  85         MLX4_CLR_INT_SIZE       = 0x00008,
  86         MLX4_SLAVE_COMM_BASE    = 0x0,
  87         MLX4_COMM_PAGESIZE      = 0x1000,
  88         MLX4_CLOCK_SIZE         = 0x00008
  89 };
  90
  91 enum {
  92         MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE = 10,
  93         MLX4_MIN_MGM_LOG_ENTRY_SIZE = 7,
  94         MLX4_MAX_MGM_LOG_ENTRY_SIZE = 12,
  95         MLX4_MAX_QP_PER_MGM = 4 * ((1 << MLX4_MAX_MGM_LOG_ENTRY_SIZE) / 16 - 2),
  96         MLX4_MTT_ENTRY_PER_SEG  = 8,
  97 };
  98
  99 enum {
 100         MLX4_NUM_PDS            = 1 << 15
 101 };
 102
 103 enum {
 104         MLX4_CMPT_TYPE_QP       = 0,
 105         MLX4_CMPT_TYPE_SRQ      = 1,
 106         MLX4_CMPT_TYPE_CQ       = 2,
 107         MLX4_CMPT_TYPE_EQ       = 3,
 108         MLX4_CMPT_NUM_TYPE
 109 };
 110
 111 enum {
 112         MLX4_CMPT_SHIFT         = 24,
 113         MLX4_NUM_CMPTS          = MLX4_CMPT_NUM_TYPE << MLX4_CMPT_SHIFT
 114 };
 115
 116 enum mlx4_mpt_state {
 117         MLX4_MPT_DISABLED = 0,
 118         MLX4_MPT_EN_HW,
 119         MLX4_MPT_EN_SW
 120 };
 121
 122 #define MLX4_COMM_TIME          10000
 123 enum {
 124         MLX4_COMM_CMD_RESET,
 125         MLX4_COMM_CMD_VHCR0,
 126         MLX4_COMM_CMD_VHCR1,
 127         MLX4_COMM_CMD_VHCR2,
 128         MLX4_COMM_CMD_VHCR_EN,
 129         MLX4_COMM_CMD_VHCR_POST,
 130         MLX4_COMM_CMD_FLR = 254
 131 };
 132
 133 enum {
 134         MLX4_VF_SMI_DISABLED,
 135         MLX4_VF_SMI_ENABLED
 136 };
 137
 138 /*The flag indicates that the slave should delay the RESET cmd*/
 139 #define MLX4_DELAY_RESET_SLAVE 0xbbbbbbb
 140 /*indicates how many retries will be done if we are in the middle of FLR*/
 141 #define NUM_OF_RESET_RETRIES    10
 142 #define SLEEP_TIME_IN_RESET     (2 * 1000)
 143 enum mlx4_resource {
 144         RES_QP,
 145         RES_CQ,
 146         RES_SRQ,
 147         RES_XRCD,
 148         RES_MPT,
 149         RES_MTT,
 150         RES_MAC,
 151         RES_VLAN,
 152         RES_EQ,
 153         RES_COUNTER,
 154         RES_FS_RULE,
 155         MLX4_NUM_OF_RESOURCE_TYPE
 156 };
 157
 158 enum mlx4_alloc_mode {
 159         RES_OP_RESERVE,
 160         RES_OP_RESERVE_AND_MAP,
 161         RES_OP_MAP_ICM,
 162 };
 163
 164 enum mlx4_res_tracker_free_type {
 165         RES_TR_FREE_ALL,
 166         RES_TR_FREE_SLAVES_ONLY,
 167         RES_TR_FREE_STRUCTS_ONLY,
 168 };
 169
 170 /*
 171  *Virtual HCR structures.
 172  * mlx4_vhcr is the sw representation, in machine endianess
 173  *
 174  * mlx4_vhcr_cmd is the formalized structure, the one that is passed
 175  * to FW to go through communication channel.
 176  * It is big endian, and has the same structure as the physical HCR
 177  * used by command interface
 178  */
 179 struct mlx4_vhcr {
 180         u64     in_param;
 181         u64     out_param;
 182         u32     in_modifier;
 183         u32     errno;
 184         u16     op;
 185         u16     token;
 186         u8      op_modifier;
 187         u8      e_bit;
 188 };
 189
 190 struct mlx4_vhcr_cmd {
 191         __be64 in_param;
 192         __be32 in_modifier;
 193         __be64 out_param;
 194         __be16 token;
 195         u16 reserved;
 196         u8 status;
 197         u8 flags;
 198         __be16 opcode;
 199 };
 200
 201 struct mlx4_cmd_info {
 202         u16 opcode;
 203         bool has_inbox;
 204         bool has_outbox;
 205         bool out_is_imm;
 206         bool encode_slave_id;
 207         int (*verify)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr,
 208                       struct mlx4_cmd_mailbox *inbox);
 209         int (*wrapper)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr,
 210                        struct mlx4_cmd_mailbox *inbox,
 211                        struct mlx4_cmd_mailbox *outbox,
 212                        struct mlx4_cmd_info *cmd);
 213 };
 214
 215 #ifdef CONFIG_MLX4_DEBUG
 216 extern int mlx4_debug_level;
 217 #else /* CONFIG_MLX4_DEBUG */
 218 #define mlx4_debug_level        (0)
 219 #endif /* CONFIG_MLX4_DEBUG */
 220
 221 #define mlx4_dbg(mdev, format, ...)                                     \
 222 do {                                                                    \
 223         if (mlx4_debug_level)                                           \
 224                 dev_printk(KERN_DEBUG,                                  \
 225                            &(mdev)->persist->pdev->dev, format,         \
 226                            ##__VA_ARGS__);                              \
 227 } while (0)
 228
 229 #define mlx4_err(mdev, format, ...)                                     \
 230         dev_err(&(mdev)->persist->pdev->dev, format, ##__VA_ARGS__)
 231 #define mlx4_info(mdev, format, ...)                                    \
 232         dev_info(&(mdev)->persist->pdev->dev, format, ##__VA_ARGS__)
 233 #define mlx4_warn(mdev, format, ...)                                    \
 234         dev_warn(&(mdev)->persist->pdev->dev, format, ##__VA_ARGS__)
 235
 236 extern int mlx4_log_num_mgm_entry_size;
 237 extern int log_mtts_per_seg;
 238
 239 #define MLX4_MAX_NUM_SLAVES     (MLX4_MAX_NUM_PF + MLX4_MAX_NUM_VF)
 240 #define ALL_SLAVES 0xff
 241
 242 struct mlx4_bitmap {
 243         u32                     last;
 244         u32                     top;
 245         u32                     max;
 246         u32                     reserved_top;
 247         u32                     mask;
 248         u32                     avail;
 249         u32                     effective_len;
 250         spinlock_t              lock;
 251         unsigned long          *table;
 252 };
 253
 254 struct mlx4_buddy {
 255         unsigned long         **bits;
 256         unsigned int           *num_free;
 257         u32                     max_order;
 258         spinlock_t              lock;
 259 };
 260
 261 struct mlx4_icm;
 262
 263 struct mlx4_icm_table {
 264         u64                     virt;
 265         int                     num_icm;
 266         u32                     num_obj;
 267         int                     obj_size;
 268         int                     lowmem;
 269         int                     coherent;
 270         struct mutex            mutex;
 271         struct mlx4_icm       **icm;
 272 };
 273
 274 #define MLX4_MPT_FLAG_SW_OWNS       (0xfUL << 28)
 275 #define MLX4_MPT_FLAG_FREE          (0x3UL << 28)
 276 #define MLX4_MPT_FLAG_MIO           (1 << 17)
 277 #define MLX4_MPT_FLAG_BIND_ENABLE   (1 << 15)
 278 #define MLX4_MPT_FLAG_PHYSICAL      (1 <<  9)
 279 #define MLX4_MPT_FLAG_REGION        (1 <<  8)
 280
 281 #define MLX4_MPT_PD_MASK            (0x1FFFFUL)
 282 #define MLX4_MPT_PD_VF_MASK         (0xFE0000UL)
 283 #define MLX4_MPT_PD_FLAG_FAST_REG   (1 << 27)
 284 #define MLX4_MPT_PD_FLAG_RAE        (1 << 28)
 285 #define MLX4_MPT_PD_FLAG_EN_INV     (3 << 24)
 286
 287 #define MLX4_MPT_QP_FLAG_BOUND_QP   (1 << 7)
 288
 289 #define MLX4_MPT_STATUS_SW              0xF0
 290 #define MLX4_MPT_STATUS_HW              0x00
 291
 292 #define MLX4_CQE_SIZE_MASK_STRIDE       0x3
 293 #define MLX4_EQE_SIZE_MASK_STRIDE       0x30
 294
 295 /*
 296  * Must be packed because mtt_seg is 64 bits but only aligned to 32 bits.
 297  */
 298 struct mlx4_mpt_entry {
 299         __be32 flags;
 300         __be32 qpn;
 301         __be32 key;
 302         __be32 pd_flags;
 303         __be64 start;
 304         __be64 length;
 305         __be32 lkey;
 306         __be32 win_cnt;
 307         u8      reserved1[3];
 308         u8      mtt_rep;
 309         __be64 mtt_addr;
 310         __be32 mtt_sz;
 311         __be32 entity_size;
 312         __be32 first_byte_offset;
 313 } __packed;
 314
 315 /*
 316  * Must be packed because start is 64 bits but only aligned to 32 bits.
 317  */
 318 struct mlx4_eq_context {
 319         __be32                  flags;
 320         u16                     reserved1[3];
 321         __be16                  page_offset;
 322         u8                      log_eq_size;
 323         u8                      reserved2[4];
 324         u8                      eq_period;
 325         u8                      reserved3;
 326         u8                      eq_max_count;
 327         u8                      reserved4[3];
 328         u8                      intr;
 329         u8                      log_page_size;
 330         u8                      reserved5[2];
 331         u8                      mtt_base_addr_h;
 332         __be32                  mtt_base_addr_l;
 333         u32                     reserved6[2];
 334         __be32                  consumer_index;
 335         __be32                  producer_index;
 336         u32                     reserved7[4];
 337 };
 338
 339 struct mlx4_cq_context {
 340         __be32                  flags;
 341         u16                     reserved1[3];
 342         __be16                  page_offset;
 343         __be32                  logsize_usrpage;
 344         __be16                  cq_period;
 345         __be16                  cq_max_count;
 346         u8                      reserved2[3];
 347         u8                      comp_eqn;
 348         u8                      log_page_size;
 349         u8                      reserved3[2];
 350         u8                      mtt_base_addr_h;
 351         __be32                  mtt_base_addr_l;
 352         __be32                  last_notified_index;
 353         __be32                  solicit_producer_index;
 354         __be32                  consumer_index;
 355         __be32                  producer_index;
 356         u32                     reserved4[2];
 357         __be64                  db_rec_addr;
 358 };
 359
 360 struct mlx4_srq_context {
 361         __be32                  state_logsize_srqn;
 362         u8                      logstride;
 363         u8                      reserved1;
 364         __be16                  xrcd;
 365         __be32                  pg_offset_cqn;
 366         u32                     reserved2;
 367         u8                      log_page_size;
 368         u8                      reserved3[2];
 369         u8                      mtt_base_addr_h;
 370         __be32                  mtt_base_addr_l;
 371         __be32                  pd;
 372         __be16                  limit_watermark;
 373         __be16                  wqe_cnt;
 374         u16                     reserved4;
 375         __be16                  wqe_counter;
 376         u32                     reserved5;
 377         __be64                  db_rec_addr;
 378 };
 379
 380 struct mlx4_eq_tasklet {
 381         struct list_head list;
 382         struct list_head process_list;
 383         struct tasklet_struct task;
 384         /* lock on completion tasklet list */
 385         spinlock_t lock;
 386 };
 387
 388 struct mlx4_eq {
 389         struct mlx4_dev        *dev;
 390         void __iomem           *doorbell;
 391         int                     eqn;
 392         u32                     cons_index;
 393         u16                     irq;
 394         u16                     have_irq;
 395         int                     nent;
 396         struct mlx4_buf_list   *page_list;
 397         struct mlx4_mtt         mtt;
 398         struct mlx4_eq_tasklet  tasklet_ctx;
 399 };
 400
 401 struct mlx4_slave_eqe {
 402         u8 type;
 403         u8 port;
 404         u32 param;
 405 };
 406
 407 struct mlx4_slave_event_eq_info {
 408         int eqn;
 409         u16 token;
 410 };
 411
 412 struct mlx4_profile {
 413         int                     num_qp;
 414         int                     rdmarc_per_qp;
 415         int                     num_srq;
 416         int                     num_cq;
 417         int                     num_mcg;
 418         int                     num_mpt;
 419         unsigned                num_mtt;
 420 };
 421
 422 struct mlx4_fw {
 423         u64                     clr_int_base;
 424         u64                     catas_offset;
 425         u64                     comm_base;
 426         u64                     clock_offset;
 427         struct mlx4_icm        *fw_icm;
 428         struct mlx4_icm        *aux_icm;
 429         u32                     catas_size;
 430         u16                     fw_pages;
 431         u8                      clr_int_bar;
 432         u8                      catas_bar;
 433         u8                      comm_bar;
 434         u8                      clock_bar;
 435 };
 436
 437 struct mlx4_comm {
 438         u32                     slave_write;
 439         u32                     slave_read;
 440 };
 441
 442 enum {
 443         MLX4_MCAST_CONFIG       = 0,
 444         MLX4_MCAST_DISABLE      = 1,
 445         MLX4_MCAST_ENABLE       = 2,
 446 };
 447
 448 #define VLAN_FLTR_SIZE  128
 449
 450 struct mlx4_vlan_fltr {
 451         __be32 entry[VLAN_FLTR_SIZE];
 452 };
 453
 454 struct mlx4_mcast_entry {
 455         struct list_head list;
 456         u64 addr;
 457 };
 458
 459 struct mlx4_promisc_qp {
 460         struct list_head list;
 461         u32 qpn;
 462 };
 463
 464 struct mlx4_steer_index {
 465         struct list_head list;
 466         unsigned int index;
 467         struct list_head duplicates;
 468 };
 469
 470 #define MLX4_EVENT_TYPES_NUM 64
 471
 472 struct mlx4_slave_state {
 473         u8 comm_toggle;
 474         u8 last_cmd;
 475         u8 init_port_mask;
 476         bool active;
 477         bool old_vlan_api;
 478         u8 function;
 479         dma_addr_t vhcr_dma;
 480         u16 mtu[MLX4_MAX_PORTS + 1];
 481         __be32 ib_cap_mask[MLX4_MAX_PORTS + 1];
 482         struct mlx4_slave_eqe eq[MLX4_MFUNC_MAX_EQES];
 483         struct list_head mcast_filters[MLX4_MAX_PORTS + 1];
 484         struct mlx4_vlan_fltr *vlan_filter[MLX4_MAX_PORTS + 1];
 485         /* event type to eq number lookup */
 486         struct mlx4_slave_event_eq_info event_eq[MLX4_EVENT_TYPES_NUM];
 487         u16 eq_pi;
 488         u16 eq_ci;
 489         spinlock_t lock;
 490         /*initialized via the kzalloc*/
 491         u8 is_slave_going_down;
 492         u32 cookie;
 493         enum slave_port_state port_state[MLX4_MAX_PORTS + 1];
 494 };
 495
 496 #define MLX4_VGT 4095
 497 #define NO_INDX  (-1)
 498
 499 struct mlx4_vport_state {
 500         u64 mac;
 501         u16 default_vlan;
 502         u8  default_qos;
 503         u32 tx_rate;
 504         bool spoofchk;
 505         u32 link_state;
 506 };
 507
 508 struct mlx4_vf_admin_state {
 509         struct mlx4_vport_state vport[MLX4_MAX_PORTS + 1];
 510         u8 enable_smi[MLX4_MAX_PORTS + 1];
 511 };
 512
 513 struct mlx4_vport_oper_state {
 514         struct mlx4_vport_state state;
 515         int mac_idx;
 516         int vlan_idx;
 517 };
 518
 519 struct mlx4_vf_oper_state {
 520         struct mlx4_vport_oper_state vport[MLX4_MAX_PORTS + 1];
 521         u8 smi_enabled[MLX4_MAX_PORTS + 1];
 522 };
 523
 524 struct slave_list {
 525         struct mutex mutex;
 526         struct list_head res_list[MLX4_NUM_OF_RESOURCE_TYPE];
 527 };
 528
 529 struct resource_allocator {
 530         spinlock_t alloc_lock; /* protect quotas */
 531         union {
 532                 int res_reserved;
 533                 int res_port_rsvd[MLX4_MAX_PORTS];
 534         };
 535         union {
 536                 int res_free;
 537                 int res_port_free[MLX4_MAX_PORTS];
 538         };
 539         int *quota;
 540         int *allocated;
 541         int *guaranteed;
 542 };
 543
 544 struct mlx4_resource_tracker {
 545         spinlock_t lock;
 546         /* tree for each resources */
 547         struct rb_root res_tree[MLX4_NUM_OF_RESOURCE_TYPE];
 548         /* num_of_slave's lists, one per slave */
 549         struct slave_list *slave_list;
 550         struct resource_allocator res_alloc[MLX4_NUM_OF_RESOURCE_TYPE];
 551 };
 552
 553 #define SLAVE_EVENT_EQ_SIZE     128
 554 struct mlx4_slave_event_eq {
 555         u32 eqn;
 556         u32 cons;
 557         u32 prod;
 558         spinlock_t event_lock;
 559         struct mlx4_eqe event_eqe[SLAVE_EVENT_EQ_SIZE];
 560 };
 561
 562 struct mlx4_master_qp0_state {
 563         int proxy_qp0_active;
 564         int qp0_active;
 565         int port_active;
 566 };
 567
 568 struct mlx4_mfunc_master_ctx {
 569         struct mlx4_slave_state *slave_state;
 570         struct mlx4_vf_admin_state *vf_admin;
 571         struct mlx4_vf_oper_state *vf_oper;
 572         struct mlx4_master_qp0_state qp0_state[MLX4_MAX_PORTS + 1];
 573         int                     init_port_ref[MLX4_MAX_PORTS + 1];
 574         u16                     max_mtu[MLX4_MAX_PORTS + 1];
 575         int                     disable_mcast_ref[MLX4_MAX_PORTS + 1];
 576         struct mlx4_resource_tracker res_tracker;
 577         struct workqueue_struct *comm_wq;
 578         struct work_struct      comm_work;
 579         struct work_struct      slave_event_work;
 580         struct work_struct      slave_flr_event_work;
 581         spinlock_t              slave_state_lock;
 582         __be32                  comm_arm_bit_vector[4];
 583         struct mlx4_eqe         cmd_eqe;
 584         struct mlx4_slave_event_eq slave_eq;
 585         struct mutex            gen_eqe_mutex[MLX4_MFUNC_MAX];
 586 };
 587
 588 struct mlx4_mfunc {
 589         struct mlx4_comm __iomem       *comm;
 590         struct mlx4_vhcr_cmd           *vhcr;
 591         dma_addr_t                      vhcr_dma;
 592
 593         struct mlx4_mfunc_master_ctx    master;
 594 };
 595
 596 #define MGM_QPN_MASK       0x00FFFFFF
 597 #define MGM_BLCK_LB_BIT    30
 598
 599 struct mlx4_mgm {
 600         __be32                  next_gid_index;
 601         __be32                  members_count;
 602         u32                     reserved[2];
 603         u8                      gid[16];
 604         __be32                  qp[MLX4_MAX_QP_PER_MGM];
 605 };
 606
 607 struct mlx4_cmd {
 608         struct pci_pool        *pool;
 609         void __iomem           *hcr;
 610         struct mutex            hcr_mutex;
 611         struct mutex            slave_cmd_mutex;
 612         struct semaphore        poll_sem;
 613         struct semaphore        event_sem;
 614         int                     max_cmds;
 615         spinlock_t              context_lock;
 616         int                     free_head;
 617         struct mlx4_cmd_context *context;
 618         u16                     token_mask;
 619         u8                      use_events;
 620         u8                      toggle;
 621         u8                      comm_toggle;
 622         u8                      initialized;
 623 };
 624
 625 enum {
 626         MLX4_VF_IMMED_VLAN_FLAG_VLAN = 1 << 0,
 627         MLX4_VF_IMMED_VLAN_FLAG_QOS = 1 << 1,
 628         MLX4_VF_IMMED_VLAN_FLAG_LINK_DISABLE = 1 << 2,
 629 };
 630 struct mlx4_vf_immed_vlan_work {
 631         struct work_struct      work;
 632         struct mlx4_priv        *priv;
 633         int                     flags;
 634         int                     slave;
 635         int                     vlan_ix;
 636         int                     orig_vlan_ix;
 637         u8                      port;
 638         u8                      qos;
 639         u16                     vlan_id;
 640         u16                     orig_vlan_id;
 641 };
 642
 643
 644 struct mlx4_uar_table {
 645         struct mlx4_bitmap      bitmap;
 646 };
 647
 648 struct mlx4_mr_table {
 649         struct mlx4_bitmap      mpt_bitmap;
 650         struct mlx4_buddy       mtt_buddy;
 651         u64                     mtt_base;
 652         u64                     mpt_base;
 653         struct mlx4_icm_table   mtt_table;
 654         struct mlx4_icm_table   dmpt_table;
 655 };
 656
 657 struct mlx4_cq_table {
 658         struct mlx4_bitmap      bitmap;
 659         spinlock_t              lock;
 660         struct radix_tree_root  tree;
 661         struct mlx4_icm_table   table;
 662         struct mlx4_icm_table   cmpt_table;
 663 };
 664
 665 struct mlx4_eq_table {
 666         struct mlx4_bitmap      bitmap;
 667         char                   *irq_names;
 668         void __iomem           *clr_int;
 669         void __iomem          **uar_map;
 670         u32                     clr_mask;
 671         struct mlx4_eq         *eq;
 672         struct mlx4_icm_table   table;
 673         struct mlx4_icm_table   cmpt_table;
 674         int                     have_irq;
 675         u8                      inta_pin;
 676 };
 677
 678 struct mlx4_srq_table {
 679         struct mlx4_bitmap      bitmap;
 680         spinlock_t              lock;
 681         struct radix_tree_root  tree;
 682         struct mlx4_icm_table   table;
 683         struct mlx4_icm_table   cmpt_table;
 684 };
 685
 686 enum mlx4_qp_table_zones {
 687         MLX4_QP_TABLE_ZONE_GENERAL,
 688         MLX4_QP_TABLE_ZONE_RSS,
 689         MLX4_QP_TABLE_ZONE_RAW_ETH,
 690         MLX4_QP_TABLE_ZONE_NUM
 691 };
 692
 693 struct mlx4_qp_table {
 694         struct mlx4_bitmap      *bitmap_gen;
 695         struct mlx4_zone_allocator *zones;
 696         u32                     zones_uids[MLX4_QP_TABLE_ZONE_NUM];
 697         u32                     rdmarc_base;
 698         int                     rdmarc_shift;
 699         spinlock_t              lock;
 700         struct mlx4_icm_table   qp_table;
 701         struct mlx4_icm_table   auxc_table;
 702         struct mlx4_icm_table   altc_table;
 703         struct mlx4_icm_table   rdmarc_table;
 704         struct mlx4_icm_table   cmpt_table;
 705 };
 706
 707 struct mlx4_mcg_table {
 708         struct mutex            mutex;
 709         struct mlx4_bitmap      bitmap;
 710         struct mlx4_icm_table   table;
 711 };
 712
 713 struct mlx4_catas_err {
 714         u32 __iomem            *map;
 715         struct timer_list       timer;
 716         struct list_head        list;
 717 };
 718
 719 #define MLX4_MAX_MAC_NUM        128
 720 #define MLX4_MAC_TABLE_SIZE     (MLX4_MAX_MAC_NUM << 3)
 721
 722 struct mlx4_mac_table {
 723         __be64                  entries[MLX4_MAX_MAC_NUM];
 724         int                     refs[MLX4_MAX_MAC_NUM];
 725         struct mutex            mutex;
 726         int                     total;
 727         int                     max;
 728 };
 729
 730 #define MLX4_ROCE_GID_ENTRY_SIZE        16
 731
 732 struct mlx4_roce_gid_entry {
 733         u8 raw[MLX4_ROCE_GID_ENTRY_SIZE];
 734 };
 735
 736 struct mlx4_roce_gid_table {
 737         struct mlx4_roce_gid_entry      roce_gids[MLX4_ROCE_MAX_GIDS];
 738         struct mutex                    mutex;
 739 };
 740
 741 #define MLX4_MAX_VLAN_NUM       128
 742 #define MLX4_VLAN_TABLE_SIZE    (MLX4_MAX_VLAN_NUM << 2)
 743
 744 struct mlx4_vlan_table {
 745         __be32                  entries[MLX4_MAX_VLAN_NUM];
 746         int                     refs[MLX4_MAX_VLAN_NUM];
 747         struct mutex            mutex;
 748         int                     total;
 749         int                     max;
 750 };
 751
 752 #define SET_PORT_GEN_ALL_VALID          0x7
 753 #define SET_PORT_PROMISC_SHIFT          31
 754 #define SET_PORT_MC_PROMISC_SHIFT       30
 755
 756 enum {
 757         MCAST_DIRECT_ONLY       = 0,
 758         MCAST_DIRECT            = 1,
 759         MCAST_DEFAULT           = 2
 760 };
 761
 762
 763 struct mlx4_set_port_general_context {
 764         u8 reserved[3];
 765         u8 flags;
 766         u16 reserved2;
 767         __be16 mtu;
 768         u8 pptx;
 769         u8 pfctx;
 770         u16 reserved3;
 771         u8 pprx;
 772         u8 pfcrx;
 773         u16 reserved4;
 774 };
 775
 776 struct mlx4_set_port_rqp_calc_context {
 777         __be32 base_qpn;
 778         u8 rererved;
 779         u8 n_mac;
 780         u8 n_vlan;
 781         u8 n_prio;
 782         u8 reserved2[3];
 783         u8 mac_miss;
 784         u8 intra_no_vlan;
 785         u8 no_vlan;
 786         u8 intra_vlan_miss;
 787         u8 vlan_miss;
 788         u8 reserved3[3];
 789         u8 no_vlan_prio;
 790         __be32 promisc;
 791         __be32 mcast;
 792 };
 793
 794 struct mlx4_port_info {
 795         struct mlx4_dev        *dev;
 796         int                     port;
 797         char                    dev_name[16];
 798         struct device_attribute port_attr;
 799         enum mlx4_port_type     tmp_type;
 800         char                    dev_mtu_name[16];
 801         struct device_attribute port_mtu_attr;
 802         struct mlx4_mac_table   mac_table;
 803         struct mlx4_vlan_table  vlan_table;
 804         struct mlx4_roce_gid_table gid_table;
 805         int                     base_qpn;
 806 };
 807
 808 struct mlx4_sense {
 809         struct mlx4_dev         *dev;
 810         u8                      do_sense_port[MLX4_MAX_PORTS + 1];
 811         u8                      sense_allowed[MLX4_MAX_PORTS + 1];
 812         struct delayed_work     sense_poll;
 813 };
 814
 815 struct mlx4_msix_ctl {
 816         u64             pool_bm;
 817         struct mutex    pool_lock;
 818 };
 819
 820 struct mlx4_steer {
 821         struct list_head promisc_qps[MLX4_NUM_STEERS];
 822         struct list_head steer_entries[MLX4_NUM_STEERS];
 823 };
 824
 825 enum {
 826         MLX4_PCI_DEV_IS_VF              = 1 << 0,
 827         MLX4_PCI_DEV_FORCE_SENSE_PORT   = 1 << 1,
 828 };
 829
 830 enum {
 831         MLX4_NO_RR      = 0,
 832         MLX4_USE_RR     = 1,
 833 };
 834
 835 struct mlx4_priv {
 836         struct mlx4_dev         dev;
 837
 838         struct list_head        dev_list;
 839         struct list_head        ctx_list;
 840         spinlock_t              ctx_lock;
 841
 842         int                     pci_dev_data;
 843         int                     removed;
 844
 845         struct list_head        pgdir_list;
 846         struct mutex            pgdir_mutex;
 847
 848         struct mlx4_fw          fw;
 849         struct mlx4_cmd         cmd;
 850         struct mlx4_mfunc       mfunc;
 851
 852         struct mlx4_bitmap      pd_bitmap;
 853         struct mlx4_bitmap      xrcd_bitmap;
 854         struct mlx4_uar_table   uar_table;
 855         struct mlx4_mr_table    mr_table;
 856         struct mlx4_cq_table    cq_table;
 857         struct mlx4_eq_table    eq_table;
 858         struct mlx4_srq_table   srq_table;
 859         struct mlx4_qp_table    qp_table;
 860         struct mlx4_mcg_table   mcg_table;
 861         struct mlx4_bitmap      counters_bitmap;
 862
 863         struct mlx4_catas_err   catas_err;
 864
 865         void __iomem           *clr_base;
 866
 867         struct mlx4_uar         driver_uar;
 868         void __iomem           *kar;
 869         struct mlx4_port_info   port[MLX4_MAX_PORTS + 1];
 870         struct mlx4_sense       sense;
 871         struct mutex            port_mutex;
 872         struct mlx4_msix_ctl    msix_ctl;
 873         struct mlx4_steer       *steer;
 874         struct list_head        bf_list;
 875         struct mutex            bf_mutex;
 876         struct io_mapping       *bf_mapping;
 877         void __iomem            *clock_mapping;
 878         int                     reserved_mtts;
 879         int                     fs_hash_mode;
 880         u8 virt2phys_pkey[MLX4_MFUNC_MAX][MLX4_MAX_PORTS][MLX4_MAX_PORT_PKEYS];
 881         __be64                  slave_node_guids[MLX4_MFUNC_MAX];
 882
 883         atomic_t                opreq_count;
 884         struct work_struct      opreq_task;
 885 };
 886
 887 static inline struct mlx4_priv *mlx4_priv(struct mlx4_dev *dev)
 888 {
 889         return container_of(dev, struct mlx4_priv, dev);
 890 }
 891
 892 #define MLX4_SENSE_RANGE        (HZ * 3)
 893
 894 extern struct workqueue_struct *mlx4_wq;
 895
 896 u32 mlx4_bitmap_alloc(struct mlx4_bitmap *bitmap);
 897 void mlx4_bitmap_free(struct mlx4_bitmap *bitmap, u32 obj, int use_rr);
 898 u32 mlx4_bitmap_alloc_range(struct mlx4_bitmap *bitmap, int cnt,
 899                             int align, u32 skip_mask);
 900 void mlx4_bitmap_free_range(struct mlx4_bitmap *bitmap, u32 obj, int cnt,
 901                             int use_rr);
 902 u32 mlx4_bitmap_avail(struct mlx4_bitmap *bitmap);
 903 int mlx4_bitmap_init(struct mlx4_bitmap *bitmap, u32 num, u32 mask,
 904                      u32 reserved_bot, u32 resetrved_top);
 905 void mlx4_bitmap_cleanup(struct mlx4_bitmap *bitmap);
 906
 907 int mlx4_reset(struct mlx4_dev *dev);
 908
 909 int mlx4_alloc_eq_table(struct mlx4_dev *dev);
 910 void mlx4_free_eq_table(struct mlx4_dev *dev);
 911
 912 int mlx4_init_pd_table(struct mlx4_dev *dev);
 913 int mlx4_init_xrcd_table(struct mlx4_dev *dev);
 914 int mlx4_init_uar_table(struct mlx4_dev *dev);
 915 int mlx4_init_mr_table(struct mlx4_dev *dev);
 916 int mlx4_init_eq_table(struct mlx4_dev *dev);
 917 int mlx4_init_cq_table(struct mlx4_dev *dev);
 918 int mlx4_init_qp_table(struct mlx4_dev *dev);
 919 int mlx4_init_srq_table(struct mlx4_dev *dev);
 920 int mlx4_init_mcg_table(struct mlx4_dev *dev);
 921
 922 void mlx4_cleanup_pd_table(struct mlx4_dev *dev);
 923 void mlx4_cleanup_xrcd_table(struct mlx4_dev *dev);
 924 void mlx4_cleanup_uar_table(struct mlx4_dev *dev);
 925 void mlx4_cleanup_mr_table(struct mlx4_dev *dev);
 926 void mlx4_cleanup_eq_table(struct mlx4_dev *dev);
 927 void mlx4_cleanup_cq_table(struct mlx4_dev *dev);
 928 void mlx4_cleanup_qp_table(struct mlx4_dev *dev);
 929 void mlx4_cleanup_srq_table(struct mlx4_dev *dev);
 930 void mlx4_cleanup_mcg_table(struct mlx4_dev *dev);
 931 int __mlx4_qp_alloc_icm(struct mlx4_dev *dev, int qpn, gfp_t gfp);
 932 void __mlx4_qp_free_icm(struct mlx4_dev *dev, int qpn);
 933 int __mlx4_cq_alloc_icm(struct mlx4_dev *dev, int *cqn);
 934 void __mlx4_cq_free_icm(struct mlx4_dev *dev, int cqn);
 935 int __mlx4_srq_alloc_icm(struct mlx4_dev *dev, int *srqn);
 936 void __mlx4_srq_free_icm(struct mlx4_dev *dev, int srqn);
 937 int __mlx4_mpt_reserve(struct mlx4_dev *dev);
 938 void __mlx4_mpt_release(struct mlx4_dev *dev, u32 index);
 939 int __mlx4_mpt_alloc_icm(struct mlx4_dev *dev, u32 index, gfp_t gfp);
 940 void __mlx4_mpt_free_icm(struct mlx4_dev *dev, u32 index);
 941 u32 __mlx4_alloc_mtt_range(struct mlx4_dev *dev, int order);
 942 void __mlx4_free_mtt_range(struct mlx4_dev *dev, u32 first_seg, int order);
 943
 944 int mlx4_WRITE_MTT_wrapper(struct mlx4_dev *dev, int slave,
 945                            struct mlx4_vhcr *vhcr,
 946                            struct mlx4_cmd_mailbox *inbox,
 947                            struct mlx4_cmd_mailbox *outbox,
 948                            struct mlx4_cmd_info *cmd);
 949 int mlx4_SYNC_TPT_wrapper(struct mlx4_dev *dev, int slave,
 950                            struct mlx4_vhcr *vhcr,
 951                            struct mlx4_cmd_mailbox *inbox,
 952                            struct mlx4_cmd_mailbox *outbox,
 953                            struct mlx4_cmd_info *cmd);
 954 int mlx4_SW2HW_MPT_wrapper(struct mlx4_dev *dev, int slave,
 955                            struct mlx4_vhcr *vhcr,
 956                            struct mlx4_cmd_mailbox *inbox,
 957                            struct mlx4_cmd_mailbox *outbox,
 958                            struct mlx4_cmd_info *cmd);
 959 int mlx4_HW2SW_MPT_wrapper(struct mlx4_dev *dev, int slave,
 960                            struct mlx4_vhcr *vhcr,
 961                            struct mlx4_cmd_mailbox *inbox,
 962                            struct mlx4_cmd_mailbox *outbox,
 963                            struct mlx4_cmd_info *cmd);
 964 int mlx4_QUERY_MPT_wrapper(struct mlx4_dev *dev, int slave,
 965                            struct mlx4_vhcr *vhcr,
 966                            struct mlx4_cmd_mailbox *inbox,
 967                            struct mlx4_cmd_mailbox *outbox,
 968                            struct mlx4_cmd_info *cmd);
 969 int mlx4_SW2HW_EQ_wrapper(struct mlx4_dev *dev, int slave,
 970                           struct mlx4_vhcr *vhcr,
 971                           struct mlx4_cmd_mailbox *inbox,
 972                           struct mlx4_cmd_mailbox *outbox,
 973                           struct mlx4_cmd_info *cmd);
 974 int mlx4_CONFIG_DEV_wrapper(struct mlx4_dev *dev, int slave,
 975                             struct mlx4_vhcr *vhcr,
 976                             struct mlx4_cmd_mailbox *inbox,
 977                             struct mlx4_cmd_mailbox *outbox,
 978                             struct mlx4_cmd_info *cmd);
 979 int mlx4_DMA_wrapper(struct mlx4_dev *dev, int slave,
 980                      struct mlx4_vhcr *vhcr,
 981                      struct mlx4_cmd_mailbox *inbox,
 982                      struct mlx4_cmd_mailbox *outbox,
 983                      struct mlx4_cmd_info *cmd);
 984 int __mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align,
 985                             int *base, u8 flags);
 986 void __mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt);
 987 int __mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac);
 988 void __mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac);
 989 int __mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
 990                      int start_index, int npages, u64 *page_list);
 991 int __mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx);
 992 void __mlx4_counter_free(struct mlx4_dev *dev, u32 idx);
 993 int __mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn);
 994 void __mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn);
 995
 996 void mlx4_start_catas_poll(struct mlx4_dev *dev);
 997 void mlx4_stop_catas_poll(struct mlx4_dev *dev);
 998 void mlx4_catas_init(void);
 999 int mlx4_restart_one(struct pci_dev *pdev);
1000 int mlx4_register_device(struct mlx4_dev *dev);
1001 void mlx4_unregister_device(struct mlx4_dev *dev);
1002 void mlx4_dispatch_event(struct mlx4_dev *dev, enum mlx4_dev_event type,
1003                          unsigned long param);
1004
1005 struct mlx4_dev_cap;
1006 struct mlx4_init_hca_param;
1007
1008 u64 mlx4_make_profile(struct mlx4_dev *dev,
1009                       struct mlx4_profile *request,
1010                       struct mlx4_dev_cap *dev_cap,
1011                       struct mlx4_init_hca_param *init_hca);
1012 void mlx4_master_comm_channel(struct work_struct *work);
1013 void mlx4_gen_slave_eqe(struct work_struct *work);
1014 void mlx4_master_handle_slave_flr(struct work_struct *work);
1015
1016 int mlx4_ALLOC_RES_wrapper(struct mlx4_dev *dev, int slave,
1017                            struct mlx4_vhcr *vhcr,
1018                            struct mlx4_cmd_mailbox *inbox,
1019                            struct mlx4_cmd_mailbox *outbox,
1020                            struct mlx4_cmd_info *cmd);
1021 int mlx4_FREE_RES_wrapper(struct mlx4_dev *dev, int slave,
1022                           struct mlx4_vhcr *vhcr,
1023                           struct mlx4_cmd_mailbox *inbox,
1024                           struct mlx4_cmd_mailbox *outbox,
1025                           struct mlx4_cmd_info *cmd);
1026 int mlx4_MAP_EQ_wrapper(struct mlx4_dev *dev, int slave,
1027                         struct mlx4_vhcr *vhcr, struct mlx4_cmd_mailbox *inbox,
1028                         struct mlx4_cmd_mailbox *outbox,
1029                         struct mlx4_cmd_info *cmd);
1030 int mlx4_COMM_INT_wrapper(struct mlx4_dev *dev, int slave,
1031                           struct mlx4_vhcr *vhcr,
1032                           struct mlx4_cmd_mailbox *inbox,
1033                           struct mlx4_cmd_mailbox *outbox,
1034                           struct mlx4_cmd_info *cmd);
1035 int mlx4_HW2SW_EQ_wrapper(struct mlx4_dev *dev, int slave,
1036                             struct mlx4_vhcr *vhcr,
1037                             struct mlx4_cmd_mailbox *inbox,
1038                             struct mlx4_cmd_mailbox *outbox,
1039                           struct mlx4_cmd_info *cmd);
1040 int mlx4_QUERY_EQ_wrapper(struct mlx4_dev *dev, int slave,
1041                           struct mlx4_vhcr *vhcr,
1042                           struct mlx4_cmd_mailbox *inbox,
1043                           struct mlx4_cmd_mailbox *outbox,
1044                           struct mlx4_cmd_info *cmd);
1045 int mlx4_SW2HW_CQ_wrapper(struct mlx4_dev *dev, int slave,
1046                           struct mlx4_vhcr *vhcr,
1047                           struct mlx4_cmd_mailbox *inbox,
1048                           struct mlx4_cmd_mailbox *outbox,
1049                           struct mlx4_cmd_info *cmd);
1050 int mlx4_HW2SW_CQ_wrapper(struct mlx4_dev *dev, int slave,
1051                           struct mlx4_vhcr *vhcr,
1052                           struct mlx4_cmd_mailbox *inbox,
1053                           struct mlx4_cmd_mailbox *outbox,
1054                           struct mlx4_cmd_info *cmd);
1055 int mlx4_QUERY_CQ_wrapper(struct mlx4_dev *dev, int slave,
1056                           struct mlx4_vhcr *vhcr,
1057                           struct mlx4_cmd_mailbox *inbox,
1058                           struct mlx4_cmd_mailbox *outbox,
1059                           struct mlx4_cmd_info *cmd);
1060 int mlx4_MODIFY_CQ_wrapper(struct mlx4_dev *dev, int slave,
1061                           struct mlx4_vhcr *vhcr,
1062                           struct mlx4_cmd_mailbox *inbox,
1063                           struct mlx4_cmd_mailbox *outbox,
1064                            struct mlx4_cmd_info *cmd);
1065 int mlx4_SW2HW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
1066                            struct mlx4_vhcr *vhcr,
1067                            struct mlx4_cmd_mailbox *inbox,
1068                            struct mlx4_cmd_mailbox *outbox,
1069                            struct mlx4_cmd_info *cmd);
1070 int mlx4_HW2SW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
1071                            struct mlx4_vhcr *vhcr,
1072                            struct mlx4_cmd_mailbox *inbox,
1073                            struct mlx4_cmd_mailbox *outbox,
1074                            struct mlx4_cmd_info *cmd);
1075 int mlx4_QUERY_SRQ_wrapper(struct mlx4_dev *dev, int slave,
1076                            struct mlx4_vhcr *vhcr,
1077                            struct mlx4_cmd_mailbox *inbox,
1078                            struct mlx4_cmd_mailbox *outbox,
1079                            struct mlx4_cmd_info *cmd);
1080 int mlx4_ARM_SRQ_wrapper(struct mlx4_dev *dev, int slave,
1081                          struct mlx4_vhcr *vhcr,
1082                          struct mlx4_cmd_mailbox *inbox,
1083                          struct mlx4_cmd_mailbox *outbox,
1084                          struct mlx4_cmd_info *cmd);
1085 int mlx4_GEN_QP_wrapper(struct mlx4_dev *dev, int slave,
1086                         struct mlx4_vhcr *vhcr,
1087                         struct mlx4_cmd_mailbox *inbox,
1088                         struct mlx4_cmd_mailbox *outbox,
1089                         struct mlx4_cmd_info *cmd);
1090 int mlx4_RST2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
1091                              struct mlx4_vhcr *vhcr,
1092                              struct mlx4_cmd_mailbox *inbox,
1093                              struct mlx4_cmd_mailbox *outbox,
1094                              struct mlx4_cmd_info *cmd);
1095 int mlx4_INIT2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
1096                               struct mlx4_vhcr *vhcr,
1097                               struct mlx4_cmd_mailbox *inbox,
1098                               struct mlx4_cmd_mailbox *outbox,
1099                               struct mlx4_cmd_info *cmd);
1100 int mlx4_INIT2RTR_QP_wrapper(struct mlx4_dev *dev, int slave,
1101                              struct mlx4_vhcr *vhcr,
1102                              struct mlx4_cmd_mailbox *inbox,
1103                              struct mlx4_cmd_mailbox *outbox,
1104                              struct mlx4_cmd_info *cmd);
1105 int mlx4_RTR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
1106                             struct mlx4_vhcr *vhcr,
1107                             struct mlx4_cmd_mailbox *inbox,
1108                             struct mlx4_cmd_mailbox *outbox,
1109                             struct mlx4_cmd_info *cmd);
1110 int mlx4_RTS2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
1111                             struct mlx4_vhcr *vhcr,
1112                             struct mlx4_cmd_mailbox *inbox,
1113                             struct mlx4_cmd_mailbox *outbox,
1114                             struct mlx4_cmd_info *cmd);
1115 int mlx4_SQERR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
1116                               struct mlx4_vhcr *vhcr,
1117                               struct mlx4_cmd_mailbox *inbox,
1118                               struct mlx4_cmd_mailbox *outbox,
1119                               struct mlx4_cmd_info *cmd);
1120 int mlx4_2ERR_QP_wrapper(struct mlx4_dev *dev, int slave,
1121                          struct mlx4_vhcr *vhcr,
1122                          struct mlx4_cmd_mailbox *inbox,
1123                          struct mlx4_cmd_mailbox *outbox,
1124                          struct mlx4_cmd_info *cmd);
1125 int mlx4_RTS2SQD_QP_wrapper(struct mlx4_dev *dev, int slave,
1126                             struct mlx4_vhcr *vhcr,
1127                             struct mlx4_cmd_mailbox *inbox,
1128                             struct mlx4_cmd_mailbox *outbox,
1129                             struct mlx4_cmd_info *cmd);
1130 int mlx4_SQD2SQD_QP_wrapper(struct mlx4_dev *dev, int slave,
1131                             struct mlx4_vhcr *vhcr,
1132                             struct mlx4_cmd_mailbox *inbox,
1133                             struct mlx4_cmd_mailbox *outbox,
1134                             struct mlx4_cmd_info *cmd);
1135 int mlx4_SQD2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
1136                             struct mlx4_vhcr *vhcr,
1137                             struct mlx4_cmd_mailbox *inbox,
1138                             struct mlx4_cmd_mailbox *outbox,
1139                             struct mlx4_cmd_info *cmd);
1140 int mlx4_2RST_QP_wrapper(struct mlx4_dev *dev, int slave,
1141                          struct mlx4_vhcr *vhcr,
1142                          struct mlx4_cmd_mailbox *inbox,
1143                          struct mlx4_cmd_mailbox *outbox,
1144                          struct mlx4_cmd_info *cmd);
1145 int mlx4_QUERY_QP_wrapper(struct mlx4_dev *dev, int slave,
1146                           struct mlx4_vhcr *vhcr,
1147                           struct mlx4_cmd_mailbox *inbox,
1148                           struct mlx4_cmd_mailbox *outbox,
1149                           struct mlx4_cmd_info *cmd);
1150
1151 int mlx4_GEN_EQE(struct mlx4_dev *dev, int slave, struct mlx4_eqe *eqe);
1152
1153 enum {
1154         MLX4_CMD_CLEANUP_STRUCT = 1UL << 0,
1155         MLX4_CMD_CLEANUP_POOL   = 1UL << 1,
1156         MLX4_CMD_CLEANUP_HCR    = 1UL << 2,
1157         MLX4_CMD_CLEANUP_VHCR   = 1UL << 3,
1158         MLX4_CMD_CLEANUP_ALL    = (MLX4_CMD_CLEANUP_VHCR << 1) - 1
1159 };
1160
1161 int mlx4_cmd_init(struct mlx4_dev *dev);
1162 void mlx4_cmd_cleanup(struct mlx4_dev *dev, int cleanup_mask);
1163 int mlx4_multi_func_init(struct mlx4_dev *dev);
1164 void mlx4_multi_func_cleanup(struct mlx4_dev *dev);
1165 void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param);
1166 int mlx4_cmd_use_events(struct mlx4_dev *dev);
1167 void mlx4_cmd_use_polling(struct mlx4_dev *dev);
1168
1169 int mlx4_comm_cmd(struct mlx4_dev *dev, u8 cmd, u16 param,
1170                   unsigned long timeout);
1171
1172 void mlx4_cq_tasklet_cb(unsigned long data);
1173 void mlx4_cq_completion(struct mlx4_dev *dev, u32 cqn);
1174 void mlx4_cq_event(struct mlx4_dev *dev, u32 cqn, int event_type);
1175
1176 void mlx4_qp_event(struct mlx4_dev *dev, u32 qpn, int event_type);
1177
1178 void mlx4_srq_event(struct mlx4_dev *dev, u32 srqn, int event_type);
1179
1180 void mlx4_handle_catas_err(struct mlx4_dev *dev);
1181
1182 int mlx4_SENSE_PORT(struct mlx4_dev *dev, int port,
1183                     enum mlx4_port_type *type);
1184 void mlx4_do_sense_ports(struct mlx4_dev *dev,
1185                          enum mlx4_port_type *stype,
1186                          enum mlx4_port_type *defaults);
1187 void mlx4_start_sense(struct mlx4_dev *dev);
1188 void mlx4_stop_sense(struct mlx4_dev *dev);
1189 void mlx4_sense_init(struct mlx4_dev *dev);
1190 int mlx4_check_port_params(struct mlx4_dev *dev,
1191                            enum mlx4_port_type *port_type);
1192 int mlx4_change_port_types(struct mlx4_dev *dev,
1193                            enum mlx4_port_type *port_types);
1194
1195 void mlx4_init_mac_table(struct mlx4_dev *dev, struct mlx4_mac_table *table);
1196 void mlx4_init_vlan_table(struct mlx4_dev *dev, struct mlx4_vlan_table *table);
1197 void mlx4_init_roce_gid_table(struct mlx4_dev *dev,
1198                               struct mlx4_roce_gid_table *table);
1199 void __mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, u16 vlan);
1200 int __mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index);
1201
1202 int mlx4_SET_PORT(struct mlx4_dev *dev, u8 port, int pkey_tbl_sz);
1203 /* resource tracker functions*/
1204 int mlx4_get_slave_from_resource_id(struct mlx4_dev *dev,
1205                                     enum mlx4_resource resource_type,
1206                                     u64 resource_id, int *slave);
1207 void mlx4_delete_all_resources_for_slave(struct mlx4_dev *dev, int slave_id);
1208 void mlx4_reset_roce_gids(struct mlx4_dev *dev, int slave);
1209 int mlx4_init_resource_tracker(struct mlx4_dev *dev);
1210
1211 void mlx4_free_resource_tracker(struct mlx4_dev *dev,
1212                                 enum mlx4_res_tracker_free_type type);
1213
1214 int mlx4_QUERY_FW_wrapper(struct mlx4_dev *dev, int slave,
1215                           struct mlx4_vhcr *vhcr,
1216                           struct mlx4_cmd_mailbox *inbox,
1217                           struct mlx4_cmd_mailbox *outbox,
1218                           struct mlx4_cmd_info *cmd);
1219 int mlx4_SET_PORT_wrapper(struct mlx4_dev *dev, int slave,
1220                           struct mlx4_vhcr *vhcr,
1221                           struct mlx4_cmd_mailbox *inbox,
1222                           struct mlx4_cmd_mailbox *outbox,
1223                           struct mlx4_cmd_info *cmd);
1224 int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave,
1225                            struct mlx4_vhcr *vhcr,
1226                            struct mlx4_cmd_mailbox *inbox,
1227                            struct mlx4_cmd_mailbox *outbox,
1228                            struct mlx4_cmd_info *cmd);
1229 int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave,
1230                             struct mlx4_vhcr *vhcr,
1231                             struct mlx4_cmd_mailbox *inbox,
1232                             struct mlx4_cmd_mailbox *outbox,
1233                             struct mlx4_cmd_info *cmd);
1234 int mlx4_QUERY_DEV_CAP_wrapper(struct mlx4_dev *dev, int slave,
1235                                struct mlx4_vhcr *vhcr,
1236                                struct mlx4_cmd_mailbox *inbox,
1237                                struct mlx4_cmd_mailbox *outbox,
1238                                struct mlx4_cmd_info *cmd);
1239 int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave,
1240                             struct mlx4_vhcr *vhcr,
1241                             struct mlx4_cmd_mailbox *inbox,
1242                             struct mlx4_cmd_mailbox *outbox,
1243                             struct mlx4_cmd_info *cmd);
1244 int mlx4_get_port_ib_caps(struct mlx4_dev *dev, u8 port, __be32 *caps);
1245
1246 int mlx4_get_slave_pkey_gid_tbl_len(struct mlx4_dev *dev, u8 port,
1247                                     int *gid_tbl_len, int *pkey_tbl_len);
1248
1249 int mlx4_QP_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
1250                            struct mlx4_vhcr *vhcr,
1251                            struct mlx4_cmd_mailbox *inbox,
1252                            struct mlx4_cmd_mailbox *outbox,
1253                            struct mlx4_cmd_info *cmd);
1254
1255 int mlx4_UPDATE_QP_wrapper(struct mlx4_dev *dev, int slave,
1256                            struct mlx4_vhcr *vhcr,
1257                            struct mlx4_cmd_mailbox *inbox,
1258                            struct mlx4_cmd_mailbox *outbox,
1259                            struct mlx4_cmd_info *cmd);
1260
1261 int mlx4_PROMISC_wrapper(struct mlx4_dev *dev, int slave,
1262                          struct mlx4_vhcr *vhcr,
1263                          struct mlx4_cmd_mailbox *inbox,
1264                          struct mlx4_cmd_mailbox *outbox,
1265                          struct mlx4_cmd_info *cmd);
1266 int mlx4_qp_detach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1267                           enum mlx4_protocol prot, enum mlx4_steer_type steer);
1268 int mlx4_qp_attach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1269                           int block_mcast_loopback, enum mlx4_protocol prot,
1270                           enum mlx4_steer_type steer);
1271 int mlx4_trans_to_dmfs_attach(struct mlx4_dev *dev, struct mlx4_qp *qp,
1272                               u8 gid[16], u8 port,
1273                               int block_mcast_loopback,
1274                               enum mlx4_protocol prot, u64 *reg_id);
1275 int mlx4_SET_MCAST_FLTR_wrapper(struct mlx4_dev *dev, int slave,
1276                                 struct mlx4_vhcr *vhcr,
1277                                 struct mlx4_cmd_mailbox *inbox,
1278                                 struct mlx4_cmd_mailbox *outbox,
1279                                 struct mlx4_cmd_info *cmd);
1280 int mlx4_SET_VLAN_FLTR_wrapper(struct mlx4_dev *dev, int slave,
1281                                struct mlx4_vhcr *vhcr,
1282                                struct mlx4_cmd_mailbox *inbox,
1283                                struct mlx4_cmd_mailbox *outbox,
1284                                struct mlx4_cmd_info *cmd);
1285 int mlx4_common_set_vlan_fltr(struct mlx4_dev *dev, int function,
1286                                      int port, void *buf);
1287 int mlx4_common_dump_eth_stats(struct mlx4_dev *dev, int slave, u32 in_mod,
1288                                 struct mlx4_cmd_mailbox *outbox);
1289 int mlx4_DUMP_ETH_STATS_wrapper(struct mlx4_dev *dev, int slave,
1290                                    struct mlx4_vhcr *vhcr,
1291                                    struct mlx4_cmd_mailbox *inbox,
1292                                    struct mlx4_cmd_mailbox *outbox,
1293                                 struct mlx4_cmd_info *cmd);
1294 int mlx4_PKEY_TABLE_wrapper(struct mlx4_dev *dev, int slave,
1295                             struct mlx4_vhcr *vhcr,
1296                             struct mlx4_cmd_mailbox *inbox,
1297                             struct mlx4_cmd_mailbox *outbox,
1298                             struct mlx4_cmd_info *cmd);
1299 int mlx4_QUERY_IF_STAT_wrapper(struct mlx4_dev *dev, int slave,
1300                                struct mlx4_vhcr *vhcr,
1301                                struct mlx4_cmd_mailbox *inbox,
1302                                struct mlx4_cmd_mailbox *outbox,
1303                                struct mlx4_cmd_info *cmd);
1304 int mlx4_QP_FLOW_STEERING_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
1305                                          struct mlx4_vhcr *vhcr,
1306                                          struct mlx4_cmd_mailbox *inbox,
1307                                          struct mlx4_cmd_mailbox *outbox,
1308                                          struct mlx4_cmd_info *cmd);
1309 int mlx4_QP_FLOW_STEERING_DETACH_wrapper(struct mlx4_dev *dev, int slave,
1310                                          struct mlx4_vhcr *vhcr,
1311                                          struct mlx4_cmd_mailbox *inbox,
1312                                          struct mlx4_cmd_mailbox *outbox,
1313                                          struct mlx4_cmd_info *cmd);
1314 int mlx4_ACCESS_REG_wrapper(struct mlx4_dev *dev, int slave,
1315                             struct mlx4_vhcr *vhcr,
1316                             struct mlx4_cmd_mailbox *inbox,
1317                             struct mlx4_cmd_mailbox *outbox,
1318                             struct mlx4_cmd_info *cmd);
1319
1320 int mlx4_get_mgm_entry_size(struct mlx4_dev *dev);
1321 int mlx4_get_qp_per_mgm(struct mlx4_dev *dev);
1322
1323 static inline void set_param_l(u64 *arg, u32 val)
1324 {
1325         *arg = (*arg & 0xffffffff00000000ULL) | (u64) val;
1326 }
1327
1328 static inline void set_param_h(u64 *arg, u32 val)
1329 {
1330         *arg = (*arg & 0xffffffff) | ((u64) val << 32);
1331 }
1332
1333 static inline u32 get_param_l(u64 *arg)
1334 {
1335         return (u32) (*arg & 0xffffffff);
1336 }
1337
1338 static inline u32 get_param_h(u64 *arg)
1339 {
1340         return (u32)(*arg >> 32);
1341 }
1342
1343 static inline spinlock_t *mlx4_tlock(struct mlx4_dev *dev)
1344 {
1345         return &mlx4_priv(dev)->mfunc.master.res_tracker.lock;
1346 }
1347
1348 #define NOT_MASKED_PD_BITS 17
1349
1350 void mlx4_vf_immed_vlan_work_handler(struct work_struct *_work);
1351
1352 void mlx4_init_quotas(struct mlx4_dev *dev);
1353
1354 int mlx4_get_slave_num_gids(struct mlx4_dev *dev, int slave, int port);
1355 /* Returns the VF index of slave */
1356 int mlx4_get_vf_indx(struct mlx4_dev *dev, int slave);
1357 int mlx4_config_mad_demux(struct mlx4_dev *dev);
1358
1359 enum mlx4_zone_flags {
1360         MLX4_ZONE_ALLOW_ALLOC_FROM_LOWER_PRIO   = 1UL << 0,
1361         MLX4_ZONE_ALLOW_ALLOC_FROM_EQ_PRIO      = 1UL << 1,
1362         MLX4_ZONE_FALLBACK_TO_HIGHER_PRIO       = 1UL << 2,
1363         MLX4_ZONE_USE_RR                        = 1UL << 3,
1364 };
1365
1366 enum mlx4_zone_alloc_flags {
1367         /* No two objects could overlap between zones. UID
1368          * could be left unused. If this flag is given and
1369          * two overlapped zones are used, an object will be free'd
1370          * from the smallest possible matching zone.
1371          */
1372         MLX4_ZONE_ALLOC_FLAGS_NO_OVERLAP        = 1UL << 0,
1373 };
1374
1375 struct mlx4_zone_allocator;
1376
1377 /* Create a new zone allocator */
1378 struct mlx4_zone_allocator *mlx4_zone_allocator_create(enum mlx4_zone_alloc_flags flags);
1379
1380 /* Attach a mlx4_bitmap <bitmap> of priority <priority> to the zone allocator
1381  * <zone_alloc>. Allocating an object from this zone adds an offset <offset>.
1382  * Similarly, when searching for an object to free, this offset it taken into
1383  * account. The use_rr mlx4_ib parameter for allocating objects from this <bitmap>
1384  * is given through the MLX4_ZONE_USE_RR flag in <flags>.
1385  * When an allocation fails, <zone_alloc> tries to allocate from other zones
1386  * according to the policy set by <flags>. <puid> is the unique identifier
1387  * received to this zone.
1388  */
1389 int mlx4_zone_add_one(struct mlx4_zone_allocator *zone_alloc,
1390                       struct mlx4_bitmap *bitmap,
1391                       u32 flags,
1392                       int priority,
1393                       int offset,
1394                       u32 *puid);
1395
1396 /* Remove bitmap indicated by <uid> from <zone_alloc> */
1397 int mlx4_zone_remove_one(struct mlx4_zone_allocator *zone_alloc, u32 uid);
1398
1399 /* Delete the zone allocator <zone_alloc. This function doesn't destroy
1400  * the attached bitmaps.
1401  */
1402 void mlx4_zone_allocator_destroy(struct mlx4_zone_allocator *zone_alloc);
1403
1404 /* Allocate <count> objects with align <align> and skip_mask <skip_mask>
1405  * from the mlx4_bitmap whose uid is <uid>. The bitmap which we actually
1406  * allocated from is returned in <puid>. If the allocation fails, a negative
1407  * number is returned. Otherwise, the offset of the first object is returned.
1408  */
1409 u32 mlx4_zone_alloc_entries(struct mlx4_zone_allocator *zones, u32 uid, int count,
1410                             int align, u32 skip_mask, u32 *puid);
1411
1412 /* Free <count> objects, start from <obj> of the uid <uid> from zone_allocator
1413  * <zones>.
1414  */
1415 u32 mlx4_zone_free_entries(struct mlx4_zone_allocator *zones,
1416                            u32 uid, u32 obj, u32 count);
1417
1418 /* If <zones> was allocated with MLX4_ZONE_ALLOC_FLAGS_NO_OVERLAP, instead of
1419  * specifying the uid when freeing an object, zone allocator could figure it by
1420  * itself. Other parameters are similar to mlx4_zone_free.
1421  */
1422 u32 mlx4_zone_free_entries_unique(struct mlx4_zone_allocator *zones, u32 obj, u32 count);
1423
1424 /* Returns a pointer to mlx4_bitmap that was attached to <zones> with <uid> */
1425 struct mlx4_bitmap *mlx4_zone_get_bitmap(struct mlx4_zone_allocator *zones, u32 uid);
1426
1427 #endif /* MLX4_H */