drivers/net/ethernet/mellanox/mlx4/mlx4_en.h

   1 /*
   2  * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  *
  32  */
  33
  34 #ifndef _MLX4_EN_H_
  35 #define _MLX4_EN_H_
  36
  37 #include <linux/bitops.h>
  38 #include <linux/compiler.h>
  39 #include <linux/list.h>
  40 #include <linux/mutex.h>
  41 #include <linux/netdevice.h>
  42 #include <linux/if_vlan.h>
  43 #include <linux/net_tstamp.h>
  44 #ifdef CONFIG_MLX4_EN_DCB
  45 #include <linux/dcbnl.h>
  46 #endif
  47 #include <linux/cpu_rmap.h>
  48 #include <linux/ptp_clock_kernel.h>
  49
  50 #include <linux/mlx4/device.h>
  51 #include <linux/mlx4/qp.h>
  52 #include <linux/mlx4/cq.h>
  53 #include <linux/mlx4/srq.h>
  54 #include <linux/mlx4/doorbell.h>
  55 #include <linux/mlx4/cmd.h>
  56
  57 #include "en_port.h"
  58
  59 #define DRV_NAME        "mlx4_en"
  60 #define DRV_VERSION     "2.2-1"
  61 #define DRV_RELDATE     "Feb 2014"
  62
  63 #define MLX4_EN_MSG_LEVEL       (NETIF_MSG_LINK | NETIF_MSG_IFDOWN)
  64
  65 /*
  66  * Device constants
  67  */
  68
  69
  70 #define MLX4_EN_PAGE_SHIFT      12
  71 #define MLX4_EN_PAGE_SIZE       (1 << MLX4_EN_PAGE_SHIFT)
  72 #define DEF_RX_RINGS            16
  73 #define MAX_RX_RINGS            128
  74 #define MIN_RX_RINGS            4
  75 #define TXBB_SIZE               64
  76 #define HEADROOM                (2048 / TXBB_SIZE + 1)
  77 #define STAMP_STRIDE            64
  78 #define STAMP_DWORDS            (STAMP_STRIDE / 4)
  79 #define STAMP_SHIFT             31
  80 #define STAMP_VAL               0x7fffffff
  81 #define STATS_DELAY             (HZ / 4)
  82 #define SERVICE_TASK_DELAY      (HZ / 4)
  83 #define MAX_NUM_OF_FS_RULES     256
  84
  85 #define MLX4_EN_FILTER_HASH_SHIFT 4
  86 #define MLX4_EN_FILTER_EXPIRY_QUOTA 60
  87
  88 /* Typical TSO descriptor with 16 gather entries is 352 bytes... */
  89 #define MAX_DESC_SIZE           512
  90 #define MAX_DESC_TXBBS          (MAX_DESC_SIZE / TXBB_SIZE)
  91
  92 /*
  93  * OS related constants and tunables
  94  */
  95
  96 #define MLX4_EN_WATCHDOG_TIMEOUT        (15 * HZ)
  97
  98 /* Use the maximum between 16384 and a single page */
  99 #define MLX4_EN_ALLOC_SIZE      PAGE_ALIGN(16384)
 100
 101 #define MLX4_EN_ALLOC_PREFER_ORDER      PAGE_ALLOC_COSTLY_ORDER
 102
 103 /* Receive fragment sizes; we use at most 3 fragments (for 9600 byte MTU
 104  * and 4K allocations) */
 105 enum {
 106         FRAG_SZ0 = 1536 - NET_IP_ALIGN,
 107         FRAG_SZ1 = 4096,
 108         FRAG_SZ2 = 4096,
 109         FRAG_SZ3 = MLX4_EN_ALLOC_SIZE
 110 };
 111 #define MLX4_EN_MAX_RX_FRAGS    4
 112
 113 /* Maximum ring sizes */
 114 #define MLX4_EN_MAX_TX_SIZE     8192
 115 #define MLX4_EN_MAX_RX_SIZE     8192
 116
 117 /* Minimum ring size for our page-allocation scheme to work */
 118 #define MLX4_EN_MIN_RX_SIZE     (MLX4_EN_ALLOC_SIZE / SMP_CACHE_BYTES)
 119 #define MLX4_EN_MIN_TX_SIZE     (4096 / TXBB_SIZE)
 120
 121 #define MLX4_EN_SMALL_PKT_SIZE          64
 122 #define MLX4_EN_MAX_TX_RING_P_UP        32
 123 #define MLX4_EN_NUM_UP                  8
 124 #define MLX4_EN_DEF_TX_RING_SIZE        512
 125 #define MLX4_EN_DEF_RX_RING_SIZE        1024
 126 #define MAX_TX_RINGS                    (MLX4_EN_MAX_TX_RING_P_UP * \
 127                                          MLX4_EN_NUM_UP)
 128
 129 /* Target number of packets to coalesce with interrupt moderation */
 130 #define MLX4_EN_RX_COAL_TARGET  44
 131 #define MLX4_EN_RX_COAL_TIME    0x10
 132
 133 #define MLX4_EN_TX_COAL_PKTS    16
 134 #define MLX4_EN_TX_COAL_TIME    0x10
 135
 136 #define MLX4_EN_RX_RATE_LOW             400000
 137 #define MLX4_EN_RX_COAL_TIME_LOW        0
 138 #define MLX4_EN_RX_RATE_HIGH            450000
 139 #define MLX4_EN_RX_COAL_TIME_HIGH       128
 140 #define MLX4_EN_RX_SIZE_THRESH          1024
 141 #define MLX4_EN_RX_RATE_THRESH          (1000000 / MLX4_EN_RX_COAL_TIME_HIGH)
 142 #define MLX4_EN_SAMPLE_INTERVAL         0
 143 #define MLX4_EN_AVG_PKT_SMALL           256
 144
 145 #define MLX4_EN_AUTO_CONF       0xffff
 146
 147 #define MLX4_EN_DEF_RX_PAUSE    1
 148 #define MLX4_EN_DEF_TX_PAUSE    1
 149
 150 /* Interval between successive polls in the Tx routine when polling is used
 151    instead of interrupts (in per-core Tx rings) - should be power of 2 */
 152 #define MLX4_EN_TX_POLL_MODER   16
 153 #define MLX4_EN_TX_POLL_TIMEOUT (HZ / 4)
 154
 155 #define ETH_LLC_SNAP_SIZE       8
 156
 157 #define SMALL_PACKET_SIZE      (256 - NET_IP_ALIGN)
 158 #define HEADER_COPY_SIZE       (128 - NET_IP_ALIGN)
 159 #define MLX4_LOOPBACK_TEST_PAYLOAD (HEADER_COPY_SIZE - ETH_HLEN)
 160
 161 #define MLX4_EN_MIN_MTU         46
 162 #define ETH_BCAST               0xffffffffffffULL
 163
 164 #define MLX4_EN_LOOPBACK_RETRIES        5
 165 #define MLX4_EN_LOOPBACK_TIMEOUT        100
 166
 167 #ifdef MLX4_EN_PERF_STAT
 168 /* Number of samples to 'average' */
 169 #define AVG_SIZE                        128
 170 #define AVG_FACTOR                      1024
 171 #define NUM_PERF_STATS                  NUM_PERF_COUNTERS
 172
 173 #define INC_PERF_COUNTER(cnt)           (++(cnt))
 174 #define ADD_PERF_COUNTER(cnt, add)      ((cnt) += (add))
 175 #define AVG_PERF_COUNTER(cnt, sample) \
 176         ((cnt) = ((cnt) * (AVG_SIZE - 1) + (sample) * AVG_FACTOR) / AVG_SIZE)
 177 #define GET_PERF_COUNTER(cnt)           (cnt)
 178 #define GET_AVG_PERF_COUNTER(cnt)       ((cnt) / AVG_FACTOR)
 179
 180 #else
 181
 182 #define NUM_PERF_STATS                  0
 183 #define INC_PERF_COUNTER(cnt)           do {} while (0)
 184 #define ADD_PERF_COUNTER(cnt, add)      do {} while (0)
 185 #define AVG_PERF_COUNTER(cnt, sample)   do {} while (0)
 186 #define GET_PERF_COUNTER(cnt)           (0)
 187 #define GET_AVG_PERF_COUNTER(cnt)       (0)
 188 #endif /* MLX4_EN_PERF_STAT */
 189
 190 /* Constants for TX flow */
 191 enum {
 192         MAX_INLINE = 104, /* 128 - 16 - 4 - 4 */
 193         MAX_BF = 256,
 194         MIN_PKT_LEN = 17,
 195 };
 196
 197 /*
 198  * Configurables
 199  */
 200
 201 enum cq_type {
 202         RX = 0,
 203         TX = 1,
 204 };
 205
 206
 207 /*
 208  * Useful macros
 209  */
 210 #define ROUNDUP_LOG2(x)         ilog2(roundup_pow_of_two(x))
 211 #define XNOR(x, y)              (!(x) == !(y))
 212
 213
 214 struct mlx4_en_tx_info {
 215         struct sk_buff *skb;
 216         u32 nr_txbb;
 217         u32 nr_bytes;
 218         u8 linear;
 219         u8 data_offset;
 220         u8 inl;
 221         u8 ts_requested;
 222 };
 223
 224
 225 #define MLX4_EN_BIT_DESC_OWN    0x80000000
 226 #define CTRL_SIZE       sizeof(struct mlx4_wqe_ctrl_seg)
 227 #define MLX4_EN_MEMTYPE_PAD     0x100
 228 #define DS_SIZE         sizeof(struct mlx4_wqe_data_seg)
 229
 230
 231 struct mlx4_en_tx_desc {
 232         struct mlx4_wqe_ctrl_seg ctrl;
 233         union {
 234                 struct mlx4_wqe_data_seg data; /* at least one data segment */
 235                 struct mlx4_wqe_lso_seg lso;
 236                 struct mlx4_wqe_inline_seg inl;
 237         };
 238 };
 239
 240 #define MLX4_EN_USE_SRQ         0x01000000
 241
 242 #define MLX4_EN_CX3_LOW_ID      0x1000
 243 #define MLX4_EN_CX3_HIGH_ID     0x1005
 244
 245 struct mlx4_en_rx_alloc {
 246         struct page     *page;
 247         dma_addr_t      dma;
 248         u32             page_offset;
 249         u32             page_size;
 250 };
 251
 252 struct mlx4_en_tx_ring {
 253         struct mlx4_hwq_resources wqres;
 254         u32 size ; /* number of TXBBs */
 255         u32 size_mask;
 256         u16 stride;
 257         u16 cqn;        /* index of port CQ associated with this ring */
 258         u32 prod;
 259         u32 cons;
 260         u32 buf_size;
 261         u32 doorbell_qpn;
 262         void *buf;
 263         u16 poll_cnt;
 264         struct mlx4_en_tx_info *tx_info;
 265         u8 *bounce_buf;
 266         u8 queue_index;
 267         cpumask_t affinity_mask;
 268         u32 last_nr_txbb;
 269         struct mlx4_qp qp;
 270         struct mlx4_qp_context context;
 271         int qpn;
 272         enum mlx4_qp_state qp_state;
 273         struct mlx4_srq dummy;
 274         unsigned long bytes;
 275         unsigned long packets;
 276         unsigned long tx_csum;
 277         unsigned long queue_stopped;
 278         unsigned long wake_queue;
 279         struct mlx4_bf bf;
 280         bool bf_enabled;
 281         struct netdev_queue *tx_queue;
 282         int hwtstamp_tx_type;
 283         int inline_thold;
 284 };
 285
 286 struct mlx4_en_rx_desc {
 287         /* actual number of entries depends on rx ring stride */
 288         struct mlx4_wqe_data_seg data[0];
 289 };
 290
 291 struct mlx4_en_rx_ring {
 292         struct mlx4_hwq_resources wqres;
 293         struct mlx4_en_rx_alloc page_alloc[MLX4_EN_MAX_RX_FRAGS];
 294         u32 size ;      /* number of Rx descs*/
 295         u32 actual_size;
 296         u32 size_mask;
 297         u16 stride;
 298         u16 log_stride;
 299         u16 cqn;        /* index of port CQ associated with this ring */
 300         u32 prod;
 301         u32 cons;
 302         u32 buf_size;
 303         u8  fcs_del;
 304         void *buf;
 305         void *rx_info;
 306         unsigned long bytes;
 307         unsigned long packets;
 308 #ifdef CONFIG_NET_RX_BUSY_POLL
 309         unsigned long yields;
 310         unsigned long misses;
 311         unsigned long cleaned;
 312 #endif
 313         unsigned long csum_ok;
 314         unsigned long csum_none;
 315         int hwtstamp_rx_filter;
 316 };
 317
 318 struct mlx4_en_cq {
 319         struct mlx4_cq          mcq;
 320         struct mlx4_hwq_resources wqres;
 321         int                     ring;
 322         struct net_device      *dev;
 323         struct napi_struct      napi;
 324         int size;
 325         int buf_size;
 326         unsigned vector;
 327         enum cq_type is_tx;
 328         u16 moder_time;
 329         u16 moder_cnt;
 330         struct mlx4_cqe *buf;
 331 #define MLX4_EN_OPCODE_ERROR    0x1e
 332
 333 #ifdef CONFIG_NET_RX_BUSY_POLL
 334         unsigned int state;
 335 #define MLX4_EN_CQ_STATE_IDLE        0
 336 #define MLX4_EN_CQ_STATE_NAPI     1    /* NAPI owns this CQ */
 337 #define MLX4_EN_CQ_STATE_POLL     2    /* poll owns this CQ */
 338 #define MLX4_CQ_LOCKED (MLX4_EN_CQ_STATE_NAPI | MLX4_EN_CQ_STATE_POLL)
 339 #define MLX4_EN_CQ_STATE_NAPI_YIELD  4    /* NAPI yielded this CQ */
 340 #define MLX4_EN_CQ_STATE_POLL_YIELD  8    /* poll yielded this CQ */
 341 #define CQ_YIELD (MLX4_EN_CQ_STATE_NAPI_YIELD | MLX4_EN_CQ_STATE_POLL_YIELD)
 342 #define CQ_USER_PEND (MLX4_EN_CQ_STATE_POLL | MLX4_EN_CQ_STATE_POLL_YIELD)
 343         spinlock_t poll_lock; /* protects from LLS/napi conflicts */
 344 #endif  /* CONFIG_NET_RX_BUSY_POLL */
 345 };
 346
 347 struct mlx4_en_port_profile {
 348         u32 flags;
 349         u32 tx_ring_num;
 350         u32 rx_ring_num;
 351         u32 tx_ring_size;
 352         u32 rx_ring_size;
 353         u8 rx_pause;
 354         u8 rx_ppp;
 355         u8 tx_pause;
 356         u8 tx_ppp;
 357         int rss_rings;
 358         int inline_thold;
 359 };
 360
 361 struct mlx4_en_profile {
 362         int rss_xor;
 363         int udp_rss;
 364         u8 rss_mask;
 365         u32 active_ports;
 366         u32 small_pkt_int;
 367         u8 no_reset;
 368         u8 num_tx_rings_p_up;
 369         struct mlx4_en_port_profile prof[MLX4_MAX_PORTS + 1];
 370 };
 371
 372 struct mlx4_en_dev {
 373         struct mlx4_dev         *dev;
 374         struct pci_dev          *pdev;
 375         struct mutex            state_lock;
 376         struct net_device       *pndev[MLX4_MAX_PORTS + 1];
 377         u32                     port_cnt;
 378         bool                    device_up;
 379         struct mlx4_en_profile  profile;
 380         u32                     LSO_support;
 381         struct workqueue_struct *workqueue;
 382         struct device           *dma_device;
 383         void __iomem            *uar_map;
 384         struct mlx4_uar         priv_uar;
 385         struct mlx4_mr          mr;
 386         u32                     priv_pdn;
 387         spinlock_t              uar_lock;
 388         u8                      mac_removed[MLX4_MAX_PORTS + 1];
 389         rwlock_t                clock_lock;
 390         u32                     nominal_c_mult;
 391         struct cyclecounter     cycles;
 392         struct timecounter      clock;
 393         unsigned long           last_overflow_check;
 394         unsigned long           overflow_period;
 395         struct ptp_clock        *ptp_clock;
 396         struct ptp_clock_info   ptp_clock_info;
 397 };
 398
 399
 400 struct mlx4_en_rss_map {
 401         int base_qpn;
 402         struct mlx4_qp qps[MAX_RX_RINGS];
 403         enum mlx4_qp_state state[MAX_RX_RINGS];
 404         struct mlx4_qp indir_qp;
 405         enum mlx4_qp_state indir_state;
 406 };
 407
 408 struct mlx4_en_port_state {
 409         int link_state;
 410         int link_speed;
 411         int transciver;
 412 };
 413
 414 struct mlx4_en_pkt_stats {
 415         unsigned long broadcast;
 416         unsigned long rx_prio[8];
 417         unsigned long tx_prio[8];
 418 #define NUM_PKT_STATS           17
 419 };
 420
 421 struct mlx4_en_port_stats {
 422         unsigned long tso_packets;
 423         unsigned long queue_stopped;
 424         unsigned long wake_queue;
 425         unsigned long tx_timeout;
 426         unsigned long rx_alloc_failed;
 427         unsigned long rx_chksum_good;
 428         unsigned long rx_chksum_none;
 429         unsigned long tx_chksum_offload;
 430 #define NUM_PORT_STATS          8
 431 };
 432
 433 struct mlx4_en_perf_stats {
 434         u32 tx_poll;
 435         u64 tx_pktsz_avg;
 436         u32 inflight_avg;
 437         u16 tx_coal_avg;
 438         u16 rx_coal_avg;
 439         u32 napi_quota;
 440 #define NUM_PERF_COUNTERS               6
 441 };
 442
 443 enum mlx4_en_mclist_act {
 444         MCLIST_NONE,
 445         MCLIST_REM,
 446         MCLIST_ADD,
 447 };
 448
 449 struct mlx4_en_mc_list {
 450         struct list_head        list;
 451         enum mlx4_en_mclist_act action;
 452         u8                      addr[ETH_ALEN];
 453         u64                     reg_id;
 454         u64                     tunnel_reg_id;
 455 };
 456
 457 struct mlx4_en_frag_info {
 458         u16 frag_size;
 459         u16 frag_prefix_size;
 460         u16 frag_stride;
 461         u16 frag_align;
 462 };
 463
 464 #ifdef CONFIG_MLX4_EN_DCB
 465 /* Minimal TC BW - setting to 0 will block traffic */
 466 #define MLX4_EN_BW_MIN 1
 467 #define MLX4_EN_BW_MAX 100 /* Utilize 100% of the line */
 468
 469 #define MLX4_EN_TC_ETS 7
 470
 471 #endif
 472
 473 struct ethtool_flow_id {
 474         struct list_head list;
 475         struct ethtool_rx_flow_spec flow_spec;
 476         u64 id;
 477 };
 478
 479 enum {
 480         MLX4_EN_FLAG_PROMISC            = (1 << 0),
 481         MLX4_EN_FLAG_MC_PROMISC         = (1 << 1),
 482         /* whether we need to enable hardware loopback by putting dmac
 483          * in Tx WQE
 484          */
 485         MLX4_EN_FLAG_ENABLE_HW_LOOPBACK = (1 << 2),
 486         /* whether we need to drop packets that hardware loopback-ed */
 487         MLX4_EN_FLAG_RX_FILTER_NEEDED   = (1 << 3),
 488         MLX4_EN_FLAG_FORCE_PROMISC      = (1 << 4)
 489 };
 490
 491 #define MLX4_EN_MAC_HASH_SIZE (1 << BITS_PER_BYTE)
 492 #define MLX4_EN_MAC_HASH_IDX 5
 493
 494 struct mlx4_en_priv {
 495         struct mlx4_en_dev *mdev;
 496         struct mlx4_en_port_profile *prof;
 497         struct net_device *dev;
 498         unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
 499         struct net_device_stats stats;
 500         struct net_device_stats ret_stats;
 501         struct mlx4_en_port_state port_state;
 502         spinlock_t stats_lock;
 503         struct ethtool_flow_id ethtool_rules[MAX_NUM_OF_FS_RULES];
 504         /* To allow rules removal while port is going down */
 505         struct list_head ethtool_list;
 506
 507         unsigned long last_moder_packets[MAX_RX_RINGS];
 508         unsigned long last_moder_tx_packets;
 509         unsigned long last_moder_bytes[MAX_RX_RINGS];
 510         unsigned long last_moder_jiffies;
 511         int last_moder_time[MAX_RX_RINGS];
 512         u16 rx_usecs;
 513         u16 rx_frames;
 514         u16 tx_usecs;
 515         u16 tx_frames;
 516         u32 pkt_rate_low;
 517         u16 rx_usecs_low;
 518         u32 pkt_rate_high;
 519         u16 rx_usecs_high;
 520         u16 sample_interval;
 521         u16 adaptive_rx_coal;
 522         u32 msg_enable;
 523         u32 loopback_ok;
 524         u32 validate_loopback;
 525
 526         struct mlx4_hwq_resources res;
 527         int link_state;
 528         int last_link_state;
 529         bool port_up;
 530         int port;
 531         int registered;
 532         int allocated;
 533         int stride;
 534         unsigned char prev_mac[ETH_ALEN + 2];
 535         int mac_index;
 536         unsigned max_mtu;
 537         int base_qpn;
 538         int cqe_factor;
 539
 540         struct mlx4_en_rss_map rss_map;
 541         __be32 ctrl_flags;
 542         u32 flags;
 543         u8 num_tx_rings_p_up;
 544         u32 tx_ring_num;
 545         u32 rx_ring_num;
 546         u32 rx_skb_size;
 547         struct mlx4_en_frag_info frag_info[MLX4_EN_MAX_RX_FRAGS];
 548         u16 num_frags;
 549         u16 log_rx_info;
 550
 551         struct mlx4_en_tx_ring **tx_ring;
 552         struct mlx4_en_rx_ring *rx_ring[MAX_RX_RINGS];
 553         struct mlx4_en_cq **tx_cq;
 554         struct mlx4_en_cq *rx_cq[MAX_RX_RINGS];
 555         struct mlx4_qp drop_qp;
 556         struct work_struct rx_mode_task;
 557         struct work_struct watchdog_task;
 558         struct work_struct linkstate_task;
 559         struct delayed_work stats_task;
 560         struct delayed_work service_task;
 561 #ifdef CONFIG_MLX4_EN_VXLAN
 562         struct work_struct vxlan_add_task;
 563         struct work_struct vxlan_del_task;
 564 #endif
 565         struct mlx4_en_perf_stats pstats;
 566         struct mlx4_en_pkt_stats pkstats;
 567         struct mlx4_en_port_stats port_stats;
 568         u64 stats_bitmap;
 569         struct list_head mc_list;
 570         struct list_head curr_list;
 571         u64 broadcast_id;
 572         struct mlx4_en_stat_out_mbox hw_stats;
 573         int vids[128];
 574         bool wol;
 575         struct device *ddev;
 576         int base_tx_qpn;
 577         struct hlist_head mac_hash[MLX4_EN_MAC_HASH_SIZE];
 578         struct hwtstamp_config hwtstamp_config;
 579
 580 #ifdef CONFIG_MLX4_EN_DCB
 581         struct ieee_ets ets;
 582         u16 maxrate[IEEE_8021QAZ_MAX_TCS];
 583 #endif
 584 #ifdef CONFIG_RFS_ACCEL
 585         spinlock_t filters_lock;
 586         int last_filter_id;
 587         struct list_head filters;
 588         struct hlist_head filter_hash[1 << MLX4_EN_FILTER_HASH_SHIFT];
 589 #endif
 590         u64 tunnel_reg_id;
 591         __be16 vxlan_port;
 592 };
 593
 594 enum mlx4_en_wol {
 595         MLX4_EN_WOL_MAGIC = (1ULL << 61),
 596         MLX4_EN_WOL_ENABLED = (1ULL << 62),
 597 };
 598
 599 struct mlx4_mac_entry {
 600         struct hlist_node hlist;
 601         unsigned char mac[ETH_ALEN + 2];
 602         u64 reg_id;
 603         struct rcu_head rcu;
 604 };
 605
 606 #ifdef CONFIG_NET_RX_BUSY_POLL
 607 static inline void mlx4_en_cq_init_lock(struct mlx4_en_cq *cq)
 608 {
 609         spin_lock_init(&cq->poll_lock);
 610         cq->state = MLX4_EN_CQ_STATE_IDLE;
 611 }
 612
 613 /* called from the device poll rutine to get ownership of a cq */
 614 static inline bool mlx4_en_cq_lock_napi(struct mlx4_en_cq *cq)
 615 {
 616         int rc = true;
 617         spin_lock(&cq->poll_lock);
 618         if (cq->state & MLX4_CQ_LOCKED) {
 619                 WARN_ON(cq->state & MLX4_EN_CQ_STATE_NAPI);
 620                 cq->state |= MLX4_EN_CQ_STATE_NAPI_YIELD;
 621                 rc = false;
 622         } else
 623                 /* we don't care if someone yielded */
 624                 cq->state = MLX4_EN_CQ_STATE_NAPI;
 625         spin_unlock(&cq->poll_lock);
 626         return rc;
 627 }
 628
 629 /* returns true is someone tried to get the cq while napi had it */
 630 static inline bool mlx4_en_cq_unlock_napi(struct mlx4_en_cq *cq)
 631 {
 632         int rc = false;
 633         spin_lock(&cq->poll_lock);
 634         WARN_ON(cq->state & (MLX4_EN_CQ_STATE_POLL |
 635                                MLX4_EN_CQ_STATE_NAPI_YIELD));
 636
 637         if (cq->state & MLX4_EN_CQ_STATE_POLL_YIELD)
 638                 rc = true;
 639         cq->state = MLX4_EN_CQ_STATE_IDLE;
 640         spin_unlock(&cq->poll_lock);
 641         return rc;
 642 }
 643
 644 /* called from mlx4_en_low_latency_poll() */
 645 static inline bool mlx4_en_cq_lock_poll(struct mlx4_en_cq *cq)
 646 {
 647         int rc = true;
 648         spin_lock_bh(&cq->poll_lock);
 649         if ((cq->state & MLX4_CQ_LOCKED)) {
 650                 struct net_device *dev = cq->dev;
 651                 struct mlx4_en_priv *priv = netdev_priv(dev);
 652                 struct mlx4_en_rx_ring *rx_ring = priv->rx_ring[cq->ring];
 653
 654                 cq->state |= MLX4_EN_CQ_STATE_POLL_YIELD;
 655                 rc = false;
 656                 rx_ring->yields++;
 657         } else
 658                 /* preserve yield marks */
 659                 cq->state |= MLX4_EN_CQ_STATE_POLL;
 660         spin_unlock_bh(&cq->poll_lock);
 661         return rc;
 662 }
 663
 664 /* returns true if someone tried to get the cq while it was locked */
 665 static inline bool mlx4_en_cq_unlock_poll(struct mlx4_en_cq *cq)
 666 {
 667         int rc = false;
 668         spin_lock_bh(&cq->poll_lock);
 669         WARN_ON(cq->state & (MLX4_EN_CQ_STATE_NAPI));
 670
 671         if (cq->state & MLX4_EN_CQ_STATE_POLL_YIELD)
 672                 rc = true;
 673         cq->state = MLX4_EN_CQ_STATE_IDLE;
 674         spin_unlock_bh(&cq->poll_lock);
 675         return rc;
 676 }
 677
 678 /* true if a socket is polling, even if it did not get the lock */
 679 static inline bool mlx4_en_cq_busy_polling(struct mlx4_en_cq *cq)
 680 {
 681         WARN_ON(!(cq->state & MLX4_CQ_LOCKED));
 682         return cq->state & CQ_USER_PEND;
 683 }
 684 #else
 685 static inline void mlx4_en_cq_init_lock(struct mlx4_en_cq *cq)
 686 {
 687 }
 688
 689 static inline bool mlx4_en_cq_lock_napi(struct mlx4_en_cq *cq)
 690 {
 691         return true;
 692 }
 693
 694 static inline bool mlx4_en_cq_unlock_napi(struct mlx4_en_cq *cq)
 695 {
 696         return false;
 697 }
 698
 699 static inline bool mlx4_en_cq_lock_poll(struct mlx4_en_cq *cq)
 700 {
 701         return false;
 702 }
 703
 704 static inline bool mlx4_en_cq_unlock_poll(struct mlx4_en_cq *cq)
 705 {
 706         return false;
 707 }
 708
 709 static inline bool mlx4_en_cq_busy_polling(struct mlx4_en_cq *cq)
 710 {
 711         return false;
 712 }
 713 #endif /* CONFIG_NET_RX_BUSY_POLL */
 714
 715 #define MLX4_EN_WOL_DO_MODIFY (1ULL << 63)
 716
 717 void mlx4_en_update_loopback_state(struct net_device *dev,
 718                                    netdev_features_t features);
 719
 720 void mlx4_en_destroy_netdev(struct net_device *dev);
 721 int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port,
 722                         struct mlx4_en_port_profile *prof);
 723
 724 int mlx4_en_start_port(struct net_device *dev);
 725 void mlx4_en_stop_port(struct net_device *dev, int detach);
 726
 727 void mlx4_en_free_resources(struct mlx4_en_priv *priv);
 728 int mlx4_en_alloc_resources(struct mlx4_en_priv *priv);
 729
 730 int mlx4_en_create_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq **pcq,
 731                       int entries, int ring, enum cq_type mode, int node);
 732 void mlx4_en_destroy_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq **pcq);
 733 int mlx4_en_activate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq,
 734                         int cq_idx);
 735 void mlx4_en_deactivate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
 736 int mlx4_en_set_cq_moder(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
 737 int mlx4_en_arm_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
 738
 739 void mlx4_en_tx_irq(struct mlx4_cq *mcq);
 740 u16 mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb,
 741                          void *accel_priv, select_queue_fallback_t fallback);
 742 netdev_tx_t mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev);
 743
 744 int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv,
 745                            struct mlx4_en_tx_ring **pring,
 746                            int qpn, u32 size, u16 stride,
 747                            int node, int queue_index);
 748 void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv,
 749                              struct mlx4_en_tx_ring **pring);
 750 int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv,
 751                              struct mlx4_en_tx_ring *ring,
 752                              int cq, int user_prio);
 753 void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv,
 754                                 struct mlx4_en_tx_ring *ring);
 755 void mlx4_en_set_num_rx_rings(struct mlx4_en_dev *mdev);
 756 int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv,
 757                            struct mlx4_en_rx_ring **pring,
 758                            u32 size, u16 stride, int node);
 759 void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv,
 760                              struct mlx4_en_rx_ring **pring,
 761                              u32 size, u16 stride);
 762 int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv);
 763 void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv,
 764                                 struct mlx4_en_rx_ring *ring);
 765 int mlx4_en_process_rx_cq(struct net_device *dev,
 766                           struct mlx4_en_cq *cq,
 767                           int budget);
 768 int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget);
 769 int mlx4_en_poll_tx_cq(struct napi_struct *napi, int budget);
 770 void mlx4_en_fill_qp_context(struct mlx4_en_priv *priv, int size, int stride,
 771                 int is_tx, int rss, int qpn, int cqn, int user_prio,
 772                 struct mlx4_qp_context *context);
 773 void mlx4_en_sqp_event(struct mlx4_qp *qp, enum mlx4_event event);
 774 int mlx4_en_map_buffer(struct mlx4_buf *buf);
 775 void mlx4_en_unmap_buffer(struct mlx4_buf *buf);
 776
 777 void mlx4_en_calc_rx_buf(struct net_device *dev);
 778 int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv);
 779 void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv);
 780 int mlx4_en_create_drop_qp(struct mlx4_en_priv *priv);
 781 void mlx4_en_destroy_drop_qp(struct mlx4_en_priv *priv);
 782 int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring);
 783 void mlx4_en_rx_irq(struct mlx4_cq *mcq);
 784
 785 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode);
 786 int mlx4_SET_VLAN_FLTR(struct mlx4_dev *dev, struct mlx4_en_priv *priv);
 787
 788 int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev *mdev, u8 port, u8 reset);
 789 int mlx4_en_QUERY_PORT(struct mlx4_en_dev *mdev, u8 port);
 790
 791 #ifdef CONFIG_MLX4_EN_DCB
 792 extern const struct dcbnl_rtnl_ops mlx4_en_dcbnl_ops;
 793 extern const struct dcbnl_rtnl_ops mlx4_en_dcbnl_pfc_ops;
 794 #endif
 795
 796 int mlx4_en_setup_tc(struct net_device *dev, u8 up);
 797
 798 #ifdef CONFIG_RFS_ACCEL
 799 void mlx4_en_cleanup_filters(struct mlx4_en_priv *priv);
 800 #endif
 801
 802 #define MLX4_EN_NUM_SELF_TEST   5
 803 void mlx4_en_ex_selftest(struct net_device *dev, u32 *flags, u64 *buf);
 804 void mlx4_en_ptp_overflow_check(struct mlx4_en_dev *mdev);
 805
 806 /*
 807  * Functions for time stamping
 808  */
 809 u64 mlx4_en_get_cqe_ts(struct mlx4_cqe *cqe);
 810 void mlx4_en_fill_hwtstamps(struct mlx4_en_dev *mdev,
 811                             struct skb_shared_hwtstamps *hwts,
 812                             u64 timestamp);
 813 void mlx4_en_init_timestamp(struct mlx4_en_dev *mdev);
 814 void mlx4_en_remove_timestamp(struct mlx4_en_dev *mdev);
 815 int mlx4_en_timestamp_config(struct net_device *dev,
 816                              int tx_type,
 817                              int rx_filter);
 818
 819 /* Globals
 820  */
 821 extern const struct ethtool_ops mlx4_en_ethtool_ops;
 822
 823
 824
 825 /*
 826  * printk / logging functions
 827  */
 828
 829 __printf(3, 4)
 830 int en_print(const char *level, const struct mlx4_en_priv *priv,
 831              const char *format, ...);
 832
 833 #define en_dbg(mlevel, priv, format, arg...)                    \
 834 do {                                                            \
 835         if (NETIF_MSG_##mlevel & priv->msg_enable)              \
 836                 en_print(KERN_DEBUG, priv, format, ##arg);      \
 837 } while (0)
 838 #define en_warn(priv, format, arg...)                   \
 839         en_print(KERN_WARNING, priv, format, ##arg)
 840 #define en_err(priv, format, arg...)                    \
 841         en_print(KERN_ERR, priv, format, ##arg)
 842 #define en_info(priv, format, arg...)                   \
 843         en_print(KERN_INFO, priv, format, ## arg)
 844
 845 #define mlx4_err(mdev, format, arg...)                  \
 846         pr_err("%s %s: " format, DRV_NAME,              \
 847                dev_name(&mdev->pdev->dev), ##arg)
 848 #define mlx4_info(mdev, format, arg...)                 \
 849         pr_info("%s %s: " format, DRV_NAME,             \
 850                 dev_name(&mdev->pdev->dev), ##arg)
 851 #define mlx4_warn(mdev, format, arg...)                 \
 852         pr_warning("%s %s: " format, DRV_NAME,          \
 853                    dev_name(&mdev->pdev->dev), ##arg)
 854
 855 #endif