2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
37 #include <linux/bitops.h>
38 #include <linux/compiler.h>
39 #include <linux/list.h>
40 #include <linux/mutex.h>
41 #include <linux/netdevice.h>
42 #include <linux/if_vlan.h>
43 #ifdef CONFIG_MLX4_EN_DCB
44 #include <linux/dcbnl.h>
47 #include <linux/mlx4/device.h>
48 #include <linux/mlx4/qp.h>
49 #include <linux/mlx4/cq.h>
50 #include <linux/mlx4/srq.h>
51 #include <linux/mlx4/doorbell.h>
52 #include <linux/mlx4/cmd.h>
56 #define DRV_NAME "mlx4_en"
57 #define DRV_VERSION "2.0"
58 #define DRV_RELDATE "Dec 2011"
60 #define MLX4_EN_MSG_LEVEL (NETIF_MSG_LINK | NETIF_MSG_IFDOWN)
67 #define MLX4_EN_PAGE_SHIFT 12
68 #define MLX4_EN_PAGE_SIZE (1 << MLX4_EN_PAGE_SHIFT)
69 #define MAX_RX_RINGS 16
70 #define MIN_RX_RINGS 4
72 #define HEADROOM (2048 / TXBB_SIZE + 1)
73 #define STAMP_STRIDE 64
74 #define STAMP_DWORDS (STAMP_STRIDE / 4)
75 #define STAMP_SHIFT 31
76 #define STAMP_VAL 0x7fffffff
77 #define STATS_DELAY (HZ / 4)
79 /* Typical TSO descriptor with 16 gather entries is 352 bytes... */
80 #define MAX_DESC_SIZE 512
81 #define MAX_DESC_TXBBS (MAX_DESC_SIZE / TXBB_SIZE)
84 * OS related constants and tunables
87 #define MLX4_EN_WATCHDOG_TIMEOUT (15 * HZ)
89 /* Use the maximum between 16384 and a single page */
90 #define MLX4_EN_ALLOC_SIZE PAGE_ALIGN(16384)
91 #define MLX4_EN_ALLOC_ORDER get_order(MLX4_EN_ALLOC_SIZE)
93 #define MLX4_EN_MAX_LRO_DESCRIPTORS 32
95 /* Receive fragment sizes; we use at most 4 fragments (for 9600 byte MTU
96 * and 4K allocations) */
98 FRAG_SZ0
= 512 - NET_IP_ALIGN
,
101 FRAG_SZ3
= MLX4_EN_ALLOC_SIZE
103 #define MLX4_EN_MAX_RX_FRAGS 4
105 /* Maximum ring sizes */
106 #define MLX4_EN_MAX_TX_SIZE 8192
107 #define MLX4_EN_MAX_RX_SIZE 8192
109 /* Minimum ring size for our page-allocation sceme to work */
110 #define MLX4_EN_MIN_RX_SIZE (MLX4_EN_ALLOC_SIZE / SMP_CACHE_BYTES)
111 #define MLX4_EN_MIN_TX_SIZE (4096 / TXBB_SIZE)
113 #define MLX4_EN_SMALL_PKT_SIZE 64
114 #define MLX4_EN_MAX_TX_RING_P_UP 32
115 #define MLX4_EN_NUM_UP 8
116 #define MLX4_EN_DEF_TX_RING_SIZE 512
117 #define MLX4_EN_DEF_RX_RING_SIZE 1024
119 /* Target number of packets to coalesce with interrupt moderation */
120 #define MLX4_EN_RX_COAL_TARGET 44
121 #define MLX4_EN_RX_COAL_TIME 0x10
123 #define MLX4_EN_TX_COAL_PKTS 16
124 #define MLX4_EN_TX_COAL_TIME 0x80
126 #define MLX4_EN_RX_RATE_LOW 400000
127 #define MLX4_EN_RX_COAL_TIME_LOW 0
128 #define MLX4_EN_RX_RATE_HIGH 450000
129 #define MLX4_EN_RX_COAL_TIME_HIGH 128
130 #define MLX4_EN_RX_SIZE_THRESH 1024
131 #define MLX4_EN_RX_RATE_THRESH (1000000 / MLX4_EN_RX_COAL_TIME_HIGH)
132 #define MLX4_EN_SAMPLE_INTERVAL 0
133 #define MLX4_EN_AVG_PKT_SMALL 256
135 #define MLX4_EN_AUTO_CONF 0xffff
137 #define MLX4_EN_DEF_RX_PAUSE 1
138 #define MLX4_EN_DEF_TX_PAUSE 1
140 /* Interval between successive polls in the Tx routine when polling is used
141 instead of interrupts (in per-core Tx rings) - should be power of 2 */
142 #define MLX4_EN_TX_POLL_MODER 16
143 #define MLX4_EN_TX_POLL_TIMEOUT (HZ / 4)
145 #define ETH_LLC_SNAP_SIZE 8
147 #define SMALL_PACKET_SIZE (256 - NET_IP_ALIGN)
148 #define HEADER_COPY_SIZE (128 - NET_IP_ALIGN)
149 #define MLX4_LOOPBACK_TEST_PAYLOAD (HEADER_COPY_SIZE - ETH_HLEN)
151 #define MLX4_EN_MIN_MTU 46
152 #define ETH_BCAST 0xffffffffffffULL
154 #define MLX4_EN_LOOPBACK_RETRIES 5
155 #define MLX4_EN_LOOPBACK_TIMEOUT 100
157 #ifdef MLX4_EN_PERF_STAT
158 /* Number of samples to 'average' */
160 #define AVG_FACTOR 1024
161 #define NUM_PERF_STATS NUM_PERF_COUNTERS
163 #define INC_PERF_COUNTER(cnt) (++(cnt))
164 #define ADD_PERF_COUNTER(cnt, add) ((cnt) += (add))
165 #define AVG_PERF_COUNTER(cnt, sample) \
166 ((cnt) = ((cnt) * (AVG_SIZE - 1) + (sample) * AVG_FACTOR) / AVG_SIZE)
167 #define GET_PERF_COUNTER(cnt) (cnt)
168 #define GET_AVG_PERF_COUNTER(cnt) ((cnt) / AVG_FACTOR)
172 #define NUM_PERF_STATS 0
173 #define INC_PERF_COUNTER(cnt) do {} while (0)
174 #define ADD_PERF_COUNTER(cnt, add) do {} while (0)
175 #define AVG_PERF_COUNTER(cnt, sample) do {} while (0)
176 #define GET_PERF_COUNTER(cnt) (0)
177 #define GET_AVG_PERF_COUNTER(cnt) (0)
178 #endif /* MLX4_EN_PERF_STAT */
193 #define ROUNDUP_LOG2(x) ilog2(roundup_pow_of_two(x))
194 #define XNOR(x, y) (!(x) == !(y))
195 #define ILLEGAL_MAC(addr) (addr == 0xffffffffffffULL || addr == 0x0)
198 struct mlx4_en_tx_info
{
208 #define MLX4_EN_BIT_DESC_OWN 0x80000000
209 #define CTRL_SIZE sizeof(struct mlx4_wqe_ctrl_seg)
210 #define MLX4_EN_MEMTYPE_PAD 0x100
211 #define DS_SIZE sizeof(struct mlx4_wqe_data_seg)
214 struct mlx4_en_tx_desc
{
215 struct mlx4_wqe_ctrl_seg ctrl
;
217 struct mlx4_wqe_data_seg data
; /* at least one data segment */
218 struct mlx4_wqe_lso_seg lso
;
219 struct mlx4_wqe_inline_seg inl
;
223 #define MLX4_EN_USE_SRQ 0x01000000
225 #define MLX4_EN_CX3_LOW_ID 0x1000
226 #define MLX4_EN_CX3_HIGH_ID 0x1005
228 struct mlx4_en_rx_alloc
{
233 struct mlx4_en_tx_ring
{
234 struct mlx4_hwq_resources wqres
;
235 u32 size
; /* number of TXBBs */
238 u16 cqn
; /* index of port CQ associated with this ring */
246 struct mlx4_en_tx_info
*tx_info
;
250 struct mlx4_qp_context context
;
252 enum mlx4_qp_state qp_state
;
253 struct mlx4_srq dummy
;
255 unsigned long packets
;
256 unsigned long tx_csum
;
259 struct netdev_queue
*tx_queue
;
262 struct mlx4_en_rx_desc
{
263 /* actual number of entries depends on rx ring stride */
264 struct mlx4_wqe_data_seg data
[0];
267 struct mlx4_en_rx_ring
{
268 struct mlx4_hwq_resources wqres
;
269 struct mlx4_en_rx_alloc page_alloc
[MLX4_EN_MAX_RX_FRAGS
];
270 u32 size
; /* number of Rx descs*/
275 u16 cqn
; /* index of port CQ associated with this ring */
283 unsigned long packets
;
284 unsigned long csum_ok
;
285 unsigned long csum_none
;
289 static inline int mlx4_en_can_lro(__be16 status
)
291 return (status
& cpu_to_be16(MLX4_CQE_STATUS_IPV4
|
292 MLX4_CQE_STATUS_IPV4F
|
293 MLX4_CQE_STATUS_IPV6
|
294 MLX4_CQE_STATUS_IPV4OPT
|
295 MLX4_CQE_STATUS_TCP
|
296 MLX4_CQE_STATUS_UDP
|
297 MLX4_CQE_STATUS_IPOK
)) ==
298 cpu_to_be16(MLX4_CQE_STATUS_IPV4
|
299 MLX4_CQE_STATUS_IPOK
|
300 MLX4_CQE_STATUS_TCP
);
305 struct mlx4_hwq_resources wqres
;
308 struct net_device
*dev
;
309 struct napi_struct napi
;
316 struct mlx4_cqe
*buf
;
317 #define MLX4_EN_OPCODE_ERROR 0x1e
320 struct mlx4_en_port_profile
{
333 struct mlx4_en_profile
{
340 u8 num_tx_rings_p_up
;
341 struct mlx4_en_port_profile prof
[MLX4_MAX_PORTS
+ 1];
345 struct mlx4_dev
*dev
;
346 struct pci_dev
*pdev
;
347 struct mutex state_lock
;
348 struct net_device
*pndev
[MLX4_MAX_PORTS
+ 1];
351 struct mlx4_en_profile profile
;
353 struct workqueue_struct
*workqueue
;
354 struct device
*dma_device
;
355 void __iomem
*uar_map
;
356 struct mlx4_uar priv_uar
;
360 u8 mac_removed
[MLX4_MAX_PORTS
+ 1];
364 struct mlx4_en_rss_map
{
366 struct mlx4_qp qps
[MAX_RX_RINGS
];
367 enum mlx4_qp_state state
[MAX_RX_RINGS
];
368 struct mlx4_qp indir_qp
;
369 enum mlx4_qp_state indir_state
;
372 struct mlx4_en_port_state
{
378 struct mlx4_en_pkt_stats
{
379 unsigned long broadcast
;
380 unsigned long rx_prio
[8];
381 unsigned long tx_prio
[8];
382 #define NUM_PKT_STATS 17
385 struct mlx4_en_port_stats
{
386 unsigned long tso_packets
;
387 unsigned long queue_stopped
;
388 unsigned long wake_queue
;
389 unsigned long tx_timeout
;
390 unsigned long rx_alloc_failed
;
391 unsigned long rx_chksum_good
;
392 unsigned long rx_chksum_none
;
393 unsigned long tx_chksum_offload
;
394 #define NUM_PORT_STATS 8
397 struct mlx4_en_perf_stats
{
404 #define NUM_PERF_COUNTERS 6
407 struct mlx4_en_frag_info
{
409 u16 frag_prefix_size
;
416 #ifdef CONFIG_MLX4_EN_DCB
417 /* Minimal TC BW - setting to 0 will block traffic */
418 #define MLX4_EN_BW_MIN 1
419 #define MLX4_EN_BW_MAX 100 /* Utilize 100% of the line */
421 #define MLX4_EN_TC_ETS 7
425 struct mlx4_en_priv
{
426 struct mlx4_en_dev
*mdev
;
427 struct mlx4_en_port_profile
*prof
;
428 struct net_device
*dev
;
429 unsigned long active_vlans
[BITS_TO_LONGS(VLAN_N_VID
)];
430 struct net_device_stats stats
;
431 struct net_device_stats ret_stats
;
432 struct mlx4_en_port_state port_state
;
433 spinlock_t stats_lock
;
435 unsigned long last_moder_packets
[MAX_RX_RINGS
];
436 unsigned long last_moder_tx_packets
;
437 unsigned long last_moder_bytes
[MAX_RX_RINGS
];
438 unsigned long last_moder_jiffies
;
439 int last_moder_time
[MAX_RX_RINGS
];
449 u16 adaptive_rx_coal
;
452 u32 validate_loopback
;
454 struct mlx4_hwq_resources res
;
467 struct mlx4_en_rss_map rss_map
;
470 #define MLX4_EN_FLAG_PROMISC 0x1
471 #define MLX4_EN_FLAG_MC_PROMISC 0x2
475 struct mlx4_en_frag_info frag_info
[MLX4_EN_MAX_RX_FRAGS
];
479 struct mlx4_en_tx_ring
*tx_ring
;
480 struct mlx4_en_rx_ring rx_ring
[MAX_RX_RINGS
];
481 struct mlx4_en_cq
*tx_cq
;
482 struct mlx4_en_cq rx_cq
[MAX_RX_RINGS
];
483 struct work_struct mcast_task
;
484 struct work_struct mac_task
;
485 struct work_struct watchdog_task
;
486 struct work_struct linkstate_task
;
487 struct delayed_work stats_task
;
488 struct mlx4_en_perf_stats pstats
;
489 struct mlx4_en_pkt_stats pkstats
;
490 struct mlx4_en_port_stats port_stats
;
494 struct mlx4_en_stat_out_mbox hw_stats
;
499 #ifdef CONFIG_MLX4_EN_DCB
501 u16 maxrate
[IEEE_8021QAZ_MAX_TCS
];
506 MLX4_EN_WOL_MAGIC
= (1ULL << 61),
507 MLX4_EN_WOL_ENABLED
= (1ULL << 62),
510 #define MLX4_EN_WOL_DO_MODIFY (1ULL << 63)
512 void mlx4_en_destroy_netdev(struct net_device
*dev
);
513 int mlx4_en_init_netdev(struct mlx4_en_dev
*mdev
, int port
,
514 struct mlx4_en_port_profile
*prof
);
516 int mlx4_en_start_port(struct net_device
*dev
);
517 void mlx4_en_stop_port(struct net_device
*dev
);
519 void mlx4_en_free_resources(struct mlx4_en_priv
*priv
);
520 int mlx4_en_alloc_resources(struct mlx4_en_priv
*priv
);
522 int mlx4_en_create_cq(struct mlx4_en_priv
*priv
, struct mlx4_en_cq
*cq
,
523 int entries
, int ring
, enum cq_type mode
);
524 void mlx4_en_destroy_cq(struct mlx4_en_priv
*priv
, struct mlx4_en_cq
*cq
);
525 int mlx4_en_activate_cq(struct mlx4_en_priv
*priv
, struct mlx4_en_cq
*cq
,
527 void mlx4_en_deactivate_cq(struct mlx4_en_priv
*priv
, struct mlx4_en_cq
*cq
);
528 int mlx4_en_set_cq_moder(struct mlx4_en_priv
*priv
, struct mlx4_en_cq
*cq
);
529 int mlx4_en_arm_cq(struct mlx4_en_priv
*priv
, struct mlx4_en_cq
*cq
);
531 void mlx4_en_tx_irq(struct mlx4_cq
*mcq
);
532 u16
mlx4_en_select_queue(struct net_device
*dev
, struct sk_buff
*skb
);
533 netdev_tx_t
mlx4_en_xmit(struct sk_buff
*skb
, struct net_device
*dev
);
535 int mlx4_en_create_tx_ring(struct mlx4_en_priv
*priv
, struct mlx4_en_tx_ring
*ring
,
536 int qpn
, u32 size
, u16 stride
);
537 void mlx4_en_destroy_tx_ring(struct mlx4_en_priv
*priv
, struct mlx4_en_tx_ring
*ring
);
538 int mlx4_en_activate_tx_ring(struct mlx4_en_priv
*priv
,
539 struct mlx4_en_tx_ring
*ring
,
540 int cq
, int user_prio
);
541 void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv
*priv
,
542 struct mlx4_en_tx_ring
*ring
);
544 int mlx4_en_create_rx_ring(struct mlx4_en_priv
*priv
,
545 struct mlx4_en_rx_ring
*ring
,
546 u32 size
, u16 stride
);
547 void mlx4_en_destroy_rx_ring(struct mlx4_en_priv
*priv
,
548 struct mlx4_en_rx_ring
*ring
,
549 u32 size
, u16 stride
);
550 int mlx4_en_activate_rx_rings(struct mlx4_en_priv
*priv
);
551 void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv
*priv
,
552 struct mlx4_en_rx_ring
*ring
);
553 int mlx4_en_process_rx_cq(struct net_device
*dev
,
554 struct mlx4_en_cq
*cq
,
556 int mlx4_en_poll_rx_cq(struct napi_struct
*napi
, int budget
);
557 void mlx4_en_fill_qp_context(struct mlx4_en_priv
*priv
, int size
, int stride
,
558 int is_tx
, int rss
, int qpn
, int cqn
, int user_prio
,
559 struct mlx4_qp_context
*context
);
560 void mlx4_en_sqp_event(struct mlx4_qp
*qp
, enum mlx4_event event
);
561 int mlx4_en_map_buffer(struct mlx4_buf
*buf
);
562 void mlx4_en_unmap_buffer(struct mlx4_buf
*buf
);
564 void mlx4_en_calc_rx_buf(struct net_device
*dev
);
565 int mlx4_en_config_rss_steer(struct mlx4_en_priv
*priv
);
566 void mlx4_en_release_rss_steer(struct mlx4_en_priv
*priv
);
567 int mlx4_en_free_tx_buf(struct net_device
*dev
, struct mlx4_en_tx_ring
*ring
);
568 void mlx4_en_rx_irq(struct mlx4_cq
*mcq
);
570 int mlx4_SET_MCAST_FLTR(struct mlx4_dev
*dev
, u8 port
, u64 mac
, u64 clear
, u8 mode
);
571 int mlx4_SET_VLAN_FLTR(struct mlx4_dev
*dev
, struct mlx4_en_priv
*priv
);
573 int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev
*mdev
, u8 port
, u8 reset
);
574 int mlx4_en_QUERY_PORT(struct mlx4_en_dev
*mdev
, u8 port
);
576 #ifdef CONFIG_MLX4_EN_DCB
577 extern const struct dcbnl_rtnl_ops mlx4_en_dcbnl_ops
;
580 #define MLX4_EN_NUM_SELF_TEST 5
581 void mlx4_en_ex_selftest(struct net_device
*dev
, u32
*flags
, u64
*buf
);
582 u64
mlx4_en_mac_to_u64(u8
*addr
);
587 extern const struct ethtool_ops mlx4_en_ethtool_ops
;
592 * printk / logging functions
596 int en_print(const char *level
, const struct mlx4_en_priv
*priv
,
597 const char *format
, ...);
599 #define en_dbg(mlevel, priv, format, arg...) \
601 if (NETIF_MSG_##mlevel & priv->msg_enable) \
602 en_print(KERN_DEBUG, priv, format, ##arg); \
604 #define en_warn(priv, format, arg...) \
605 en_print(KERN_WARNING, priv, format, ##arg)
606 #define en_err(priv, format, arg...) \
607 en_print(KERN_ERR, priv, format, ##arg)
608 #define en_info(priv, format, arg...) \
609 en_print(KERN_INFO, priv, format, ## arg)
611 #define mlx4_err(mdev, format, arg...) \
612 pr_err("%s %s: " format, DRV_NAME, \
613 dev_name(&mdev->pdev->dev), ##arg)
614 #define mlx4_info(mdev, format, arg...) \
615 pr_info("%s %s: " format, DRV_NAME, \
616 dev_name(&mdev->pdev->dev), ##arg)
617 #define mlx4_warn(mdev, format, arg...) \
618 pr_warning("%s %s: " format, DRV_NAME, \
619 dev_name(&mdev->pdev->dev), ##arg)