drivers/net/ethernet/mellanox/mlx4/mlx4_en.h

   1 /*
   2  * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  *
  32  */
  33
  34 #ifndef _MLX4_EN_H_
  35 #define _MLX4_EN_H_
  36
  37 #include <linux/bitops.h>
  38 #include <linux/compiler.h>
  39 #include <linux/list.h>
  40 #include <linux/mutex.h>
  41 #include <linux/netdevice.h>
  42 #include <linux/if_vlan.h>
  43 #include <linux/net_tstamp.h>
  44 #ifdef CONFIG_MLX4_EN_DCB
  45 #include <linux/dcbnl.h>
  46 #endif
  47 #include <linux/cpu_rmap.h>
  48 #include <linux/ptp_clock_kernel.h>
  49
  50 #include <linux/mlx4/device.h>
  51 #include <linux/mlx4/qp.h>
  52 #include <linux/mlx4/cq.h>
  53 #include <linux/mlx4/srq.h>
  54 #include <linux/mlx4/doorbell.h>
  55 #include <linux/mlx4/cmd.h>
  56
  57 #include "en_port.h"
  58
  59 #define DRV_NAME        "mlx4_en"
  60 #define DRV_VERSION     "2.2-1"
  61 #define DRV_RELDATE     "Feb 2014"
  62
  63 #define MLX4_EN_MSG_LEVEL       (NETIF_MSG_LINK | NETIF_MSG_IFDOWN)
  64
  65 /*
  66  * Device constants
  67  */
  68
  69
  70 #define MLX4_EN_PAGE_SHIFT      12
  71 #define MLX4_EN_PAGE_SIZE       (1 << MLX4_EN_PAGE_SHIFT)
  72 #define DEF_RX_RINGS            16
  73 #define MAX_RX_RINGS            128
  74 #define MIN_RX_RINGS            4
  75 #define TXBB_SIZE               64
  76 #define HEADROOM                (2048 / TXBB_SIZE + 1)
  77 #define STAMP_STRIDE            64
  78 #define STAMP_DWORDS            (STAMP_STRIDE / 4)
  79 #define STAMP_SHIFT             31
  80 #define STAMP_VAL               0x7fffffff
  81 #define STATS_DELAY             (HZ / 4)
  82 #define SERVICE_TASK_DELAY      (HZ / 4)
  83 #define MAX_NUM_OF_FS_RULES     256
  84
  85 #define MLX4_EN_FILTER_HASH_SHIFT 4
  86 #define MLX4_EN_FILTER_EXPIRY_QUOTA 60
  87
  88 /* Typical TSO descriptor with 16 gather entries is 352 bytes... */
  89 #define MAX_DESC_SIZE           512
  90 #define MAX_DESC_TXBBS          (MAX_DESC_SIZE / TXBB_SIZE)
  91
  92 /*
  93  * OS related constants and tunables
  94  */
  95
  96 #define MLX4_EN_WATCHDOG_TIMEOUT        (15 * HZ)
  97
  98 /* Use the maximum between 16384 and a single page */
  99 #define MLX4_EN_ALLOC_SIZE      PAGE_ALIGN(16384)
 100
 101 #define MLX4_EN_ALLOC_PREFER_ORDER      PAGE_ALLOC_COSTLY_ORDER
 102
 103 /* Receive fragment sizes; we use at most 3 fragments (for 9600 byte MTU
 104  * and 4K allocations) */
 105 enum {
 106         FRAG_SZ0 = 1536 - NET_IP_ALIGN,
 107         FRAG_SZ1 = 4096,
 108         FRAG_SZ2 = 4096,
 109         FRAG_SZ3 = MLX4_EN_ALLOC_SIZE
 110 };
 111 #define MLX4_EN_MAX_RX_FRAGS    4
 112
 113 /* Maximum ring sizes */
 114 #define MLX4_EN_MAX_TX_SIZE     8192
 115 #define MLX4_EN_MAX_RX_SIZE     8192
 116
 117 /* Minimum ring size for our page-allocation scheme to work */
 118 #define MLX4_EN_MIN_RX_SIZE     (MLX4_EN_ALLOC_SIZE / SMP_CACHE_BYTES)
 119 #define MLX4_EN_MIN_TX_SIZE     (4096 / TXBB_SIZE)
 120
 121 #define MLX4_EN_SMALL_PKT_SIZE          64
 122 #define MLX4_EN_MAX_TX_RING_P_UP        32
 123 #define MLX4_EN_NUM_UP                  8
 124 #define MLX4_EN_DEF_TX_RING_SIZE        512
 125 #define MLX4_EN_DEF_RX_RING_SIZE        1024
 126 #define MAX_TX_RINGS                    (MLX4_EN_MAX_TX_RING_P_UP * \
 127                                          MLX4_EN_NUM_UP)
 128
 129 /* Target number of packets to coalesce with interrupt moderation */
 130 #define MLX4_EN_RX_COAL_TARGET  44
 131 #define MLX4_EN_RX_COAL_TIME    0x10
 132
 133 #define MLX4_EN_TX_COAL_PKTS    16
 134 #define MLX4_EN_TX_COAL_TIME    0x10
 135
 136 #define MLX4_EN_RX_RATE_LOW             400000
 137 #define MLX4_EN_RX_COAL_TIME_LOW        0
 138 #define MLX4_EN_RX_RATE_HIGH            450000
 139 #define MLX4_EN_RX_COAL_TIME_HIGH       128
 140 #define MLX4_EN_RX_SIZE_THRESH          1024
 141 #define MLX4_EN_RX_RATE_THRESH          (1000000 / MLX4_EN_RX_COAL_TIME_HIGH)
 142 #define MLX4_EN_SAMPLE_INTERVAL         0
 143 #define MLX4_EN_AVG_PKT_SMALL           256
 144
 145 #define MLX4_EN_AUTO_CONF       0xffff
 146
 147 #define MLX4_EN_DEF_RX_PAUSE    1
 148 #define MLX4_EN_DEF_TX_PAUSE    1
 149
 150 /* Interval between successive polls in the Tx routine when polling is used
 151    instead of interrupts (in per-core Tx rings) - should be power of 2 */
 152 #define MLX4_EN_TX_POLL_MODER   16
 153 #define MLX4_EN_TX_POLL_TIMEOUT (HZ / 4)
 154
 155 #define ETH_LLC_SNAP_SIZE       8
 156
 157 #define SMALL_PACKET_SIZE      (256 - NET_IP_ALIGN)
 158 #define HEADER_COPY_SIZE       (128 - NET_IP_ALIGN)
 159 #define MLX4_LOOPBACK_TEST_PAYLOAD (HEADER_COPY_SIZE - ETH_HLEN)
 160
 161 #define MLX4_EN_MIN_MTU         46
 162 #define ETH_BCAST               0xffffffffffffULL
 163
 164 #define MLX4_EN_LOOPBACK_RETRIES        5
 165 #define MLX4_EN_LOOPBACK_TIMEOUT        100
 166
 167 #ifdef MLX4_EN_PERF_STAT
 168 /* Number of samples to 'average' */
 169 #define AVG_SIZE                        128
 170 #define AVG_FACTOR                      1024
 171 #define NUM_PERF_STATS                  NUM_PERF_COUNTERS
 172
 173 #define INC_PERF_COUNTER(cnt)           (++(cnt))
 174 #define ADD_PERF_COUNTER(cnt, add)      ((cnt) += (add))
 175 #define AVG_PERF_COUNTER(cnt, sample) \
 176         ((cnt) = ((cnt) * (AVG_SIZE - 1) + (sample) * AVG_FACTOR) / AVG_SIZE)
 177 #define GET_PERF_COUNTER(cnt)           (cnt)
 178 #define GET_AVG_PERF_COUNTER(cnt)       ((cnt) / AVG_FACTOR)
 179
 180 #else
 181
 182 #define NUM_PERF_STATS                  0
 183 #define INC_PERF_COUNTER(cnt)           do {} while (0)
 184 #define ADD_PERF_COUNTER(cnt, add)      do {} while (0)
 185 #define AVG_PERF_COUNTER(cnt, sample)   do {} while (0)
 186 #define GET_PERF_COUNTER(cnt)           (0)
 187 #define GET_AVG_PERF_COUNTER(cnt)       (0)
 188 #endif /* MLX4_EN_PERF_STAT */
 189
 190 /* Constants for TX flow */
 191 enum {
 192         MAX_INLINE = 104, /* 128 - 16 - 4 - 4 */
 193         MAX_BF = 256,
 194         MIN_PKT_LEN = 17,
 195 };
 196
 197 /*
 198  * Configurables
 199  */
 200
 201 enum cq_type {
 202         RX = 0,
 203         TX = 1,
 204 };
 205
 206
 207 /*
 208  * Useful macros
 209  */
 210 #define ROUNDUP_LOG2(x)         ilog2(roundup_pow_of_two(x))
 211 #define XNOR(x, y)              (!(x) == !(y))
 212
 213
 214 struct mlx4_en_tx_info {
 215         struct sk_buff *skb;
 216         u32 nr_txbb;
 217         u32 nr_bytes;
 218         u8 linear;
 219         u8 data_offset;
 220         u8 inl;
 221         u8 ts_requested;
 222 };
 223
 224
 225 #define MLX4_EN_BIT_DESC_OWN    0x80000000
 226 #define CTRL_SIZE       sizeof(struct mlx4_wqe_ctrl_seg)
 227 #define MLX4_EN_MEMTYPE_PAD     0x100
 228 #define DS_SIZE         sizeof(struct mlx4_wqe_data_seg)
 229
 230
 231 struct mlx4_en_tx_desc {
 232         struct mlx4_wqe_ctrl_seg ctrl;
 233         union {
 234                 struct mlx4_wqe_data_seg data; /* at least one data segment */
 235                 struct mlx4_wqe_lso_seg lso;
 236                 struct mlx4_wqe_inline_seg inl;
 237         };
 238 };
 239
 240 #define MLX4_EN_USE_SRQ         0x01000000
 241
 242 #define MLX4_EN_CX3_LOW_ID      0x1000
 243 #define MLX4_EN_CX3_HIGH_ID     0x1005
 244
 245 struct mlx4_en_rx_alloc {
 246         struct page     *page;
 247         dma_addr_t      dma;
 248         u32             page_offset;
 249         u32             page_size;
 250 };
 251
 252 struct mlx4_en_tx_ring {
 253         struct mlx4_hwq_resources wqres;
 254         u32 size ; /* number of TXBBs */
 255         u32 size_mask;
 256         u16 stride;
 257         u16 cqn;        /* index of port CQ associated with this ring */
 258         u32 prod;
 259         u32 cons;
 260         u32 buf_size;
 261         u32 doorbell_qpn;
 262         void *buf;
 263         u16 poll_cnt;
 264         struct mlx4_en_tx_info *tx_info;
 265         u8 *bounce_buf;
 266         u8 queue_index;
 267         cpumask_t affinity_mask;
 268         u32 last_nr_txbb;
 269         struct mlx4_qp qp;
 270         struct mlx4_qp_context context;
 271         int qpn;
 272         enum mlx4_qp_state qp_state;
 273         struct mlx4_srq dummy;
 274         unsigned long bytes;
 275         unsigned long packets;
 276         unsigned long tx_csum;
 277         unsigned long queue_stopped;
 278         unsigned long wake_queue;
 279         struct mlx4_bf bf;
 280         bool bf_enabled;
 281         struct netdev_queue *tx_queue;
 282         int hwtstamp_tx_type;
 283         int inline_thold;
 284 };
 285
 286 struct mlx4_en_rx_desc {
 287         /* actual number of entries depends on rx ring stride */
 288         struct mlx4_wqe_data_seg data[0];
 289 };
 290
 291 struct mlx4_en_rx_ring {
 292         struct mlx4_hwq_resources wqres;
 293         struct mlx4_en_rx_alloc page_alloc[MLX4_EN_MAX_RX_FRAGS];
 294         u32 size ;      /* number of Rx descs*/
 295         u32 actual_size;
 296         u32 size_mask;
 297         u16 stride;
 298         u16 log_stride;
 299         u16 cqn;        /* index of port CQ associated with this ring */
 300         u32 prod;
 301         u32 cons;
 302         u32 buf_size;
 303         u8  fcs_del;
 304         void *buf;
 305         void *rx_info;
 306         unsigned long bytes;
 307         unsigned long packets;
 308 #ifdef CONFIG_NET_RX_BUSY_POLL
 309         unsigned long yields;
 310         unsigned long misses;
 311         unsigned long cleaned;
 312 #endif
 313         unsigned long csum_ok;
 314         unsigned long csum_none;
 315         int hwtstamp_rx_filter;
 316 };
 317
 318 struct mlx4_en_cq {
 319         struct mlx4_cq          mcq;
 320         struct mlx4_hwq_resources wqres;
 321         int                     ring;
 322         spinlock_t              lock;
 323         struct net_device      *dev;
 324         struct napi_struct      napi;
 325         int size;
 326         int buf_size;
 327         unsigned vector;
 328         enum cq_type is_tx;
 329         u16 moder_time;
 330         u16 moder_cnt;
 331         struct mlx4_cqe *buf;
 332 #define MLX4_EN_OPCODE_ERROR    0x1e
 333
 334 #ifdef CONFIG_NET_RX_BUSY_POLL
 335         unsigned int state;
 336 #define MLX4_EN_CQ_STATE_IDLE        0
 337 #define MLX4_EN_CQ_STATE_NAPI     1    /* NAPI owns this CQ */
 338 #define MLX4_EN_CQ_STATE_POLL     2    /* poll owns this CQ */
 339 #define MLX4_CQ_LOCKED (MLX4_EN_CQ_STATE_NAPI | MLX4_EN_CQ_STATE_POLL)
 340 #define MLX4_EN_CQ_STATE_NAPI_YIELD  4    /* NAPI yielded this CQ */
 341 #define MLX4_EN_CQ_STATE_POLL_YIELD  8    /* poll yielded this CQ */
 342 #define CQ_YIELD (MLX4_EN_CQ_STATE_NAPI_YIELD | MLX4_EN_CQ_STATE_POLL_YIELD)
 343 #define CQ_USER_PEND (MLX4_EN_CQ_STATE_POLL | MLX4_EN_CQ_STATE_POLL_YIELD)
 344         spinlock_t poll_lock; /* protects from LLS/napi conflicts */
 345 #endif  /* CONFIG_NET_RX_BUSY_POLL */
 346 };
 347
 348 struct mlx4_en_port_profile {
 349         u32 flags;
 350         u32 tx_ring_num;
 351         u32 rx_ring_num;
 352         u32 tx_ring_size;
 353         u32 rx_ring_size;
 354         u8 rx_pause;
 355         u8 rx_ppp;
 356         u8 tx_pause;
 357         u8 tx_ppp;
 358         int rss_rings;
 359         int inline_thold;
 360 };
 361
 362 struct mlx4_en_profile {
 363         int rss_xor;
 364         int udp_rss;
 365         u8 rss_mask;
 366         u32 active_ports;
 367         u32 small_pkt_int;
 368         u8 no_reset;
 369         u8 num_tx_rings_p_up;
 370         struct mlx4_en_port_profile prof[MLX4_MAX_PORTS + 1];
 371 };
 372
 373 struct mlx4_en_dev {
 374         struct mlx4_dev         *dev;
 375         struct pci_dev          *pdev;
 376         struct mutex            state_lock;
 377         struct net_device       *pndev[MLX4_MAX_PORTS + 1];
 378         u32                     port_cnt;
 379         bool                    device_up;
 380         struct mlx4_en_profile  profile;
 381         u32                     LSO_support;
 382         struct workqueue_struct *workqueue;
 383         struct device           *dma_device;
 384         void __iomem            *uar_map;
 385         struct mlx4_uar         priv_uar;
 386         struct mlx4_mr          mr;
 387         u32                     priv_pdn;
 388         spinlock_t              uar_lock;
 389         u8                      mac_removed[MLX4_MAX_PORTS + 1];
 390         rwlock_t                clock_lock;
 391         u32                     nominal_c_mult;
 392         struct cyclecounter     cycles;
 393         struct timecounter      clock;
 394         unsigned long           last_overflow_check;
 395         unsigned long           overflow_period;
 396         struct ptp_clock        *ptp_clock;
 397         struct ptp_clock_info   ptp_clock_info;
 398 };
 399
 400
 401 struct mlx4_en_rss_map {
 402         int base_qpn;
 403         struct mlx4_qp qps[MAX_RX_RINGS];
 404         enum mlx4_qp_state state[MAX_RX_RINGS];
 405         struct mlx4_qp indir_qp;
 406         enum mlx4_qp_state indir_state;
 407 };
 408
 409 struct mlx4_en_port_state {
 410         int link_state;
 411         int link_speed;
 412         int transciver;
 413 };
 414
 415 struct mlx4_en_pkt_stats {
 416         unsigned long broadcast;
 417         unsigned long rx_prio[8];
 418         unsigned long tx_prio[8];
 419 #define NUM_PKT_STATS           17
 420 };
 421
 422 struct mlx4_en_port_stats {
 423         unsigned long tso_packets;
 424         unsigned long queue_stopped;
 425         unsigned long wake_queue;
 426         unsigned long tx_timeout;
 427         unsigned long rx_alloc_failed;
 428         unsigned long rx_chksum_good;
 429         unsigned long rx_chksum_none;
 430         unsigned long tx_chksum_offload;
 431 #define NUM_PORT_STATS          8
 432 };
 433
 434 struct mlx4_en_perf_stats {
 435         u32 tx_poll;
 436         u64 tx_pktsz_avg;
 437         u32 inflight_avg;
 438         u16 tx_coal_avg;
 439         u16 rx_coal_avg;
 440         u32 napi_quota;
 441 #define NUM_PERF_COUNTERS               6
 442 };
 443
 444 enum mlx4_en_mclist_act {
 445         MCLIST_NONE,
 446         MCLIST_REM,
 447         MCLIST_ADD,
 448 };
 449
 450 struct mlx4_en_mc_list {
 451         struct list_head        list;
 452         enum mlx4_en_mclist_act action;
 453         u8                      addr[ETH_ALEN];
 454         u64                     reg_id;
 455         u64                     tunnel_reg_id;
 456 };
 457
 458 struct mlx4_en_frag_info {
 459         u16 frag_size;
 460         u16 frag_prefix_size;
 461         u16 frag_stride;
 462         u16 frag_align;
 463 };
 464
 465 #ifdef CONFIG_MLX4_EN_DCB
 466 /* Minimal TC BW - setting to 0 will block traffic */
 467 #define MLX4_EN_BW_MIN 1
 468 #define MLX4_EN_BW_MAX 100 /* Utilize 100% of the line */
 469
 470 #define MLX4_EN_TC_ETS 7
 471
 472 #endif
 473
 474 struct ethtool_flow_id {
 475         struct list_head list;
 476         struct ethtool_rx_flow_spec flow_spec;
 477         u64 id;
 478 };
 479
 480 enum {
 481         MLX4_EN_FLAG_PROMISC            = (1 << 0),
 482         MLX4_EN_FLAG_MC_PROMISC         = (1 << 1),
 483         /* whether we need to enable hardware loopback by putting dmac
 484          * in Tx WQE
 485          */
 486         MLX4_EN_FLAG_ENABLE_HW_LOOPBACK = (1 << 2),
 487         /* whether we need to drop packets that hardware loopback-ed */
 488         MLX4_EN_FLAG_RX_FILTER_NEEDED   = (1 << 3),
 489         MLX4_EN_FLAG_FORCE_PROMISC      = (1 << 4)
 490 };
 491
 492 #define MLX4_EN_MAC_HASH_SIZE (1 << BITS_PER_BYTE)
 493 #define MLX4_EN_MAC_HASH_IDX 5
 494
 495 struct mlx4_en_priv {
 496         struct mlx4_en_dev *mdev;
 497         struct mlx4_en_port_profile *prof;
 498         struct net_device *dev;
 499         unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
 500         struct net_device_stats stats;
 501         struct net_device_stats ret_stats;
 502         struct mlx4_en_port_state port_state;
 503         spinlock_t stats_lock;
 504         struct ethtool_flow_id ethtool_rules[MAX_NUM_OF_FS_RULES];
 505         /* To allow rules removal while port is going down */
 506         struct list_head ethtool_list;
 507
 508         unsigned long last_moder_packets[MAX_RX_RINGS];
 509         unsigned long last_moder_tx_packets;
 510         unsigned long last_moder_bytes[MAX_RX_RINGS];
 511         unsigned long last_moder_jiffies;
 512         int last_moder_time[MAX_RX_RINGS];
 513         u16 rx_usecs;
 514         u16 rx_frames;
 515         u16 tx_usecs;
 516         u16 tx_frames;
 517         u32 pkt_rate_low;
 518         u16 rx_usecs_low;
 519         u32 pkt_rate_high;
 520         u16 rx_usecs_high;
 521         u16 sample_interval;
 522         u16 adaptive_rx_coal;
 523         u32 msg_enable;
 524         u32 loopback_ok;
 525         u32 validate_loopback;
 526
 527         struct mlx4_hwq_resources res;
 528         int link_state;
 529         int last_link_state;
 530         bool port_up;
 531         int port;
 532         int registered;
 533         int allocated;
 534         int stride;
 535         unsigned char prev_mac[ETH_ALEN + 2];
 536         int mac_index;
 537         unsigned max_mtu;
 538         int base_qpn;
 539         int cqe_factor;
 540
 541         struct mlx4_en_rss_map rss_map;
 542         __be32 ctrl_flags;
 543         u32 flags;
 544         u8 num_tx_rings_p_up;
 545         u32 tx_ring_num;
 546         u32 rx_ring_num;
 547         u32 rx_skb_size;
 548         struct mlx4_en_frag_info frag_info[MLX4_EN_MAX_RX_FRAGS];
 549         u16 num_frags;
 550         u16 log_rx_info;
 551
 552         struct mlx4_en_tx_ring **tx_ring;
 553         struct mlx4_en_rx_ring *rx_ring[MAX_RX_RINGS];
 554         struct mlx4_en_cq **tx_cq;
 555         struct mlx4_en_cq *rx_cq[MAX_RX_RINGS];
 556         struct mlx4_qp drop_qp;
 557         struct work_struct rx_mode_task;
 558         struct work_struct watchdog_task;
 559         struct work_struct linkstate_task;
 560         struct delayed_work stats_task;
 561         struct delayed_work service_task;
 562 #ifdef CONFIG_MLX4_EN_VXLAN
 563         struct work_struct vxlan_add_task;
 564         struct work_struct vxlan_del_task;
 565 #endif
 566         struct mlx4_en_perf_stats pstats;
 567         struct mlx4_en_pkt_stats pkstats;
 568         struct mlx4_en_port_stats port_stats;
 569         u64 stats_bitmap;
 570         struct list_head mc_list;
 571         struct list_head curr_list;
 572         u64 broadcast_id;
 573         struct mlx4_en_stat_out_mbox hw_stats;
 574         int vids[128];
 575         bool wol;
 576         struct device *ddev;
 577         int base_tx_qpn;
 578         struct hlist_head mac_hash[MLX4_EN_MAC_HASH_SIZE];
 579         struct hwtstamp_config hwtstamp_config;
 580
 581 #ifdef CONFIG_MLX4_EN_DCB
 582         struct ieee_ets ets;
 583         u16 maxrate[IEEE_8021QAZ_MAX_TCS];
 584 #endif
 585 #ifdef CONFIG_RFS_ACCEL
 586         spinlock_t filters_lock;
 587         int last_filter_id;
 588         struct list_head filters;
 589         struct hlist_head filter_hash[1 << MLX4_EN_FILTER_HASH_SHIFT];
 590 #endif
 591         u64 tunnel_reg_id;
 592         __be16 vxlan_port;
 593 };
 594
 595 enum mlx4_en_wol {
 596         MLX4_EN_WOL_MAGIC = (1ULL << 61),
 597         MLX4_EN_WOL_ENABLED = (1ULL << 62),
 598 };
 599
 600 struct mlx4_mac_entry {
 601         struct hlist_node hlist;
 602         unsigned char mac[ETH_ALEN + 2];
 603         u64 reg_id;
 604         struct rcu_head rcu;
 605 };
 606
 607 #ifdef CONFIG_NET_RX_BUSY_POLL
 608 static inline void mlx4_en_cq_init_lock(struct mlx4_en_cq *cq)
 609 {
 610         spin_lock_init(&cq->poll_lock);
 611         cq->state = MLX4_EN_CQ_STATE_IDLE;
 612 }
 613
 614 /* called from the device poll rutine to get ownership of a cq */
 615 static inline bool mlx4_en_cq_lock_napi(struct mlx4_en_cq *cq)
 616 {
 617         int rc = true;
 618         spin_lock(&cq->poll_lock);
 619         if (cq->state & MLX4_CQ_LOCKED) {
 620                 WARN_ON(cq->state & MLX4_EN_CQ_STATE_NAPI);
 621                 cq->state |= MLX4_EN_CQ_STATE_NAPI_YIELD;
 622                 rc = false;
 623         } else
 624                 /* we don't care if someone yielded */
 625                 cq->state = MLX4_EN_CQ_STATE_NAPI;
 626         spin_unlock(&cq->poll_lock);
 627         return rc;
 628 }
 629
 630 /* returns true is someone tried to get the cq while napi had it */
 631 static inline bool mlx4_en_cq_unlock_napi(struct mlx4_en_cq *cq)
 632 {
 633         int rc = false;
 634         spin_lock(&cq->poll_lock);
 635         WARN_ON(cq->state & (MLX4_EN_CQ_STATE_POLL |
 636                                MLX4_EN_CQ_STATE_NAPI_YIELD));
 637
 638         if (cq->state & MLX4_EN_CQ_STATE_POLL_YIELD)
 639                 rc = true;
 640         cq->state = MLX4_EN_CQ_STATE_IDLE;
 641         spin_unlock(&cq->poll_lock);
 642         return rc;
 643 }
 644
 645 /* called from mlx4_en_low_latency_poll() */
 646 static inline bool mlx4_en_cq_lock_poll(struct mlx4_en_cq *cq)
 647 {
 648         int rc = true;
 649         spin_lock_bh(&cq->poll_lock);
 650         if ((cq->state & MLX4_CQ_LOCKED)) {
 651                 struct net_device *dev = cq->dev;
 652                 struct mlx4_en_priv *priv = netdev_priv(dev);
 653                 struct mlx4_en_rx_ring *rx_ring = priv->rx_ring[cq->ring];
 654
 655                 cq->state |= MLX4_EN_CQ_STATE_POLL_YIELD;
 656                 rc = false;
 657                 rx_ring->yields++;
 658         } else
 659                 /* preserve yield marks */
 660                 cq->state |= MLX4_EN_CQ_STATE_POLL;
 661         spin_unlock_bh(&cq->poll_lock);
 662         return rc;
 663 }
 664
 665 /* returns true if someone tried to get the cq while it was locked */
 666 static inline bool mlx4_en_cq_unlock_poll(struct mlx4_en_cq *cq)
 667 {
 668         int rc = false;
 669         spin_lock_bh(&cq->poll_lock);
 670         WARN_ON(cq->state & (MLX4_EN_CQ_STATE_NAPI));
 671
 672         if (cq->state & MLX4_EN_CQ_STATE_POLL_YIELD)
 673                 rc = true;
 674         cq->state = MLX4_EN_CQ_STATE_IDLE;
 675         spin_unlock_bh(&cq->poll_lock);
 676         return rc;
 677 }
 678
 679 /* true if a socket is polling, even if it did not get the lock */
 680 static inline bool mlx4_en_cq_busy_polling(struct mlx4_en_cq *cq)
 681 {
 682         WARN_ON(!(cq->state & MLX4_CQ_LOCKED));
 683         return cq->state & CQ_USER_PEND;
 684 }
 685 #else
 686 static inline void mlx4_en_cq_init_lock(struct mlx4_en_cq *cq)
 687 {
 688 }
 689
 690 static inline bool mlx4_en_cq_lock_napi(struct mlx4_en_cq *cq)
 691 {
 692         return true;
 693 }
 694
 695 static inline bool mlx4_en_cq_unlock_napi(struct mlx4_en_cq *cq)
 696 {
 697         return false;
 698 }
 699
 700 static inline bool mlx4_en_cq_lock_poll(struct mlx4_en_cq *cq)
 701 {
 702         return false;
 703 }
 704
 705 static inline bool mlx4_en_cq_unlock_poll(struct mlx4_en_cq *cq)
 706 {
 707         return false;
 708 }
 709
 710 static inline bool mlx4_en_cq_busy_polling(struct mlx4_en_cq *cq)
 711 {
 712         return false;
 713 }
 714 #endif /* CONFIG_NET_RX_BUSY_POLL */
 715
 716 #define MLX4_EN_WOL_DO_MODIFY (1ULL << 63)
 717
 718 void mlx4_en_update_loopback_state(struct net_device *dev,
 719                                    netdev_features_t features);
 720
 721 void mlx4_en_destroy_netdev(struct net_device *dev);
 722 int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port,
 723                         struct mlx4_en_port_profile *prof);
 724
 725 int mlx4_en_start_port(struct net_device *dev);
 726 void mlx4_en_stop_port(struct net_device *dev, int detach);
 727
 728 void mlx4_en_free_resources(struct mlx4_en_priv *priv);
 729 int mlx4_en_alloc_resources(struct mlx4_en_priv *priv);
 730
 731 int mlx4_en_create_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq **pcq,
 732                       int entries, int ring, enum cq_type mode, int node);
 733 void mlx4_en_destroy_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq **pcq);
 734 int mlx4_en_activate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq,
 735                         int cq_idx);
 736 void mlx4_en_deactivate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
 737 int mlx4_en_set_cq_moder(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
 738 int mlx4_en_arm_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
 739
 740 void mlx4_en_tx_irq(struct mlx4_cq *mcq);
 741 u16 mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb,
 742                          void *accel_priv, select_queue_fallback_t fallback);
 743 netdev_tx_t mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev);
 744
 745 int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv,
 746                            struct mlx4_en_tx_ring **pring,
 747                            int qpn, u32 size, u16 stride,
 748                            int node, int queue_index);
 749 void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv,
 750                              struct mlx4_en_tx_ring **pring);
 751 int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv,
 752                              struct mlx4_en_tx_ring *ring,
 753                              int cq, int user_prio);
 754 void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv,
 755                                 struct mlx4_en_tx_ring *ring);
 756 void mlx4_en_set_num_rx_rings(struct mlx4_en_dev *mdev);
 757 int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv,
 758                            struct mlx4_en_rx_ring **pring,
 759                            u32 size, u16 stride, int node);
 760 void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv,
 761                              struct mlx4_en_rx_ring **pring,
 762                              u32 size, u16 stride);
 763 int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv);
 764 void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv,
 765                                 struct mlx4_en_rx_ring *ring);
 766 int mlx4_en_process_rx_cq(struct net_device *dev,
 767                           struct mlx4_en_cq *cq,
 768                           int budget);
 769 int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget);
 770 int mlx4_en_poll_tx_cq(struct napi_struct *napi, int budget);
 771 void mlx4_en_fill_qp_context(struct mlx4_en_priv *priv, int size, int stride,
 772                 int is_tx, int rss, int qpn, int cqn, int user_prio,
 773                 struct mlx4_qp_context *context);
 774 void mlx4_en_sqp_event(struct mlx4_qp *qp, enum mlx4_event event);
 775 int mlx4_en_map_buffer(struct mlx4_buf *buf);
 776 void mlx4_en_unmap_buffer(struct mlx4_buf *buf);
 777
 778 void mlx4_en_calc_rx_buf(struct net_device *dev);
 779 int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv);
 780 void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv);
 781 int mlx4_en_create_drop_qp(struct mlx4_en_priv *priv);
 782 void mlx4_en_destroy_drop_qp(struct mlx4_en_priv *priv);
 783 int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring);
 784 void mlx4_en_rx_irq(struct mlx4_cq *mcq);
 785
 786 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode);
 787 int mlx4_SET_VLAN_FLTR(struct mlx4_dev *dev, struct mlx4_en_priv *priv);
 788
 789 int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev *mdev, u8 port, u8 reset);
 790 int mlx4_en_QUERY_PORT(struct mlx4_en_dev *mdev, u8 port);
 791
 792 #ifdef CONFIG_MLX4_EN_DCB
 793 extern const struct dcbnl_rtnl_ops mlx4_en_dcbnl_ops;
 794 extern const struct dcbnl_rtnl_ops mlx4_en_dcbnl_pfc_ops;
 795 #endif
 796
 797 int mlx4_en_setup_tc(struct net_device *dev, u8 up);
 798
 799 #ifdef CONFIG_RFS_ACCEL
 800 void mlx4_en_cleanup_filters(struct mlx4_en_priv *priv);
 801 #endif
 802
 803 #define MLX4_EN_NUM_SELF_TEST   5
 804 void mlx4_en_ex_selftest(struct net_device *dev, u32 *flags, u64 *buf);
 805 void mlx4_en_ptp_overflow_check(struct mlx4_en_dev *mdev);
 806
 807 /*
 808  * Functions for time stamping
 809  */
 810 u64 mlx4_en_get_cqe_ts(struct mlx4_cqe *cqe);
 811 void mlx4_en_fill_hwtstamps(struct mlx4_en_dev *mdev,
 812                             struct skb_shared_hwtstamps *hwts,
 813                             u64 timestamp);
 814 void mlx4_en_init_timestamp(struct mlx4_en_dev *mdev);
 815 void mlx4_en_remove_timestamp(struct mlx4_en_dev *mdev);
 816 int mlx4_en_timestamp_config(struct net_device *dev,
 817                              int tx_type,
 818                              int rx_filter);
 819
 820 /* Globals
 821  */
 822 extern const struct ethtool_ops mlx4_en_ethtool_ops;
 823
 824
 825
 826 /*
 827  * printk / logging functions
 828  */
 829
 830 __printf(3, 4)
 831 int en_print(const char *level, const struct mlx4_en_priv *priv,
 832              const char *format, ...);
 833
 834 #define en_dbg(mlevel, priv, format, arg...)                    \
 835 do {                                                            \
 836         if (NETIF_MSG_##mlevel & priv->msg_enable)              \
 837                 en_print(KERN_DEBUG, priv, format, ##arg);      \
 838 } while (0)
 839 #define en_warn(priv, format, arg...)                   \
 840         en_print(KERN_WARNING, priv, format, ##arg)
 841 #define en_err(priv, format, arg...)                    \
 842         en_print(KERN_ERR, priv, format, ##arg)
 843 #define en_info(priv, format, arg...)                   \
 844         en_print(KERN_INFO, priv, format, ## arg)
 845
 846 #define mlx4_err(mdev, format, arg...)                  \
 847         pr_err("%s %s: " format, DRV_NAME,              \
 848                dev_name(&mdev->pdev->dev), ##arg)
 849 #define mlx4_info(mdev, format, arg...)                 \
 850         pr_info("%s %s: " format, DRV_NAME,             \
 851                 dev_name(&mdev->pdev->dev), ##arg)
 852 #define mlx4_warn(mdev, format, arg...)                 \
 853         pr_warning("%s %s: " format, DRV_NAME,          \
 854                    dev_name(&mdev->pdev->dev), ##arg)
 855
 856 #endif