drivers/net/ethernet/mellanox/mlx4/mlx4_en.h

   1 /*
   2  * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  *
  32  */
  33
  34 #ifndef _MLX4_EN_H_
  35 #define _MLX4_EN_H_
  36
  37 #include <linux/bitops.h>
  38 #include <linux/compiler.h>
  39 #include <linux/list.h>
  40 #include <linux/mutex.h>
  41 #include <linux/netdevice.h>
  42 #include <linux/if_vlan.h>
  43 #ifdef CONFIG_MLX4_EN_DCB
  44 #include <linux/dcbnl.h>
  45 #endif
  46 #include <linux/cpu_rmap.h>
  47
  48 #include <linux/mlx4/device.h>
  49 #include <linux/mlx4/qp.h>
  50 #include <linux/mlx4/cq.h>
  51 #include <linux/mlx4/srq.h>
  52 #include <linux/mlx4/doorbell.h>
  53 #include <linux/mlx4/cmd.h>
  54
  55 #include "en_port.h"
  56
  57 #define DRV_NAME        "mlx4_en"
  58 #define DRV_VERSION     "2.0"
  59 #define DRV_RELDATE     "Dec 2011"
  60
  61 #define MLX4_EN_MSG_LEVEL       (NETIF_MSG_LINK | NETIF_MSG_IFDOWN)
  62
  63 /*
  64  * Device constants
  65  */
  66
  67
  68 #define MLX4_EN_PAGE_SHIFT      12
  69 #define MLX4_EN_PAGE_SIZE       (1 << MLX4_EN_PAGE_SHIFT)
  70 #define DEF_RX_RINGS            16
  71 #define MAX_RX_RINGS            128
  72 #define MIN_RX_RINGS            4
  73 #define TXBB_SIZE               64
  74 #define HEADROOM                (2048 / TXBB_SIZE + 1)
  75 #define STAMP_STRIDE            64
  76 #define STAMP_DWORDS            (STAMP_STRIDE / 4)
  77 #define STAMP_SHIFT             31
  78 #define STAMP_VAL               0x7fffffff
  79 #define STATS_DELAY             (HZ / 4)
  80 #define MAX_NUM_OF_FS_RULES     256
  81
  82 #define MLX4_EN_FILTER_HASH_SHIFT 4
  83 #define MLX4_EN_FILTER_EXPIRY_QUOTA 60
  84
  85 /* Typical TSO descriptor with 16 gather entries is 352 bytes... */
  86 #define MAX_DESC_SIZE           512
  87 #define MAX_DESC_TXBBS          (MAX_DESC_SIZE / TXBB_SIZE)
  88
  89 /*
  90  * OS related constants and tunables
  91  */
  92
  93 #define MLX4_EN_WATCHDOG_TIMEOUT        (15 * HZ)
  94
  95 /* Use the maximum between 16384 and a single page */
  96 #define MLX4_EN_ALLOC_SIZE      PAGE_ALIGN(16384)
  97 #define MLX4_EN_ALLOC_ORDER     get_order(MLX4_EN_ALLOC_SIZE)
  98
  99 /* Receive fragment sizes; we use at most 4 fragments (for 9600 byte MTU
 100  * and 4K allocations) */
 101 enum {
 102         FRAG_SZ0 = 512 - NET_IP_ALIGN,
 103         FRAG_SZ1 = 1024,
 104         FRAG_SZ2 = 4096,
 105         FRAG_SZ3 = MLX4_EN_ALLOC_SIZE
 106 };
 107 #define MLX4_EN_MAX_RX_FRAGS    4
 108
 109 /* Maximum ring sizes */
 110 #define MLX4_EN_MAX_TX_SIZE     8192
 111 #define MLX4_EN_MAX_RX_SIZE     8192
 112
 113 /* Minimum ring size for our page-allocation scheme to work */
 114 #define MLX4_EN_MIN_RX_SIZE     (MLX4_EN_ALLOC_SIZE / SMP_CACHE_BYTES)
 115 #define MLX4_EN_MIN_TX_SIZE     (4096 / TXBB_SIZE)
 116
 117 #define MLX4_EN_SMALL_PKT_SIZE          64
 118 #define MLX4_EN_MAX_TX_RING_P_UP        32
 119 #define MLX4_EN_NUM_UP                  8
 120 #define MLX4_EN_DEF_TX_RING_SIZE        512
 121 #define MLX4_EN_DEF_RX_RING_SIZE        1024
 122 #define MAX_TX_RINGS                    (MLX4_EN_MAX_TX_RING_P_UP * \
 123                                          MLX4_EN_NUM_UP)
 124
 125 /* Target number of packets to coalesce with interrupt moderation */
 126 #define MLX4_EN_RX_COAL_TARGET  44
 127 #define MLX4_EN_RX_COAL_TIME    0x10
 128
 129 #define MLX4_EN_TX_COAL_PKTS    16
 130 #define MLX4_EN_TX_COAL_TIME    0x10
 131
 132 #define MLX4_EN_RX_RATE_LOW             400000
 133 #define MLX4_EN_RX_COAL_TIME_LOW        0
 134 #define MLX4_EN_RX_RATE_HIGH            450000
 135 #define MLX4_EN_RX_COAL_TIME_HIGH       128
 136 #define MLX4_EN_RX_SIZE_THRESH          1024
 137 #define MLX4_EN_RX_RATE_THRESH          (1000000 / MLX4_EN_RX_COAL_TIME_HIGH)
 138 #define MLX4_EN_SAMPLE_INTERVAL         0
 139 #define MLX4_EN_AVG_PKT_SMALL           256
 140
 141 #define MLX4_EN_AUTO_CONF       0xffff
 142
 143 #define MLX4_EN_DEF_RX_PAUSE    1
 144 #define MLX4_EN_DEF_TX_PAUSE    1
 145
 146 /* Interval between successive polls in the Tx routine when polling is used
 147    instead of interrupts (in per-core Tx rings) - should be power of 2 */
 148 #define MLX4_EN_TX_POLL_MODER   16
 149 #define MLX4_EN_TX_POLL_TIMEOUT (HZ / 4)
 150
 151 #define ETH_LLC_SNAP_SIZE       8
 152
 153 #define SMALL_PACKET_SIZE      (256 - NET_IP_ALIGN)
 154 #define HEADER_COPY_SIZE       (128 - NET_IP_ALIGN)
 155 #define MLX4_LOOPBACK_TEST_PAYLOAD (HEADER_COPY_SIZE - ETH_HLEN)
 156
 157 #define MLX4_EN_MIN_MTU         46
 158 #define ETH_BCAST               0xffffffffffffULL
 159
 160 #define MLX4_EN_LOOPBACK_RETRIES        5
 161 #define MLX4_EN_LOOPBACK_TIMEOUT        100
 162
 163 #ifdef MLX4_EN_PERF_STAT
 164 /* Number of samples to 'average' */
 165 #define AVG_SIZE                        128
 166 #define AVG_FACTOR                      1024
 167 #define NUM_PERF_STATS                  NUM_PERF_COUNTERS
 168
 169 #define INC_PERF_COUNTER(cnt)           (++(cnt))
 170 #define ADD_PERF_COUNTER(cnt, add)      ((cnt) += (add))
 171 #define AVG_PERF_COUNTER(cnt, sample) \
 172         ((cnt) = ((cnt) * (AVG_SIZE - 1) + (sample) * AVG_FACTOR) / AVG_SIZE)
 173 #define GET_PERF_COUNTER(cnt)           (cnt)
 174 #define GET_AVG_PERF_COUNTER(cnt)       ((cnt) / AVG_FACTOR)
 175
 176 #else
 177
 178 #define NUM_PERF_STATS                  0
 179 #define INC_PERF_COUNTER(cnt)           do {} while (0)
 180 #define ADD_PERF_COUNTER(cnt, add)      do {} while (0)
 181 #define AVG_PERF_COUNTER(cnt, sample)   do {} while (0)
 182 #define GET_PERF_COUNTER(cnt)           (0)
 183 #define GET_AVG_PERF_COUNTER(cnt)       (0)
 184 #endif /* MLX4_EN_PERF_STAT */
 185
 186 /*
 187  * Configurables
 188  */
 189
 190 enum cq_type {
 191         RX = 0,
 192         TX = 1,
 193 };
 194
 195
 196 /*
 197  * Useful macros
 198  */
 199 #define ROUNDUP_LOG2(x)         ilog2(roundup_pow_of_two(x))
 200 #define XNOR(x, y)              (!(x) == !(y))
 201
 202
 203 struct mlx4_en_tx_info {
 204         struct sk_buff *skb;
 205         u32 nr_txbb;
 206         u32 nr_bytes;
 207         u8 linear;
 208         u8 data_offset;
 209         u8 inl;
 210 };
 211
 212
 213 #define MLX4_EN_BIT_DESC_OWN    0x80000000
 214 #define CTRL_SIZE       sizeof(struct mlx4_wqe_ctrl_seg)
 215 #define MLX4_EN_MEMTYPE_PAD     0x100
 216 #define DS_SIZE         sizeof(struct mlx4_wqe_data_seg)
 217
 218
 219 struct mlx4_en_tx_desc {
 220         struct mlx4_wqe_ctrl_seg ctrl;
 221         union {
 222                 struct mlx4_wqe_data_seg data; /* at least one data segment */
 223                 struct mlx4_wqe_lso_seg lso;
 224                 struct mlx4_wqe_inline_seg inl;
 225         };
 226 };
 227
 228 #define MLX4_EN_USE_SRQ         0x01000000
 229
 230 #define MLX4_EN_CX3_LOW_ID      0x1000
 231 #define MLX4_EN_CX3_HIGH_ID     0x1005
 232
 233 struct mlx4_en_rx_alloc {
 234         struct page *page;
 235         dma_addr_t dma;
 236         u16 offset;
 237 };
 238
 239 struct mlx4_en_tx_ring {
 240         struct mlx4_hwq_resources wqres;
 241         u32 size ; /* number of TXBBs */
 242         u32 size_mask;
 243         u16 stride;
 244         u16 cqn;        /* index of port CQ associated with this ring */
 245         u32 prod;
 246         u32 cons;
 247         u32 buf_size;
 248         u32 doorbell_qpn;
 249         void *buf;
 250         u16 poll_cnt;
 251         struct mlx4_en_tx_info *tx_info;
 252         u8 *bounce_buf;
 253         u32 last_nr_txbb;
 254         struct mlx4_qp qp;
 255         struct mlx4_qp_context context;
 256         int qpn;
 257         enum mlx4_qp_state qp_state;
 258         struct mlx4_srq dummy;
 259         unsigned long bytes;
 260         unsigned long packets;
 261         unsigned long tx_csum;
 262         struct mlx4_bf bf;
 263         bool bf_enabled;
 264         struct netdev_queue *tx_queue;
 265 };
 266
 267 struct mlx4_en_rx_desc {
 268         /* actual number of entries depends on rx ring stride */
 269         struct mlx4_wqe_data_seg data[0];
 270 };
 271
 272 struct mlx4_en_rx_ring {
 273         struct mlx4_hwq_resources wqres;
 274         struct mlx4_en_rx_alloc page_alloc[MLX4_EN_MAX_RX_FRAGS];
 275         u32 size ;      /* number of Rx descs*/
 276         u32 actual_size;
 277         u32 size_mask;
 278         u16 stride;
 279         u16 log_stride;
 280         u16 cqn;        /* index of port CQ associated with this ring */
 281         u32 prod;
 282         u32 cons;
 283         u32 buf_size;
 284         u8  fcs_del;
 285         void *buf;
 286         void *rx_info;
 287         unsigned long bytes;
 288         unsigned long packets;
 289         unsigned long csum_ok;
 290         unsigned long csum_none;
 291 };
 292
 293 struct mlx4_en_cq {
 294         struct mlx4_cq          mcq;
 295         struct mlx4_hwq_resources wqres;
 296         int                     ring;
 297         spinlock_t              lock;
 298         struct net_device      *dev;
 299         struct napi_struct      napi;
 300         int size;
 301         int buf_size;
 302         unsigned vector;
 303         enum cq_type is_tx;
 304         u16 moder_time;
 305         u16 moder_cnt;
 306         struct mlx4_cqe *buf;
 307 #define MLX4_EN_OPCODE_ERROR    0x1e
 308 };
 309
 310 struct mlx4_en_port_profile {
 311         u32 flags;
 312         u32 tx_ring_num;
 313         u32 rx_ring_num;
 314         u32 tx_ring_size;
 315         u32 rx_ring_size;
 316         u8 rx_pause;
 317         u8 rx_ppp;
 318         u8 tx_pause;
 319         u8 tx_ppp;
 320         int rss_rings;
 321 };
 322
 323 struct mlx4_en_profile {
 324         int rss_xor;
 325         int udp_rss;
 326         u8 rss_mask;
 327         u32 active_ports;
 328         u32 small_pkt_int;
 329         u8 no_reset;
 330         u8 num_tx_rings_p_up;
 331         struct mlx4_en_port_profile prof[MLX4_MAX_PORTS + 1];
 332 };
 333
 334 struct mlx4_en_dev {
 335         struct mlx4_dev         *dev;
 336         struct pci_dev          *pdev;
 337         struct mutex            state_lock;
 338         struct net_device       *pndev[MLX4_MAX_PORTS + 1];
 339         u32                     port_cnt;
 340         bool                    device_up;
 341         struct mlx4_en_profile  profile;
 342         u32                     LSO_support;
 343         struct workqueue_struct *workqueue;
 344         struct device           *dma_device;
 345         void __iomem            *uar_map;
 346         struct mlx4_uar         priv_uar;
 347         struct mlx4_mr          mr;
 348         u32                     priv_pdn;
 349         spinlock_t              uar_lock;
 350         u8                      mac_removed[MLX4_MAX_PORTS + 1];
 351 };
 352
 353
 354 struct mlx4_en_rss_map {
 355         int base_qpn;
 356         struct mlx4_qp qps[MAX_RX_RINGS];
 357         enum mlx4_qp_state state[MAX_RX_RINGS];
 358         struct mlx4_qp indir_qp;
 359         enum mlx4_qp_state indir_state;
 360 };
 361
 362 struct mlx4_en_port_state {
 363         int link_state;
 364         int link_speed;
 365         int transciver;
 366 };
 367
 368 struct mlx4_en_pkt_stats {
 369         unsigned long broadcast;
 370         unsigned long rx_prio[8];
 371         unsigned long tx_prio[8];
 372 #define NUM_PKT_STATS           17
 373 };
 374
 375 struct mlx4_en_port_stats {
 376         unsigned long tso_packets;
 377         unsigned long queue_stopped;
 378         unsigned long wake_queue;
 379         unsigned long tx_timeout;
 380         unsigned long rx_alloc_failed;
 381         unsigned long rx_chksum_good;
 382         unsigned long rx_chksum_none;
 383         unsigned long tx_chksum_offload;
 384 #define NUM_PORT_STATS          8
 385 };
 386
 387 struct mlx4_en_perf_stats {
 388         u32 tx_poll;
 389         u64 tx_pktsz_avg;
 390         u32 inflight_avg;
 391         u16 tx_coal_avg;
 392         u16 rx_coal_avg;
 393         u32 napi_quota;
 394 #define NUM_PERF_COUNTERS               6
 395 };
 396
 397 enum mlx4_en_mclist_act {
 398         MCLIST_NONE,
 399         MCLIST_REM,
 400         MCLIST_ADD,
 401 };
 402
 403 struct mlx4_en_mc_list {
 404         struct list_head        list;
 405         enum mlx4_en_mclist_act action;
 406         u8                      addr[ETH_ALEN];
 407         u64                     reg_id;
 408 };
 409
 410 struct mlx4_en_frag_info {
 411         u16 frag_size;
 412         u16 frag_prefix_size;
 413         u16 frag_stride;
 414         u16 frag_align;
 415         u16 last_offset;
 416
 417 };
 418
 419 #ifdef CONFIG_MLX4_EN_DCB
 420 /* Minimal TC BW - setting to 0 will block traffic */
 421 #define MLX4_EN_BW_MIN 1
 422 #define MLX4_EN_BW_MAX 100 /* Utilize 100% of the line */
 423
 424 #define MLX4_EN_TC_ETS 7
 425
 426 #endif
 427
 428 struct ethtool_flow_id {
 429         struct list_head list;
 430         struct ethtool_rx_flow_spec flow_spec;
 431         u64 id;
 432 };
 433
 434 enum {
 435         MLX4_EN_FLAG_PROMISC            = (1 << 0),
 436         MLX4_EN_FLAG_MC_PROMISC         = (1 << 1),
 437         /* whether we need to enable hardware loopback by putting dmac
 438          * in Tx WQE
 439          */
 440         MLX4_EN_FLAG_ENABLE_HW_LOOPBACK = (1 << 2),
 441         /* whether we need to drop packets that hardware loopback-ed */
 442         MLX4_EN_FLAG_RX_FILTER_NEEDED   = (1 << 3)
 443 };
 444
 445 struct mlx4_en_priv {
 446         struct mlx4_en_dev *mdev;
 447         struct mlx4_en_port_profile *prof;
 448         struct net_device *dev;
 449         unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
 450         struct net_device_stats stats;
 451         struct net_device_stats ret_stats;
 452         struct mlx4_en_port_state port_state;
 453         spinlock_t stats_lock;
 454         struct ethtool_flow_id ethtool_rules[MAX_NUM_OF_FS_RULES];
 455         /* To allow rules removal while port is going down */
 456         struct list_head ethtool_list;
 457
 458         unsigned long last_moder_packets[MAX_RX_RINGS];
 459         unsigned long last_moder_tx_packets;
 460         unsigned long last_moder_bytes[MAX_RX_RINGS];
 461         unsigned long last_moder_jiffies;
 462         int last_moder_time[MAX_RX_RINGS];
 463         u16 rx_usecs;
 464         u16 rx_frames;
 465         u16 tx_usecs;
 466         u16 tx_frames;
 467         u32 pkt_rate_low;
 468         u16 rx_usecs_low;
 469         u32 pkt_rate_high;
 470         u16 rx_usecs_high;
 471         u16 sample_interval;
 472         u16 adaptive_rx_coal;
 473         u32 msg_enable;
 474         u32 loopback_ok;
 475         u32 validate_loopback;
 476
 477         struct mlx4_hwq_resources res;
 478         int link_state;
 479         int last_link_state;
 480         bool port_up;
 481         int port;
 482         int registered;
 483         int allocated;
 484         int stride;
 485         unsigned char prev_mac[ETH_ALEN + 2];
 486         int mac_index;
 487         unsigned max_mtu;
 488         int base_qpn;
 489         int cqe_factor;
 490
 491         struct mlx4_en_rss_map rss_map;
 492         __be32 ctrl_flags;
 493         u32 flags;
 494         u8 num_tx_rings_p_up;
 495         u32 tx_ring_num;
 496         u32 rx_ring_num;
 497         u32 rx_skb_size;
 498         struct mlx4_en_frag_info frag_info[MLX4_EN_MAX_RX_FRAGS];
 499         u16 num_frags;
 500         u16 log_rx_info;
 501
 502         struct mlx4_en_tx_ring *tx_ring;
 503         struct mlx4_en_rx_ring rx_ring[MAX_RX_RINGS];
 504         struct mlx4_en_cq *tx_cq;
 505         struct mlx4_en_cq rx_cq[MAX_RX_RINGS];
 506         struct mlx4_qp drop_qp;
 507         struct work_struct mcast_task;
 508         struct work_struct mac_task;
 509         struct work_struct watchdog_task;
 510         struct work_struct linkstate_task;
 511         struct delayed_work stats_task;
 512         struct mlx4_en_perf_stats pstats;
 513         struct mlx4_en_pkt_stats pkstats;
 514         struct mlx4_en_port_stats port_stats;
 515         u64 stats_bitmap;
 516         struct list_head mc_list;
 517         struct list_head curr_list;
 518         u64 broadcast_id;
 519         struct mlx4_en_stat_out_mbox hw_stats;
 520         int vids[128];
 521         bool wol;
 522         struct device *ddev;
 523         int base_tx_qpn;
 524
 525 #ifdef CONFIG_MLX4_EN_DCB
 526         struct ieee_ets ets;
 527         u16 maxrate[IEEE_8021QAZ_MAX_TCS];
 528 #endif
 529 #ifdef CONFIG_RFS_ACCEL
 530         spinlock_t filters_lock;
 531         int last_filter_id;
 532         struct list_head filters;
 533         struct hlist_head filter_hash[1 << MLX4_EN_FILTER_HASH_SHIFT];
 534 #endif
 535
 536 };
 537
 538 enum mlx4_en_wol {
 539         MLX4_EN_WOL_MAGIC = (1ULL << 61),
 540         MLX4_EN_WOL_ENABLED = (1ULL << 62),
 541 };
 542
 543 #define MLX4_EN_WOL_DO_MODIFY (1ULL << 63)
 544
 545 void mlx4_en_update_loopback_state(struct net_device *dev,
 546                                    netdev_features_t features);
 547
 548 void mlx4_en_destroy_netdev(struct net_device *dev);
 549 int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port,
 550                         struct mlx4_en_port_profile *prof);
 551
 552 int mlx4_en_start_port(struct net_device *dev);
 553 void mlx4_en_stop_port(struct net_device *dev, int detach);
 554
 555 void mlx4_en_free_resources(struct mlx4_en_priv *priv);
 556 int mlx4_en_alloc_resources(struct mlx4_en_priv *priv);
 557
 558 int mlx4_en_create_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq,
 559                       int entries, int ring, enum cq_type mode);
 560 void mlx4_en_destroy_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
 561 int mlx4_en_activate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq,
 562                         int cq_idx);
 563 void mlx4_en_deactivate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
 564 int mlx4_en_set_cq_moder(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
 565 int mlx4_en_arm_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
 566
 567 void mlx4_en_tx_irq(struct mlx4_cq *mcq);
 568 u16 mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb);
 569 netdev_tx_t mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev);
 570
 571 int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv, struct mlx4_en_tx_ring *ring,
 572                            int qpn, u32 size, u16 stride);
 573 void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv, struct mlx4_en_tx_ring *ring);
 574 int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv,
 575                              struct mlx4_en_tx_ring *ring,
 576                              int cq, int user_prio);
 577 void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv,
 578                                 struct mlx4_en_tx_ring *ring);
 579
 580 int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv,
 581                            struct mlx4_en_rx_ring *ring,
 582                            u32 size, u16 stride);
 583 void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv,
 584                              struct mlx4_en_rx_ring *ring,
 585                              u32 size, u16 stride);
 586 int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv);
 587 void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv,
 588                                 struct mlx4_en_rx_ring *ring);
 589 int mlx4_en_process_rx_cq(struct net_device *dev,
 590                           struct mlx4_en_cq *cq,
 591                           int budget);
 592 int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget);
 593 void mlx4_en_fill_qp_context(struct mlx4_en_priv *priv, int size, int stride,
 594                 int is_tx, int rss, int qpn, int cqn, int user_prio,
 595                 struct mlx4_qp_context *context);
 596 void mlx4_en_sqp_event(struct mlx4_qp *qp, enum mlx4_event event);
 597 int mlx4_en_map_buffer(struct mlx4_buf *buf);
 598 void mlx4_en_unmap_buffer(struct mlx4_buf *buf);
 599
 600 void mlx4_en_calc_rx_buf(struct net_device *dev);
 601 int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv);
 602 void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv);
 603 int mlx4_en_create_drop_qp(struct mlx4_en_priv *priv);
 604 void mlx4_en_destroy_drop_qp(struct mlx4_en_priv *priv);
 605 int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring);
 606 void mlx4_en_rx_irq(struct mlx4_cq *mcq);
 607
 608 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode);
 609 int mlx4_SET_VLAN_FLTR(struct mlx4_dev *dev, struct mlx4_en_priv *priv);
 610
 611 int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev *mdev, u8 port, u8 reset);
 612 int mlx4_en_QUERY_PORT(struct mlx4_en_dev *mdev, u8 port);
 613
 614 #ifdef CONFIG_MLX4_EN_DCB
 615 extern const struct dcbnl_rtnl_ops mlx4_en_dcbnl_ops;
 616 #endif
 617
 618 int mlx4_en_setup_tc(struct net_device *dev, u8 up);
 619
 620 #ifdef CONFIG_RFS_ACCEL
 621 void mlx4_en_cleanup_filters(struct mlx4_en_priv *priv,
 622                              struct mlx4_en_rx_ring *rx_ring);
 623 #endif
 624
 625 #define MLX4_EN_NUM_SELF_TEST   5
 626 void mlx4_en_ex_selftest(struct net_device *dev, u32 *flags, u64 *buf);
 627 u64 mlx4_en_mac_to_u64(u8 *addr);
 628
 629 /*
 630  * Globals
 631  */
 632 extern const struct ethtool_ops mlx4_en_ethtool_ops;
 633
 634
 635
 636 /*
 637  * printk / logging functions
 638  */
 639
 640 __printf(3, 4)
 641 int en_print(const char *level, const struct mlx4_en_priv *priv,
 642              const char *format, ...);
 643
 644 #define en_dbg(mlevel, priv, format, arg...)                    \
 645 do {                                                            \
 646         if (NETIF_MSG_##mlevel & priv->msg_enable)              \
 647                 en_print(KERN_DEBUG, priv, format, ##arg);      \
 648 } while (0)
 649 #define en_warn(priv, format, arg...)                   \
 650         en_print(KERN_WARNING, priv, format, ##arg)
 651 #define en_err(priv, format, arg...)                    \
 652         en_print(KERN_ERR, priv, format, ##arg)
 653 #define en_info(priv, format, arg...)                   \
 654         en_print(KERN_INFO, priv, format, ## arg)
 655
 656 #define mlx4_err(mdev, format, arg...)                  \
 657         pr_err("%s %s: " format, DRV_NAME,              \
 658                dev_name(&mdev->pdev->dev), ##arg)
 659 #define mlx4_info(mdev, format, arg...)                 \
 660         pr_info("%s %s: " format, DRV_NAME,             \
 661                 dev_name(&mdev->pdev->dev), ##arg)
 662 #define mlx4_warn(mdev, format, arg...)                 \
 663         pr_warning("%s %s: " format, DRV_NAME,          \
 664                    dev_name(&mdev->pdev->dev), ##arg)
 665
 666 #endif