drivers/net/ethernet/mellanox/mlx4/mlx4_en.h

   1 /*
   2  * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  *
  32  */
  33
  34 #ifndef _MLX4_EN_H_
  35 #define _MLX4_EN_H_
  36
  37 #include <linux/bitops.h>
  38 #include <linux/compiler.h>
  39 #include <linux/list.h>
  40 #include <linux/mutex.h>
  41 #include <linux/netdevice.h>
  42 #include <linux/if_vlan.h>
  43 #ifdef CONFIG_MLX4_EN_DCB
  44 #include <linux/dcbnl.h>
  45 #endif
  46
  47 #include <linux/mlx4/device.h>
  48 #include <linux/mlx4/qp.h>
  49 #include <linux/mlx4/cq.h>
  50 #include <linux/mlx4/srq.h>
  51 #include <linux/mlx4/doorbell.h>
  52 #include <linux/mlx4/cmd.h>
  53
  54 #include "en_port.h"
  55
  56 #define DRV_NAME        "mlx4_en"
  57 #define DRV_VERSION     "2.0"
  58 #define DRV_RELDATE     "Dec 2011"
  59
  60 #define MLX4_EN_MSG_LEVEL       (NETIF_MSG_LINK | NETIF_MSG_IFDOWN)
  61
  62 /*
  63  * Device constants
  64  */
  65
  66
  67 #define MLX4_EN_PAGE_SHIFT      12
  68 #define MLX4_EN_PAGE_SIZE       (1 << MLX4_EN_PAGE_SHIFT)
  69 #define MAX_RX_RINGS            16
  70 #define MIN_RX_RINGS            4
  71 #define TXBB_SIZE               64
  72 #define HEADROOM                (2048 / TXBB_SIZE + 1)
  73 #define STAMP_STRIDE            64
  74 #define STAMP_DWORDS            (STAMP_STRIDE / 4)
  75 #define STAMP_SHIFT             31
  76 #define STAMP_VAL               0x7fffffff
  77 #define STATS_DELAY             (HZ / 4)
  78 #define MAX_NUM_OF_FS_RULES     256
  79
  80 /* Typical TSO descriptor with 16 gather entries is 352 bytes... */
  81 #define MAX_DESC_SIZE           512
  82 #define MAX_DESC_TXBBS          (MAX_DESC_SIZE / TXBB_SIZE)
  83
  84 /*
  85  * OS related constants and tunables
  86  */
  87
  88 #define MLX4_EN_WATCHDOG_TIMEOUT        (15 * HZ)
  89
  90 /* Use the maximum between 16384 and a single page */
  91 #define MLX4_EN_ALLOC_SIZE      PAGE_ALIGN(16384)
  92 #define MLX4_EN_ALLOC_ORDER     get_order(MLX4_EN_ALLOC_SIZE)
  93
  94 #define MLX4_EN_MAX_LRO_DESCRIPTORS     32
  95
  96 /* Receive fragment sizes; we use at most 4 fragments (for 9600 byte MTU
  97  * and 4K allocations) */
  98 enum {
  99         FRAG_SZ0 = 512 - NET_IP_ALIGN,
 100         FRAG_SZ1 = 1024,
 101         FRAG_SZ2 = 4096,
 102         FRAG_SZ3 = MLX4_EN_ALLOC_SIZE
 103 };
 104 #define MLX4_EN_MAX_RX_FRAGS    4
 105
 106 /* Maximum ring sizes */
 107 #define MLX4_EN_MAX_TX_SIZE     8192
 108 #define MLX4_EN_MAX_RX_SIZE     8192
 109
 110 /* Minimum ring size for our page-allocation sceme to work */
 111 #define MLX4_EN_MIN_RX_SIZE     (MLX4_EN_ALLOC_SIZE / SMP_CACHE_BYTES)
 112 #define MLX4_EN_MIN_TX_SIZE     (4096 / TXBB_SIZE)
 113
 114 #define MLX4_EN_SMALL_PKT_SIZE          64
 115 #define MLX4_EN_MAX_TX_RING_P_UP        32
 116 #define MLX4_EN_NUM_UP                  8
 117 #define MLX4_EN_DEF_TX_RING_SIZE        512
 118 #define MLX4_EN_DEF_RX_RING_SIZE        1024
 119
 120 /* Target number of packets to coalesce with interrupt moderation */
 121 #define MLX4_EN_RX_COAL_TARGET  44
 122 #define MLX4_EN_RX_COAL_TIME    0x10
 123
 124 #define MLX4_EN_TX_COAL_PKTS    16
 125 #define MLX4_EN_TX_COAL_TIME    0x80
 126
 127 #define MLX4_EN_RX_RATE_LOW             400000
 128 #define MLX4_EN_RX_COAL_TIME_LOW        0
 129 #define MLX4_EN_RX_RATE_HIGH            450000
 130 #define MLX4_EN_RX_COAL_TIME_HIGH       128
 131 #define MLX4_EN_RX_SIZE_THRESH          1024
 132 #define MLX4_EN_RX_RATE_THRESH          (1000000 / MLX4_EN_RX_COAL_TIME_HIGH)
 133 #define MLX4_EN_SAMPLE_INTERVAL         0
 134 #define MLX4_EN_AVG_PKT_SMALL           256
 135
 136 #define MLX4_EN_AUTO_CONF       0xffff
 137
 138 #define MLX4_EN_DEF_RX_PAUSE    1
 139 #define MLX4_EN_DEF_TX_PAUSE    1
 140
 141 /* Interval between successive polls in the Tx routine when polling is used
 142    instead of interrupts (in per-core Tx rings) - should be power of 2 */
 143 #define MLX4_EN_TX_POLL_MODER   16
 144 #define MLX4_EN_TX_POLL_TIMEOUT (HZ / 4)
 145
 146 #define ETH_LLC_SNAP_SIZE       8
 147
 148 #define SMALL_PACKET_SIZE      (256 - NET_IP_ALIGN)
 149 #define HEADER_COPY_SIZE       (128 - NET_IP_ALIGN)
 150 #define MLX4_LOOPBACK_TEST_PAYLOAD (HEADER_COPY_SIZE - ETH_HLEN)
 151
 152 #define MLX4_EN_MIN_MTU         46
 153 #define ETH_BCAST               0xffffffffffffULL
 154
 155 #define MLX4_EN_LOOPBACK_RETRIES        5
 156 #define MLX4_EN_LOOPBACK_TIMEOUT        100
 157
 158 #ifdef MLX4_EN_PERF_STAT
 159 /* Number of samples to 'average' */
 160 #define AVG_SIZE                        128
 161 #define AVG_FACTOR                      1024
 162 #define NUM_PERF_STATS                  NUM_PERF_COUNTERS
 163
 164 #define INC_PERF_COUNTER(cnt)           (++(cnt))
 165 #define ADD_PERF_COUNTER(cnt, add)      ((cnt) += (add))
 166 #define AVG_PERF_COUNTER(cnt, sample) \
 167         ((cnt) = ((cnt) * (AVG_SIZE - 1) + (sample) * AVG_FACTOR) / AVG_SIZE)
 168 #define GET_PERF_COUNTER(cnt)           (cnt)
 169 #define GET_AVG_PERF_COUNTER(cnt)       ((cnt) / AVG_FACTOR)
 170
 171 #else
 172
 173 #define NUM_PERF_STATS                  0
 174 #define INC_PERF_COUNTER(cnt)           do {} while (0)
 175 #define ADD_PERF_COUNTER(cnt, add)      do {} while (0)
 176 #define AVG_PERF_COUNTER(cnt, sample)   do {} while (0)
 177 #define GET_PERF_COUNTER(cnt)           (0)
 178 #define GET_AVG_PERF_COUNTER(cnt)       (0)
 179 #endif /* MLX4_EN_PERF_STAT */
 180
 181 /*
 182  * Configurables
 183  */
 184
 185 enum cq_type {
 186         RX = 0,
 187         TX = 1,
 188 };
 189
 190
 191 /*
 192  * Useful macros
 193  */
 194 #define ROUNDUP_LOG2(x)         ilog2(roundup_pow_of_two(x))
 195 #define XNOR(x, y)              (!(x) == !(y))
 196 #define ILLEGAL_MAC(addr)       (addr == 0xffffffffffffULL || addr == 0x0)
 197
 198
 199 struct mlx4_en_tx_info {
 200         struct sk_buff *skb;
 201         u32 nr_txbb;
 202         u32 nr_bytes;
 203         u8 linear;
 204         u8 data_offset;
 205         u8 inl;
 206 };
 207
 208
 209 #define MLX4_EN_BIT_DESC_OWN    0x80000000
 210 #define CTRL_SIZE       sizeof(struct mlx4_wqe_ctrl_seg)
 211 #define MLX4_EN_MEMTYPE_PAD     0x100
 212 #define DS_SIZE         sizeof(struct mlx4_wqe_data_seg)
 213
 214
 215 struct mlx4_en_tx_desc {
 216         struct mlx4_wqe_ctrl_seg ctrl;
 217         union {
 218                 struct mlx4_wqe_data_seg data; /* at least one data segment */
 219                 struct mlx4_wqe_lso_seg lso;
 220                 struct mlx4_wqe_inline_seg inl;
 221         };
 222 };
 223
 224 #define MLX4_EN_USE_SRQ         0x01000000
 225
 226 #define MLX4_EN_CX3_LOW_ID      0x1000
 227 #define MLX4_EN_CX3_HIGH_ID     0x1005
 228
 229 struct mlx4_en_rx_alloc {
 230         struct page *page;
 231         u16 offset;
 232 };
 233
 234 struct mlx4_en_tx_ring {
 235         struct mlx4_hwq_resources wqres;
 236         u32 size ; /* number of TXBBs */
 237         u32 size_mask;
 238         u16 stride;
 239         u16 cqn;        /* index of port CQ associated with this ring */
 240         u32 prod;
 241         u32 cons;
 242         u32 buf_size;
 243         u32 doorbell_qpn;
 244         void *buf;
 245         u16 poll_cnt;
 246         int blocked;
 247         struct mlx4_en_tx_info *tx_info;
 248         u8 *bounce_buf;
 249         u32 last_nr_txbb;
 250         struct mlx4_qp qp;
 251         struct mlx4_qp_context context;
 252         int qpn;
 253         enum mlx4_qp_state qp_state;
 254         struct mlx4_srq dummy;
 255         unsigned long bytes;
 256         unsigned long packets;
 257         unsigned long tx_csum;
 258         struct mlx4_bf bf;
 259         bool bf_enabled;
 260         struct netdev_queue *tx_queue;
 261 };
 262
 263 struct mlx4_en_rx_desc {
 264         /* actual number of entries depends on rx ring stride */
 265         struct mlx4_wqe_data_seg data[0];
 266 };
 267
 268 struct mlx4_en_rx_ring {
 269         struct mlx4_hwq_resources wqres;
 270         struct mlx4_en_rx_alloc page_alloc[MLX4_EN_MAX_RX_FRAGS];
 271         u32 size ;      /* number of Rx descs*/
 272         u32 actual_size;
 273         u32 size_mask;
 274         u16 stride;
 275         u16 log_stride;
 276         u16 cqn;        /* index of port CQ associated with this ring */
 277         u32 prod;
 278         u32 cons;
 279         u32 buf_size;
 280         u8  fcs_del;
 281         void *buf;
 282         void *rx_info;
 283         unsigned long bytes;
 284         unsigned long packets;
 285         unsigned long csum_ok;
 286         unsigned long csum_none;
 287 };
 288
 289
 290 static inline int mlx4_en_can_lro(__be16 status)
 291 {
 292         return (status & cpu_to_be16(MLX4_CQE_STATUS_IPV4       |
 293                                      MLX4_CQE_STATUS_IPV4F      |
 294                                      MLX4_CQE_STATUS_IPV6       |
 295                                      MLX4_CQE_STATUS_IPV4OPT    |
 296                                      MLX4_CQE_STATUS_TCP        |
 297                                      MLX4_CQE_STATUS_UDP        |
 298                                      MLX4_CQE_STATUS_IPOK)) ==
 299                 cpu_to_be16(MLX4_CQE_STATUS_IPV4 |
 300                             MLX4_CQE_STATUS_IPOK |
 301                             MLX4_CQE_STATUS_TCP);
 302 }
 303
 304 struct mlx4_en_cq {
 305         struct mlx4_cq          mcq;
 306         struct mlx4_hwq_resources wqres;
 307         int                     ring;
 308         spinlock_t              lock;
 309         struct net_device      *dev;
 310         struct napi_struct      napi;
 311         int size;
 312         int buf_size;
 313         unsigned vector;
 314         enum cq_type is_tx;
 315         u16 moder_time;
 316         u16 moder_cnt;
 317         struct mlx4_cqe *buf;
 318 #define MLX4_EN_OPCODE_ERROR    0x1e
 319 };
 320
 321 struct mlx4_en_port_profile {
 322         u32 flags;
 323         u32 tx_ring_num;
 324         u32 rx_ring_num;
 325         u32 tx_ring_size;
 326         u32 rx_ring_size;
 327         u8 rx_pause;
 328         u8 rx_ppp;
 329         u8 tx_pause;
 330         u8 tx_ppp;
 331         int rss_rings;
 332 };
 333
 334 struct mlx4_en_profile {
 335         int rss_xor;
 336         int udp_rss;
 337         u8 rss_mask;
 338         u32 active_ports;
 339         u32 small_pkt_int;
 340         u8 no_reset;
 341         u8 num_tx_rings_p_up;
 342         struct mlx4_en_port_profile prof[MLX4_MAX_PORTS + 1];
 343 };
 344
 345 struct mlx4_en_dev {
 346         struct mlx4_dev         *dev;
 347         struct pci_dev          *pdev;
 348         struct mutex            state_lock;
 349         struct net_device       *pndev[MLX4_MAX_PORTS + 1];
 350         u32                     port_cnt;
 351         bool                    device_up;
 352         struct mlx4_en_profile  profile;
 353         u32                     LSO_support;
 354         struct workqueue_struct *workqueue;
 355         struct device           *dma_device;
 356         void __iomem            *uar_map;
 357         struct mlx4_uar         priv_uar;
 358         struct mlx4_mr          mr;
 359         u32                     priv_pdn;
 360         spinlock_t              uar_lock;
 361         u8                      mac_removed[MLX4_MAX_PORTS + 1];
 362 };
 363
 364
 365 struct mlx4_en_rss_map {
 366         int base_qpn;
 367         struct mlx4_qp qps[MAX_RX_RINGS];
 368         enum mlx4_qp_state state[MAX_RX_RINGS];
 369         struct mlx4_qp indir_qp;
 370         enum mlx4_qp_state indir_state;
 371 };
 372
 373 struct mlx4_en_port_state {
 374         int link_state;
 375         int link_speed;
 376         int transciver;
 377 };
 378
 379 struct mlx4_en_pkt_stats {
 380         unsigned long broadcast;
 381         unsigned long rx_prio[8];
 382         unsigned long tx_prio[8];
 383 #define NUM_PKT_STATS           17
 384 };
 385
 386 struct mlx4_en_port_stats {
 387         unsigned long tso_packets;
 388         unsigned long queue_stopped;
 389         unsigned long wake_queue;
 390         unsigned long tx_timeout;
 391         unsigned long rx_alloc_failed;
 392         unsigned long rx_chksum_good;
 393         unsigned long rx_chksum_none;
 394         unsigned long tx_chksum_offload;
 395 #define NUM_PORT_STATS          8
 396 };
 397
 398 struct mlx4_en_perf_stats {
 399         u32 tx_poll;
 400         u64 tx_pktsz_avg;
 401         u32 inflight_avg;
 402         u16 tx_coal_avg;
 403         u16 rx_coal_avg;
 404         u32 napi_quota;
 405 #define NUM_PERF_COUNTERS               6
 406 };
 407
 408 enum mlx4_en_mclist_act {
 409         MCLIST_NONE,
 410         MCLIST_REM,
 411         MCLIST_ADD,
 412 };
 413
 414 struct mlx4_en_mc_list {
 415         struct list_head        list;
 416         enum mlx4_en_mclist_act action;
 417         u8                      addr[ETH_ALEN];
 418         u64                     reg_id;
 419 };
 420
 421 struct mlx4_en_frag_info {
 422         u16 frag_size;
 423         u16 frag_prefix_size;
 424         u16 frag_stride;
 425         u16 frag_align;
 426         u16 last_offset;
 427
 428 };
 429
 430 #ifdef CONFIG_MLX4_EN_DCB
 431 /* Minimal TC BW - setting to 0 will block traffic */
 432 #define MLX4_EN_BW_MIN 1
 433 #define MLX4_EN_BW_MAX 100 /* Utilize 100% of the line */
 434
 435 #define MLX4_EN_TC_ETS 7
 436
 437 #endif
 438
 439 struct ethtool_flow_id {
 440         struct ethtool_rx_flow_spec flow_spec;
 441         u64 id;
 442 };
 443
 444 struct mlx4_en_priv {
 445         struct mlx4_en_dev *mdev;
 446         struct mlx4_en_port_profile *prof;
 447         struct net_device *dev;
 448         unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
 449         struct net_device_stats stats;
 450         struct net_device_stats ret_stats;
 451         struct mlx4_en_port_state port_state;
 452         spinlock_t stats_lock;
 453         struct ethtool_flow_id ethtool_rules[MAX_NUM_OF_FS_RULES];
 454
 455         unsigned long last_moder_packets[MAX_RX_RINGS];
 456         unsigned long last_moder_tx_packets;
 457         unsigned long last_moder_bytes[MAX_RX_RINGS];
 458         unsigned long last_moder_jiffies;
 459         int last_moder_time[MAX_RX_RINGS];
 460         u16 rx_usecs;
 461         u16 rx_frames;
 462         u16 tx_usecs;
 463         u16 tx_frames;
 464         u32 pkt_rate_low;
 465         u16 rx_usecs_low;
 466         u32 pkt_rate_high;
 467         u16 rx_usecs_high;
 468         u16 sample_interval;
 469         u16 adaptive_rx_coal;
 470         u32 msg_enable;
 471         u32 loopback_ok;
 472         u32 validate_loopback;
 473
 474         struct mlx4_hwq_resources res;
 475         int link_state;
 476         int last_link_state;
 477         bool port_up;
 478         int port;
 479         int registered;
 480         int allocated;
 481         int stride;
 482         u64 mac;
 483         int mac_index;
 484         unsigned max_mtu;
 485         int base_qpn;
 486
 487         struct mlx4_en_rss_map rss_map;
 488         __be32 ctrl_flags;
 489         u32 flags;
 490 #define MLX4_EN_FLAG_PROMISC    0x1
 491 #define MLX4_EN_FLAG_MC_PROMISC 0x2
 492         u32 tx_ring_num;
 493         u32 rx_ring_num;
 494         u32 rx_skb_size;
 495         struct mlx4_en_frag_info frag_info[MLX4_EN_MAX_RX_FRAGS];
 496         u16 num_frags;
 497         u16 log_rx_info;
 498
 499         struct mlx4_en_tx_ring *tx_ring;
 500         struct mlx4_en_rx_ring rx_ring[MAX_RX_RINGS];
 501         struct mlx4_en_cq *tx_cq;
 502         struct mlx4_en_cq rx_cq[MAX_RX_RINGS];
 503         struct mlx4_qp drop_qp;
 504         struct work_struct mcast_task;
 505         struct work_struct mac_task;
 506         struct work_struct watchdog_task;
 507         struct work_struct linkstate_task;
 508         struct delayed_work stats_task;
 509         struct mlx4_en_perf_stats pstats;
 510         struct mlx4_en_pkt_stats pkstats;
 511         struct mlx4_en_port_stats port_stats;
 512         u64 stats_bitmap;
 513         struct list_head mc_list;
 514         struct list_head curr_list;
 515         u64 broadcast_id;
 516         struct mlx4_en_stat_out_mbox hw_stats;
 517         int vids[128];
 518         bool wol;
 519         struct device *ddev;
 520         int base_tx_qpn;
 521
 522 #ifdef CONFIG_MLX4_EN_DCB
 523         struct ieee_ets ets;
 524         u16 maxrate[IEEE_8021QAZ_MAX_TCS];
 525 #endif
 526 };
 527
 528 enum mlx4_en_wol {
 529         MLX4_EN_WOL_MAGIC = (1ULL << 61),
 530         MLX4_EN_WOL_ENABLED = (1ULL << 62),
 531 };
 532
 533 #define MLX4_EN_WOL_DO_MODIFY (1ULL << 63)
 534
 535 void mlx4_en_destroy_netdev(struct net_device *dev);
 536 int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port,
 537                         struct mlx4_en_port_profile *prof);
 538
 539 int mlx4_en_start_port(struct net_device *dev);
 540 void mlx4_en_stop_port(struct net_device *dev);
 541
 542 void mlx4_en_free_resources(struct mlx4_en_priv *priv);
 543 int mlx4_en_alloc_resources(struct mlx4_en_priv *priv);
 544
 545 int mlx4_en_create_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq,
 546                       int entries, int ring, enum cq_type mode);
 547 void mlx4_en_destroy_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
 548 int mlx4_en_activate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq,
 549                         int cq_idx);
 550 void mlx4_en_deactivate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
 551 int mlx4_en_set_cq_moder(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
 552 int mlx4_en_arm_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
 553
 554 void mlx4_en_tx_irq(struct mlx4_cq *mcq);
 555 u16 mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb);
 556 netdev_tx_t mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev);
 557
 558 int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv, struct mlx4_en_tx_ring *ring,
 559                            int qpn, u32 size, u16 stride);
 560 void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv, struct mlx4_en_tx_ring *ring);
 561 int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv,
 562                              struct mlx4_en_tx_ring *ring,
 563                              int cq, int user_prio);
 564 void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv,
 565                                 struct mlx4_en_tx_ring *ring);
 566
 567 int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv,
 568                            struct mlx4_en_rx_ring *ring,
 569                            u32 size, u16 stride);
 570 void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv,
 571                              struct mlx4_en_rx_ring *ring,
 572                              u32 size, u16 stride);
 573 int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv);
 574 void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv,
 575                                 struct mlx4_en_rx_ring *ring);
 576 int mlx4_en_process_rx_cq(struct net_device *dev,
 577                           struct mlx4_en_cq *cq,
 578                           int budget);
 579 int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget);
 580 void mlx4_en_fill_qp_context(struct mlx4_en_priv *priv, int size, int stride,
 581                 int is_tx, int rss, int qpn, int cqn, int user_prio,
 582                 struct mlx4_qp_context *context);
 583 void mlx4_en_sqp_event(struct mlx4_qp *qp, enum mlx4_event event);
 584 int mlx4_en_map_buffer(struct mlx4_buf *buf);
 585 void mlx4_en_unmap_buffer(struct mlx4_buf *buf);
 586
 587 void mlx4_en_calc_rx_buf(struct net_device *dev);
 588 int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv);
 589 void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv);
 590 int mlx4_en_create_drop_qp(struct mlx4_en_priv *priv);
 591 void mlx4_en_destroy_drop_qp(struct mlx4_en_priv *priv);
 592 int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring);
 593 void mlx4_en_rx_irq(struct mlx4_cq *mcq);
 594
 595 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode);
 596 int mlx4_SET_VLAN_FLTR(struct mlx4_dev *dev, struct mlx4_en_priv *priv);
 597
 598 int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev *mdev, u8 port, u8 reset);
 599 int mlx4_en_QUERY_PORT(struct mlx4_en_dev *mdev, u8 port);
 600
 601 #ifdef CONFIG_MLX4_EN_DCB
 602 extern const struct dcbnl_rtnl_ops mlx4_en_dcbnl_ops;
 603 #endif
 604
 605 #define MLX4_EN_NUM_SELF_TEST   5
 606 void mlx4_en_ex_selftest(struct net_device *dev, u32 *flags, u64 *buf);
 607 u64 mlx4_en_mac_to_u64(u8 *addr);
 608
 609 /*
 610  * Globals
 611  */
 612 extern const struct ethtool_ops mlx4_en_ethtool_ops;
 613
 614
 615
 616 /*
 617  * printk / logging functions
 618  */
 619
 620 __printf(3, 4)
 621 int en_print(const char *level, const struct mlx4_en_priv *priv,
 622              const char *format, ...);
 623
 624 #define en_dbg(mlevel, priv, format, arg...)                    \
 625 do {                                                            \
 626         if (NETIF_MSG_##mlevel & priv->msg_enable)              \
 627                 en_print(KERN_DEBUG, priv, format, ##arg);      \
 628 } while (0)
 629 #define en_warn(priv, format, arg...)                   \
 630         en_print(KERN_WARNING, priv, format, ##arg)
 631 #define en_err(priv, format, arg...)                    \
 632         en_print(KERN_ERR, priv, format, ##arg)
 633 #define en_info(priv, format, arg...)                   \
 634         en_print(KERN_INFO, priv, format, ## arg)
 635
 636 #define mlx4_err(mdev, format, arg...)                  \
 637         pr_err("%s %s: " format, DRV_NAME,              \
 638                dev_name(&mdev->pdev->dev), ##arg)
 639 #define mlx4_info(mdev, format, arg...)                 \
 640         pr_info("%s %s: " format, DRV_NAME,             \
 641                 dev_name(&mdev->pdev->dev), ##arg)
 642 #define mlx4_warn(mdev, format, arg...)                 \
 643         pr_warning("%s %s: " format, DRV_NAME,          \
 644                    dev_name(&mdev->pdev->dev), ##arg)
 645
 646 #endif