drivers/net/ethernet/mellanox/mlx4/mlx4_en.h

   1 /*
   2  * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  *
  32  */
  33
  34 #ifndef _MLX4_EN_H_
  35 #define _MLX4_EN_H_
  36
  37 #include <linux/bitops.h>
  38 #include <linux/compiler.h>
  39 #include <linux/list.h>
  40 #include <linux/mutex.h>
  41 #include <linux/netdevice.h>
  42 #include <linux/if_vlan.h>
  43 #include <linux/net_tstamp.h>
  44 #ifdef CONFIG_MLX4_EN_DCB
  45 #include <linux/dcbnl.h>
  46 #endif
  47 #include <linux/cpu_rmap.h>
  48 #include <linux/ptp_clock_kernel.h>
  49
  50 #include <linux/mlx4/device.h>
  51 #include <linux/mlx4/qp.h>
  52 #include <linux/mlx4/cq.h>
  53 #include <linux/mlx4/srq.h>
  54 #include <linux/mlx4/doorbell.h>
  55 #include <linux/mlx4/cmd.h>
  56
  57 #include "en_port.h"
  58
  59 #define DRV_NAME        "mlx4_en"
  60 #define DRV_VERSION     "2.2-1"
  61 #define DRV_RELDATE     "Feb 2014"
  62
  63 #define MLX4_EN_MSG_LEVEL       (NETIF_MSG_LINK | NETIF_MSG_IFDOWN)
  64
  65 /*
  66  * Device constants
  67  */
  68
  69
  70 #define MLX4_EN_PAGE_SHIFT      12
  71 #define MLX4_EN_PAGE_SIZE       (1 << MLX4_EN_PAGE_SHIFT)
  72 #define DEF_RX_RINGS            16
  73 #define MAX_RX_RINGS            128
  74 #define MIN_RX_RINGS            4
  75 #define TXBB_SIZE               64
  76 #define HEADROOM                (2048 / TXBB_SIZE + 1)
  77 #define STAMP_STRIDE            64
  78 #define STAMP_DWORDS            (STAMP_STRIDE / 4)
  79 #define STAMP_SHIFT             31
  80 #define STAMP_VAL               0x7fffffff
  81 #define STATS_DELAY             (HZ / 4)
  82 #define SERVICE_TASK_DELAY      (HZ / 4)
  83 #define MAX_NUM_OF_FS_RULES     256
  84
  85 #define MLX4_EN_FILTER_HASH_SHIFT 4
  86 #define MLX4_EN_FILTER_EXPIRY_QUOTA 60
  87
  88 /* Typical TSO descriptor with 16 gather entries is 352 bytes... */
  89 #define MAX_DESC_SIZE           512
  90 #define MAX_DESC_TXBBS          (MAX_DESC_SIZE / TXBB_SIZE)
  91
  92 /*
  93  * OS related constants and tunables
  94  */
  95
  96 #define MLX4_EN_WATCHDOG_TIMEOUT        (15 * HZ)
  97
  98 /* Use the maximum between 16384 and a single page */
  99 #define MLX4_EN_ALLOC_SIZE      PAGE_ALIGN(16384)
 100
 101 #define MLX4_EN_ALLOC_PREFER_ORDER      PAGE_ALLOC_COSTLY_ORDER
 102
 103 /* Receive fragment sizes; we use at most 3 fragments (for 9600 byte MTU
 104  * and 4K allocations) */
 105 enum {
 106         FRAG_SZ0 = 1536 - NET_IP_ALIGN,
 107         FRAG_SZ1 = 4096,
 108         FRAG_SZ2 = 4096,
 109         FRAG_SZ3 = MLX4_EN_ALLOC_SIZE
 110 };
 111 #define MLX4_EN_MAX_RX_FRAGS    4
 112
 113 /* Maximum ring sizes */
 114 #define MLX4_EN_MAX_TX_SIZE     8192
 115 #define MLX4_EN_MAX_RX_SIZE     8192
 116
 117 /* Minimum ring size for our page-allocation scheme to work */
 118 #define MLX4_EN_MIN_RX_SIZE     (MLX4_EN_ALLOC_SIZE / SMP_CACHE_BYTES)
 119 #define MLX4_EN_MIN_TX_SIZE     (4096 / TXBB_SIZE)
 120
 121 #define MLX4_EN_SMALL_PKT_SIZE          64
 122 #define MLX4_EN_MAX_TX_RING_P_UP        32
 123 #define MLX4_EN_NUM_UP                  8
 124 #define MLX4_EN_DEF_TX_RING_SIZE        512
 125 #define MLX4_EN_DEF_RX_RING_SIZE        1024
 126 #define MAX_TX_RINGS                    (MLX4_EN_MAX_TX_RING_P_UP * \
 127                                          MLX4_EN_NUM_UP)
 128
 129 /* Target number of packets to coalesce with interrupt moderation */
 130 #define MLX4_EN_RX_COAL_TARGET  44
 131 #define MLX4_EN_RX_COAL_TIME    0x10
 132
 133 #define MLX4_EN_TX_COAL_PKTS    16
 134 #define MLX4_EN_TX_COAL_TIME    0x10
 135
 136 #define MLX4_EN_RX_RATE_LOW             400000
 137 #define MLX4_EN_RX_COAL_TIME_LOW        0
 138 #define MLX4_EN_RX_RATE_HIGH            450000
 139 #define MLX4_EN_RX_COAL_TIME_HIGH       128
 140 #define MLX4_EN_RX_SIZE_THRESH          1024
 141 #define MLX4_EN_RX_RATE_THRESH          (1000000 / MLX4_EN_RX_COAL_TIME_HIGH)
 142 #define MLX4_EN_SAMPLE_INTERVAL         0
 143 #define MLX4_EN_AVG_PKT_SMALL           256
 144
 145 #define MLX4_EN_AUTO_CONF       0xffff
 146
 147 #define MLX4_EN_DEF_RX_PAUSE    1
 148 #define MLX4_EN_DEF_TX_PAUSE    1
 149
 150 /* Interval between successive polls in the Tx routine when polling is used
 151    instead of interrupts (in per-core Tx rings) - should be power of 2 */
 152 #define MLX4_EN_TX_POLL_MODER   16
 153 #define MLX4_EN_TX_POLL_TIMEOUT (HZ / 4)
 154
 155 #define SMALL_PACKET_SIZE      (256 - NET_IP_ALIGN)
 156 #define HEADER_COPY_SIZE       (128 - NET_IP_ALIGN)
 157 #define MLX4_LOOPBACK_TEST_PAYLOAD (HEADER_COPY_SIZE - ETH_HLEN)
 158
 159 #define MLX4_EN_MIN_MTU         46
 160 #define ETH_BCAST               0xffffffffffffULL
 161
 162 #define MLX4_EN_LOOPBACK_RETRIES        5
 163 #define MLX4_EN_LOOPBACK_TIMEOUT        100
 164
 165 #ifdef MLX4_EN_PERF_STAT
 166 /* Number of samples to 'average' */
 167 #define AVG_SIZE                        128
 168 #define AVG_FACTOR                      1024
 169 #define NUM_PERF_STATS                  NUM_PERF_COUNTERS
 170
 171 #define INC_PERF_COUNTER(cnt)           (++(cnt))
 172 #define ADD_PERF_COUNTER(cnt, add)      ((cnt) += (add))
 173 #define AVG_PERF_COUNTER(cnt, sample) \
 174         ((cnt) = ((cnt) * (AVG_SIZE - 1) + (sample) * AVG_FACTOR) / AVG_SIZE)
 175 #define GET_PERF_COUNTER(cnt)           (cnt)
 176 #define GET_AVG_PERF_COUNTER(cnt)       ((cnt) / AVG_FACTOR)
 177
 178 #else
 179
 180 #define NUM_PERF_STATS                  0
 181 #define INC_PERF_COUNTER(cnt)           do {} while (0)
 182 #define ADD_PERF_COUNTER(cnt, add)      do {} while (0)
 183 #define AVG_PERF_COUNTER(cnt, sample)   do {} while (0)
 184 #define GET_PERF_COUNTER(cnt)           (0)
 185 #define GET_AVG_PERF_COUNTER(cnt)       (0)
 186 #endif /* MLX4_EN_PERF_STAT */
 187
 188 /* Constants for TX flow */
 189 enum {
 190         MAX_INLINE = 104, /* 128 - 16 - 4 - 4 */
 191         MAX_BF = 256,
 192         MIN_PKT_LEN = 17,
 193 };
 194
 195 /*
 196  * Configurables
 197  */
 198
 199 enum cq_type {
 200         RX = 0,
 201         TX = 1,
 202 };
 203
 204
 205 /*
 206  * Useful macros
 207  */
 208 #define ROUNDUP_LOG2(x)         ilog2(roundup_pow_of_two(x))
 209 #define XNOR(x, y)              (!(x) == !(y))
 210
 211
 212 struct mlx4_en_tx_info {
 213         struct sk_buff *skb;
 214         u32 nr_txbb;
 215         u32 nr_bytes;
 216         u8 linear;
 217         u8 data_offset;
 218         u8 inl;
 219         u8 ts_requested;
 220 };
 221
 222
 223 #define MLX4_EN_BIT_DESC_OWN    0x80000000
 224 #define CTRL_SIZE       sizeof(struct mlx4_wqe_ctrl_seg)
 225 #define MLX4_EN_MEMTYPE_PAD     0x100
 226 #define DS_SIZE         sizeof(struct mlx4_wqe_data_seg)
 227
 228
 229 struct mlx4_en_tx_desc {
 230         struct mlx4_wqe_ctrl_seg ctrl;
 231         union {
 232                 struct mlx4_wqe_data_seg data; /* at least one data segment */
 233                 struct mlx4_wqe_lso_seg lso;
 234                 struct mlx4_wqe_inline_seg inl;
 235         };
 236 };
 237
 238 #define MLX4_EN_USE_SRQ         0x01000000
 239
 240 #define MLX4_EN_CX3_LOW_ID      0x1000
 241 #define MLX4_EN_CX3_HIGH_ID     0x1005
 242
 243 struct mlx4_en_rx_alloc {
 244         struct page     *page;
 245         dma_addr_t      dma;
 246         u32             page_offset;
 247         u32             page_size;
 248 };
 249
 250 struct mlx4_en_tx_ring {
 251         struct mlx4_hwq_resources wqres;
 252         u32 size ; /* number of TXBBs */
 253         u32 size_mask;
 254         u16 stride;
 255         u16 cqn;        /* index of port CQ associated with this ring */
 256         u32 prod;
 257         u32 cons;
 258         u32 buf_size;
 259         u32 doorbell_qpn;
 260         void *buf;
 261         u16 poll_cnt;
 262         struct mlx4_en_tx_info *tx_info;
 263         u8 *bounce_buf;
 264         u8 queue_index;
 265         cpumask_t affinity_mask;
 266         u32 last_nr_txbb;
 267         struct mlx4_qp qp;
 268         struct mlx4_qp_context context;
 269         int qpn;
 270         enum mlx4_qp_state qp_state;
 271         struct mlx4_srq dummy;
 272         unsigned long bytes;
 273         unsigned long packets;
 274         unsigned long tx_csum;
 275         unsigned long queue_stopped;
 276         unsigned long wake_queue;
 277         struct mlx4_bf bf;
 278         bool bf_enabled;
 279         struct netdev_queue *tx_queue;
 280         int hwtstamp_tx_type;
 281         int inline_thold;
 282 };
 283
 284 struct mlx4_en_rx_desc {
 285         /* actual number of entries depends on rx ring stride */
 286         struct mlx4_wqe_data_seg data[0];
 287 };
 288
 289 struct mlx4_en_rx_ring {
 290         struct mlx4_hwq_resources wqres;
 291         struct mlx4_en_rx_alloc page_alloc[MLX4_EN_MAX_RX_FRAGS];
 292         u32 size ;      /* number of Rx descs*/
 293         u32 actual_size;
 294         u32 size_mask;
 295         u16 stride;
 296         u16 log_stride;
 297         u16 cqn;        /* index of port CQ associated with this ring */
 298         u32 prod;
 299         u32 cons;
 300         u32 buf_size;
 301         u8  fcs_del;
 302         void *buf;
 303         void *rx_info;
 304         unsigned long bytes;
 305         unsigned long packets;
 306 #ifdef CONFIG_NET_RX_BUSY_POLL
 307         unsigned long yields;
 308         unsigned long misses;
 309         unsigned long cleaned;
 310 #endif
 311         unsigned long csum_ok;
 312         unsigned long csum_none;
 313         int hwtstamp_rx_filter;
 314         cpumask_var_t affinity_mask;
 315 };
 316
 317 struct mlx4_en_cq {
 318         struct mlx4_cq          mcq;
 319         struct mlx4_hwq_resources wqres;
 320         int                     ring;
 321         struct net_device      *dev;
 322         struct napi_struct      napi;
 323         int size;
 324         int buf_size;
 325         unsigned vector;
 326         enum cq_type is_tx;
 327         u16 moder_time;
 328         u16 moder_cnt;
 329         struct mlx4_cqe *buf;
 330 #define MLX4_EN_OPCODE_ERROR    0x1e
 331
 332 #ifdef CONFIG_NET_RX_BUSY_POLL
 333         unsigned int state;
 334 #define MLX4_EN_CQ_STATE_IDLE        0
 335 #define MLX4_EN_CQ_STATE_NAPI     1    /* NAPI owns this CQ */
 336 #define MLX4_EN_CQ_STATE_POLL     2    /* poll owns this CQ */
 337 #define MLX4_CQ_LOCKED (MLX4_EN_CQ_STATE_NAPI | MLX4_EN_CQ_STATE_POLL)
 338 #define MLX4_EN_CQ_STATE_NAPI_YIELD  4    /* NAPI yielded this CQ */
 339 #define MLX4_EN_CQ_STATE_POLL_YIELD  8    /* poll yielded this CQ */
 340 #define CQ_YIELD (MLX4_EN_CQ_STATE_NAPI_YIELD | MLX4_EN_CQ_STATE_POLL_YIELD)
 341 #define CQ_USER_PEND (MLX4_EN_CQ_STATE_POLL | MLX4_EN_CQ_STATE_POLL_YIELD)
 342         spinlock_t poll_lock; /* protects from LLS/napi conflicts */
 343 #endif  /* CONFIG_NET_RX_BUSY_POLL */
 344 };
 345
 346 struct mlx4_en_port_profile {
 347         u32 flags;
 348         u32 tx_ring_num;
 349         u32 rx_ring_num;
 350         u32 tx_ring_size;
 351         u32 rx_ring_size;
 352         u8 rx_pause;
 353         u8 rx_ppp;
 354         u8 tx_pause;
 355         u8 tx_ppp;
 356         int rss_rings;
 357         int inline_thold;
 358 };
 359
 360 struct mlx4_en_profile {
 361         int rss_xor;
 362         int udp_rss;
 363         u8 rss_mask;
 364         u32 active_ports;
 365         u32 small_pkt_int;
 366         u8 no_reset;
 367         u8 num_tx_rings_p_up;
 368         struct mlx4_en_port_profile prof[MLX4_MAX_PORTS + 1];
 369 };
 370
 371 struct mlx4_en_dev {
 372         struct mlx4_dev         *dev;
 373         struct pci_dev          *pdev;
 374         struct mutex            state_lock;
 375         struct net_device       *pndev[MLX4_MAX_PORTS + 1];
 376         u32                     port_cnt;
 377         bool                    device_up;
 378         struct mlx4_en_profile  profile;
 379         u32                     LSO_support;
 380         struct workqueue_struct *workqueue;
 381         struct device           *dma_device;
 382         void __iomem            *uar_map;
 383         struct mlx4_uar         priv_uar;
 384         struct mlx4_mr          mr;
 385         u32                     priv_pdn;
 386         spinlock_t              uar_lock;
 387         u8                      mac_removed[MLX4_MAX_PORTS + 1];
 388         rwlock_t                clock_lock;
 389         u32                     nominal_c_mult;
 390         struct cyclecounter     cycles;
 391         struct timecounter      clock;
 392         unsigned long           last_overflow_check;
 393         unsigned long           overflow_period;
 394         struct ptp_clock        *ptp_clock;
 395         struct ptp_clock_info   ptp_clock_info;
 396 };
 397
 398
 399 struct mlx4_en_rss_map {
 400         int base_qpn;
 401         struct mlx4_qp qps[MAX_RX_RINGS];
 402         enum mlx4_qp_state state[MAX_RX_RINGS];
 403         struct mlx4_qp indir_qp;
 404         enum mlx4_qp_state indir_state;
 405 };
 406
 407 struct mlx4_en_port_state {
 408         int link_state;
 409         int link_speed;
 410         int transciver;
 411 };
 412
 413 struct mlx4_en_pkt_stats {
 414         unsigned long broadcast;
 415         unsigned long rx_prio[8];
 416         unsigned long tx_prio[8];
 417 #define NUM_PKT_STATS           17
 418 };
 419
 420 struct mlx4_en_port_stats {
 421         unsigned long tso_packets;
 422         unsigned long queue_stopped;
 423         unsigned long wake_queue;
 424         unsigned long tx_timeout;
 425         unsigned long rx_alloc_failed;
 426         unsigned long rx_chksum_good;
 427         unsigned long rx_chksum_none;
 428         unsigned long tx_chksum_offload;
 429 #define NUM_PORT_STATS          8
 430 };
 431
 432 struct mlx4_en_perf_stats {
 433         u32 tx_poll;
 434         u64 tx_pktsz_avg;
 435         u32 inflight_avg;
 436         u16 tx_coal_avg;
 437         u16 rx_coal_avg;
 438         u32 napi_quota;
 439 #define NUM_PERF_COUNTERS               6
 440 };
 441
 442 enum mlx4_en_mclist_act {
 443         MCLIST_NONE,
 444         MCLIST_REM,
 445         MCLIST_ADD,
 446 };
 447
 448 struct mlx4_en_mc_list {
 449         struct list_head        list;
 450         enum mlx4_en_mclist_act action;
 451         u8                      addr[ETH_ALEN];
 452         u64                     reg_id;
 453         u64                     tunnel_reg_id;
 454 };
 455
 456 struct mlx4_en_frag_info {
 457         u16 frag_size;
 458         u16 frag_prefix_size;
 459         u16 frag_stride;
 460         u16 frag_align;
 461 };
 462
 463 #ifdef CONFIG_MLX4_EN_DCB
 464 /* Minimal TC BW - setting to 0 will block traffic */
 465 #define MLX4_EN_BW_MIN 1
 466 #define MLX4_EN_BW_MAX 100 /* Utilize 100% of the line */
 467
 468 #define MLX4_EN_TC_ETS 7
 469
 470 #endif
 471
 472 struct ethtool_flow_id {
 473         struct list_head list;
 474         struct ethtool_rx_flow_spec flow_spec;
 475         u64 id;
 476 };
 477
 478 enum {
 479         MLX4_EN_FLAG_PROMISC            = (1 << 0),
 480         MLX4_EN_FLAG_MC_PROMISC         = (1 << 1),
 481         /* whether we need to enable hardware loopback by putting dmac
 482          * in Tx WQE
 483          */
 484         MLX4_EN_FLAG_ENABLE_HW_LOOPBACK = (1 << 2),
 485         /* whether we need to drop packets that hardware loopback-ed */
 486         MLX4_EN_FLAG_RX_FILTER_NEEDED   = (1 << 3),
 487         MLX4_EN_FLAG_FORCE_PROMISC      = (1 << 4)
 488 };
 489
 490 #define MLX4_EN_MAC_HASH_SIZE (1 << BITS_PER_BYTE)
 491 #define MLX4_EN_MAC_HASH_IDX 5
 492
 493 struct mlx4_en_priv {
 494         struct mlx4_en_dev *mdev;
 495         struct mlx4_en_port_profile *prof;
 496         struct net_device *dev;
 497         unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
 498         struct net_device_stats stats;
 499         struct net_device_stats ret_stats;
 500         struct mlx4_en_port_state port_state;
 501         spinlock_t stats_lock;
 502         struct ethtool_flow_id ethtool_rules[MAX_NUM_OF_FS_RULES];
 503         /* To allow rules removal while port is going down */
 504         struct list_head ethtool_list;
 505
 506         unsigned long last_moder_packets[MAX_RX_RINGS];
 507         unsigned long last_moder_tx_packets;
 508         unsigned long last_moder_bytes[MAX_RX_RINGS];
 509         unsigned long last_moder_jiffies;
 510         int last_moder_time[MAX_RX_RINGS];
 511         u16 rx_usecs;
 512         u16 rx_frames;
 513         u16 tx_usecs;
 514         u16 tx_frames;
 515         u32 pkt_rate_low;
 516         u16 rx_usecs_low;
 517         u32 pkt_rate_high;
 518         u16 rx_usecs_high;
 519         u16 sample_interval;
 520         u16 adaptive_rx_coal;
 521         u32 msg_enable;
 522         u32 loopback_ok;
 523         u32 validate_loopback;
 524
 525         struct mlx4_hwq_resources res;
 526         int link_state;
 527         int last_link_state;
 528         bool port_up;
 529         int port;
 530         int registered;
 531         int allocated;
 532         int stride;
 533         unsigned char current_mac[ETH_ALEN + 2];
 534         int mac_index;
 535         unsigned max_mtu;
 536         int base_qpn;
 537         int cqe_factor;
 538
 539         struct mlx4_en_rss_map rss_map;
 540         __be32 ctrl_flags;
 541         u32 flags;
 542         u8 num_tx_rings_p_up;
 543         u32 tx_ring_num;
 544         u32 rx_ring_num;
 545         u32 rx_skb_size;
 546         struct mlx4_en_frag_info frag_info[MLX4_EN_MAX_RX_FRAGS];
 547         u16 num_frags;
 548         u16 log_rx_info;
 549
 550         struct mlx4_en_tx_ring **tx_ring;
 551         struct mlx4_en_rx_ring *rx_ring[MAX_RX_RINGS];
 552         struct mlx4_en_cq **tx_cq;
 553         struct mlx4_en_cq *rx_cq[MAX_RX_RINGS];
 554         struct mlx4_qp drop_qp;
 555         struct work_struct rx_mode_task;
 556         struct work_struct watchdog_task;
 557         struct work_struct linkstate_task;
 558         struct delayed_work stats_task;
 559         struct delayed_work service_task;
 560 #ifdef CONFIG_MLX4_EN_VXLAN
 561         struct work_struct vxlan_add_task;
 562         struct work_struct vxlan_del_task;
 563 #endif
 564         struct mlx4_en_perf_stats pstats;
 565         struct mlx4_en_pkt_stats pkstats;
 566         struct mlx4_en_port_stats port_stats;
 567         u64 stats_bitmap;
 568         struct list_head mc_list;
 569         struct list_head curr_list;
 570         u64 broadcast_id;
 571         struct mlx4_en_stat_out_mbox hw_stats;
 572         int vids[128];
 573         bool wol;
 574         struct device *ddev;
 575         int base_tx_qpn;
 576         struct hlist_head mac_hash[MLX4_EN_MAC_HASH_SIZE];
 577         struct hwtstamp_config hwtstamp_config;
 578
 579 #ifdef CONFIG_MLX4_EN_DCB
 580         struct ieee_ets ets;
 581         u16 maxrate[IEEE_8021QAZ_MAX_TCS];
 582 #endif
 583 #ifdef CONFIG_RFS_ACCEL
 584         spinlock_t filters_lock;
 585         int last_filter_id;
 586         struct list_head filters;
 587         struct hlist_head filter_hash[1 << MLX4_EN_FILTER_HASH_SHIFT];
 588 #endif
 589         u64 tunnel_reg_id;
 590         __be16 vxlan_port;
 591 };
 592
 593 enum mlx4_en_wol {
 594         MLX4_EN_WOL_MAGIC = (1ULL << 61),
 595         MLX4_EN_WOL_ENABLED = (1ULL << 62),
 596 };
 597
 598 struct mlx4_mac_entry {
 599         struct hlist_node hlist;
 600         unsigned char mac[ETH_ALEN + 2];
 601         u64 reg_id;
 602         struct rcu_head rcu;
 603 };
 604
 605 #ifdef CONFIG_NET_RX_BUSY_POLL
 606 static inline void mlx4_en_cq_init_lock(struct mlx4_en_cq *cq)
 607 {
 608         spin_lock_init(&cq->poll_lock);
 609         cq->state = MLX4_EN_CQ_STATE_IDLE;
 610 }
 611
 612 /* called from the device poll rutine to get ownership of a cq */
 613 static inline bool mlx4_en_cq_lock_napi(struct mlx4_en_cq *cq)
 614 {
 615         int rc = true;
 616         spin_lock(&cq->poll_lock);
 617         if (cq->state & MLX4_CQ_LOCKED) {
 618                 WARN_ON(cq->state & MLX4_EN_CQ_STATE_NAPI);
 619                 cq->state |= MLX4_EN_CQ_STATE_NAPI_YIELD;
 620                 rc = false;
 621         } else
 622                 /* we don't care if someone yielded */
 623                 cq->state = MLX4_EN_CQ_STATE_NAPI;
 624         spin_unlock(&cq->poll_lock);
 625         return rc;
 626 }
 627
 628 /* returns true is someone tried to get the cq while napi had it */
 629 static inline bool mlx4_en_cq_unlock_napi(struct mlx4_en_cq *cq)
 630 {
 631         int rc = false;
 632         spin_lock(&cq->poll_lock);
 633         WARN_ON(cq->state & (MLX4_EN_CQ_STATE_POLL |
 634                                MLX4_EN_CQ_STATE_NAPI_YIELD));
 635
 636         if (cq->state & MLX4_EN_CQ_STATE_POLL_YIELD)
 637                 rc = true;
 638         cq->state = MLX4_EN_CQ_STATE_IDLE;
 639         spin_unlock(&cq->poll_lock);
 640         return rc;
 641 }
 642
 643 /* called from mlx4_en_low_latency_poll() */
 644 static inline bool mlx4_en_cq_lock_poll(struct mlx4_en_cq *cq)
 645 {
 646         int rc = true;
 647         spin_lock_bh(&cq->poll_lock);
 648         if ((cq->state & MLX4_CQ_LOCKED)) {
 649                 struct net_device *dev = cq->dev;
 650                 struct mlx4_en_priv *priv = netdev_priv(dev);
 651                 struct mlx4_en_rx_ring *rx_ring = priv->rx_ring[cq->ring];
 652
 653                 cq->state |= MLX4_EN_CQ_STATE_POLL_YIELD;
 654                 rc = false;
 655                 rx_ring->yields++;
 656         } else
 657                 /* preserve yield marks */
 658                 cq->state |= MLX4_EN_CQ_STATE_POLL;
 659         spin_unlock_bh(&cq->poll_lock);
 660         return rc;
 661 }
 662
 663 /* returns true if someone tried to get the cq while it was locked */
 664 static inline bool mlx4_en_cq_unlock_poll(struct mlx4_en_cq *cq)
 665 {
 666         int rc = false;
 667         spin_lock_bh(&cq->poll_lock);
 668         WARN_ON(cq->state & (MLX4_EN_CQ_STATE_NAPI));
 669
 670         if (cq->state & MLX4_EN_CQ_STATE_POLL_YIELD)
 671                 rc = true;
 672         cq->state = MLX4_EN_CQ_STATE_IDLE;
 673         spin_unlock_bh(&cq->poll_lock);
 674         return rc;
 675 }
 676
 677 /* true if a socket is polling, even if it did not get the lock */
 678 static inline bool mlx4_en_cq_busy_polling(struct mlx4_en_cq *cq)
 679 {
 680         WARN_ON(!(cq->state & MLX4_CQ_LOCKED));
 681         return cq->state & CQ_USER_PEND;
 682 }
 683 #else
 684 static inline void mlx4_en_cq_init_lock(struct mlx4_en_cq *cq)
 685 {
 686 }
 687
 688 static inline bool mlx4_en_cq_lock_napi(struct mlx4_en_cq *cq)
 689 {
 690         return true;
 691 }
 692
 693 static inline bool mlx4_en_cq_unlock_napi(struct mlx4_en_cq *cq)
 694 {
 695         return false;
 696 }
 697
 698 static inline bool mlx4_en_cq_lock_poll(struct mlx4_en_cq *cq)
 699 {
 700         return false;
 701 }
 702
 703 static inline bool mlx4_en_cq_unlock_poll(struct mlx4_en_cq *cq)
 704 {
 705         return false;
 706 }
 707
 708 static inline bool mlx4_en_cq_busy_polling(struct mlx4_en_cq *cq)
 709 {
 710         return false;
 711 }
 712 #endif /* CONFIG_NET_RX_BUSY_POLL */
 713
 714 #define MLX4_EN_WOL_DO_MODIFY (1ULL << 63)
 715
 716 void mlx4_en_update_loopback_state(struct net_device *dev,
 717                                    netdev_features_t features);
 718
 719 void mlx4_en_destroy_netdev(struct net_device *dev);
 720 int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port,
 721                         struct mlx4_en_port_profile *prof);
 722
 723 int mlx4_en_start_port(struct net_device *dev);
 724 void mlx4_en_stop_port(struct net_device *dev, int detach);
 725
 726 void mlx4_en_free_resources(struct mlx4_en_priv *priv);
 727 int mlx4_en_alloc_resources(struct mlx4_en_priv *priv);
 728
 729 int mlx4_en_create_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq **pcq,
 730                       int entries, int ring, enum cq_type mode, int node);
 731 void mlx4_en_destroy_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq **pcq);
 732 int mlx4_en_activate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq,
 733                         int cq_idx);
 734 void mlx4_en_deactivate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
 735 int mlx4_en_set_cq_moder(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
 736 int mlx4_en_arm_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
 737
 738 void mlx4_en_tx_irq(struct mlx4_cq *mcq);
 739 u16 mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb,
 740                          void *accel_priv, select_queue_fallback_t fallback);
 741 netdev_tx_t mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev);
 742
 743 int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv,
 744                            struct mlx4_en_tx_ring **pring,
 745                            int qpn, u32 size, u16 stride,
 746                            int node, int queue_index);
 747 void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv,
 748                              struct mlx4_en_tx_ring **pring);
 749 int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv,
 750                              struct mlx4_en_tx_ring *ring,
 751                              int cq, int user_prio);
 752 void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv,
 753                                 struct mlx4_en_tx_ring *ring);
 754 void mlx4_en_set_num_rx_rings(struct mlx4_en_dev *mdev);
 755 int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv,
 756                            struct mlx4_en_rx_ring **pring,
 757                            u32 size, u16 stride, int node);
 758 void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv,
 759                              struct mlx4_en_rx_ring **pring,
 760                              u32 size, u16 stride);
 761 int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv);
 762 void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv,
 763                                 struct mlx4_en_rx_ring *ring);
 764 int mlx4_en_process_rx_cq(struct net_device *dev,
 765                           struct mlx4_en_cq *cq,
 766                           int budget);
 767 int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget);
 768 int mlx4_en_poll_tx_cq(struct napi_struct *napi, int budget);
 769 void mlx4_en_fill_qp_context(struct mlx4_en_priv *priv, int size, int stride,
 770                 int is_tx, int rss, int qpn, int cqn, int user_prio,
 771                 struct mlx4_qp_context *context);
 772 void mlx4_en_sqp_event(struct mlx4_qp *qp, enum mlx4_event event);
 773 int mlx4_en_map_buffer(struct mlx4_buf *buf);
 774 void mlx4_en_unmap_buffer(struct mlx4_buf *buf);
 775
 776 void mlx4_en_calc_rx_buf(struct net_device *dev);
 777 int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv);
 778 void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv);
 779 int mlx4_en_create_drop_qp(struct mlx4_en_priv *priv);
 780 void mlx4_en_destroy_drop_qp(struct mlx4_en_priv *priv);
 781 int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring);
 782 void mlx4_en_rx_irq(struct mlx4_cq *mcq);
 783
 784 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode);
 785 int mlx4_SET_VLAN_FLTR(struct mlx4_dev *dev, struct mlx4_en_priv *priv);
 786
 787 int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev *mdev, u8 port, u8 reset);
 788 int mlx4_en_QUERY_PORT(struct mlx4_en_dev *mdev, u8 port);
 789
 790 #ifdef CONFIG_MLX4_EN_DCB
 791 extern const struct dcbnl_rtnl_ops mlx4_en_dcbnl_ops;
 792 extern const struct dcbnl_rtnl_ops mlx4_en_dcbnl_pfc_ops;
 793 #endif
 794
 795 int mlx4_en_setup_tc(struct net_device *dev, u8 up);
 796
 797 #ifdef CONFIG_RFS_ACCEL
 798 void mlx4_en_cleanup_filters(struct mlx4_en_priv *priv);
 799 #endif
 800
 801 #define MLX4_EN_NUM_SELF_TEST   5
 802 void mlx4_en_ex_selftest(struct net_device *dev, u32 *flags, u64 *buf);
 803 void mlx4_en_ptp_overflow_check(struct mlx4_en_dev *mdev);
 804
 805 /*
 806  * Functions for time stamping
 807  */
 808 u64 mlx4_en_get_cqe_ts(struct mlx4_cqe *cqe);
 809 void mlx4_en_fill_hwtstamps(struct mlx4_en_dev *mdev,
 810                             struct skb_shared_hwtstamps *hwts,
 811                             u64 timestamp);
 812 void mlx4_en_init_timestamp(struct mlx4_en_dev *mdev);
 813 void mlx4_en_remove_timestamp(struct mlx4_en_dev *mdev);
 814 int mlx4_en_timestamp_config(struct net_device *dev,
 815                              int tx_type,
 816                              int rx_filter);
 817
 818 /* Globals
 819  */
 820 extern const struct ethtool_ops mlx4_en_ethtool_ops;
 821
 822
 823
 824 /*
 825  * printk / logging functions
 826  */
 827
 828 __printf(3, 4)
 829 int en_print(const char *level, const struct mlx4_en_priv *priv,
 830              const char *format, ...);
 831
 832 #define en_dbg(mlevel, priv, format, ...)                               \
 833 do {                                                                    \
 834         if (NETIF_MSG_##mlevel & (priv)->msg_enable)                    \
 835                 en_print(KERN_DEBUG, priv, format, ##__VA_ARGS__);      \
 836 } while (0)
 837 #define en_warn(priv, format, ...)                                      \
 838         en_print(KERN_WARNING, priv, format, ##__VA_ARGS__)
 839 #define en_err(priv, format, ...)                                       \
 840         en_print(KERN_ERR, priv, format, ##__VA_ARGS__)
 841 #define en_info(priv, format, ...)                                      \
 842         en_print(KERN_INFO, priv, format, ##__VA_ARGS__)
 843
 844 #define mlx4_err(mdev, format, ...)                                     \
 845         pr_err(DRV_NAME " %s: " format,                                 \
 846                dev_name(&(mdev)->pdev->dev), ##__VA_ARGS__)
 847 #define mlx4_info(mdev, format, ...)                                    \
 848         pr_info(DRV_NAME " %s: " format,                                \
 849                 dev_name(&(mdev)->pdev->dev), ##__VA_ARGS__)
 850 #define mlx4_warn(mdev, format, ...)                                    \
 851         pr_warn(DRV_NAME " %s: " format,                                \
 852                 dev_name(&(mdev)->pdev->dev), ##__VA_ARGS__)
 853
 854 #endif