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Merge branch 'stable/for-jens-4.7' of git://git.kernel.org/pub/scm/linux/kernel/git...
[deliverable/linux.git] / drivers / net / ethernet / mellanox / mlx4 / mr.c
1 /*
2 * Copyright (c) 2004 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35 #include <linux/errno.h>
36 #include <linux/export.h>
37 #include <linux/slab.h>
38 #include <linux/kernel.h>
39 #include <linux/vmalloc.h>
40
41 #include <linux/mlx4/cmd.h>
42
43 #include "mlx4.h"
44 #include "icm.h"
45
46 static u32 mlx4_buddy_alloc(struct mlx4_buddy *buddy, int order)
47 {
48 int o;
49 int m;
50 u32 seg;
51
52 spin_lock(&buddy->lock);
53
54 for (o = order; o <= buddy->max_order; ++o)
55 if (buddy->num_free[o]) {
56 m = 1 << (buddy->max_order - o);
57 seg = find_first_bit(buddy->bits[o], m);
58 if (seg < m)
59 goto found;
60 }
61
62 spin_unlock(&buddy->lock);
63 return -1;
64
65 found:
66 clear_bit(seg, buddy->bits[o]);
67 --buddy->num_free[o];
68
69 while (o > order) {
70 --o;
71 seg <<= 1;
72 set_bit(seg ^ 1, buddy->bits[o]);
73 ++buddy->num_free[o];
74 }
75
76 spin_unlock(&buddy->lock);
77
78 seg <<= order;
79
80 return seg;
81 }
82
83 static void mlx4_buddy_free(struct mlx4_buddy *buddy, u32 seg, int order)
84 {
85 seg >>= order;
86
87 spin_lock(&buddy->lock);
88
89 while (test_bit(seg ^ 1, buddy->bits[order])) {
90 clear_bit(seg ^ 1, buddy->bits[order]);
91 --buddy->num_free[order];
92 seg >>= 1;
93 ++order;
94 }
95
96 set_bit(seg, buddy->bits[order]);
97 ++buddy->num_free[order];
98
99 spin_unlock(&buddy->lock);
100 }
101
102 static int mlx4_buddy_init(struct mlx4_buddy *buddy, int max_order)
103 {
104 int i, s;
105
106 buddy->max_order = max_order;
107 spin_lock_init(&buddy->lock);
108
109 buddy->bits = kcalloc(buddy->max_order + 1, sizeof (long *),
110 GFP_KERNEL);
111 buddy->num_free = kcalloc((buddy->max_order + 1), sizeof *buddy->num_free,
112 GFP_KERNEL);
113 if (!buddy->bits || !buddy->num_free)
114 goto err_out;
115
116 for (i = 0; i <= buddy->max_order; ++i) {
117 s = BITS_TO_LONGS(1 << (buddy->max_order - i));
118 buddy->bits[i] = kcalloc(s, sizeof (long), GFP_KERNEL | __GFP_NOWARN);
119 if (!buddy->bits[i]) {
120 buddy->bits[i] = vzalloc(s * sizeof(long));
121 if (!buddy->bits[i])
122 goto err_out_free;
123 }
124 }
125
126 set_bit(0, buddy->bits[buddy->max_order]);
127 buddy->num_free[buddy->max_order] = 1;
128
129 return 0;
130
131 err_out_free:
132 for (i = 0; i <= buddy->max_order; ++i)
133 kvfree(buddy->bits[i]);
134
135 err_out:
136 kfree(buddy->bits);
137 kfree(buddy->num_free);
138
139 return -ENOMEM;
140 }
141
142 static void mlx4_buddy_cleanup(struct mlx4_buddy *buddy)
143 {
144 int i;
145
146 for (i = 0; i <= buddy->max_order; ++i)
147 kvfree(buddy->bits[i]);
148
149 kfree(buddy->bits);
150 kfree(buddy->num_free);
151 }
152
153 u32 __mlx4_alloc_mtt_range(struct mlx4_dev *dev, int order)
154 {
155 struct mlx4_mr_table *mr_table = &mlx4_priv(dev)->mr_table;
156 u32 seg;
157 int seg_order;
158 u32 offset;
159
160 seg_order = max_t(int, order - log_mtts_per_seg, 0);
161
162 seg = mlx4_buddy_alloc(&mr_table->mtt_buddy, seg_order);
163 if (seg == -1)
164 return -1;
165
166 offset = seg * (1 << log_mtts_per_seg);
167
168 if (mlx4_table_get_range(dev, &mr_table->mtt_table, offset,
169 offset + (1 << order) - 1)) {
170 mlx4_buddy_free(&mr_table->mtt_buddy, seg, seg_order);
171 return -1;
172 }
173
174 return offset;
175 }
176
177 static u32 mlx4_alloc_mtt_range(struct mlx4_dev *dev, int order)
178 {
179 u64 in_param = 0;
180 u64 out_param;
181 int err;
182
183 if (mlx4_is_mfunc(dev)) {
184 set_param_l(&in_param, order);
185 err = mlx4_cmd_imm(dev, in_param, &out_param, RES_MTT,
186 RES_OP_RESERVE_AND_MAP,
187 MLX4_CMD_ALLOC_RES,
188 MLX4_CMD_TIME_CLASS_A,
189 MLX4_CMD_WRAPPED);
190 if (err)
191 return -1;
192 return get_param_l(&out_param);
193 }
194 return __mlx4_alloc_mtt_range(dev, order);
195 }
196
197 int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift,
198 struct mlx4_mtt *mtt)
199 {
200 int i;
201
202 if (!npages) {
203 mtt->order = -1;
204 mtt->page_shift = MLX4_ICM_PAGE_SHIFT;
205 return 0;
206 } else
207 mtt->page_shift = page_shift;
208
209 for (mtt->order = 0, i = 1; i < npages; i <<= 1)
210 ++mtt->order;
211
212 mtt->offset = mlx4_alloc_mtt_range(dev, mtt->order);
213 if (mtt->offset == -1)
214 return -ENOMEM;
215
216 return 0;
217 }
218 EXPORT_SYMBOL_GPL(mlx4_mtt_init);
219
220 void __mlx4_free_mtt_range(struct mlx4_dev *dev, u32 offset, int order)
221 {
222 u32 first_seg;
223 int seg_order;
224 struct mlx4_mr_table *mr_table = &mlx4_priv(dev)->mr_table;
225
226 seg_order = max_t(int, order - log_mtts_per_seg, 0);
227 first_seg = offset / (1 << log_mtts_per_seg);
228
229 mlx4_buddy_free(&mr_table->mtt_buddy, first_seg, seg_order);
230 mlx4_table_put_range(dev, &mr_table->mtt_table, offset,
231 offset + (1 << order) - 1);
232 }
233
234 static void mlx4_free_mtt_range(struct mlx4_dev *dev, u32 offset, int order)
235 {
236 u64 in_param = 0;
237 int err;
238
239 if (mlx4_is_mfunc(dev)) {
240 set_param_l(&in_param, offset);
241 set_param_h(&in_param, order);
242 err = mlx4_cmd(dev, in_param, RES_MTT, RES_OP_RESERVE_AND_MAP,
243 MLX4_CMD_FREE_RES,
244 MLX4_CMD_TIME_CLASS_A,
245 MLX4_CMD_WRAPPED);
246 if (err)
247 mlx4_warn(dev, "Failed to free mtt range at:%d order:%d\n",
248 offset, order);
249 return;
250 }
251 __mlx4_free_mtt_range(dev, offset, order);
252 }
253
254 void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt)
255 {
256 if (mtt->order < 0)
257 return;
258
259 mlx4_free_mtt_range(dev, mtt->offset, mtt->order);
260 }
261 EXPORT_SYMBOL_GPL(mlx4_mtt_cleanup);
262
263 u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt)
264 {
265 return (u64) mtt->offset * dev->caps.mtt_entry_sz;
266 }
267 EXPORT_SYMBOL_GPL(mlx4_mtt_addr);
268
269 static u32 hw_index_to_key(u32 ind)
270 {
271 return (ind >> 24) | (ind << 8);
272 }
273
274 static u32 key_to_hw_index(u32 key)
275 {
276 return (key << 24) | (key >> 8);
277 }
278
279 static int mlx4_SW2HW_MPT(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
280 int mpt_index)
281 {
282 return mlx4_cmd(dev, mailbox->dma, mpt_index,
283 0, MLX4_CMD_SW2HW_MPT, MLX4_CMD_TIME_CLASS_B,
284 MLX4_CMD_WRAPPED);
285 }
286
287 static int mlx4_HW2SW_MPT(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
288 int mpt_index)
289 {
290 return mlx4_cmd_box(dev, 0, mailbox ? mailbox->dma : 0, mpt_index,
291 !mailbox, MLX4_CMD_HW2SW_MPT,
292 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_WRAPPED);
293 }
294
295 /* Must protect against concurrent access */
296 int mlx4_mr_hw_get_mpt(struct mlx4_dev *dev, struct mlx4_mr *mmr,
297 struct mlx4_mpt_entry ***mpt_entry)
298 {
299 int err;
300 int key = key_to_hw_index(mmr->key) & (dev->caps.num_mpts - 1);
301 struct mlx4_cmd_mailbox *mailbox = NULL;
302
303 if (mmr->enabled != MLX4_MPT_EN_HW)
304 return -EINVAL;
305
306 err = mlx4_HW2SW_MPT(dev, NULL, key);
307 if (err) {
308 mlx4_warn(dev, "HW2SW_MPT failed (%d).", err);
309 mlx4_warn(dev, "Most likely the MR has MWs bound to it.\n");
310 return err;
311 }
312
313 mmr->enabled = MLX4_MPT_EN_SW;
314
315 if (!mlx4_is_mfunc(dev)) {
316 **mpt_entry = mlx4_table_find(
317 &mlx4_priv(dev)->mr_table.dmpt_table,
318 key, NULL);
319 } else {
320 mailbox = mlx4_alloc_cmd_mailbox(dev);
321 if (IS_ERR(mailbox))
322 return PTR_ERR(mailbox);
323
324 err = mlx4_cmd_box(dev, 0, mailbox->dma, key,
325 0, MLX4_CMD_QUERY_MPT,
326 MLX4_CMD_TIME_CLASS_B,
327 MLX4_CMD_WRAPPED);
328 if (err)
329 goto free_mailbox;
330
331 *mpt_entry = (struct mlx4_mpt_entry **)&mailbox->buf;
332 }
333
334 if (!(*mpt_entry) || !(**mpt_entry)) {
335 err = -ENOMEM;
336 goto free_mailbox;
337 }
338
339 return 0;
340
341 free_mailbox:
342 mlx4_free_cmd_mailbox(dev, mailbox);
343 return err;
344 }
345 EXPORT_SYMBOL_GPL(mlx4_mr_hw_get_mpt);
346
347 int mlx4_mr_hw_write_mpt(struct mlx4_dev *dev, struct mlx4_mr *mmr,
348 struct mlx4_mpt_entry **mpt_entry)
349 {
350 int err;
351
352 if (!mlx4_is_mfunc(dev)) {
353 /* Make sure any changes to this entry are flushed */
354 wmb();
355
356 *(u8 *)(*mpt_entry) = MLX4_MPT_STATUS_HW;
357
358 /* Make sure the new status is written */
359 wmb();
360
361 err = mlx4_SYNC_TPT(dev);
362 } else {
363 int key = key_to_hw_index(mmr->key) & (dev->caps.num_mpts - 1);
364
365 struct mlx4_cmd_mailbox *mailbox =
366 container_of((void *)mpt_entry, struct mlx4_cmd_mailbox,
367 buf);
368
369 err = mlx4_SW2HW_MPT(dev, mailbox, key);
370 }
371
372 if (!err) {
373 mmr->pd = be32_to_cpu((*mpt_entry)->pd_flags) & MLX4_MPT_PD_MASK;
374 mmr->enabled = MLX4_MPT_EN_HW;
375 }
376 return err;
377 }
378 EXPORT_SYMBOL_GPL(mlx4_mr_hw_write_mpt);
379
380 void mlx4_mr_hw_put_mpt(struct mlx4_dev *dev,
381 struct mlx4_mpt_entry **mpt_entry)
382 {
383 if (mlx4_is_mfunc(dev)) {
384 struct mlx4_cmd_mailbox *mailbox =
385 container_of((void *)mpt_entry, struct mlx4_cmd_mailbox,
386 buf);
387 mlx4_free_cmd_mailbox(dev, mailbox);
388 }
389 }
390 EXPORT_SYMBOL_GPL(mlx4_mr_hw_put_mpt);
391
392 int mlx4_mr_hw_change_pd(struct mlx4_dev *dev, struct mlx4_mpt_entry *mpt_entry,
393 u32 pdn)
394 {
395 u32 pd_flags = be32_to_cpu(mpt_entry->pd_flags) & ~MLX4_MPT_PD_MASK;
396 /* The wrapper function will put the slave's id here */
397 if (mlx4_is_mfunc(dev))
398 pd_flags &= ~MLX4_MPT_PD_VF_MASK;
399
400 mpt_entry->pd_flags = cpu_to_be32(pd_flags |
401 (pdn & MLX4_MPT_PD_MASK)
402 | MLX4_MPT_PD_FLAG_EN_INV);
403 return 0;
404 }
405 EXPORT_SYMBOL_GPL(mlx4_mr_hw_change_pd);
406
407 int mlx4_mr_hw_change_access(struct mlx4_dev *dev,
408 struct mlx4_mpt_entry *mpt_entry,
409 u32 access)
410 {
411 u32 flags = (be32_to_cpu(mpt_entry->flags) & ~MLX4_PERM_MASK) |
412 (access & MLX4_PERM_MASK);
413
414 mpt_entry->flags = cpu_to_be32(flags);
415 return 0;
416 }
417 EXPORT_SYMBOL_GPL(mlx4_mr_hw_change_access);
418
419 static int mlx4_mr_alloc_reserved(struct mlx4_dev *dev, u32 mridx, u32 pd,
420 u64 iova, u64 size, u32 access, int npages,
421 int page_shift, struct mlx4_mr *mr)
422 {
423 mr->iova = iova;
424 mr->size = size;
425 mr->pd = pd;
426 mr->access = access;
427 mr->enabled = MLX4_MPT_DISABLED;
428 mr->key = hw_index_to_key(mridx);
429
430 return mlx4_mtt_init(dev, npages, page_shift, &mr->mtt);
431 }
432
433 static int mlx4_WRITE_MTT(struct mlx4_dev *dev,
434 struct mlx4_cmd_mailbox *mailbox,
435 int num_entries)
436 {
437 return mlx4_cmd(dev, mailbox->dma, num_entries, 0, MLX4_CMD_WRITE_MTT,
438 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
439 }
440
441 int __mlx4_mpt_reserve(struct mlx4_dev *dev)
442 {
443 struct mlx4_priv *priv = mlx4_priv(dev);
444
445 return mlx4_bitmap_alloc(&priv->mr_table.mpt_bitmap);
446 }
447
448 static int mlx4_mpt_reserve(struct mlx4_dev *dev)
449 {
450 u64 out_param;
451
452 if (mlx4_is_mfunc(dev)) {
453 if (mlx4_cmd_imm(dev, 0, &out_param, RES_MPT, RES_OP_RESERVE,
454 MLX4_CMD_ALLOC_RES,
455 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED))
456 return -1;
457 return get_param_l(&out_param);
458 }
459 return __mlx4_mpt_reserve(dev);
460 }
461
462 void __mlx4_mpt_release(struct mlx4_dev *dev, u32 index)
463 {
464 struct mlx4_priv *priv = mlx4_priv(dev);
465
466 mlx4_bitmap_free(&priv->mr_table.mpt_bitmap, index, MLX4_NO_RR);
467 }
468
469 static void mlx4_mpt_release(struct mlx4_dev *dev, u32 index)
470 {
471 u64 in_param = 0;
472
473 if (mlx4_is_mfunc(dev)) {
474 set_param_l(&in_param, index);
475 if (mlx4_cmd(dev, in_param, RES_MPT, RES_OP_RESERVE,
476 MLX4_CMD_FREE_RES,
477 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED))
478 mlx4_warn(dev, "Failed to release mr index:%d\n",
479 index);
480 return;
481 }
482 __mlx4_mpt_release(dev, index);
483 }
484
485 int __mlx4_mpt_alloc_icm(struct mlx4_dev *dev, u32 index, gfp_t gfp)
486 {
487 struct mlx4_mr_table *mr_table = &mlx4_priv(dev)->mr_table;
488
489 return mlx4_table_get(dev, &mr_table->dmpt_table, index, gfp);
490 }
491
492 static int mlx4_mpt_alloc_icm(struct mlx4_dev *dev, u32 index, gfp_t gfp)
493 {
494 u64 param = 0;
495
496 if (mlx4_is_mfunc(dev)) {
497 set_param_l(&param, index);
498 return mlx4_cmd_imm(dev, param, &param, RES_MPT, RES_OP_MAP_ICM,
499 MLX4_CMD_ALLOC_RES,
500 MLX4_CMD_TIME_CLASS_A,
501 MLX4_CMD_WRAPPED);
502 }
503 return __mlx4_mpt_alloc_icm(dev, index, gfp);
504 }
505
506 void __mlx4_mpt_free_icm(struct mlx4_dev *dev, u32 index)
507 {
508 struct mlx4_mr_table *mr_table = &mlx4_priv(dev)->mr_table;
509
510 mlx4_table_put(dev, &mr_table->dmpt_table, index);
511 }
512
513 static void mlx4_mpt_free_icm(struct mlx4_dev *dev, u32 index)
514 {
515 u64 in_param = 0;
516
517 if (mlx4_is_mfunc(dev)) {
518 set_param_l(&in_param, index);
519 if (mlx4_cmd(dev, in_param, RES_MPT, RES_OP_MAP_ICM,
520 MLX4_CMD_FREE_RES, MLX4_CMD_TIME_CLASS_A,
521 MLX4_CMD_WRAPPED))
522 mlx4_warn(dev, "Failed to free icm of mr index:%d\n",
523 index);
524 return;
525 }
526 return __mlx4_mpt_free_icm(dev, index);
527 }
528
529 int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access,
530 int npages, int page_shift, struct mlx4_mr *mr)
531 {
532 u32 index;
533 int err;
534
535 index = mlx4_mpt_reserve(dev);
536 if (index == -1)
537 return -ENOMEM;
538
539 err = mlx4_mr_alloc_reserved(dev, index, pd, iova, size,
540 access, npages, page_shift, mr);
541 if (err)
542 mlx4_mpt_release(dev, index);
543
544 return err;
545 }
546 EXPORT_SYMBOL_GPL(mlx4_mr_alloc);
547
548 static int mlx4_mr_free_reserved(struct mlx4_dev *dev, struct mlx4_mr *mr)
549 {
550 int err;
551
552 if (mr->enabled == MLX4_MPT_EN_HW) {
553 err = mlx4_HW2SW_MPT(dev, NULL,
554 key_to_hw_index(mr->key) &
555 (dev->caps.num_mpts - 1));
556 if (err) {
557 mlx4_warn(dev, "HW2SW_MPT failed (%d), MR has MWs bound to it\n",
558 err);
559 return err;
560 }
561
562 mr->enabled = MLX4_MPT_EN_SW;
563 }
564 mlx4_mtt_cleanup(dev, &mr->mtt);
565
566 return 0;
567 }
568
569 int mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr)
570 {
571 int ret;
572
573 ret = mlx4_mr_free_reserved(dev, mr);
574 if (ret)
575 return ret;
576 if (mr->enabled)
577 mlx4_mpt_free_icm(dev, key_to_hw_index(mr->key));
578 mlx4_mpt_release(dev, key_to_hw_index(mr->key));
579
580 return 0;
581 }
582 EXPORT_SYMBOL_GPL(mlx4_mr_free);
583
584 void mlx4_mr_rereg_mem_cleanup(struct mlx4_dev *dev, struct mlx4_mr *mr)
585 {
586 mlx4_mtt_cleanup(dev, &mr->mtt);
587 mr->mtt.order = -1;
588 }
589 EXPORT_SYMBOL_GPL(mlx4_mr_rereg_mem_cleanup);
590
591 int mlx4_mr_rereg_mem_write(struct mlx4_dev *dev, struct mlx4_mr *mr,
592 u64 iova, u64 size, int npages,
593 int page_shift, struct mlx4_mpt_entry *mpt_entry)
594 {
595 int err;
596
597 err = mlx4_mtt_init(dev, npages, page_shift, &mr->mtt);
598 if (err)
599 return err;
600
601 mpt_entry->start = cpu_to_be64(iova);
602 mpt_entry->length = cpu_to_be64(size);
603 mpt_entry->entity_size = cpu_to_be32(page_shift);
604 mpt_entry->flags &= ~(cpu_to_be32(MLX4_MPT_FLAG_FREE |
605 MLX4_MPT_FLAG_SW_OWNS));
606 if (mr->mtt.order < 0) {
607 mpt_entry->flags |= cpu_to_be32(MLX4_MPT_FLAG_PHYSICAL);
608 mpt_entry->mtt_addr = 0;
609 } else {
610 mpt_entry->mtt_addr = cpu_to_be64(mlx4_mtt_addr(dev,
611 &mr->mtt));
612 if (mr->mtt.page_shift == 0)
613 mpt_entry->mtt_sz = cpu_to_be32(1 << mr->mtt.order);
614 }
615 if (mr->mtt.order >= 0 && mr->mtt.page_shift == 0) {
616 /* fast register MR in free state */
617 mpt_entry->flags |= cpu_to_be32(MLX4_MPT_FLAG_FREE);
618 mpt_entry->pd_flags |= cpu_to_be32(MLX4_MPT_PD_FLAG_FAST_REG |
619 MLX4_MPT_PD_FLAG_RAE);
620 } else {
621 mpt_entry->flags |= cpu_to_be32(MLX4_MPT_FLAG_SW_OWNS);
622 }
623 mr->enabled = MLX4_MPT_EN_SW;
624
625 return 0;
626 }
627 EXPORT_SYMBOL_GPL(mlx4_mr_rereg_mem_write);
628
629 int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr)
630 {
631 struct mlx4_cmd_mailbox *mailbox;
632 struct mlx4_mpt_entry *mpt_entry;
633 int err;
634
635 err = mlx4_mpt_alloc_icm(dev, key_to_hw_index(mr->key), GFP_KERNEL);
636 if (err)
637 return err;
638
639 mailbox = mlx4_alloc_cmd_mailbox(dev);
640 if (IS_ERR(mailbox)) {
641 err = PTR_ERR(mailbox);
642 goto err_table;
643 }
644 mpt_entry = mailbox->buf;
645 mpt_entry->flags = cpu_to_be32(MLX4_MPT_FLAG_MIO |
646 MLX4_MPT_FLAG_REGION |
647 mr->access);
648
649 mpt_entry->key = cpu_to_be32(key_to_hw_index(mr->key));
650 mpt_entry->pd_flags = cpu_to_be32(mr->pd | MLX4_MPT_PD_FLAG_EN_INV);
651 mpt_entry->start = cpu_to_be64(mr->iova);
652 mpt_entry->length = cpu_to_be64(mr->size);
653 mpt_entry->entity_size = cpu_to_be32(mr->mtt.page_shift);
654
655 if (mr->mtt.order < 0) {
656 mpt_entry->flags |= cpu_to_be32(MLX4_MPT_FLAG_PHYSICAL);
657 mpt_entry->mtt_addr = 0;
658 } else {
659 mpt_entry->mtt_addr = cpu_to_be64(mlx4_mtt_addr(dev,
660 &mr->mtt));
661 }
662
663 if (mr->mtt.order >= 0 && mr->mtt.page_shift == 0) {
664 /* fast register MR in free state */
665 mpt_entry->flags |= cpu_to_be32(MLX4_MPT_FLAG_FREE);
666 mpt_entry->pd_flags |= cpu_to_be32(MLX4_MPT_PD_FLAG_FAST_REG |
667 MLX4_MPT_PD_FLAG_RAE);
668 mpt_entry->mtt_sz = cpu_to_be32(1 << mr->mtt.order);
669 } else {
670 mpt_entry->flags |= cpu_to_be32(MLX4_MPT_FLAG_SW_OWNS);
671 }
672
673 err = mlx4_SW2HW_MPT(dev, mailbox,
674 key_to_hw_index(mr->key) & (dev->caps.num_mpts - 1));
675 if (err) {
676 mlx4_warn(dev, "SW2HW_MPT failed (%d)\n", err);
677 goto err_cmd;
678 }
679 mr->enabled = MLX4_MPT_EN_HW;
680
681 mlx4_free_cmd_mailbox(dev, mailbox);
682
683 return 0;
684
685 err_cmd:
686 mlx4_free_cmd_mailbox(dev, mailbox);
687
688 err_table:
689 mlx4_mpt_free_icm(dev, key_to_hw_index(mr->key));
690 return err;
691 }
692 EXPORT_SYMBOL_GPL(mlx4_mr_enable);
693
694 static int mlx4_write_mtt_chunk(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
695 int start_index, int npages, u64 *page_list)
696 {
697 struct mlx4_priv *priv = mlx4_priv(dev);
698 __be64 *mtts;
699 dma_addr_t dma_handle;
700 int i;
701
702 mtts = mlx4_table_find(&priv->mr_table.mtt_table, mtt->offset +
703 start_index, &dma_handle);
704
705 if (!mtts)
706 return -ENOMEM;
707
708 dma_sync_single_for_cpu(&dev->persist->pdev->dev, dma_handle,
709 npages * sizeof (u64), DMA_TO_DEVICE);
710
711 for (i = 0; i < npages; ++i)
712 mtts[i] = cpu_to_be64(page_list[i] | MLX4_MTT_FLAG_PRESENT);
713
714 dma_sync_single_for_device(&dev->persist->pdev->dev, dma_handle,
715 npages * sizeof (u64), DMA_TO_DEVICE);
716
717 return 0;
718 }
719
720 int __mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
721 int start_index, int npages, u64 *page_list)
722 {
723 int err = 0;
724 int chunk;
725 int mtts_per_page;
726 int max_mtts_first_page;
727
728 /* compute how may mtts fit in the first page */
729 mtts_per_page = PAGE_SIZE / sizeof(u64);
730 max_mtts_first_page = mtts_per_page - (mtt->offset + start_index)
731 % mtts_per_page;
732
733 chunk = min_t(int, max_mtts_first_page, npages);
734
735 while (npages > 0) {
736 err = mlx4_write_mtt_chunk(dev, mtt, start_index, chunk, page_list);
737 if (err)
738 return err;
739 npages -= chunk;
740 start_index += chunk;
741 page_list += chunk;
742
743 chunk = min_t(int, mtts_per_page, npages);
744 }
745 return err;
746 }
747
748 int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
749 int start_index, int npages, u64 *page_list)
750 {
751 struct mlx4_cmd_mailbox *mailbox = NULL;
752 __be64 *inbox = NULL;
753 int chunk;
754 int err = 0;
755 int i;
756
757 if (mtt->order < 0)
758 return -EINVAL;
759
760 if (mlx4_is_mfunc(dev)) {
761 mailbox = mlx4_alloc_cmd_mailbox(dev);
762 if (IS_ERR(mailbox))
763 return PTR_ERR(mailbox);
764 inbox = mailbox->buf;
765
766 while (npages > 0) {
767 chunk = min_t(int, MLX4_MAILBOX_SIZE / sizeof(u64) - 2,
768 npages);
769 inbox[0] = cpu_to_be64(mtt->offset + start_index);
770 inbox[1] = 0;
771 for (i = 0; i < chunk; ++i)
772 inbox[i + 2] = cpu_to_be64(page_list[i] |
773 MLX4_MTT_FLAG_PRESENT);
774 err = mlx4_WRITE_MTT(dev, mailbox, chunk);
775 if (err) {
776 mlx4_free_cmd_mailbox(dev, mailbox);
777 return err;
778 }
779
780 npages -= chunk;
781 start_index += chunk;
782 page_list += chunk;
783 }
784 mlx4_free_cmd_mailbox(dev, mailbox);
785 return err;
786 }
787
788 return __mlx4_write_mtt(dev, mtt, start_index, npages, page_list);
789 }
790 EXPORT_SYMBOL_GPL(mlx4_write_mtt);
791
792 int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
793 struct mlx4_buf *buf, gfp_t gfp)
794 {
795 u64 *page_list;
796 int err;
797 int i;
798
799 page_list = kmalloc(buf->npages * sizeof *page_list,
800 gfp);
801 if (!page_list)
802 return -ENOMEM;
803
804 for (i = 0; i < buf->npages; ++i)
805 if (buf->nbufs == 1)
806 page_list[i] = buf->direct.map + (i << buf->page_shift);
807 else
808 page_list[i] = buf->page_list[i].map;
809
810 err = mlx4_write_mtt(dev, mtt, 0, buf->npages, page_list);
811
812 kfree(page_list);
813 return err;
814 }
815 EXPORT_SYMBOL_GPL(mlx4_buf_write_mtt);
816
817 int mlx4_mw_alloc(struct mlx4_dev *dev, u32 pd, enum mlx4_mw_type type,
818 struct mlx4_mw *mw)
819 {
820 u32 index;
821
822 if ((type == MLX4_MW_TYPE_1 &&
823 !(dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW)) ||
824 (type == MLX4_MW_TYPE_2 &&
825 !(dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN)))
826 return -ENOTSUPP;
827
828 index = mlx4_mpt_reserve(dev);
829 if (index == -1)
830 return -ENOMEM;
831
832 mw->key = hw_index_to_key(index);
833 mw->pd = pd;
834 mw->type = type;
835 mw->enabled = MLX4_MPT_DISABLED;
836
837 return 0;
838 }
839 EXPORT_SYMBOL_GPL(mlx4_mw_alloc);
840
841 int mlx4_mw_enable(struct mlx4_dev *dev, struct mlx4_mw *mw)
842 {
843 struct mlx4_cmd_mailbox *mailbox;
844 struct mlx4_mpt_entry *mpt_entry;
845 int err;
846
847 err = mlx4_mpt_alloc_icm(dev, key_to_hw_index(mw->key), GFP_KERNEL);
848 if (err)
849 return err;
850
851 mailbox = mlx4_alloc_cmd_mailbox(dev);
852 if (IS_ERR(mailbox)) {
853 err = PTR_ERR(mailbox);
854 goto err_table;
855 }
856 mpt_entry = mailbox->buf;
857
858 /* Note that the MLX4_MPT_FLAG_REGION bit in mpt_entry->flags is turned
859 * off, thus creating a memory window and not a memory region.
860 */
861 mpt_entry->key = cpu_to_be32(key_to_hw_index(mw->key));
862 mpt_entry->pd_flags = cpu_to_be32(mw->pd);
863 if (mw->type == MLX4_MW_TYPE_2) {
864 mpt_entry->flags |= cpu_to_be32(MLX4_MPT_FLAG_FREE);
865 mpt_entry->qpn = cpu_to_be32(MLX4_MPT_QP_FLAG_BOUND_QP);
866 mpt_entry->pd_flags |= cpu_to_be32(MLX4_MPT_PD_FLAG_EN_INV);
867 }
868
869 err = mlx4_SW2HW_MPT(dev, mailbox,
870 key_to_hw_index(mw->key) &
871 (dev->caps.num_mpts - 1));
872 if (err) {
873 mlx4_warn(dev, "SW2HW_MPT failed (%d)\n", err);
874 goto err_cmd;
875 }
876 mw->enabled = MLX4_MPT_EN_HW;
877
878 mlx4_free_cmd_mailbox(dev, mailbox);
879
880 return 0;
881
882 err_cmd:
883 mlx4_free_cmd_mailbox(dev, mailbox);
884
885 err_table:
886 mlx4_mpt_free_icm(dev, key_to_hw_index(mw->key));
887 return err;
888 }
889 EXPORT_SYMBOL_GPL(mlx4_mw_enable);
890
891 void mlx4_mw_free(struct mlx4_dev *dev, struct mlx4_mw *mw)
892 {
893 int err;
894
895 if (mw->enabled == MLX4_MPT_EN_HW) {
896 err = mlx4_HW2SW_MPT(dev, NULL,
897 key_to_hw_index(mw->key) &
898 (dev->caps.num_mpts - 1));
899 if (err)
900 mlx4_warn(dev, "xxx HW2SW_MPT failed (%d)\n", err);
901
902 mw->enabled = MLX4_MPT_EN_SW;
903 }
904 if (mw->enabled)
905 mlx4_mpt_free_icm(dev, key_to_hw_index(mw->key));
906 mlx4_mpt_release(dev, key_to_hw_index(mw->key));
907 }
908 EXPORT_SYMBOL_GPL(mlx4_mw_free);
909
910 int mlx4_init_mr_table(struct mlx4_dev *dev)
911 {
912 struct mlx4_priv *priv = mlx4_priv(dev);
913 struct mlx4_mr_table *mr_table = &priv->mr_table;
914 int err;
915
916 /* Nothing to do for slaves - all MR handling is forwarded
917 * to the master */
918 if (mlx4_is_slave(dev))
919 return 0;
920
921 if (!is_power_of_2(dev->caps.num_mpts))
922 return -EINVAL;
923
924 err = mlx4_bitmap_init(&mr_table->mpt_bitmap, dev->caps.num_mpts,
925 ~0, dev->caps.reserved_mrws, 0);
926 if (err)
927 return err;
928
929 err = mlx4_buddy_init(&mr_table->mtt_buddy,
930 ilog2((u32)dev->caps.num_mtts /
931 (1 << log_mtts_per_seg)));
932 if (err)
933 goto err_buddy;
934
935 if (dev->caps.reserved_mtts) {
936 priv->reserved_mtts =
937 mlx4_alloc_mtt_range(dev,
938 fls(dev->caps.reserved_mtts - 1));
939 if (priv->reserved_mtts < 0) {
940 mlx4_warn(dev, "MTT table of order %u is too small\n",
941 mr_table->mtt_buddy.max_order);
942 err = -ENOMEM;
943 goto err_reserve_mtts;
944 }
945 }
946
947 return 0;
948
949 err_reserve_mtts:
950 mlx4_buddy_cleanup(&mr_table->mtt_buddy);
951
952 err_buddy:
953 mlx4_bitmap_cleanup(&mr_table->mpt_bitmap);
954
955 return err;
956 }
957
958 void mlx4_cleanup_mr_table(struct mlx4_dev *dev)
959 {
960 struct mlx4_priv *priv = mlx4_priv(dev);
961 struct mlx4_mr_table *mr_table = &priv->mr_table;
962
963 if (mlx4_is_slave(dev))
964 return;
965 if (priv->reserved_mtts >= 0)
966 mlx4_free_mtt_range(dev, priv->reserved_mtts,
967 fls(dev->caps.reserved_mtts - 1));
968 mlx4_buddy_cleanup(&mr_table->mtt_buddy);
969 mlx4_bitmap_cleanup(&mr_table->mpt_bitmap);
970 }
971
972 static inline int mlx4_check_fmr(struct mlx4_fmr *fmr, u64 *page_list,
973 int npages, u64 iova)
974 {
975 int i, page_mask;
976
977 if (npages > fmr->max_pages)
978 return -EINVAL;
979
980 page_mask = (1 << fmr->page_shift) - 1;
981
982 /* We are getting page lists, so va must be page aligned. */
983 if (iova & page_mask)
984 return -EINVAL;
985
986 /* Trust the user not to pass misaligned data in page_list */
987 if (0)
988 for (i = 0; i < npages; ++i) {
989 if (page_list[i] & ~page_mask)
990 return -EINVAL;
991 }
992
993 if (fmr->maps >= fmr->max_maps)
994 return -EINVAL;
995
996 return 0;
997 }
998
999 int mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list,
1000 int npages, u64 iova, u32 *lkey, u32 *rkey)
1001 {
1002 u32 key;
1003 int i, err;
1004
1005 err = mlx4_check_fmr(fmr, page_list, npages, iova);
1006 if (err)
1007 return err;
1008
1009 ++fmr->maps;
1010
1011 key = key_to_hw_index(fmr->mr.key);
1012 key += dev->caps.num_mpts;
1013 *lkey = *rkey = fmr->mr.key = hw_index_to_key(key);
1014
1015 *(u8 *) fmr->mpt = MLX4_MPT_STATUS_SW;
1016
1017 /* Make sure MPT status is visible before writing MTT entries */
1018 wmb();
1019
1020 dma_sync_single_for_cpu(&dev->persist->pdev->dev, fmr->dma_handle,
1021 npages * sizeof(u64), DMA_TO_DEVICE);
1022
1023 for (i = 0; i < npages; ++i)
1024 fmr->mtts[i] = cpu_to_be64(page_list[i] | MLX4_MTT_FLAG_PRESENT);
1025
1026 dma_sync_single_for_device(&dev->persist->pdev->dev, fmr->dma_handle,
1027 npages * sizeof(u64), DMA_TO_DEVICE);
1028
1029 fmr->mpt->key = cpu_to_be32(key);
1030 fmr->mpt->lkey = cpu_to_be32(key);
1031 fmr->mpt->length = cpu_to_be64(npages * (1ull << fmr->page_shift));
1032 fmr->mpt->start = cpu_to_be64(iova);
1033
1034 /* Make MTT entries are visible before setting MPT status */
1035 wmb();
1036
1037 *(u8 *) fmr->mpt = MLX4_MPT_STATUS_HW;
1038
1039 /* Make sure MPT status is visible before consumer can use FMR */
1040 wmb();
1041
1042 return 0;
1043 }
1044 EXPORT_SYMBOL_GPL(mlx4_map_phys_fmr);
1045
1046 int mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages,
1047 int max_maps, u8 page_shift, struct mlx4_fmr *fmr)
1048 {
1049 struct mlx4_priv *priv = mlx4_priv(dev);
1050 int err = -ENOMEM;
1051
1052 if (max_maps > dev->caps.max_fmr_maps)
1053 return -EINVAL;
1054
1055 if (page_shift < (ffs(dev->caps.page_size_cap) - 1) || page_shift >= 32)
1056 return -EINVAL;
1057
1058 /* All MTTs must fit in the same page */
1059 if (max_pages * sizeof *fmr->mtts > PAGE_SIZE)
1060 return -EINVAL;
1061
1062 fmr->page_shift = page_shift;
1063 fmr->max_pages = max_pages;
1064 fmr->max_maps = max_maps;
1065 fmr->maps = 0;
1066
1067 err = mlx4_mr_alloc(dev, pd, 0, 0, access, max_pages,
1068 page_shift, &fmr->mr);
1069 if (err)
1070 return err;
1071
1072 fmr->mtts = mlx4_table_find(&priv->mr_table.mtt_table,
1073 fmr->mr.mtt.offset,
1074 &fmr->dma_handle);
1075
1076 if (!fmr->mtts) {
1077 err = -ENOMEM;
1078 goto err_free;
1079 }
1080
1081 return 0;
1082
1083 err_free:
1084 (void) mlx4_mr_free(dev, &fmr->mr);
1085 return err;
1086 }
1087 EXPORT_SYMBOL_GPL(mlx4_fmr_alloc);
1088
1089 int mlx4_fmr_enable(struct mlx4_dev *dev, struct mlx4_fmr *fmr)
1090 {
1091 struct mlx4_priv *priv = mlx4_priv(dev);
1092 int err;
1093
1094 err = mlx4_mr_enable(dev, &fmr->mr);
1095 if (err)
1096 return err;
1097
1098 fmr->mpt = mlx4_table_find(&priv->mr_table.dmpt_table,
1099 key_to_hw_index(fmr->mr.key), NULL);
1100 if (!fmr->mpt)
1101 return -ENOMEM;
1102
1103 return 0;
1104 }
1105 EXPORT_SYMBOL_GPL(mlx4_fmr_enable);
1106
1107 void mlx4_fmr_unmap(struct mlx4_dev *dev, struct mlx4_fmr *fmr,
1108 u32 *lkey, u32 *rkey)
1109 {
1110 struct mlx4_cmd_mailbox *mailbox;
1111 int err;
1112
1113 if (!fmr->maps)
1114 return;
1115
1116 fmr->maps = 0;
1117
1118 mailbox = mlx4_alloc_cmd_mailbox(dev);
1119 if (IS_ERR(mailbox)) {
1120 err = PTR_ERR(mailbox);
1121 pr_warn("mlx4_ib: mlx4_alloc_cmd_mailbox failed (%d)\n", err);
1122 return;
1123 }
1124
1125 err = mlx4_HW2SW_MPT(dev, NULL,
1126 key_to_hw_index(fmr->mr.key) &
1127 (dev->caps.num_mpts - 1));
1128 mlx4_free_cmd_mailbox(dev, mailbox);
1129 if (err) {
1130 pr_warn("mlx4_ib: mlx4_HW2SW_MPT failed (%d)\n", err);
1131 return;
1132 }
1133 fmr->mr.enabled = MLX4_MPT_EN_SW;
1134 }
1135 EXPORT_SYMBOL_GPL(mlx4_fmr_unmap);
1136
1137 int mlx4_fmr_free(struct mlx4_dev *dev, struct mlx4_fmr *fmr)
1138 {
1139 int ret;
1140
1141 if (fmr->maps)
1142 return -EBUSY;
1143
1144 ret = mlx4_mr_free(dev, &fmr->mr);
1145 if (ret)
1146 return ret;
1147 fmr->mr.enabled = MLX4_MPT_DISABLED;
1148
1149 return 0;
1150 }
1151 EXPORT_SYMBOL_GPL(mlx4_fmr_free);
1152
1153 int mlx4_SYNC_TPT(struct mlx4_dev *dev)
1154 {
1155 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_SYNC_TPT,
1156 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1157 }
1158 EXPORT_SYMBOL_GPL(mlx4_SYNC_TPT);
Linux kernel - Deliverables
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