2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/errno.h>
34 #include <linux/if_ether.h>
35 #include <linux/export.h>
37 #include <linux/mlx4/cmd.h>
41 #define MLX4_MAC_VALID (1ull << 63)
42 #define MLX4_MAC_MASK 0xffffffffffffULL
44 #define MLX4_VLAN_VALID (1u << 31)
45 #define MLX4_VLAN_MASK 0xfff
47 #define MLX4_STATS_TRAFFIC_COUNTERS_MASK 0xfULL
48 #define MLX4_STATS_TRAFFIC_DROPS_MASK 0xc0ULL
49 #define MLX4_STATS_ERROR_COUNTERS_MASK 0x1ffc30ULL
50 #define MLX4_STATS_PORT_COUNTERS_MASK 0x1fe00000ULL
52 void mlx4_init_mac_table(struct mlx4_dev
*dev
, struct mlx4_mac_table
*table
)
56 mutex_init(&table
->mutex
);
57 for (i
= 0; i
< MLX4_MAX_MAC_NUM
; i
++) {
58 table
->entries
[i
] = 0;
61 table
->max
= 1 << dev
->caps
.log_num_macs
;
65 void mlx4_init_vlan_table(struct mlx4_dev
*dev
, struct mlx4_vlan_table
*table
)
69 mutex_init(&table
->mutex
);
70 for (i
= 0; i
< MLX4_MAX_VLAN_NUM
; i
++) {
71 table
->entries
[i
] = 0;
74 table
->max
= (1 << dev
->caps
.log_num_vlans
) - MLX4_VLAN_REGULAR
;
78 static int mlx4_uc_steer_add(struct mlx4_dev
*dev
, u8 port
, u64 mac
, int *qpn
)
87 mac
&= 0xffffffffffffULL
;
88 be_mac
= cpu_to_be64(mac
<< 16);
89 memcpy(&gid
[10], &be_mac
, ETH_ALEN
);
92 err
= mlx4_unicast_attach(dev
, &qp
, gid
, 0, MLX4_PROT_ETH
);
94 mlx4_warn(dev
, "Failed Attaching Unicast\n");
99 static void mlx4_uc_steer_release(struct mlx4_dev
*dev
, u8 port
,
107 mac
&= 0xffffffffffffULL
;
108 be_mac
= cpu_to_be64(mac
<< 16);
109 memcpy(&gid
[10], &be_mac
, ETH_ALEN
);
112 mlx4_unicast_detach(dev
, &qp
, gid
, MLX4_PROT_ETH
);
115 static int validate_index(struct mlx4_dev
*dev
,
116 struct mlx4_mac_table
*table
, int index
)
120 if (index
< 0 || index
>= table
->max
|| !table
->entries
[index
]) {
121 mlx4_warn(dev
, "No valid Mac entry for the given index\n");
127 static int find_index(struct mlx4_dev
*dev
,
128 struct mlx4_mac_table
*table
, u64 mac
)
132 for (i
= 0; i
< MLX4_MAX_MAC_NUM
; i
++) {
133 if ((mac
& MLX4_MAC_MASK
) ==
134 (MLX4_MAC_MASK
& be64_to_cpu(table
->entries
[i
])))
141 int mlx4_get_eth_qp(struct mlx4_dev
*dev
, u8 port
, u64 mac
, int *qpn
)
143 struct mlx4_port_info
*info
= &mlx4_priv(dev
)->port
[port
];
144 struct mlx4_mac_entry
*entry
;
148 mlx4_dbg(dev
, "Registering MAC: 0x%llx for adding\n",
149 (unsigned long long) mac
);
150 index
= mlx4_register_mac(dev
, port
, mac
);
153 mlx4_err(dev
, "Failed adding MAC: 0x%llx\n",
154 (unsigned long long) mac
);
158 if (!(dev
->caps
.flags
& MLX4_DEV_CAP_FLAG_VEP_UC_STEER
)) {
159 *qpn
= info
->base_qpn
+ index
;
163 err
= mlx4_qp_reserve_range(dev
, 1, 1, qpn
);
164 mlx4_dbg(dev
, "Reserved qp %d\n", *qpn
);
166 mlx4_err(dev
, "Failed to reserve qp for mac registration\n");
170 err
= mlx4_uc_steer_add(dev
, port
, mac
, qpn
);
174 entry
= kmalloc(sizeof *entry
, GFP_KERNEL
);
180 err
= radix_tree_insert(&info
->mac_tree
, *qpn
, entry
);
189 mlx4_uc_steer_release(dev
, port
, mac
, *qpn
);
192 mlx4_qp_release_range(dev
, *qpn
, 1);
195 mlx4_unregister_mac(dev
, port
, mac
);
198 EXPORT_SYMBOL_GPL(mlx4_get_eth_qp
);
200 void mlx4_put_eth_qp(struct mlx4_dev
*dev
, u8 port
, u64 mac
, int qpn
)
202 struct mlx4_port_info
*info
= &mlx4_priv(dev
)->port
[port
];
203 struct mlx4_mac_entry
*entry
;
205 mlx4_dbg(dev
, "Registering MAC: 0x%llx for deleting\n",
206 (unsigned long long) mac
);
207 mlx4_unregister_mac(dev
, port
, mac
);
209 if (dev
->caps
.flags
& MLX4_DEV_CAP_FLAG_VEP_UC_STEER
) {
210 entry
= radix_tree_lookup(&info
->mac_tree
, qpn
);
212 mlx4_dbg(dev
, "Releasing qp: port %d, mac 0x%llx,"
214 (unsigned long long) mac
, qpn
);
215 mlx4_uc_steer_release(dev
, port
, entry
->mac
, qpn
);
216 mlx4_qp_release_range(dev
, qpn
, 1);
217 radix_tree_delete(&info
->mac_tree
, qpn
);
222 EXPORT_SYMBOL_GPL(mlx4_put_eth_qp
);
224 static int mlx4_set_port_mac_table(struct mlx4_dev
*dev
, u8 port
,
227 struct mlx4_cmd_mailbox
*mailbox
;
231 mailbox
= mlx4_alloc_cmd_mailbox(dev
);
233 return PTR_ERR(mailbox
);
235 memcpy(mailbox
->buf
, entries
, MLX4_MAC_TABLE_SIZE
);
237 in_mod
= MLX4_SET_PORT_MAC_TABLE
<< 8 | port
;
239 err
= mlx4_cmd(dev
, mailbox
->dma
, in_mod
, 1, MLX4_CMD_SET_PORT
,
240 MLX4_CMD_TIME_CLASS_B
, MLX4_CMD_NATIVE
);
242 mlx4_free_cmd_mailbox(dev
, mailbox
);
246 int __mlx4_register_mac(struct mlx4_dev
*dev
, u8 port
, u64 mac
)
248 struct mlx4_port_info
*info
= &mlx4_priv(dev
)->port
[port
];
249 struct mlx4_mac_table
*table
= &info
->mac_table
;
253 mlx4_dbg(dev
, "Registering MAC: 0x%llx for port %d\n",
254 (unsigned long long) mac
, port
);
256 mutex_lock(&table
->mutex
);
257 for (i
= 0; i
< MLX4_MAX_MAC_NUM
; i
++) {
258 if (free
< 0 && !table
->entries
[i
]) {
263 if (mac
== (MLX4_MAC_MASK
& be64_to_cpu(table
->entries
[i
]))) {
264 /* MAC already registered, Must not have duplicates */
270 mlx4_dbg(dev
, "Free MAC index is %d\n", free
);
272 if (table
->total
== table
->max
) {
273 /* No free mac entries */
278 /* Register new MAC */
279 table
->entries
[free
] = cpu_to_be64(mac
| MLX4_MAC_VALID
);
281 err
= mlx4_set_port_mac_table(dev
, port
, table
->entries
);
283 mlx4_err(dev
, "Failed adding MAC: 0x%llx\n",
284 (unsigned long long) mac
);
285 table
->entries
[free
] = 0;
292 mutex_unlock(&table
->mutex
);
295 EXPORT_SYMBOL_GPL(__mlx4_register_mac
);
297 int mlx4_register_mac(struct mlx4_dev
*dev
, u8 port
, u64 mac
)
302 if (mlx4_is_mfunc(dev
)) {
303 set_param_l(&out_param
, port
);
304 err
= mlx4_cmd_imm(dev
, mac
, &out_param
, RES_MAC
,
305 RES_OP_RESERVE_AND_MAP
, MLX4_CMD_ALLOC_RES
,
306 MLX4_CMD_TIME_CLASS_A
, MLX4_CMD_WRAPPED
);
310 return get_param_l(&out_param
);
312 return __mlx4_register_mac(dev
, port
, mac
);
314 EXPORT_SYMBOL_GPL(mlx4_register_mac
);
317 void __mlx4_unregister_mac(struct mlx4_dev
*dev
, u8 port
, u64 mac
)
319 struct mlx4_port_info
*info
= &mlx4_priv(dev
)->port
[port
];
320 struct mlx4_mac_table
*table
= &info
->mac_table
;
323 index
= find_index(dev
, table
, mac
);
325 mutex_lock(&table
->mutex
);
327 if (validate_index(dev
, table
, index
))
330 table
->entries
[index
] = 0;
331 mlx4_set_port_mac_table(dev
, port
, table
->entries
);
334 mutex_unlock(&table
->mutex
);
336 EXPORT_SYMBOL_GPL(__mlx4_unregister_mac
);
338 void mlx4_unregister_mac(struct mlx4_dev
*dev
, u8 port
, u64 mac
)
342 if (mlx4_is_mfunc(dev
)) {
343 set_param_l(&out_param
, port
);
344 (void) mlx4_cmd_imm(dev
, mac
, &out_param
, RES_MAC
,
345 RES_OP_RESERVE_AND_MAP
, MLX4_CMD_FREE_RES
,
346 MLX4_CMD_TIME_CLASS_A
, MLX4_CMD_WRAPPED
);
349 __mlx4_unregister_mac(dev
, port
, mac
);
352 EXPORT_SYMBOL_GPL(mlx4_unregister_mac
);
354 int mlx4_replace_mac(struct mlx4_dev
*dev
, u8 port
, int qpn
, u64 new_mac
)
356 struct mlx4_port_info
*info
= &mlx4_priv(dev
)->port
[port
];
357 struct mlx4_mac_table
*table
= &info
->mac_table
;
358 struct mlx4_mac_entry
*entry
;
359 int index
= qpn
- info
->base_qpn
;
362 if (dev
->caps
.flags
& MLX4_DEV_CAP_FLAG_VEP_UC_STEER
) {
363 entry
= radix_tree_lookup(&info
->mac_tree
, qpn
);
366 mlx4_uc_steer_release(dev
, port
, entry
->mac
, qpn
);
367 mlx4_unregister_mac(dev
, port
, entry
->mac
);
368 entry
->mac
= new_mac
;
369 mlx4_register_mac(dev
, port
, new_mac
);
370 err
= mlx4_uc_steer_add(dev
, port
, entry
->mac
, &qpn
);
374 /* CX1 doesn't support multi-functions */
375 mutex_lock(&table
->mutex
);
377 err
= validate_index(dev
, table
, index
);
381 table
->entries
[index
] = cpu_to_be64(new_mac
| MLX4_MAC_VALID
);
383 err
= mlx4_set_port_mac_table(dev
, port
, table
->entries
);
385 mlx4_err(dev
, "Failed adding MAC: 0x%llx\n",
386 (unsigned long long) new_mac
);
387 table
->entries
[index
] = 0;
390 mutex_unlock(&table
->mutex
);
393 EXPORT_SYMBOL_GPL(mlx4_replace_mac
);
395 static int mlx4_set_port_vlan_table(struct mlx4_dev
*dev
, u8 port
,
398 struct mlx4_cmd_mailbox
*mailbox
;
402 mailbox
= mlx4_alloc_cmd_mailbox(dev
);
404 return PTR_ERR(mailbox
);
406 memcpy(mailbox
->buf
, entries
, MLX4_VLAN_TABLE_SIZE
);
407 in_mod
= MLX4_SET_PORT_VLAN_TABLE
<< 8 | port
;
408 err
= mlx4_cmd(dev
, mailbox
->dma
, in_mod
, 1, MLX4_CMD_SET_PORT
,
409 MLX4_CMD_TIME_CLASS_B
, MLX4_CMD_WRAPPED
);
411 mlx4_free_cmd_mailbox(dev
, mailbox
);
416 int mlx4_find_cached_vlan(struct mlx4_dev
*dev
, u8 port
, u16 vid
, int *idx
)
418 struct mlx4_vlan_table
*table
= &mlx4_priv(dev
)->port
[port
].vlan_table
;
421 for (i
= 0; i
< MLX4_MAX_VLAN_NUM
; ++i
) {
422 if (table
->refs
[i
] &&
423 (vid
== (MLX4_VLAN_MASK
&
424 be32_to_cpu(table
->entries
[i
])))) {
425 /* VLAN already registered, increase reference count */
433 EXPORT_SYMBOL_GPL(mlx4_find_cached_vlan
);
435 static int __mlx4_register_vlan(struct mlx4_dev
*dev
, u8 port
, u16 vlan
,
438 struct mlx4_vlan_table
*table
= &mlx4_priv(dev
)->port
[port
].vlan_table
;
442 mutex_lock(&table
->mutex
);
444 if (table
->total
== table
->max
) {
445 /* No free vlan entries */
450 for (i
= MLX4_VLAN_REGULAR
; i
< MLX4_MAX_VLAN_NUM
; i
++) {
451 if (free
< 0 && (table
->refs
[i
] == 0)) {
456 if (table
->refs
[i
] &&
457 (vlan
== (MLX4_VLAN_MASK
&
458 be32_to_cpu(table
->entries
[i
])))) {
459 /* Vlan already registered, increase references count */
471 /* Register new VLAN */
472 table
->refs
[free
] = 1;
473 table
->entries
[free
] = cpu_to_be32(vlan
| MLX4_VLAN_VALID
);
475 err
= mlx4_set_port_vlan_table(dev
, port
, table
->entries
);
477 mlx4_warn(dev
, "Failed adding vlan: %u\n", vlan
);
478 table
->refs
[free
] = 0;
479 table
->entries
[free
] = 0;
486 mutex_unlock(&table
->mutex
);
490 int mlx4_register_vlan(struct mlx4_dev
*dev
, u8 port
, u16 vlan
, int *index
)
495 if (mlx4_is_mfunc(dev
)) {
496 set_param_l(&out_param
, port
);
497 err
= mlx4_cmd_imm(dev
, vlan
, &out_param
, RES_VLAN
,
498 RES_OP_RESERVE_AND_MAP
, MLX4_CMD_ALLOC_RES
,
499 MLX4_CMD_TIME_CLASS_A
, MLX4_CMD_WRAPPED
);
501 *index
= get_param_l(&out_param
);
505 return __mlx4_register_vlan(dev
, port
, vlan
, index
);
507 EXPORT_SYMBOL_GPL(mlx4_register_vlan
);
509 static void __mlx4_unregister_vlan(struct mlx4_dev
*dev
, u8 port
, int index
)
511 struct mlx4_vlan_table
*table
= &mlx4_priv(dev
)->port
[port
].vlan_table
;
513 if (index
< MLX4_VLAN_REGULAR
) {
514 mlx4_warn(dev
, "Trying to free special vlan index %d\n", index
);
518 mutex_lock(&table
->mutex
);
519 if (!table
->refs
[index
]) {
520 mlx4_warn(dev
, "No vlan entry for index %d\n", index
);
523 if (--table
->refs
[index
]) {
524 mlx4_dbg(dev
, "Have more references for index %d,"
525 "no need to modify vlan table\n", index
);
528 table
->entries
[index
] = 0;
529 mlx4_set_port_vlan_table(dev
, port
, table
->entries
);
532 mutex_unlock(&table
->mutex
);
535 void mlx4_unregister_vlan(struct mlx4_dev
*dev
, u8 port
, int index
)
540 if (mlx4_is_mfunc(dev
)) {
541 set_param_l(&in_param
, port
);
542 err
= mlx4_cmd(dev
, in_param
, RES_VLAN
, RES_OP_RESERVE_AND_MAP
,
543 MLX4_CMD_FREE_RES
, MLX4_CMD_TIME_CLASS_A
,
546 mlx4_warn(dev
, "Failed freeing vlan at index:%d\n",
551 __mlx4_unregister_vlan(dev
, port
, index
);
553 EXPORT_SYMBOL_GPL(mlx4_unregister_vlan
);
555 int mlx4_get_port_ib_caps(struct mlx4_dev
*dev
, u8 port
, __be32
*caps
)
557 struct mlx4_cmd_mailbox
*inmailbox
, *outmailbox
;
561 inmailbox
= mlx4_alloc_cmd_mailbox(dev
);
562 if (IS_ERR(inmailbox
))
563 return PTR_ERR(inmailbox
);
565 outmailbox
= mlx4_alloc_cmd_mailbox(dev
);
566 if (IS_ERR(outmailbox
)) {
567 mlx4_free_cmd_mailbox(dev
, inmailbox
);
568 return PTR_ERR(outmailbox
);
571 inbuf
= inmailbox
->buf
;
572 outbuf
= outmailbox
->buf
;
573 memset(inbuf
, 0, 256);
574 memset(outbuf
, 0, 256);
579 *(__be16
*) (&inbuf
[16]) = cpu_to_be16(0x0015);
580 *(__be32
*) (&inbuf
[20]) = cpu_to_be32(port
);
582 err
= mlx4_cmd_box(dev
, inmailbox
->dma
, outmailbox
->dma
, port
, 3,
583 MLX4_CMD_MAD_IFC
, MLX4_CMD_TIME_CLASS_C
,
586 *caps
= *(__be32
*) (outbuf
+ 84);
587 mlx4_free_cmd_mailbox(dev
, inmailbox
);
588 mlx4_free_cmd_mailbox(dev
, outmailbox
);
592 static int mlx4_common_set_port(struct mlx4_dev
*dev
, int slave
, u32 in_mod
,
593 u8 op_mod
, struct mlx4_cmd_mailbox
*inbox
)
595 struct mlx4_priv
*priv
= mlx4_priv(dev
);
596 struct mlx4_port_info
*port_info
;
597 struct mlx4_mfunc_master_ctx
*master
= &priv
->mfunc
.master
;
598 struct mlx4_slave_state
*slave_st
= &master
->slave_state
[slave
];
599 struct mlx4_set_port_rqp_calc_context
*qpn_context
;
600 struct mlx4_set_port_general_context
*gen_context
;
601 int reset_qkey_viols
;
610 __be32 slave_cap_mask
;
613 port
= in_mod
& 0xff;
614 in_modifier
= in_mod
>> 8;
616 port_info
= &priv
->port
[port
];
618 /* Slaves cannot perform SET_PORT operations except changing MTU */
620 if (slave
!= dev
->caps
.function
&&
621 in_modifier
!= MLX4_SET_PORT_GENERAL
) {
622 mlx4_warn(dev
, "denying SET_PORT for slave:%d\n",
626 switch (in_modifier
) {
627 case MLX4_SET_PORT_RQP_CALC
:
628 qpn_context
= inbox
->buf
;
629 qpn_context
->base_qpn
=
630 cpu_to_be32(port_info
->base_qpn
);
631 qpn_context
->n_mac
= 0x7;
632 promisc
= be32_to_cpu(qpn_context
->promisc
) >>
633 SET_PORT_PROMISC_SHIFT
;
634 qpn_context
->promisc
= cpu_to_be32(
635 promisc
<< SET_PORT_PROMISC_SHIFT
|
636 port_info
->base_qpn
);
637 promisc
= be32_to_cpu(qpn_context
->mcast
) >>
638 SET_PORT_MC_PROMISC_SHIFT
;
639 qpn_context
->mcast
= cpu_to_be32(
640 promisc
<< SET_PORT_MC_PROMISC_SHIFT
|
641 port_info
->base_qpn
);
643 case MLX4_SET_PORT_GENERAL
:
644 gen_context
= inbox
->buf
;
645 /* Mtu is configured as the max MTU among all the
646 * the functions on the port. */
647 mtu
= be16_to_cpu(gen_context
->mtu
);
648 mtu
= min_t(int, mtu
, dev
->caps
.eth_mtu_cap
[port
]);
649 prev_mtu
= slave_st
->mtu
[port
];
650 slave_st
->mtu
[port
] = mtu
;
651 if (mtu
> master
->max_mtu
[port
])
652 master
->max_mtu
[port
] = mtu
;
653 if (mtu
< prev_mtu
&& prev_mtu
==
654 master
->max_mtu
[port
]) {
655 slave_st
->mtu
[port
] = mtu
;
656 master
->max_mtu
[port
] = mtu
;
657 for (i
= 0; i
< dev
->num_slaves
; i
++) {
658 master
->max_mtu
[port
] =
659 max(master
->max_mtu
[port
],
660 master
->slave_state
[i
].mtu
[port
]);
664 gen_context
->mtu
= cpu_to_be16(master
->max_mtu
[port
]);
667 return mlx4_cmd(dev
, inbox
->dma
, in_mod
, op_mod
,
668 MLX4_CMD_SET_PORT
, MLX4_CMD_TIME_CLASS_B
,
672 /* For IB, we only consider:
673 * - The capability mask, which is set to the aggregate of all
674 * slave function capabilities
675 * - The QKey violatin counter - reset according to each request.
678 if (dev
->flags
& MLX4_FLAG_OLD_PORT_CMDS
) {
679 reset_qkey_viols
= (*(u8
*) inbox
->buf
) & 0x40;
680 new_cap_mask
= ((__be32
*) inbox
->buf
)[2];
682 reset_qkey_viols
= ((u8
*) inbox
->buf
)[3] & 0x1;
683 new_cap_mask
= ((__be32
*) inbox
->buf
)[1];
688 priv
->mfunc
.master
.slave_state
[slave
].ib_cap_mask
[port
];
689 priv
->mfunc
.master
.slave_state
[slave
].ib_cap_mask
[port
] = new_cap_mask
;
690 for (i
= 0; i
< dev
->num_slaves
; i
++)
692 priv
->mfunc
.master
.slave_state
[i
].ib_cap_mask
[port
];
694 /* only clear mailbox for guests. Master may be setting
695 * MTU or PKEY table size
697 if (slave
!= dev
->caps
.function
)
698 memset(inbox
->buf
, 0, 256);
699 if (dev
->flags
& MLX4_FLAG_OLD_PORT_CMDS
) {
700 *(u8
*) inbox
->buf
|= !!reset_qkey_viols
<< 6;
701 ((__be32
*) inbox
->buf
)[2] = agg_cap_mask
;
703 ((u8
*) inbox
->buf
)[3] |= !!reset_qkey_viols
;
704 ((__be32
*) inbox
->buf
)[1] = agg_cap_mask
;
707 err
= mlx4_cmd(dev
, inbox
->dma
, port
, is_eth
, MLX4_CMD_SET_PORT
,
708 MLX4_CMD_TIME_CLASS_B
, MLX4_CMD_NATIVE
);
710 priv
->mfunc
.master
.slave_state
[slave
].ib_cap_mask
[port
] =
715 int mlx4_SET_PORT_wrapper(struct mlx4_dev
*dev
, int slave
,
716 struct mlx4_vhcr
*vhcr
,
717 struct mlx4_cmd_mailbox
*inbox
,
718 struct mlx4_cmd_mailbox
*outbox
,
719 struct mlx4_cmd_info
*cmd
)
721 return mlx4_common_set_port(dev
, slave
, vhcr
->in_modifier
,
722 vhcr
->op_modifier
, inbox
);
725 /* bit locations for set port command with zero op modifier */
727 MLX4_SET_PORT_VL_CAP
= 4, /* bits 7:4 */
728 MLX4_SET_PORT_MTU_CAP
= 12, /* bits 15:12 */
729 MLX4_CHANGE_PORT_PKEY_TBL_SZ
= 20,
730 MLX4_CHANGE_PORT_VL_CAP
= 21,
731 MLX4_CHANGE_PORT_MTU_CAP
= 22,
734 int mlx4_SET_PORT(struct mlx4_dev
*dev
, u8 port
, int pkey_tbl_sz
)
736 struct mlx4_cmd_mailbox
*mailbox
;
737 int err
, vl_cap
, pkey_tbl_flag
= 0;
739 if (dev
->caps
.port_type
[port
] == MLX4_PORT_TYPE_ETH
)
742 mailbox
= mlx4_alloc_cmd_mailbox(dev
);
744 return PTR_ERR(mailbox
);
746 memset(mailbox
->buf
, 0, 256);
748 ((__be32
*) mailbox
->buf
)[1] = dev
->caps
.ib_port_def_cap
[port
];
750 if (pkey_tbl_sz
>= 0 && mlx4_is_master(dev
)) {
752 ((__be16
*) mailbox
->buf
)[20] = cpu_to_be16(pkey_tbl_sz
);
755 /* IB VL CAP enum isn't used by the firmware, just numerical values */
756 for (vl_cap
= 8; vl_cap
>= 1; vl_cap
>>= 1) {
757 ((__be32
*) mailbox
->buf
)[0] = cpu_to_be32(
758 (1 << MLX4_CHANGE_PORT_MTU_CAP
) |
759 (1 << MLX4_CHANGE_PORT_VL_CAP
) |
760 (pkey_tbl_flag
<< MLX4_CHANGE_PORT_PKEY_TBL_SZ
) |
761 (dev
->caps
.port_ib_mtu
[port
] << MLX4_SET_PORT_MTU_CAP
) |
762 (vl_cap
<< MLX4_SET_PORT_VL_CAP
));
763 err
= mlx4_cmd(dev
, mailbox
->dma
, port
, 0, MLX4_CMD_SET_PORT
,
764 MLX4_CMD_TIME_CLASS_B
, MLX4_CMD_WRAPPED
);
769 mlx4_free_cmd_mailbox(dev
, mailbox
);
773 int mlx4_SET_PORT_general(struct mlx4_dev
*dev
, u8 port
, int mtu
,
774 u8 pptx
, u8 pfctx
, u8 pprx
, u8 pfcrx
)
776 struct mlx4_cmd_mailbox
*mailbox
;
777 struct mlx4_set_port_general_context
*context
;
781 mailbox
= mlx4_alloc_cmd_mailbox(dev
);
783 return PTR_ERR(mailbox
);
784 context
= mailbox
->buf
;
785 memset(context
, 0, sizeof *context
);
787 context
->flags
= SET_PORT_GEN_ALL_VALID
;
788 context
->mtu
= cpu_to_be16(mtu
);
789 context
->pptx
= (pptx
* (!pfctx
)) << 7;
790 context
->pfctx
= pfctx
;
791 context
->pprx
= (pprx
* (!pfcrx
)) << 7;
792 context
->pfcrx
= pfcrx
;
794 in_mod
= MLX4_SET_PORT_GENERAL
<< 8 | port
;
795 err
= mlx4_cmd(dev
, mailbox
->dma
, in_mod
, 1, MLX4_CMD_SET_PORT
,
796 MLX4_CMD_TIME_CLASS_B
, MLX4_CMD_WRAPPED
);
798 mlx4_free_cmd_mailbox(dev
, mailbox
);
801 EXPORT_SYMBOL(mlx4_SET_PORT_general
);
803 int mlx4_SET_PORT_qpn_calc(struct mlx4_dev
*dev
, u8 port
, u32 base_qpn
,
806 struct mlx4_cmd_mailbox
*mailbox
;
807 struct mlx4_set_port_rqp_calc_context
*context
;
810 u32 m_promisc
= (dev
->caps
.flags
& MLX4_DEV_CAP_FLAG_VEP_MC_STEER
) ?
811 MCAST_DIRECT
: MCAST_DEFAULT
;
813 if (dev
->caps
.flags
& MLX4_DEV_CAP_FLAG_VEP_MC_STEER
&&
814 dev
->caps
.flags
& MLX4_DEV_CAP_FLAG_VEP_UC_STEER
)
817 mailbox
= mlx4_alloc_cmd_mailbox(dev
);
819 return PTR_ERR(mailbox
);
820 context
= mailbox
->buf
;
821 memset(context
, 0, sizeof *context
);
823 context
->base_qpn
= cpu_to_be32(base_qpn
);
824 context
->n_mac
= dev
->caps
.log_num_macs
;
825 context
->promisc
= cpu_to_be32(promisc
<< SET_PORT_PROMISC_SHIFT
|
827 context
->mcast
= cpu_to_be32(m_promisc
<< SET_PORT_MC_PROMISC_SHIFT
|
829 context
->intra_no_vlan
= 0;
830 context
->no_vlan
= MLX4_NO_VLAN_IDX
;
831 context
->intra_vlan_miss
= 0;
832 context
->vlan_miss
= MLX4_VLAN_MISS_IDX
;
834 in_mod
= MLX4_SET_PORT_RQP_CALC
<< 8 | port
;
835 err
= mlx4_cmd(dev
, mailbox
->dma
, in_mod
, 1, MLX4_CMD_SET_PORT
,
836 MLX4_CMD_TIME_CLASS_B
, MLX4_CMD_WRAPPED
);
838 mlx4_free_cmd_mailbox(dev
, mailbox
);
841 EXPORT_SYMBOL(mlx4_SET_PORT_qpn_calc
);
843 int mlx4_SET_PORT_PRIO2TC(struct mlx4_dev
*dev
, u8 port
, u8
*prio2tc
)
845 struct mlx4_cmd_mailbox
*mailbox
;
846 struct mlx4_set_port_prio2tc_context
*context
;
851 mailbox
= mlx4_alloc_cmd_mailbox(dev
);
853 return PTR_ERR(mailbox
);
854 context
= mailbox
->buf
;
855 memset(context
, 0, sizeof *context
);
857 for (i
= 0; i
< MLX4_NUM_UP
; i
+= 2)
858 context
->prio2tc
[i
>> 1] = prio2tc
[i
] << 4 | prio2tc
[i
+ 1];
860 in_mod
= MLX4_SET_PORT_PRIO2TC
<< 8 | port
;
861 err
= mlx4_cmd(dev
, mailbox
->dma
, in_mod
, 1, MLX4_CMD_SET_PORT
,
862 MLX4_CMD_TIME_CLASS_B
, MLX4_CMD_NATIVE
);
864 mlx4_free_cmd_mailbox(dev
, mailbox
);
867 EXPORT_SYMBOL(mlx4_SET_PORT_PRIO2TC
);
869 int mlx4_SET_PORT_SCHEDULER(struct mlx4_dev
*dev
, u8 port
, u8
*tc_tx_bw
,
870 u8
*pg
, u16
*ratelimit
)
872 struct mlx4_cmd_mailbox
*mailbox
;
873 struct mlx4_set_port_scheduler_context
*context
;
878 mailbox
= mlx4_alloc_cmd_mailbox(dev
);
880 return PTR_ERR(mailbox
);
881 context
= mailbox
->buf
;
882 memset(context
, 0, sizeof *context
);
884 for (i
= 0; i
< MLX4_NUM_TC
; i
++) {
885 struct mlx4_port_scheduler_tc_cfg_be
*tc
= &context
->tc
[i
];
886 u16 r
= ratelimit
&& ratelimit
[i
] ? ratelimit
[i
] :
887 MLX4_RATELIMIT_DEFAULT
;
889 tc
->pg
= htons(pg
[i
]);
890 tc
->bw_precentage
= htons(tc_tx_bw
[i
]);
892 tc
->max_bw_units
= htons(MLX4_RATELIMIT_UNITS
);
893 tc
->max_bw_value
= htons(r
);
896 in_mod
= MLX4_SET_PORT_SCHEDULER
<< 8 | port
;
897 err
= mlx4_cmd(dev
, mailbox
->dma
, in_mod
, 1, MLX4_CMD_SET_PORT
,
898 MLX4_CMD_TIME_CLASS_B
, MLX4_CMD_NATIVE
);
900 mlx4_free_cmd_mailbox(dev
, mailbox
);
903 EXPORT_SYMBOL(mlx4_SET_PORT_SCHEDULER
);
905 int mlx4_SET_MCAST_FLTR_wrapper(struct mlx4_dev
*dev
, int slave
,
906 struct mlx4_vhcr
*vhcr
,
907 struct mlx4_cmd_mailbox
*inbox
,
908 struct mlx4_cmd_mailbox
*outbox
,
909 struct mlx4_cmd_info
*cmd
)
916 int mlx4_SET_MCAST_FLTR(struct mlx4_dev
*dev
, u8 port
,
917 u64 mac
, u64 clear
, u8 mode
)
919 return mlx4_cmd(dev
, (mac
| (clear
<< 63)), port
, mode
,
920 MLX4_CMD_SET_MCAST_FLTR
, MLX4_CMD_TIME_CLASS_B
,
923 EXPORT_SYMBOL(mlx4_SET_MCAST_FLTR
);
925 int mlx4_SET_VLAN_FLTR_wrapper(struct mlx4_dev
*dev
, int slave
,
926 struct mlx4_vhcr
*vhcr
,
927 struct mlx4_cmd_mailbox
*inbox
,
928 struct mlx4_cmd_mailbox
*outbox
,
929 struct mlx4_cmd_info
*cmd
)
936 int mlx4_common_dump_eth_stats(struct mlx4_dev
*dev
, int slave
,
937 u32 in_mod
, struct mlx4_cmd_mailbox
*outbox
)
939 return mlx4_cmd_box(dev
, 0, outbox
->dma
, in_mod
, 0,
940 MLX4_CMD_DUMP_ETH_STATS
, MLX4_CMD_TIME_CLASS_B
,
944 int mlx4_DUMP_ETH_STATS_wrapper(struct mlx4_dev
*dev
, int slave
,
945 struct mlx4_vhcr
*vhcr
,
946 struct mlx4_cmd_mailbox
*inbox
,
947 struct mlx4_cmd_mailbox
*outbox
,
948 struct mlx4_cmd_info
*cmd
)
950 if (slave
!= dev
->caps
.function
)
952 return mlx4_common_dump_eth_stats(dev
, slave
,
953 vhcr
->in_modifier
, outbox
);
956 void mlx4_set_stats_bitmap(struct mlx4_dev
*dev
, u64
*stats_bitmap
)
958 if (!mlx4_is_mfunc(dev
)) {
963 *stats_bitmap
= (MLX4_STATS_TRAFFIC_COUNTERS_MASK
|
964 MLX4_STATS_TRAFFIC_DROPS_MASK
|
965 MLX4_STATS_PORT_COUNTERS_MASK
);
967 if (mlx4_is_master(dev
))
968 *stats_bitmap
|= MLX4_STATS_ERROR_COUNTERS_MASK
;
970 EXPORT_SYMBOL(mlx4_set_stats_bitmap
);