61d64ebffd56e64b0fa8bf2d0fb69308e3d02c49
2 * Copyright (c) 2004 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
5 * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * OpenIB.org BSD license below:
13 * Redistribution and use in source and binary forms, with or
14 * without modification, are permitted provided that the following
17 * - Redistributions of source code must retain the above
18 * copyright notice, this list of conditions and the following
21 * - Redistributions in binary form must reproduce the above
22 * copyright notice, this list of conditions and the following
23 * disclaimer in the documentation and/or other materials
24 * provided with the distribution.
26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/gfp.h>
37 #include <linux/export.h>
39 #include <linux/mlx4/cmd.h>
40 #include <linux/mlx4/qp.h>
45 void mlx4_qp_event(struct mlx4_dev
*dev
, u32 qpn
, int event_type
)
47 struct mlx4_qp_table
*qp_table
= &mlx4_priv(dev
)->qp_table
;
50 spin_lock(&qp_table
->lock
);
52 qp
= __mlx4_qp_lookup(dev
, qpn
);
54 atomic_inc(&qp
->refcount
);
56 spin_unlock(&qp_table
->lock
);
59 mlx4_dbg(dev
, "Async event for none existent QP %08x\n", qpn
);
63 qp
->event(qp
, event_type
);
65 if (atomic_dec_and_test(&qp
->refcount
))
69 /* used for INIT/CLOSE port logic */
70 static int is_master_qp0(struct mlx4_dev
*dev
, struct mlx4_qp
*qp
, int *real_qp0
, int *proxy_qp0
)
72 /* this procedure is called after we already know we are on the master */
73 /* qp0 is either the proxy qp0, or the real qp0 */
74 u32 pf_proxy_offset
= dev
->phys_caps
.base_proxy_sqpn
+ 8 * mlx4_master_func_num(dev
);
75 *proxy_qp0
= qp
->qpn
>= pf_proxy_offset
&& qp
->qpn
<= pf_proxy_offset
+ 1;
77 *real_qp0
= qp
->qpn
>= dev
->phys_caps
.base_sqpn
&&
78 qp
->qpn
<= dev
->phys_caps
.base_sqpn
+ 1;
80 return *real_qp0
|| *proxy_qp0
;
83 static int __mlx4_qp_modify(struct mlx4_dev
*dev
, struct mlx4_mtt
*mtt
,
84 enum mlx4_qp_state cur_state
, enum mlx4_qp_state new_state
,
85 struct mlx4_qp_context
*context
,
86 enum mlx4_qp_optpar optpar
,
87 int sqd_event
, struct mlx4_qp
*qp
, int native
)
89 static const u16 op
[MLX4_QP_NUM_STATE
][MLX4_QP_NUM_STATE
] = {
90 [MLX4_QP_STATE_RST
] = {
91 [MLX4_QP_STATE_RST
] = MLX4_CMD_2RST_QP
,
92 [MLX4_QP_STATE_ERR
] = MLX4_CMD_2ERR_QP
,
93 [MLX4_QP_STATE_INIT
] = MLX4_CMD_RST2INIT_QP
,
95 [MLX4_QP_STATE_INIT
] = {
96 [MLX4_QP_STATE_RST
] = MLX4_CMD_2RST_QP
,
97 [MLX4_QP_STATE_ERR
] = MLX4_CMD_2ERR_QP
,
98 [MLX4_QP_STATE_INIT
] = MLX4_CMD_INIT2INIT_QP
,
99 [MLX4_QP_STATE_RTR
] = MLX4_CMD_INIT2RTR_QP
,
101 [MLX4_QP_STATE_RTR
] = {
102 [MLX4_QP_STATE_RST
] = MLX4_CMD_2RST_QP
,
103 [MLX4_QP_STATE_ERR
] = MLX4_CMD_2ERR_QP
,
104 [MLX4_QP_STATE_RTS
] = MLX4_CMD_RTR2RTS_QP
,
106 [MLX4_QP_STATE_RTS
] = {
107 [MLX4_QP_STATE_RST
] = MLX4_CMD_2RST_QP
,
108 [MLX4_QP_STATE_ERR
] = MLX4_CMD_2ERR_QP
,
109 [MLX4_QP_STATE_RTS
] = MLX4_CMD_RTS2RTS_QP
,
110 [MLX4_QP_STATE_SQD
] = MLX4_CMD_RTS2SQD_QP
,
112 [MLX4_QP_STATE_SQD
] = {
113 [MLX4_QP_STATE_RST
] = MLX4_CMD_2RST_QP
,
114 [MLX4_QP_STATE_ERR
] = MLX4_CMD_2ERR_QP
,
115 [MLX4_QP_STATE_RTS
] = MLX4_CMD_SQD2RTS_QP
,
116 [MLX4_QP_STATE_SQD
] = MLX4_CMD_SQD2SQD_QP
,
118 [MLX4_QP_STATE_SQER
] = {
119 [MLX4_QP_STATE_RST
] = MLX4_CMD_2RST_QP
,
120 [MLX4_QP_STATE_ERR
] = MLX4_CMD_2ERR_QP
,
121 [MLX4_QP_STATE_RTS
] = MLX4_CMD_SQERR2RTS_QP
,
123 [MLX4_QP_STATE_ERR
] = {
124 [MLX4_QP_STATE_RST
] = MLX4_CMD_2RST_QP
,
125 [MLX4_QP_STATE_ERR
] = MLX4_CMD_2ERR_QP
,
129 struct mlx4_priv
*priv
= mlx4_priv(dev
);
130 struct mlx4_cmd_mailbox
*mailbox
;
136 if (cur_state
>= MLX4_QP_NUM_STATE
|| new_state
>= MLX4_QP_NUM_STATE
||
137 !op
[cur_state
][new_state
])
140 if (op
[cur_state
][new_state
] == MLX4_CMD_2RST_QP
) {
141 ret
= mlx4_cmd(dev
, 0, qp
->qpn
, 2,
142 MLX4_CMD_2RST_QP
, MLX4_CMD_TIME_CLASS_A
, native
);
143 if (mlx4_is_master(dev
) && cur_state
!= MLX4_QP_STATE_ERR
&&
144 cur_state
!= MLX4_QP_STATE_RST
&&
145 is_master_qp0(dev
, qp
, &real_qp0
, &proxy_qp0
)) {
146 port
= (qp
->qpn
& 1) + 1;
148 priv
->mfunc
.master
.qp0_state
[port
].proxy_qp0_active
= 0;
150 priv
->mfunc
.master
.qp0_state
[port
].qp0_active
= 0;
155 mailbox
= mlx4_alloc_cmd_mailbox(dev
);
157 return PTR_ERR(mailbox
);
159 if (cur_state
== MLX4_QP_STATE_RST
&& new_state
== MLX4_QP_STATE_INIT
) {
160 u64 mtt_addr
= mlx4_mtt_addr(dev
, mtt
);
161 context
->mtt_base_addr_h
= mtt_addr
>> 32;
162 context
->mtt_base_addr_l
= cpu_to_be32(mtt_addr
& 0xffffffff);
163 context
->log_page_size
= mtt
->page_shift
- MLX4_ICM_PAGE_SHIFT
;
166 *(__be32
*) mailbox
->buf
= cpu_to_be32(optpar
);
167 memcpy(mailbox
->buf
+ 8, context
, sizeof *context
);
169 ((struct mlx4_qp_context
*) (mailbox
->buf
+ 8))->local_qpn
=
170 cpu_to_be32(qp
->qpn
);
172 ret
= mlx4_cmd(dev
, mailbox
->dma
,
173 qp
->qpn
| (!!sqd_event
<< 31),
174 new_state
== MLX4_QP_STATE_RST
? 2 : 0,
175 op
[cur_state
][new_state
], MLX4_CMD_TIME_CLASS_C
, native
);
177 if (mlx4_is_master(dev
) && is_master_qp0(dev
, qp
, &real_qp0
, &proxy_qp0
)) {
178 port
= (qp
->qpn
& 1) + 1;
179 if (cur_state
!= MLX4_QP_STATE_ERR
&&
180 cur_state
!= MLX4_QP_STATE_RST
&&
181 new_state
== MLX4_QP_STATE_ERR
) {
183 priv
->mfunc
.master
.qp0_state
[port
].proxy_qp0_active
= 0;
185 priv
->mfunc
.master
.qp0_state
[port
].qp0_active
= 0;
186 } else if (new_state
== MLX4_QP_STATE_RTR
) {
188 priv
->mfunc
.master
.qp0_state
[port
].proxy_qp0_active
= 1;
190 priv
->mfunc
.master
.qp0_state
[port
].qp0_active
= 1;
194 mlx4_free_cmd_mailbox(dev
, mailbox
);
198 int mlx4_qp_modify(struct mlx4_dev
*dev
, struct mlx4_mtt
*mtt
,
199 enum mlx4_qp_state cur_state
, enum mlx4_qp_state new_state
,
200 struct mlx4_qp_context
*context
,
201 enum mlx4_qp_optpar optpar
,
202 int sqd_event
, struct mlx4_qp
*qp
)
204 return __mlx4_qp_modify(dev
, mtt
, cur_state
, new_state
, context
,
205 optpar
, sqd_event
, qp
, 0);
207 EXPORT_SYMBOL_GPL(mlx4_qp_modify
);
209 int __mlx4_qp_reserve_range(struct mlx4_dev
*dev
, int cnt
, int align
,
212 struct mlx4_priv
*priv
= mlx4_priv(dev
);
213 struct mlx4_qp_table
*qp_table
= &priv
->qp_table
;
215 *base
= mlx4_bitmap_alloc_range(&qp_table
->bitmap
, cnt
, align
);
222 int mlx4_qp_reserve_range(struct mlx4_dev
*dev
, int cnt
, int align
, int *base
)
228 if (mlx4_is_mfunc(dev
)) {
229 set_param_l(&in_param
, cnt
);
230 set_param_h(&in_param
, align
);
231 err
= mlx4_cmd_imm(dev
, in_param
, &out_param
,
232 RES_QP
, RES_OP_RESERVE
,
234 MLX4_CMD_TIME_CLASS_A
, MLX4_CMD_WRAPPED
);
238 *base
= get_param_l(&out_param
);
241 return __mlx4_qp_reserve_range(dev
, cnt
, align
, base
);
243 EXPORT_SYMBOL_GPL(mlx4_qp_reserve_range
);
245 void __mlx4_qp_release_range(struct mlx4_dev
*dev
, int base_qpn
, int cnt
)
247 struct mlx4_priv
*priv
= mlx4_priv(dev
);
248 struct mlx4_qp_table
*qp_table
= &priv
->qp_table
;
250 if (mlx4_is_qp_reserved(dev
, (u32
) base_qpn
))
252 mlx4_bitmap_free_range(&qp_table
->bitmap
, base_qpn
, cnt
, MLX4_USE_RR
);
255 void mlx4_qp_release_range(struct mlx4_dev
*dev
, int base_qpn
, int cnt
)
260 if (mlx4_is_mfunc(dev
)) {
261 set_param_l(&in_param
, base_qpn
);
262 set_param_h(&in_param
, cnt
);
263 err
= mlx4_cmd(dev
, in_param
, RES_QP
, RES_OP_RESERVE
,
265 MLX4_CMD_TIME_CLASS_A
, MLX4_CMD_WRAPPED
);
267 mlx4_warn(dev
, "Failed to release qp range"
268 " base:%d cnt:%d\n", base_qpn
, cnt
);
271 __mlx4_qp_release_range(dev
, base_qpn
, cnt
);
273 EXPORT_SYMBOL_GPL(mlx4_qp_release_range
);
275 int __mlx4_qp_alloc_icm(struct mlx4_dev
*dev
, int qpn
)
277 struct mlx4_priv
*priv
= mlx4_priv(dev
);
278 struct mlx4_qp_table
*qp_table
= &priv
->qp_table
;
281 err
= mlx4_table_get(dev
, &qp_table
->qp_table
, qpn
);
285 err
= mlx4_table_get(dev
, &qp_table
->auxc_table
, qpn
);
289 err
= mlx4_table_get(dev
, &qp_table
->altc_table
, qpn
);
293 err
= mlx4_table_get(dev
, &qp_table
->rdmarc_table
, qpn
);
297 err
= mlx4_table_get(dev
, &qp_table
->cmpt_table
, qpn
);
304 mlx4_table_put(dev
, &qp_table
->rdmarc_table
, qpn
);
307 mlx4_table_put(dev
, &qp_table
->altc_table
, qpn
);
310 mlx4_table_put(dev
, &qp_table
->auxc_table
, qpn
);
313 mlx4_table_put(dev
, &qp_table
->qp_table
, qpn
);
319 static int mlx4_qp_alloc_icm(struct mlx4_dev
*dev
, int qpn
)
323 if (mlx4_is_mfunc(dev
)) {
324 set_param_l(¶m
, qpn
);
325 return mlx4_cmd_imm(dev
, param
, ¶m
, RES_QP
, RES_OP_MAP_ICM
,
326 MLX4_CMD_ALLOC_RES
, MLX4_CMD_TIME_CLASS_A
,
329 return __mlx4_qp_alloc_icm(dev
, qpn
);
332 void __mlx4_qp_free_icm(struct mlx4_dev
*dev
, int qpn
)
334 struct mlx4_priv
*priv
= mlx4_priv(dev
);
335 struct mlx4_qp_table
*qp_table
= &priv
->qp_table
;
337 mlx4_table_put(dev
, &qp_table
->cmpt_table
, qpn
);
338 mlx4_table_put(dev
, &qp_table
->rdmarc_table
, qpn
);
339 mlx4_table_put(dev
, &qp_table
->altc_table
, qpn
);
340 mlx4_table_put(dev
, &qp_table
->auxc_table
, qpn
);
341 mlx4_table_put(dev
, &qp_table
->qp_table
, qpn
);
344 static void mlx4_qp_free_icm(struct mlx4_dev
*dev
, int qpn
)
348 if (mlx4_is_mfunc(dev
)) {
349 set_param_l(&in_param
, qpn
);
350 if (mlx4_cmd(dev
, in_param
, RES_QP
, RES_OP_MAP_ICM
,
351 MLX4_CMD_FREE_RES
, MLX4_CMD_TIME_CLASS_A
,
353 mlx4_warn(dev
, "Failed to free icm of qp:%d\n", qpn
);
355 __mlx4_qp_free_icm(dev
, qpn
);
358 int mlx4_qp_alloc(struct mlx4_dev
*dev
, int qpn
, struct mlx4_qp
*qp
)
360 struct mlx4_priv
*priv
= mlx4_priv(dev
);
361 struct mlx4_qp_table
*qp_table
= &priv
->qp_table
;
369 err
= mlx4_qp_alloc_icm(dev
, qpn
);
373 spin_lock_irq(&qp_table
->lock
);
374 err
= radix_tree_insert(&dev
->qp_table_tree
, qp
->qpn
&
375 (dev
->caps
.num_qps
- 1), qp
);
376 spin_unlock_irq(&qp_table
->lock
);
380 atomic_set(&qp
->refcount
, 1);
381 init_completion(&qp
->free
);
386 mlx4_qp_free_icm(dev
, qpn
);
390 EXPORT_SYMBOL_GPL(mlx4_qp_alloc
);
392 void mlx4_qp_remove(struct mlx4_dev
*dev
, struct mlx4_qp
*qp
)
394 struct mlx4_qp_table
*qp_table
= &mlx4_priv(dev
)->qp_table
;
397 spin_lock_irqsave(&qp_table
->lock
, flags
);
398 radix_tree_delete(&dev
->qp_table_tree
, qp
->qpn
& (dev
->caps
.num_qps
- 1));
399 spin_unlock_irqrestore(&qp_table
->lock
, flags
);
401 EXPORT_SYMBOL_GPL(mlx4_qp_remove
);
403 void mlx4_qp_free(struct mlx4_dev
*dev
, struct mlx4_qp
*qp
)
405 if (atomic_dec_and_test(&qp
->refcount
))
407 wait_for_completion(&qp
->free
);
409 mlx4_qp_free_icm(dev
, qp
->qpn
);
411 EXPORT_SYMBOL_GPL(mlx4_qp_free
);
413 static int mlx4_CONF_SPECIAL_QP(struct mlx4_dev
*dev
, u32 base_qpn
)
415 return mlx4_cmd(dev
, 0, base_qpn
, 0, MLX4_CMD_CONF_SPECIAL_QP
,
416 MLX4_CMD_TIME_CLASS_B
, MLX4_CMD_NATIVE
);
419 int mlx4_init_qp_table(struct mlx4_dev
*dev
)
421 struct mlx4_qp_table
*qp_table
= &mlx4_priv(dev
)->qp_table
;
423 int reserved_from_top
= 0;
426 spin_lock_init(&qp_table
->lock
);
427 INIT_RADIX_TREE(&dev
->qp_table_tree
, GFP_ATOMIC
);
428 if (mlx4_is_slave(dev
))
432 * We reserve 2 extra QPs per port for the special QPs. The
433 * block of special QPs must be aligned to a multiple of 8, so
436 * We also reserve the MSB of the 24-bit QP number to indicate
437 * that a QP is an XRC QP.
439 dev
->phys_caps
.base_sqpn
=
440 ALIGN(dev
->caps
.reserved_qps_cnt
[MLX4_QP_REGION_FW
], 8);
443 int sort
[MLX4_NUM_QP_REGION
];
445 int last_base
= dev
->caps
.num_qps
;
447 for (i
= 1; i
< MLX4_NUM_QP_REGION
; ++i
)
450 for (i
= MLX4_NUM_QP_REGION
; i
> 0; --i
) {
451 for (j
= 2; j
< i
; ++j
) {
452 if (dev
->caps
.reserved_qps_cnt
[sort
[j
]] >
453 dev
->caps
.reserved_qps_cnt
[sort
[j
- 1]]) {
455 sort
[j
] = sort
[j
- 1];
461 for (i
= 1; i
< MLX4_NUM_QP_REGION
; ++i
) {
462 last_base
-= dev
->caps
.reserved_qps_cnt
[sort
[i
]];
463 dev
->caps
.reserved_qps_base
[sort
[i
]] = last_base
;
465 dev
->caps
.reserved_qps_cnt
[sort
[i
]];
470 /* Reserve 8 real SQPs in both native and SRIOV modes.
471 * In addition, in SRIOV mode, reserve 8 proxy SQPs per function
472 * (for all PFs and VFs), and 8 corresponding tunnel QPs.
473 * Each proxy SQP works opposite its own tunnel QP.
475 * The QPs are arranged as follows:
477 * b. All the proxy SQPs (8 per function)
478 * c. All the tunnel QPs (8 per function)
481 err
= mlx4_bitmap_init(&qp_table
->bitmap
, dev
->caps
.num_qps
,
482 (1 << 23) - 1, mlx4_num_reserved_sqps(dev
),
487 if (mlx4_is_mfunc(dev
)) {
489 dev
->phys_caps
.base_proxy_sqpn
= dev
->phys_caps
.base_sqpn
+ 8;
490 dev
->phys_caps
.base_tunnel_sqpn
= dev
->phys_caps
.base_sqpn
+ 8 + 8 * MLX4_MFUNC_MAX
;
492 /* In mfunc, calculate proxy and tunnel qp offsets for the PF here,
493 * since the PF does not call mlx4_slave_caps */
494 dev
->caps
.qp0_tunnel
= kcalloc(dev
->caps
.num_ports
, sizeof (u32
), GFP_KERNEL
);
495 dev
->caps
.qp0_proxy
= kcalloc(dev
->caps
.num_ports
, sizeof (u32
), GFP_KERNEL
);
496 dev
->caps
.qp1_tunnel
= kcalloc(dev
->caps
.num_ports
, sizeof (u32
), GFP_KERNEL
);
497 dev
->caps
.qp1_proxy
= kcalloc(dev
->caps
.num_ports
, sizeof (u32
), GFP_KERNEL
);
499 if (!dev
->caps
.qp0_tunnel
|| !dev
->caps
.qp0_proxy
||
500 !dev
->caps
.qp1_tunnel
|| !dev
->caps
.qp1_proxy
) {
505 for (k
= 0; k
< dev
->caps
.num_ports
; k
++) {
506 dev
->caps
.qp0_proxy
[k
] = dev
->phys_caps
.base_proxy_sqpn
+
507 8 * mlx4_master_func_num(dev
) + k
;
508 dev
->caps
.qp0_tunnel
[k
] = dev
->caps
.qp0_proxy
[k
] + 8 * MLX4_MFUNC_MAX
;
509 dev
->caps
.qp1_proxy
[k
] = dev
->phys_caps
.base_proxy_sqpn
+
510 8 * mlx4_master_func_num(dev
) + MLX4_MAX_PORTS
+ k
;
511 dev
->caps
.qp1_tunnel
[k
] = dev
->caps
.qp1_proxy
[k
] + 8 * MLX4_MFUNC_MAX
;
516 err
= mlx4_CONF_SPECIAL_QP(dev
, dev
->phys_caps
.base_sqpn
);
522 kfree(dev
->caps
.qp0_tunnel
);
523 kfree(dev
->caps
.qp0_proxy
);
524 kfree(dev
->caps
.qp1_tunnel
);
525 kfree(dev
->caps
.qp1_proxy
);
526 dev
->caps
.qp0_tunnel
= dev
->caps
.qp0_proxy
=
527 dev
->caps
.qp1_tunnel
= dev
->caps
.qp1_proxy
= NULL
;
531 void mlx4_cleanup_qp_table(struct mlx4_dev
*dev
)
533 if (mlx4_is_slave(dev
))
536 mlx4_CONF_SPECIAL_QP(dev
, 0);
537 mlx4_bitmap_cleanup(&mlx4_priv(dev
)->qp_table
.bitmap
);
540 int mlx4_qp_query(struct mlx4_dev
*dev
, struct mlx4_qp
*qp
,
541 struct mlx4_qp_context
*context
)
543 struct mlx4_cmd_mailbox
*mailbox
;
546 mailbox
= mlx4_alloc_cmd_mailbox(dev
);
548 return PTR_ERR(mailbox
);
550 err
= mlx4_cmd_box(dev
, 0, mailbox
->dma
, qp
->qpn
, 0,
551 MLX4_CMD_QUERY_QP
, MLX4_CMD_TIME_CLASS_A
,
554 memcpy(context
, mailbox
->buf
+ 8, sizeof *context
);
556 mlx4_free_cmd_mailbox(dev
, mailbox
);
559 EXPORT_SYMBOL_GPL(mlx4_qp_query
);
561 int mlx4_qp_to_ready(struct mlx4_dev
*dev
, struct mlx4_mtt
*mtt
,
562 struct mlx4_qp_context
*context
,
563 struct mlx4_qp
*qp
, enum mlx4_qp_state
*qp_state
)
567 enum mlx4_qp_state states
[] = {
574 for (i
= 0; i
< ARRAY_SIZE(states
) - 1; i
++) {
575 context
->flags
&= cpu_to_be32(~(0xf << 28));
576 context
->flags
|= cpu_to_be32(states
[i
+ 1] << 28);
577 err
= mlx4_qp_modify(dev
, mtt
, states
[i
], states
[i
+ 1],
580 mlx4_err(dev
, "Failed to bring QP to state: "
581 "%d with error: %d\n",
586 *qp_state
= states
[i
+ 1];
591 EXPORT_SYMBOL_GPL(mlx4_qp_to_ready
);
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