drivers/net/ethernet/mellanox/mlx5/core/en.h

   1 /*
   2  * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32 #ifndef __MLX5_EN_H__
  33 #define __MLX5_EN_H__
  34
  35 #include <linux/if_vlan.h>
  36 #include <linux/etherdevice.h>
  37 #include <linux/timecounter.h>
  38 #include <linux/net_tstamp.h>
  39 #include <linux/ptp_clock_kernel.h>
  40 #include <linux/mlx5/driver.h>
  41 #include <linux/mlx5/qp.h>
  42 #include <linux/mlx5/cq.h>
  43 #include <linux/mlx5/port.h>
  44 #include <linux/mlx5/vport.h>
  45 #include <linux/mlx5/transobj.h>
  46 #include <linux/rhashtable.h>
  47 #include "wq.h"
  48 #include "mlx5_core.h"
  49
  50 #define MLX5E_MAX_NUM_TC        8
  51
  52 #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE                0x6
  53 #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE                0xa
  54 #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE                0xd
  55
  56 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE                0x1
  57 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE                0xa
  58 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE                0xd
  59
  60 #define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ                 (64 * 1024)
  61 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC      0x10
  62 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS      0x20
  63 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC      0x10
  64 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS      0x20
  65 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES                0x80
  66
  67 #define MLX5E_LOG_INDIR_RQT_SIZE       0x7
  68 #define MLX5E_INDIR_RQT_SIZE           BIT(MLX5E_LOG_INDIR_RQT_SIZE)
  69 #define MLX5E_MAX_NUM_CHANNELS         (MLX5E_INDIR_RQT_SIZE >> 1)
  70 #define MLX5E_TX_CQ_POLL_BUDGET        128
  71 #define MLX5E_UPDATE_STATS_INTERVAL    200 /* msecs */
  72 #define MLX5E_SQ_BF_BUDGET             16
  73
  74 #define MLX5E_NUM_MAIN_GROUPS 9
  75
  76 #ifdef CONFIG_MLX5_CORE_EN_DCB
  77 #define MLX5E_MAX_BW_ALLOC 100 /* Max percentage of BW allocation */
  78 #define MLX5E_MIN_BW_ALLOC 1   /* Min percentage of BW allocation */
  79 #endif
  80
  81 static const char vport_strings[][ETH_GSTRING_LEN] = {
  82         /* vport statistics */
  83         "rx_packets",
  84         "rx_bytes",
  85         "tx_packets",
  86         "tx_bytes",
  87         "rx_error_packets",
  88         "rx_error_bytes",
  89         "tx_error_packets",
  90         "tx_error_bytes",
  91         "rx_unicast_packets",
  92         "rx_unicast_bytes",
  93         "tx_unicast_packets",
  94         "tx_unicast_bytes",
  95         "rx_multicast_packets",
  96         "rx_multicast_bytes",
  97         "tx_multicast_packets",
  98         "tx_multicast_bytes",
  99         "rx_broadcast_packets",
 100         "rx_broadcast_bytes",
 101         "tx_broadcast_packets",
 102         "tx_broadcast_bytes",
 103
 104         /* SW counters */
 105         "tso_packets",
 106         "tso_bytes",
 107         "tso_inner_packets",
 108         "tso_inner_bytes",
 109         "lro_packets",
 110         "lro_bytes",
 111         "rx_csum_good",
 112         "rx_csum_none",
 113         "rx_csum_sw",
 114         "tx_csum_offload",
 115         "tx_csum_inner",
 116         "tx_queue_stopped",
 117         "tx_queue_wake",
 118         "tx_queue_dropped",
 119         "rx_wqe_err",
 120 };
 121
 122 struct mlx5e_vport_stats {
 123         /* HW counters */
 124         u64 rx_packets;
 125         u64 rx_bytes;
 126         u64 tx_packets;
 127         u64 tx_bytes;
 128         u64 rx_error_packets;
 129         u64 rx_error_bytes;
 130         u64 tx_error_packets;
 131         u64 tx_error_bytes;
 132         u64 rx_unicast_packets;
 133         u64 rx_unicast_bytes;
 134         u64 tx_unicast_packets;
 135         u64 tx_unicast_bytes;
 136         u64 rx_multicast_packets;
 137         u64 rx_multicast_bytes;
 138         u64 tx_multicast_packets;
 139         u64 tx_multicast_bytes;
 140         u64 rx_broadcast_packets;
 141         u64 rx_broadcast_bytes;
 142         u64 tx_broadcast_packets;
 143         u64 tx_broadcast_bytes;
 144
 145         /* SW counters */
 146         u64 tso_packets;
 147         u64 tso_bytes;
 148         u64 tso_inner_packets;
 149         u64 tso_inner_bytes;
 150         u64 lro_packets;
 151         u64 lro_bytes;
 152         u64 rx_csum_good;
 153         u64 rx_csum_none;
 154         u64 rx_csum_sw;
 155         u64 tx_csum_offload;
 156         u64 tx_csum_inner;
 157         u64 tx_queue_stopped;
 158         u64 tx_queue_wake;
 159         u64 tx_queue_dropped;
 160         u64 rx_wqe_err;
 161
 162 #define NUM_VPORT_COUNTERS     35
 163 };
 164
 165 static const char pport_strings[][ETH_GSTRING_LEN] = {
 166         /* IEEE802.3 counters */
 167         "frames_tx",
 168         "frames_rx",
 169         "check_seq_err",
 170         "alignment_err",
 171         "octets_tx",
 172         "octets_received",
 173         "multicast_xmitted",
 174         "broadcast_xmitted",
 175         "multicast_rx",
 176         "broadcast_rx",
 177         "in_range_len_errors",
 178         "out_of_range_len",
 179         "too_long_errors",
 180         "symbol_err",
 181         "mac_control_tx",
 182         "mac_control_rx",
 183         "unsupported_op_rx",
 184         "pause_ctrl_rx",
 185         "pause_ctrl_tx",
 186
 187         /* RFC2863 counters */
 188         "in_octets",
 189         "in_ucast_pkts",
 190         "in_discards",
 191         "in_errors",
 192         "in_unknown_protos",
 193         "out_octets",
 194         "out_ucast_pkts",
 195         "out_discards",
 196         "out_errors",
 197         "in_multicast_pkts",
 198         "in_broadcast_pkts",
 199         "out_multicast_pkts",
 200         "out_broadcast_pkts",
 201
 202         /* RFC2819 counters */
 203         "drop_events",
 204         "octets",
 205         "pkts",
 206         "broadcast_pkts",
 207         "multicast_pkts",
 208         "crc_align_errors",
 209         "undersize_pkts",
 210         "oversize_pkts",
 211         "fragments",
 212         "jabbers",
 213         "collisions",
 214         "p64octets",
 215         "p65to127octets",
 216         "p128to255octets",
 217         "p256to511octets",
 218         "p512to1023octets",
 219         "p1024to1518octets",
 220         "p1519to2047octets",
 221         "p2048to4095octets",
 222         "p4096to8191octets",
 223         "p8192to10239octets",
 224 };
 225
 226 #define NUM_IEEE_802_3_COUNTERS         19
 227 #define NUM_RFC_2863_COUNTERS           13
 228 #define NUM_RFC_2819_COUNTERS           21
 229 #define NUM_PPORT_COUNTERS              (NUM_IEEE_802_3_COUNTERS + \
 230                                          NUM_RFC_2863_COUNTERS + \
 231                                          NUM_RFC_2819_COUNTERS)
 232
 233 struct mlx5e_pport_stats {
 234         __be64 IEEE_802_3_counters[NUM_IEEE_802_3_COUNTERS];
 235         __be64 RFC_2863_counters[NUM_RFC_2863_COUNTERS];
 236         __be64 RFC_2819_counters[NUM_RFC_2819_COUNTERS];
 237 };
 238
 239 static const char qcounter_stats_strings[][ETH_GSTRING_LEN] = {
 240         "rx_out_of_buffer",
 241 };
 242
 243 struct mlx5e_qcounter_stats {
 244         u32 rx_out_of_buffer;
 245 #define NUM_Q_COUNTERS 1
 246 };
 247
 248 static const char rq_stats_strings[][ETH_GSTRING_LEN] = {
 249         "packets",
 250         "bytes",
 251         "csum_none",
 252         "csum_sw",
 253         "lro_packets",
 254         "lro_bytes",
 255         "wqe_err"
 256 };
 257
 258 struct mlx5e_rq_stats {
 259         u64 packets;
 260         u64 bytes;
 261         u64 csum_none;
 262         u64 csum_sw;
 263         u64 lro_packets;
 264         u64 lro_bytes;
 265         u64 wqe_err;
 266 #define NUM_RQ_STATS 7
 267 };
 268
 269 static const char sq_stats_strings[][ETH_GSTRING_LEN] = {
 270         "packets",
 271         "bytes",
 272         "tso_packets",
 273         "tso_bytes",
 274         "tso_inner_packets",
 275         "tso_inner_bytes",
 276         "csum_offload_inner",
 277         "nop",
 278         "csum_offload_none",
 279         "stopped",
 280         "wake",
 281         "dropped",
 282 };
 283
 284 struct mlx5e_sq_stats {
 285         /* commonly accessed in data path */
 286         u64 packets;
 287         u64 bytes;
 288         u64 tso_packets;
 289         u64 tso_bytes;
 290         u64 tso_inner_packets;
 291         u64 tso_inner_bytes;
 292         u64 csum_offload_inner;
 293         u64 nop;
 294         /* less likely accessed in data path */
 295         u64 csum_offload_none;
 296         u64 stopped;
 297         u64 wake;
 298         u64 dropped;
 299 #define NUM_SQ_STATS 12
 300 };
 301
 302 struct mlx5e_stats {
 303         struct mlx5e_vport_stats   vport;
 304         struct mlx5e_pport_stats   pport;
 305         struct mlx5e_qcounter_stats qcnt;
 306 };
 307
 308 struct mlx5e_params {
 309         u8  log_sq_size;
 310         u8  log_rq_size;
 311         u16 num_channels;
 312         u8  num_tc;
 313         u16 rx_cq_moderation_usec;
 314         u16 rx_cq_moderation_pkts;
 315         u16 tx_cq_moderation_usec;
 316         u16 tx_cq_moderation_pkts;
 317         u16 min_rx_wqes;
 318         bool lro_en;
 319         u32 lro_wqe_sz;
 320         u16 tx_max_inline;
 321         u8  rss_hfunc;
 322         u8  toeplitz_hash_key[40];
 323         u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE];
 324 #ifdef CONFIG_MLX5_CORE_EN_DCB
 325         struct ieee_ets ets;
 326 #endif
 327 };
 328
 329 struct mlx5e_tstamp {
 330         rwlock_t                   lock;
 331         struct cyclecounter        cycles;
 332         struct timecounter         clock;
 333         struct hwtstamp_config     hwtstamp_config;
 334         u32                        nominal_c_mult;
 335         unsigned long              overflow_period;
 336         struct delayed_work        overflow_work;
 337         struct mlx5_core_dev      *mdev;
 338         struct ptp_clock          *ptp;
 339         struct ptp_clock_info      ptp_info;
 340 };
 341
 342 enum {
 343         MLX5E_RQ_STATE_POST_WQES_ENABLE,
 344 };
 345
 346 struct mlx5e_cq {
 347         /* data path - accessed per cqe */
 348         struct mlx5_cqwq           wq;
 349
 350         /* data path - accessed per napi poll */
 351         struct napi_struct        *napi;
 352         struct mlx5_core_cq        mcq;
 353         struct mlx5e_channel      *channel;
 354         struct mlx5e_priv         *priv;
 355
 356         /* control */
 357         struct mlx5_wq_ctrl        wq_ctrl;
 358 } ____cacheline_aligned_in_smp;
 359
 360 struct mlx5e_rq {
 361         /* data path */
 362         struct mlx5_wq_ll      wq;
 363         u32                    wqe_sz;
 364         struct sk_buff       **skb;
 365
 366         struct device         *pdev;
 367         struct net_device     *netdev;
 368         struct mlx5e_tstamp   *tstamp;
 369         struct mlx5e_rq_stats  stats;
 370         struct mlx5e_cq        cq;
 371
 372         unsigned long          state;
 373         int                    ix;
 374
 375         /* control */
 376         struct mlx5_wq_ctrl    wq_ctrl;
 377         u32                    rqn;
 378         struct mlx5e_channel  *channel;
 379         struct mlx5e_priv     *priv;
 380 } ____cacheline_aligned_in_smp;
 381
 382 struct mlx5e_tx_wqe_info {
 383         u32 num_bytes;
 384         u8  num_wqebbs;
 385         u8  num_dma;
 386 };
 387
 388 enum mlx5e_dma_map_type {
 389         MLX5E_DMA_MAP_SINGLE,
 390         MLX5E_DMA_MAP_PAGE
 391 };
 392
 393 struct mlx5e_sq_dma {
 394         dma_addr_t              addr;
 395         u32                     size;
 396         enum mlx5e_dma_map_type type;
 397 };
 398
 399 enum {
 400         MLX5E_SQ_STATE_WAKE_TXQ_ENABLE,
 401         MLX5E_SQ_STATE_BF_ENABLE,
 402 };
 403
 404 struct mlx5e_sq {
 405         /* data path */
 406
 407         /* dirtied @completion */
 408         u16                        cc;
 409         u32                        dma_fifo_cc;
 410
 411         /* dirtied @xmit */
 412         u16                        pc ____cacheline_aligned_in_smp;
 413         u32                        dma_fifo_pc;
 414         u16                        bf_offset;
 415         u16                        prev_cc;
 416         u8                         bf_budget;
 417         struct mlx5e_sq_stats      stats;
 418
 419         struct mlx5e_cq            cq;
 420
 421         /* pointers to per packet info: write@xmit, read@completion */
 422         struct sk_buff           **skb;
 423         struct mlx5e_sq_dma       *dma_fifo;
 424         struct mlx5e_tx_wqe_info  *wqe_info;
 425
 426         /* read only */
 427         struct mlx5_wq_cyc         wq;
 428         u32                        dma_fifo_mask;
 429         void __iomem              *uar_map;
 430         struct netdev_queue       *txq;
 431         u32                        sqn;
 432         u16                        bf_buf_size;
 433         u16                        max_inline;
 434         u16                        edge;
 435         struct device             *pdev;
 436         struct mlx5e_tstamp       *tstamp;
 437         __be32                     mkey_be;
 438         unsigned long              state;
 439
 440         /* control path */
 441         struct mlx5_wq_ctrl        wq_ctrl;
 442         struct mlx5_uar            uar;
 443         struct mlx5e_channel      *channel;
 444         int                        tc;
 445 } ____cacheline_aligned_in_smp;
 446
 447 static inline bool mlx5e_sq_has_room_for(struct mlx5e_sq *sq, u16 n)
 448 {
 449         return (((sq->wq.sz_m1 & (sq->cc - sq->pc)) >= n) ||
 450                 (sq->cc  == sq->pc));
 451 }
 452
 453 enum channel_flags {
 454         MLX5E_CHANNEL_NAPI_SCHED = 1,
 455 };
 456
 457 struct mlx5e_channel {
 458         /* data path */
 459         struct mlx5e_rq            rq;
 460         struct mlx5e_sq            sq[MLX5E_MAX_NUM_TC];
 461         struct napi_struct         napi;
 462         struct device             *pdev;
 463         struct net_device         *netdev;
 464         __be32                     mkey_be;
 465         u8                         num_tc;
 466         unsigned long              flags;
 467
 468         /* control */
 469         struct mlx5e_priv         *priv;
 470         int                        ix;
 471         int                        cpu;
 472 };
 473
 474 enum mlx5e_traffic_types {
 475         MLX5E_TT_IPV4_TCP,
 476         MLX5E_TT_IPV6_TCP,
 477         MLX5E_TT_IPV4_UDP,
 478         MLX5E_TT_IPV6_UDP,
 479         MLX5E_TT_IPV4_IPSEC_AH,
 480         MLX5E_TT_IPV6_IPSEC_AH,
 481         MLX5E_TT_IPV4_IPSEC_ESP,
 482         MLX5E_TT_IPV6_IPSEC_ESP,
 483         MLX5E_TT_IPV4,
 484         MLX5E_TT_IPV6,
 485         MLX5E_TT_ANY,
 486         MLX5E_NUM_TT,
 487 };
 488
 489 #define IS_HASHING_TT(tt) (tt != MLX5E_TT_ANY)
 490
 491 enum mlx5e_rqt_ix {
 492         MLX5E_INDIRECTION_RQT,
 493         MLX5E_SINGLE_RQ_RQT,
 494         MLX5E_NUM_RQT,
 495 };
 496
 497 struct mlx5e_eth_addr_info {
 498         u8  addr[ETH_ALEN + 2];
 499         u32 tt_vec;
 500         struct mlx5_flow_rule *ft_rule[MLX5E_NUM_TT];
 501 };
 502
 503 #define MLX5E_ETH_ADDR_HASH_SIZE (1 << BITS_PER_BYTE)
 504
 505 struct mlx5e_eth_addr_db {
 506         struct hlist_head          netdev_uc[MLX5E_ETH_ADDR_HASH_SIZE];
 507         struct hlist_head          netdev_mc[MLX5E_ETH_ADDR_HASH_SIZE];
 508         struct mlx5e_eth_addr_info broadcast;
 509         struct mlx5e_eth_addr_info allmulti;
 510         struct mlx5e_eth_addr_info promisc;
 511         bool                       broadcast_enabled;
 512         bool                       allmulti_enabled;
 513         bool                       promisc_enabled;
 514 };
 515
 516 enum {
 517         MLX5E_STATE_ASYNC_EVENTS_ENABLE,
 518         MLX5E_STATE_OPENED,
 519         MLX5E_STATE_DESTROYING,
 520 };
 521
 522 struct mlx5e_vlan_db {
 523         unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
 524         struct mlx5_flow_rule   *active_vlans_rule[VLAN_N_VID];
 525         struct mlx5_flow_rule   *untagged_rule;
 526         struct mlx5_flow_rule   *any_vlan_rule;
 527         bool          filter_disabled;
 528 };
 529
 530 struct mlx5e_vxlan_db {
 531         spinlock_t                      lock; /* protect vxlan table */
 532         struct radix_tree_root          tree;
 533 };
 534
 535 struct mlx5e_flow_table {
 536         int num_groups;
 537         struct mlx5_flow_table          *t;
 538         struct mlx5_flow_group          **g;
 539 };
 540
 541 struct mlx5e_tc_flow_table {
 542         struct mlx5_flow_table          *t;
 543
 544         struct rhashtable_params        ht_params;
 545         struct rhashtable               ht;
 546 };
 547
 548 struct mlx5e_flow_tables {
 549         struct mlx5_flow_namespace      *ns;
 550         struct mlx5e_tc_flow_table      tc;
 551         struct mlx5e_flow_table         vlan;
 552         struct mlx5e_flow_table         main;
 553 };
 554
 555 struct mlx5e_priv {
 556         /* priv data path fields - start */
 557         struct mlx5e_sq            **txq_to_sq_map;
 558         int channeltc_to_txq_map[MLX5E_MAX_NUM_CHANNELS][MLX5E_MAX_NUM_TC];
 559         /* priv data path fields - end */
 560
 561         unsigned long              state;
 562         struct mutex               state_lock; /* Protects Interface state */
 563         struct mlx5_uar            cq_uar;
 564         u32                        pdn;
 565         u32                        tdn;
 566         struct mlx5_core_mkey      mkey;
 567         struct mlx5e_rq            drop_rq;
 568
 569         struct mlx5e_channel     **channel;
 570         u32                        tisn[MLX5E_MAX_NUM_TC];
 571         u32                        rqtn[MLX5E_NUM_RQT];
 572         u32                        tirn[MLX5E_NUM_TT];
 573
 574         struct mlx5e_flow_tables   fts;
 575         struct mlx5e_eth_addr_db   eth_addr;
 576         struct mlx5e_vlan_db       vlan;
 577         struct mlx5e_vxlan_db      vxlan;
 578
 579         struct mlx5e_params        params;
 580         struct work_struct         update_carrier_work;
 581         struct work_struct         set_rx_mode_work;
 582         struct delayed_work        update_stats_work;
 583
 584         struct mlx5_core_dev      *mdev;
 585         struct net_device         *netdev;
 586         struct mlx5e_stats         stats;
 587         struct mlx5e_tstamp        tstamp;
 588         u16 q_counter;
 589 };
 590
 591 #define MLX5E_NET_IP_ALIGN 2
 592
 593 struct mlx5e_tx_wqe {
 594         struct mlx5_wqe_ctrl_seg ctrl;
 595         struct mlx5_wqe_eth_seg  eth;
 596 };
 597
 598 struct mlx5e_rx_wqe {
 599         struct mlx5_wqe_srq_next_seg  next;
 600         struct mlx5_wqe_data_seg      data;
 601 };
 602
 603 enum mlx5e_link_mode {
 604         MLX5E_1000BASE_CX_SGMII  = 0,
 605         MLX5E_1000BASE_KX        = 1,
 606         MLX5E_10GBASE_CX4        = 2,
 607         MLX5E_10GBASE_KX4        = 3,
 608         MLX5E_10GBASE_KR         = 4,
 609         MLX5E_20GBASE_KR2        = 5,
 610         MLX5E_40GBASE_CR4        = 6,
 611         MLX5E_40GBASE_KR4        = 7,
 612         MLX5E_56GBASE_R4         = 8,
 613         MLX5E_10GBASE_CR         = 12,
 614         MLX5E_10GBASE_SR         = 13,
 615         MLX5E_10GBASE_ER         = 14,
 616         MLX5E_40GBASE_SR4        = 15,
 617         MLX5E_40GBASE_LR4        = 16,
 618         MLX5E_100GBASE_CR4       = 20,
 619         MLX5E_100GBASE_SR4       = 21,
 620         MLX5E_100GBASE_KR4       = 22,
 621         MLX5E_100GBASE_LR4       = 23,
 622         MLX5E_100BASE_TX         = 24,
 623         MLX5E_100BASE_T          = 25,
 624         MLX5E_10GBASE_T          = 26,
 625         MLX5E_25GBASE_CR         = 27,
 626         MLX5E_25GBASE_KR         = 28,
 627         MLX5E_25GBASE_SR         = 29,
 628         MLX5E_50GBASE_CR2        = 30,
 629         MLX5E_50GBASE_KR2        = 31,
 630         MLX5E_LINK_MODES_NUMBER,
 631 };
 632
 633 #define MLX5E_PROT_MASK(link_mode) (1 << link_mode)
 634
 635 void mlx5e_send_nop(struct mlx5e_sq *sq, bool notify_hw);
 636 u16 mlx5e_select_queue(struct net_device *dev, struct sk_buff *skb,
 637                        void *accel_priv, select_queue_fallback_t fallback);
 638 netdev_tx_t mlx5e_xmit(struct sk_buff *skb, struct net_device *dev);
 639
 640 void mlx5e_completion_event(struct mlx5_core_cq *mcq);
 641 void mlx5e_cq_error_event(struct mlx5_core_cq *mcq, enum mlx5_event event);
 642 int mlx5e_napi_poll(struct napi_struct *napi, int budget);
 643 bool mlx5e_poll_tx_cq(struct mlx5e_cq *cq, int napi_budget);
 644 int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget);
 645 bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq);
 646 struct mlx5_cqe64 *mlx5e_get_cqe(struct mlx5e_cq *cq);
 647
 648 void mlx5e_update_stats(struct mlx5e_priv *priv);
 649
 650 int mlx5e_create_flow_tables(struct mlx5e_priv *priv);
 651 void mlx5e_destroy_flow_tables(struct mlx5e_priv *priv);
 652 void mlx5e_init_eth_addr(struct mlx5e_priv *priv);
 653 void mlx5e_set_rx_mode_work(struct work_struct *work);
 654
 655 void mlx5e_fill_hwstamp(struct mlx5e_tstamp *clock, u64 timestamp,
 656                         struct skb_shared_hwtstamps *hwts);
 657 void mlx5e_timestamp_init(struct mlx5e_priv *priv);
 658 void mlx5e_timestamp_cleanup(struct mlx5e_priv *priv);
 659 int mlx5e_hwstamp_set(struct net_device *dev, struct ifreq *ifr);
 660 int mlx5e_hwstamp_get(struct net_device *dev, struct ifreq *ifr);
 661
 662 int mlx5e_vlan_rx_add_vid(struct net_device *dev, __always_unused __be16 proto,
 663                           u16 vid);
 664 int mlx5e_vlan_rx_kill_vid(struct net_device *dev, __always_unused __be16 proto,
 665                            u16 vid);
 666 void mlx5e_enable_vlan_filter(struct mlx5e_priv *priv);
 667 void mlx5e_disable_vlan_filter(struct mlx5e_priv *priv);
 668
 669 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, enum mlx5e_rqt_ix rqt_ix);
 670 void mlx5e_build_tir_ctx_hash(void *tirc, struct mlx5e_priv *priv);
 671
 672 int mlx5e_open_locked(struct net_device *netdev);
 673 int mlx5e_close_locked(struct net_device *netdev);
 674 void mlx5e_build_default_indir_rqt(u32 *indirection_rqt, int len,
 675                                    int num_channels);
 676
 677 static inline void mlx5e_tx_notify_hw(struct mlx5e_sq *sq,
 678                                       struct mlx5e_tx_wqe *wqe, int bf_sz)
 679 {
 680         u16 ofst = MLX5_BF_OFFSET + sq->bf_offset;
 681
 682         /* ensure wqe is visible to device before updating doorbell record */
 683         dma_wmb();
 684
 685         *sq->wq.db = cpu_to_be32(sq->pc);
 686
 687         /* ensure doorbell record is visible to device before ringing the
 688          * doorbell
 689          */
 690         wmb();
 691         if (bf_sz)
 692                 __iowrite64_copy(sq->uar_map + ofst, &wqe->ctrl, bf_sz);
 693         else
 694                 mlx5_write64((__be32 *)&wqe->ctrl, sq->uar_map + ofst, NULL);
 695         /* flush the write-combining mapped buffer */
 696         wmb();
 697
 698         sq->bf_offset ^= sq->bf_buf_size;
 699 }
 700
 701 static inline void mlx5e_cq_arm(struct mlx5e_cq *cq)
 702 {
 703         struct mlx5_core_cq *mcq;
 704
 705         mcq = &cq->mcq;
 706         mlx5_cq_arm(mcq, MLX5_CQ_DB_REQ_NOT, mcq->uar->map, NULL, cq->wq.cc);
 707 }
 708
 709 static inline int mlx5e_get_max_num_channels(struct mlx5_core_dev *mdev)
 710 {
 711         return min_t(int, mdev->priv.eq_table.num_comp_vectors,
 712                      MLX5E_MAX_NUM_CHANNELS);
 713 }
 714
 715 extern const struct ethtool_ops mlx5e_ethtool_ops;
 716 #ifdef CONFIG_MLX5_CORE_EN_DCB
 717 extern const struct dcbnl_rtnl_ops mlx5e_dcbnl_ops;
 718 int mlx5e_dcbnl_ieee_setets_core(struct mlx5e_priv *priv, struct ieee_ets *ets);
 719 #endif
 720
 721 u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev);
 722
 723 #endif /* __MLX5_EN_H__ */