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net/mlx5e: Introduce net device priv flags infrastructure
[deliverable/linux.git] / drivers / net / ethernet / mellanox / mlx5 / core / en.h
1 /*
2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32 #ifndef __MLX5_EN_H__
33 #define __MLX5_EN_H__
34
35 #include <linux/if_vlan.h>
36 #include <linux/etherdevice.h>
37 #include <linux/timecounter.h>
38 #include <linux/net_tstamp.h>
39 #include <linux/ptp_clock_kernel.h>
40 #include <linux/mlx5/driver.h>
41 #include <linux/mlx5/qp.h>
42 #include <linux/mlx5/cq.h>
43 #include <linux/mlx5/port.h>
44 #include <linux/mlx5/vport.h>
45 #include <linux/mlx5/transobj.h>
46 #include <linux/rhashtable.h>
47 #include "wq.h"
48 #include "mlx5_core.h"
49 #include "en_stats.h"
50
51 #define MLX5_SET_CFG(p, f, v) MLX5_SET(create_flow_group_in, p, f, v)
52
53 #define MLX5E_MAX_NUM_TC 8
54
55 #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x6
56 #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa
57 #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xd
58
59 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE 0x1
60 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa
61 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE 0xd
62
63 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW 0x1
64 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW 0x4
65 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW 0x6
66
67 #define MLX5_MPWRQ_LOG_STRIDE_SIZE 6 /* >= 6, HW restriction */
68 #define MLX5_MPWRQ_LOG_STRIDE_SIZE_CQE_COMPRESS 8 /* >= 6, HW restriction */
69 #define MLX5_MPWRQ_LOG_WQE_SZ 17
70 #define MLX5_MPWRQ_WQE_PAGE_ORDER (MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT > 0 ? \
71 MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT : 0)
72 #define MLX5_MPWRQ_PAGES_PER_WQE BIT(MLX5_MPWRQ_WQE_PAGE_ORDER)
73 #define MLX5_MPWRQ_STRIDES_PER_PAGE (MLX5_MPWRQ_NUM_STRIDES >> \
74 MLX5_MPWRQ_WQE_PAGE_ORDER)
75 #define MLX5_CHANNEL_MAX_NUM_MTTS (ALIGN(MLX5_MPWRQ_PAGES_PER_WQE, 8) * \
76 BIT(MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW))
77 #define MLX5_UMR_ALIGN (2048)
78 #define MLX5_MPWRQ_SMALL_PACKET_THRESHOLD (128)
79
80 #define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ (64 * 1024)
81 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10
82 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20
83 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10
84 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20
85 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80
86 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW 0x2
87
88 #define MLX5E_LOG_INDIR_RQT_SIZE 0x7
89 #define MLX5E_INDIR_RQT_SIZE BIT(MLX5E_LOG_INDIR_RQT_SIZE)
90 #define MLX5E_MAX_NUM_CHANNELS (MLX5E_INDIR_RQT_SIZE >> 1)
91 #define MLX5E_MAX_NUM_SQS (MLX5E_MAX_NUM_CHANNELS * MLX5E_MAX_NUM_TC)
92 #define MLX5E_TX_CQ_POLL_BUDGET 128
93 #define MLX5E_UPDATE_STATS_INTERVAL 200 /* msecs */
94 #define MLX5E_SQ_BF_BUDGET 16
95
96 #define MLX5E_NUM_MAIN_GROUPS 9
97
98 static inline u16 mlx5_min_rx_wqes(int wq_type, u32 wq_size)
99 {
100 switch (wq_type) {
101 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
102 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW,
103 wq_size / 2);
104 default:
105 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES,
106 wq_size / 2);
107 }
108 }
109
110 static inline int mlx5_min_log_rq_size(int wq_type)
111 {
112 switch (wq_type) {
113 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
114 return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW;
115 default:
116 return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE;
117 }
118 }
119
120 static inline int mlx5_max_log_rq_size(int wq_type)
121 {
122 switch (wq_type) {
123 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
124 return MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW;
125 default:
126 return MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE;
127 }
128 }
129
130 struct mlx5e_tx_wqe {
131 struct mlx5_wqe_ctrl_seg ctrl;
132 struct mlx5_wqe_eth_seg eth;
133 };
134
135 struct mlx5e_rx_wqe {
136 struct mlx5_wqe_srq_next_seg next;
137 struct mlx5_wqe_data_seg data;
138 };
139
140 struct mlx5e_umr_wqe {
141 struct mlx5_wqe_ctrl_seg ctrl;
142 struct mlx5_wqe_umr_ctrl_seg uctrl;
143 struct mlx5_mkey_seg mkc;
144 struct mlx5_wqe_data_seg data;
145 };
146
147 static const char mlx5e_priv_flags[][ETH_GSTRING_LEN] = {
148 "nop",
149 };
150
151 enum mlx5e_priv_flag {
152 MLX5E_PFLAG_NOP = (1 << 0),
153 };
154
155 #define MLX5E_SET_PRIV_FLAG(priv, pflag, enable) \
156 do { \
157 if (enable) \
158 priv->pflags |= pflag; \
159 else \
160 priv->pflags &= ~pflag; \
161 } while (0)
162
163 #ifdef CONFIG_MLX5_CORE_EN_DCB
164 #define MLX5E_MAX_BW_ALLOC 100 /* Max percentage of BW allocation */
165 #define MLX5E_MIN_BW_ALLOC 1 /* Min percentage of BW allocation */
166 #endif
167
168 struct mlx5e_params {
169 u8 log_sq_size;
170 u8 rq_wq_type;
171 u8 mpwqe_log_stride_sz;
172 u8 mpwqe_log_num_strides;
173 u8 log_rq_size;
174 u16 num_channels;
175 u8 num_tc;
176 bool rx_cqe_compress_admin;
177 bool rx_cqe_compress;
178 u16 rx_cq_moderation_usec;
179 u16 rx_cq_moderation_pkts;
180 u16 tx_cq_moderation_usec;
181 u16 tx_cq_moderation_pkts;
182 u16 min_rx_wqes;
183 bool lro_en;
184 u32 lro_wqe_sz;
185 u16 tx_max_inline;
186 u8 rss_hfunc;
187 u8 toeplitz_hash_key[40];
188 u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE];
189 bool vlan_strip_disable;
190 #ifdef CONFIG_MLX5_CORE_EN_DCB
191 struct ieee_ets ets;
192 #endif
193 };
194
195 struct mlx5e_tstamp {
196 rwlock_t lock;
197 struct cyclecounter cycles;
198 struct timecounter clock;
199 struct hwtstamp_config hwtstamp_config;
200 u32 nominal_c_mult;
201 unsigned long overflow_period;
202 struct delayed_work overflow_work;
203 struct mlx5_core_dev *mdev;
204 struct ptp_clock *ptp;
205 struct ptp_clock_info ptp_info;
206 };
207
208 enum {
209 MLX5E_RQ_STATE_POST_WQES_ENABLE,
210 MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS,
211 };
212
213 struct mlx5e_cq {
214 /* data path - accessed per cqe */
215 struct mlx5_cqwq wq;
216
217 /* data path - accessed per napi poll */
218 struct napi_struct *napi;
219 struct mlx5_core_cq mcq;
220 struct mlx5e_channel *channel;
221 struct mlx5e_priv *priv;
222
223 /* cqe decompression */
224 struct mlx5_cqe64 title;
225 struct mlx5_mini_cqe8 mini_arr[MLX5_MINI_CQE_ARRAY_SIZE];
226 u8 mini_arr_idx;
227 u16 decmprs_left;
228 u16 decmprs_wqe_counter;
229
230 /* control */
231 struct mlx5_wq_ctrl wq_ctrl;
232 } ____cacheline_aligned_in_smp;
233
234 struct mlx5e_rq;
235 typedef void (*mlx5e_fp_handle_rx_cqe)(struct mlx5e_rq *rq,
236 struct mlx5_cqe64 *cqe);
237 typedef int (*mlx5e_fp_alloc_wqe)(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe,
238 u16 ix);
239
240 struct mlx5e_dma_info {
241 struct page *page;
242 dma_addr_t addr;
243 };
244
245 struct mlx5e_rq {
246 /* data path */
247 struct mlx5_wq_ll wq;
248 u32 wqe_sz;
249 struct sk_buff **skb;
250 struct mlx5e_mpw_info *wqe_info;
251 __be32 mkey_be;
252 __be32 umr_mkey_be;
253
254 struct device *pdev;
255 struct net_device *netdev;
256 struct mlx5e_tstamp *tstamp;
257 struct mlx5e_rq_stats stats;
258 struct mlx5e_cq cq;
259 mlx5e_fp_handle_rx_cqe handle_rx_cqe;
260 mlx5e_fp_alloc_wqe alloc_wqe;
261
262 unsigned long state;
263 int ix;
264
265 /* control */
266 struct mlx5_wq_ctrl wq_ctrl;
267 u8 wq_type;
268 u32 mpwqe_stride_sz;
269 u32 mpwqe_num_strides;
270 u32 rqn;
271 struct mlx5e_channel *channel;
272 struct mlx5e_priv *priv;
273 } ____cacheline_aligned_in_smp;
274
275 struct mlx5e_umr_dma_info {
276 __be64 *mtt;
277 __be64 *mtt_no_align;
278 dma_addr_t mtt_addr;
279 struct mlx5e_dma_info *dma_info;
280 };
281
282 struct mlx5e_mpw_info {
283 union {
284 struct mlx5e_dma_info dma_info;
285 struct mlx5e_umr_dma_info umr;
286 };
287 u16 consumed_strides;
288 u16 skbs_frags[MLX5_MPWRQ_PAGES_PER_WQE];
289
290 void (*dma_pre_sync)(struct device *pdev,
291 struct mlx5e_mpw_info *wi,
292 u32 wqe_offset, u32 len);
293 void (*add_skb_frag)(struct mlx5e_rq *rq,
294 struct sk_buff *skb,
295 struct mlx5e_mpw_info *wi,
296 u32 page_idx, u32 frag_offset, u32 len);
297 void (*copy_skb_header)(struct device *pdev,
298 struct sk_buff *skb,
299 struct mlx5e_mpw_info *wi,
300 u32 page_idx, u32 offset,
301 u32 headlen);
302 void (*free_wqe)(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi);
303 };
304
305 struct mlx5e_tx_wqe_info {
306 u32 num_bytes;
307 u8 num_wqebbs;
308 u8 num_dma;
309 };
310
311 enum mlx5e_dma_map_type {
312 MLX5E_DMA_MAP_SINGLE,
313 MLX5E_DMA_MAP_PAGE
314 };
315
316 struct mlx5e_sq_dma {
317 dma_addr_t addr;
318 u32 size;
319 enum mlx5e_dma_map_type type;
320 };
321
322 enum {
323 MLX5E_SQ_STATE_WAKE_TXQ_ENABLE,
324 MLX5E_SQ_STATE_BF_ENABLE,
325 };
326
327 struct mlx5e_ico_wqe_info {
328 u8 opcode;
329 u8 num_wqebbs;
330 };
331
332 struct mlx5e_sq {
333 /* data path */
334
335 /* dirtied @completion */
336 u16 cc;
337 u32 dma_fifo_cc;
338
339 /* dirtied @xmit */
340 u16 pc ____cacheline_aligned_in_smp;
341 u32 dma_fifo_pc;
342 u16 bf_offset;
343 u16 prev_cc;
344 u8 bf_budget;
345 struct mlx5e_sq_stats stats;
346
347 struct mlx5e_cq cq;
348
349 /* pointers to per packet info: write@xmit, read@completion */
350 struct sk_buff **skb;
351 struct mlx5e_sq_dma *dma_fifo;
352 struct mlx5e_tx_wqe_info *wqe_info;
353
354 /* read only */
355 struct mlx5_wq_cyc wq;
356 u32 dma_fifo_mask;
357 void __iomem *uar_map;
358 struct netdev_queue *txq;
359 u32 sqn;
360 u16 bf_buf_size;
361 u16 max_inline;
362 u16 edge;
363 struct device *pdev;
364 struct mlx5e_tstamp *tstamp;
365 __be32 mkey_be;
366 unsigned long state;
367
368 /* control path */
369 struct mlx5_wq_ctrl wq_ctrl;
370 struct mlx5_uar uar;
371 struct mlx5e_channel *channel;
372 int tc;
373 struct mlx5e_ico_wqe_info *ico_wqe_info;
374 u32 rate_limit;
375 } ____cacheline_aligned_in_smp;
376
377 static inline bool mlx5e_sq_has_room_for(struct mlx5e_sq *sq, u16 n)
378 {
379 return (((sq->wq.sz_m1 & (sq->cc - sq->pc)) >= n) ||
380 (sq->cc == sq->pc));
381 }
382
383 enum channel_flags {
384 MLX5E_CHANNEL_NAPI_SCHED = 1,
385 };
386
387 struct mlx5e_channel {
388 /* data path */
389 struct mlx5e_rq rq;
390 struct mlx5e_sq sq[MLX5E_MAX_NUM_TC];
391 struct mlx5e_sq icosq; /* internal control operations */
392 struct napi_struct napi;
393 struct device *pdev;
394 struct net_device *netdev;
395 __be32 mkey_be;
396 u8 num_tc;
397 unsigned long flags;
398
399 /* control */
400 struct mlx5e_priv *priv;
401 int ix;
402 int cpu;
403 };
404
405 enum mlx5e_traffic_types {
406 MLX5E_TT_IPV4_TCP,
407 MLX5E_TT_IPV6_TCP,
408 MLX5E_TT_IPV4_UDP,
409 MLX5E_TT_IPV6_UDP,
410 MLX5E_TT_IPV4_IPSEC_AH,
411 MLX5E_TT_IPV6_IPSEC_AH,
412 MLX5E_TT_IPV4_IPSEC_ESP,
413 MLX5E_TT_IPV6_IPSEC_ESP,
414 MLX5E_TT_IPV4,
415 MLX5E_TT_IPV6,
416 MLX5E_TT_ANY,
417 MLX5E_NUM_TT,
418 MLX5E_NUM_INDIR_TIRS = MLX5E_TT_ANY,
419 };
420
421 enum {
422 MLX5E_STATE_ASYNC_EVENTS_ENABLE,
423 MLX5E_STATE_OPENED,
424 MLX5E_STATE_DESTROYING,
425 };
426
427 struct mlx5e_vxlan_db {
428 spinlock_t lock; /* protect vxlan table */
429 struct radix_tree_root tree;
430 };
431
432 struct mlx5e_l2_rule {
433 u8 addr[ETH_ALEN + 2];
434 struct mlx5_flow_rule *rule;
435 };
436
437 struct mlx5e_flow_table {
438 int num_groups;
439 struct mlx5_flow_table *t;
440 struct mlx5_flow_group **g;
441 };
442
443 #define MLX5E_L2_ADDR_HASH_SIZE BIT(BITS_PER_BYTE)
444
445 struct mlx5e_tc_table {
446 struct mlx5_flow_table *t;
447
448 struct rhashtable_params ht_params;
449 struct rhashtable ht;
450 };
451
452 struct mlx5e_vlan_table {
453 struct mlx5e_flow_table ft;
454 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
455 struct mlx5_flow_rule *active_vlans_rule[VLAN_N_VID];
456 struct mlx5_flow_rule *untagged_rule;
457 struct mlx5_flow_rule *any_vlan_rule;
458 bool filter_disabled;
459 };
460
461 struct mlx5e_l2_table {
462 struct mlx5e_flow_table ft;
463 struct hlist_head netdev_uc[MLX5E_L2_ADDR_HASH_SIZE];
464 struct hlist_head netdev_mc[MLX5E_L2_ADDR_HASH_SIZE];
465 struct mlx5e_l2_rule broadcast;
466 struct mlx5e_l2_rule allmulti;
467 struct mlx5e_l2_rule promisc;
468 bool broadcast_enabled;
469 bool allmulti_enabled;
470 bool promisc_enabled;
471 };
472
473 /* L3/L4 traffic type classifier */
474 struct mlx5e_ttc_table {
475 struct mlx5e_flow_table ft;
476 struct mlx5_flow_rule *rules[MLX5E_NUM_TT];
477 };
478
479 #define ARFS_HASH_SHIFT BITS_PER_BYTE
480 #define ARFS_HASH_SIZE BIT(BITS_PER_BYTE)
481 struct arfs_table {
482 struct mlx5e_flow_table ft;
483 struct mlx5_flow_rule *default_rule;
484 struct hlist_head rules_hash[ARFS_HASH_SIZE];
485 };
486
487 enum arfs_type {
488 ARFS_IPV4_TCP,
489 ARFS_IPV6_TCP,
490 ARFS_IPV4_UDP,
491 ARFS_IPV6_UDP,
492 ARFS_NUM_TYPES,
493 };
494
495 struct mlx5e_arfs_tables {
496 struct arfs_table arfs_tables[ARFS_NUM_TYPES];
497 /* Protect aRFS rules list */
498 spinlock_t arfs_lock;
499 struct list_head rules;
500 int last_filter_id;
501 struct workqueue_struct *wq;
502 };
503
504 /* NIC prio FTS */
505 enum {
506 MLX5E_VLAN_FT_LEVEL = 0,
507 MLX5E_L2_FT_LEVEL,
508 MLX5E_TTC_FT_LEVEL,
509 MLX5E_ARFS_FT_LEVEL
510 };
511
512 struct mlx5e_flow_steering {
513 struct mlx5_flow_namespace *ns;
514 struct mlx5e_tc_table tc;
515 struct mlx5e_vlan_table vlan;
516 struct mlx5e_l2_table l2;
517 struct mlx5e_ttc_table ttc;
518 struct mlx5e_arfs_tables arfs;
519 };
520
521 struct mlx5e_direct_tir {
522 u32 tirn;
523 u32 rqtn;
524 };
525
526 enum {
527 MLX5E_TC_PRIO = 0,
528 MLX5E_NIC_PRIO
529 };
530
531 struct mlx5e_priv {
532 /* priv data path fields - start */
533 struct mlx5e_sq **txq_to_sq_map;
534 int channeltc_to_txq_map[MLX5E_MAX_NUM_CHANNELS][MLX5E_MAX_NUM_TC];
535 /* priv data path fields - end */
536
537 unsigned long state;
538 struct mutex state_lock; /* Protects Interface state */
539 struct mlx5_uar cq_uar;
540 u32 pdn;
541 u32 tdn;
542 struct mlx5_core_mkey mkey;
543 struct mlx5_core_mkey umr_mkey;
544 struct mlx5e_rq drop_rq;
545
546 struct mlx5e_channel **channel;
547 u32 tisn[MLX5E_MAX_NUM_TC];
548 u32 indir_rqtn;
549 u32 indir_tirn[MLX5E_NUM_INDIR_TIRS];
550 struct mlx5e_direct_tir direct_tir[MLX5E_MAX_NUM_CHANNELS];
551 u32 tx_rates[MLX5E_MAX_NUM_SQS];
552
553 struct mlx5e_flow_steering fs;
554 struct mlx5e_vxlan_db vxlan;
555
556 struct mlx5e_params params;
557 struct workqueue_struct *wq;
558 struct work_struct update_carrier_work;
559 struct work_struct set_rx_mode_work;
560 struct delayed_work update_stats_work;
561
562 u32 pflags;
563 struct mlx5_core_dev *mdev;
564 struct net_device *netdev;
565 struct mlx5e_stats stats;
566 struct mlx5e_tstamp tstamp;
567 u16 q_counter;
568 };
569
570 enum mlx5e_link_mode {
571 MLX5E_1000BASE_CX_SGMII = 0,
572 MLX5E_1000BASE_KX = 1,
573 MLX5E_10GBASE_CX4 = 2,
574 MLX5E_10GBASE_KX4 = 3,
575 MLX5E_10GBASE_KR = 4,
576 MLX5E_20GBASE_KR2 = 5,
577 MLX5E_40GBASE_CR4 = 6,
578 MLX5E_40GBASE_KR4 = 7,
579 MLX5E_56GBASE_R4 = 8,
580 MLX5E_10GBASE_CR = 12,
581 MLX5E_10GBASE_SR = 13,
582 MLX5E_10GBASE_ER = 14,
583 MLX5E_40GBASE_SR4 = 15,
584 MLX5E_40GBASE_LR4 = 16,
585 MLX5E_100GBASE_CR4 = 20,
586 MLX5E_100GBASE_SR4 = 21,
587 MLX5E_100GBASE_KR4 = 22,
588 MLX5E_100GBASE_LR4 = 23,
589 MLX5E_100BASE_TX = 24,
590 MLX5E_1000BASE_T = 25,
591 MLX5E_10GBASE_T = 26,
592 MLX5E_25GBASE_CR = 27,
593 MLX5E_25GBASE_KR = 28,
594 MLX5E_25GBASE_SR = 29,
595 MLX5E_50GBASE_CR2 = 30,
596 MLX5E_50GBASE_KR2 = 31,
597 MLX5E_LINK_MODES_NUMBER,
598 };
599
600 #define MLX5E_PROT_MASK(link_mode) (1 << link_mode)
601
602 void mlx5e_send_nop(struct mlx5e_sq *sq, bool notify_hw);
603 u16 mlx5e_select_queue(struct net_device *dev, struct sk_buff *skb,
604 void *accel_priv, select_queue_fallback_t fallback);
605 netdev_tx_t mlx5e_xmit(struct sk_buff *skb, struct net_device *dev);
606
607 void mlx5e_completion_event(struct mlx5_core_cq *mcq);
608 void mlx5e_cq_error_event(struct mlx5_core_cq *mcq, enum mlx5_event event);
609 int mlx5e_napi_poll(struct napi_struct *napi, int budget);
610 bool mlx5e_poll_tx_cq(struct mlx5e_cq *cq, int napi_budget);
611 int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget);
612
613 void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe);
614 void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe);
615 bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq);
616 int mlx5e_alloc_rx_wqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix);
617 int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix);
618 void mlx5e_post_rx_fragmented_mpwqe(struct mlx5e_rq *rq);
619 void mlx5e_complete_rx_linear_mpwqe(struct mlx5e_rq *rq,
620 struct mlx5_cqe64 *cqe,
621 u16 byte_cnt,
622 struct mlx5e_mpw_info *wi,
623 struct sk_buff *skb);
624 void mlx5e_complete_rx_fragmented_mpwqe(struct mlx5e_rq *rq,
625 struct mlx5_cqe64 *cqe,
626 u16 byte_cnt,
627 struct mlx5e_mpw_info *wi,
628 struct sk_buff *skb);
629 void mlx5e_free_rx_linear_mpwqe(struct mlx5e_rq *rq,
630 struct mlx5e_mpw_info *wi);
631 void mlx5e_free_rx_fragmented_mpwqe(struct mlx5e_rq *rq,
632 struct mlx5e_mpw_info *wi);
633 struct mlx5_cqe64 *mlx5e_get_cqe(struct mlx5e_cq *cq);
634
635 void mlx5e_update_stats(struct mlx5e_priv *priv);
636
637 int mlx5e_create_flow_steering(struct mlx5e_priv *priv);
638 void mlx5e_destroy_flow_steering(struct mlx5e_priv *priv);
639 void mlx5e_init_l2_addr(struct mlx5e_priv *priv);
640 void mlx5e_destroy_flow_table(struct mlx5e_flow_table *ft);
641 void mlx5e_set_rx_mode_work(struct work_struct *work);
642
643 void mlx5e_fill_hwstamp(struct mlx5e_tstamp *clock, u64 timestamp,
644 struct skb_shared_hwtstamps *hwts);
645 void mlx5e_timestamp_init(struct mlx5e_priv *priv);
646 void mlx5e_timestamp_cleanup(struct mlx5e_priv *priv);
647 int mlx5e_hwstamp_set(struct net_device *dev, struct ifreq *ifr);
648 int mlx5e_hwstamp_get(struct net_device *dev, struct ifreq *ifr);
649 void mlx5e_modify_rx_cqe_compression(struct mlx5e_priv *priv, bool val);
650
651 int mlx5e_vlan_rx_add_vid(struct net_device *dev, __always_unused __be16 proto,
652 u16 vid);
653 int mlx5e_vlan_rx_kill_vid(struct net_device *dev, __always_unused __be16 proto,
654 u16 vid);
655 void mlx5e_enable_vlan_filter(struct mlx5e_priv *priv);
656 void mlx5e_disable_vlan_filter(struct mlx5e_priv *priv);
657
658 int mlx5e_modify_rqs_vsd(struct mlx5e_priv *priv, bool vsd);
659
660 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz, int ix);
661 void mlx5e_build_tir_ctx_hash(void *tirc, struct mlx5e_priv *priv);
662
663 int mlx5e_open_locked(struct net_device *netdev);
664 int mlx5e_close_locked(struct net_device *netdev);
665 void mlx5e_build_default_indir_rqt(struct mlx5_core_dev *mdev,
666 u32 *indirection_rqt, int len,
667 int num_channels);
668 int mlx5e_get_max_linkspeed(struct mlx5_core_dev *mdev, u32 *speed);
669
670 static inline void mlx5e_tx_notify_hw(struct mlx5e_sq *sq,
671 struct mlx5_wqe_ctrl_seg *ctrl, int bf_sz)
672 {
673 u16 ofst = MLX5_BF_OFFSET + sq->bf_offset;
674
675 /* ensure wqe is visible to device before updating doorbell record */
676 dma_wmb();
677
678 *sq->wq.db = cpu_to_be32(sq->pc);
679
680 /* ensure doorbell record is visible to device before ringing the
681 * doorbell
682 */
683 wmb();
684 if (bf_sz)
685 __iowrite64_copy(sq->uar_map + ofst, ctrl, bf_sz);
686 else
687 mlx5_write64((__be32 *)ctrl, sq->uar_map + ofst, NULL);
688 /* flush the write-combining mapped buffer */
689 wmb();
690
691 sq->bf_offset ^= sq->bf_buf_size;
692 }
693
694 static inline void mlx5e_cq_arm(struct mlx5e_cq *cq)
695 {
696 struct mlx5_core_cq *mcq;
697
698 mcq = &cq->mcq;
699 mlx5_cq_arm(mcq, MLX5_CQ_DB_REQ_NOT, mcq->uar->map, NULL, cq->wq.cc);
700 }
701
702 static inline int mlx5e_get_max_num_channels(struct mlx5_core_dev *mdev)
703 {
704 return min_t(int, mdev->priv.eq_table.num_comp_vectors,
705 MLX5E_MAX_NUM_CHANNELS);
706 }
707
708 static inline int mlx5e_get_mtt_octw(int npages)
709 {
710 return ALIGN(npages, 8) / 2;
711 }
712
713 extern const struct ethtool_ops mlx5e_ethtool_ops;
714 #ifdef CONFIG_MLX5_CORE_EN_DCB
715 extern const struct dcbnl_rtnl_ops mlx5e_dcbnl_ops;
716 int mlx5e_dcbnl_ieee_setets_core(struct mlx5e_priv *priv, struct ieee_ets *ets);
717 #endif
718
719 #ifndef CONFIG_RFS_ACCEL
720 static inline int mlx5e_arfs_create_tables(struct mlx5e_priv *priv)
721 {
722 return 0;
723 }
724
725 static inline void mlx5e_arfs_destroy_tables(struct mlx5e_priv *priv) {}
726
727 static inline int mlx5e_arfs_enable(struct mlx5e_priv *priv)
728 {
729 return -ENOTSUPP;
730 }
731
732 static inline int mlx5e_arfs_disable(struct mlx5e_priv *priv)
733 {
734 return -ENOTSUPP;
735 }
736 #else
737 int mlx5e_arfs_create_tables(struct mlx5e_priv *priv);
738 void mlx5e_arfs_destroy_tables(struct mlx5e_priv *priv);
739 int mlx5e_arfs_enable(struct mlx5e_priv *priv);
740 int mlx5e_arfs_disable(struct mlx5e_priv *priv);
741 int mlx5e_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
742 u16 rxq_index, u32 flow_id);
743 #endif
744
745 u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev);
746
747 #endif /* __MLX5_EN_H__ */
Linux kernel - Deliverables
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