2 * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/mlx5/fs.h>
37 struct mlx5e_rq_param
{
38 u32 rqc
[MLX5_ST_SZ_DW(rqc
)];
39 struct mlx5_wq_param wq
;
42 struct mlx5e_sq_param
{
43 u32 sqc
[MLX5_ST_SZ_DW(sqc
)];
44 struct mlx5_wq_param wq
;
48 struct mlx5e_cq_param
{
49 u32 cqc
[MLX5_ST_SZ_DW(cqc
)];
50 struct mlx5_wq_param wq
;
54 struct mlx5e_channel_param
{
55 struct mlx5e_rq_param rq
;
56 struct mlx5e_sq_param sq
;
57 struct mlx5e_cq_param rx_cq
;
58 struct mlx5e_cq_param tx_cq
;
61 static void mlx5e_update_carrier(struct mlx5e_priv
*priv
)
63 struct mlx5_core_dev
*mdev
= priv
->mdev
;
66 port_state
= mlx5_query_vport_state(mdev
,
67 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT
, 0);
69 if (port_state
== VPORT_STATE_UP
)
70 netif_carrier_on(priv
->netdev
);
72 netif_carrier_off(priv
->netdev
);
75 static void mlx5e_update_carrier_work(struct work_struct
*work
)
77 struct mlx5e_priv
*priv
= container_of(work
, struct mlx5e_priv
,
80 mutex_lock(&priv
->state_lock
);
81 if (test_bit(MLX5E_STATE_OPENED
, &priv
->state
))
82 mlx5e_update_carrier(priv
);
83 mutex_unlock(&priv
->state_lock
);
86 static void mlx5e_update_pport_counters(struct mlx5e_priv
*priv
)
88 struct mlx5_core_dev
*mdev
= priv
->mdev
;
89 struct mlx5e_pport_stats
*s
= &priv
->stats
.pport
;
92 int sz
= MLX5_ST_SZ_BYTES(ppcnt_reg
);
94 in
= mlx5_vzalloc(sz
);
95 out
= mlx5_vzalloc(sz
);
99 MLX5_SET(ppcnt_reg
, in
, local_port
, 1);
101 MLX5_SET(ppcnt_reg
, in
, grp
, MLX5_IEEE_802_3_COUNTERS_GROUP
);
102 mlx5_core_access_reg(mdev
, in
, sz
, out
,
103 sz
, MLX5_REG_PPCNT
, 0, 0);
104 memcpy(s
->IEEE_802_3_counters
,
105 MLX5_ADDR_OF(ppcnt_reg
, out
, counter_set
),
106 sizeof(s
->IEEE_802_3_counters
));
108 MLX5_SET(ppcnt_reg
, in
, grp
, MLX5_RFC_2863_COUNTERS_GROUP
);
109 mlx5_core_access_reg(mdev
, in
, sz
, out
,
110 sz
, MLX5_REG_PPCNT
, 0, 0);
111 memcpy(s
->RFC_2863_counters
,
112 MLX5_ADDR_OF(ppcnt_reg
, out
, counter_set
),
113 sizeof(s
->RFC_2863_counters
));
115 MLX5_SET(ppcnt_reg
, in
, grp
, MLX5_RFC_2819_COUNTERS_GROUP
);
116 mlx5_core_access_reg(mdev
, in
, sz
, out
,
117 sz
, MLX5_REG_PPCNT
, 0, 0);
118 memcpy(s
->RFC_2819_counters
,
119 MLX5_ADDR_OF(ppcnt_reg
, out
, counter_set
),
120 sizeof(s
->RFC_2819_counters
));
127 void mlx5e_update_stats(struct mlx5e_priv
*priv
)
129 struct mlx5_core_dev
*mdev
= priv
->mdev
;
130 struct mlx5e_vport_stats
*s
= &priv
->stats
.vport
;
131 struct mlx5e_rq_stats
*rq_stats
;
132 struct mlx5e_sq_stats
*sq_stats
;
133 u32 in
[MLX5_ST_SZ_DW(query_vport_counter_in
)];
135 int outlen
= MLX5_ST_SZ_BYTES(query_vport_counter_out
);
139 out
= mlx5_vzalloc(outlen
);
143 /* Collect firts the SW counters and then HW for consistency */
146 s
->tx_queue_stopped
= 0;
147 s
->tx_queue_wake
= 0;
148 s
->tx_queue_dropped
= 0;
155 for (i
= 0; i
< priv
->params
.num_channels
; i
++) {
156 rq_stats
= &priv
->channel
[i
]->rq
.stats
;
158 s
->lro_packets
+= rq_stats
->lro_packets
;
159 s
->lro_bytes
+= rq_stats
->lro_bytes
;
160 s
->rx_csum_none
+= rq_stats
->csum_none
;
161 s
->rx_csum_sw
+= rq_stats
->csum_sw
;
162 s
->rx_wqe_err
+= rq_stats
->wqe_err
;
164 for (j
= 0; j
< priv
->params
.num_tc
; j
++) {
165 sq_stats
= &priv
->channel
[i
]->sq
[j
].stats
;
167 s
->tso_packets
+= sq_stats
->tso_packets
;
168 s
->tso_bytes
+= sq_stats
->tso_bytes
;
169 s
->tx_queue_stopped
+= sq_stats
->stopped
;
170 s
->tx_queue_wake
+= sq_stats
->wake
;
171 s
->tx_queue_dropped
+= sq_stats
->dropped
;
172 tx_offload_none
+= sq_stats
->csum_offload_none
;
177 memset(in
, 0, sizeof(in
));
179 MLX5_SET(query_vport_counter_in
, in
, opcode
,
180 MLX5_CMD_OP_QUERY_VPORT_COUNTER
);
181 MLX5_SET(query_vport_counter_in
, in
, op_mod
, 0);
182 MLX5_SET(query_vport_counter_in
, in
, other_vport
, 0);
184 memset(out
, 0, outlen
);
186 if (mlx5_cmd_exec(mdev
, in
, sizeof(in
), out
, outlen
))
189 #define MLX5_GET_CTR(p, x) \
190 MLX5_GET64(query_vport_counter_out, p, x)
192 s
->rx_error_packets
=
193 MLX5_GET_CTR(out
, received_errors
.packets
);
195 MLX5_GET_CTR(out
, received_errors
.octets
);
196 s
->tx_error_packets
=
197 MLX5_GET_CTR(out
, transmit_errors
.packets
);
199 MLX5_GET_CTR(out
, transmit_errors
.octets
);
201 s
->rx_unicast_packets
=
202 MLX5_GET_CTR(out
, received_eth_unicast
.packets
);
203 s
->rx_unicast_bytes
=
204 MLX5_GET_CTR(out
, received_eth_unicast
.octets
);
205 s
->tx_unicast_packets
=
206 MLX5_GET_CTR(out
, transmitted_eth_unicast
.packets
);
207 s
->tx_unicast_bytes
=
208 MLX5_GET_CTR(out
, transmitted_eth_unicast
.octets
);
210 s
->rx_multicast_packets
=
211 MLX5_GET_CTR(out
, received_eth_multicast
.packets
);
212 s
->rx_multicast_bytes
=
213 MLX5_GET_CTR(out
, received_eth_multicast
.octets
);
214 s
->tx_multicast_packets
=
215 MLX5_GET_CTR(out
, transmitted_eth_multicast
.packets
);
216 s
->tx_multicast_bytes
=
217 MLX5_GET_CTR(out
, transmitted_eth_multicast
.octets
);
219 s
->rx_broadcast_packets
=
220 MLX5_GET_CTR(out
, received_eth_broadcast
.packets
);
221 s
->rx_broadcast_bytes
=
222 MLX5_GET_CTR(out
, received_eth_broadcast
.octets
);
223 s
->tx_broadcast_packets
=
224 MLX5_GET_CTR(out
, transmitted_eth_broadcast
.packets
);
225 s
->tx_broadcast_bytes
=
226 MLX5_GET_CTR(out
, transmitted_eth_broadcast
.octets
);
229 s
->rx_unicast_packets
+
230 s
->rx_multicast_packets
+
231 s
->rx_broadcast_packets
;
233 s
->rx_unicast_bytes
+
234 s
->rx_multicast_bytes
+
235 s
->rx_broadcast_bytes
;
237 s
->tx_unicast_packets
+
238 s
->tx_multicast_packets
+
239 s
->tx_broadcast_packets
;
241 s
->tx_unicast_bytes
+
242 s
->tx_multicast_bytes
+
243 s
->tx_broadcast_bytes
;
245 /* Update calculated offload counters */
246 s
->tx_csum_offload
= s
->tx_packets
- tx_offload_none
;
247 s
->rx_csum_good
= s
->rx_packets
- s
->rx_csum_none
-
250 mlx5e_update_pport_counters(priv
);
255 static void mlx5e_update_stats_work(struct work_struct
*work
)
257 struct delayed_work
*dwork
= to_delayed_work(work
);
258 struct mlx5e_priv
*priv
= container_of(dwork
, struct mlx5e_priv
,
260 mutex_lock(&priv
->state_lock
);
261 if (test_bit(MLX5E_STATE_OPENED
, &priv
->state
)) {
262 mlx5e_update_stats(priv
);
263 schedule_delayed_work(dwork
,
265 MLX5E_UPDATE_STATS_INTERVAL
));
267 mutex_unlock(&priv
->state_lock
);
270 static void __mlx5e_async_event(struct mlx5e_priv
*priv
,
271 enum mlx5_dev_event event
)
274 case MLX5_DEV_EVENT_PORT_UP
:
275 case MLX5_DEV_EVENT_PORT_DOWN
:
276 schedule_work(&priv
->update_carrier_work
);
284 static void mlx5e_async_event(struct mlx5_core_dev
*mdev
, void *vpriv
,
285 enum mlx5_dev_event event
, unsigned long param
)
287 struct mlx5e_priv
*priv
= vpriv
;
289 spin_lock(&priv
->async_events_spinlock
);
290 if (test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE
, &priv
->state
))
291 __mlx5e_async_event(priv
, event
);
292 spin_unlock(&priv
->async_events_spinlock
);
295 static void mlx5e_enable_async_events(struct mlx5e_priv
*priv
)
297 set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE
, &priv
->state
);
300 static void mlx5e_disable_async_events(struct mlx5e_priv
*priv
)
302 spin_lock_irq(&priv
->async_events_spinlock
);
303 clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE
, &priv
->state
);
304 spin_unlock_irq(&priv
->async_events_spinlock
);
307 #define MLX5E_HW2SW_MTU(hwmtu) (hwmtu - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
308 #define MLX5E_SW2HW_MTU(swmtu) (swmtu + (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
310 static int mlx5e_create_rq(struct mlx5e_channel
*c
,
311 struct mlx5e_rq_param
*param
,
314 struct mlx5e_priv
*priv
= c
->priv
;
315 struct mlx5_core_dev
*mdev
= priv
->mdev
;
316 void *rqc
= param
->rqc
;
317 void *rqc_wq
= MLX5_ADDR_OF(rqc
, rqc
, wq
);
322 param
->wq
.db_numa_node
= cpu_to_node(c
->cpu
);
324 err
= mlx5_wq_ll_create(mdev
, ¶m
->wq
, rqc_wq
, &rq
->wq
,
329 rq
->wq
.db
= &rq
->wq
.db
[MLX5_RCV_DBR
];
331 wq_sz
= mlx5_wq_ll_get_size(&rq
->wq
);
332 rq
->skb
= kzalloc_node(wq_sz
* sizeof(*rq
->skb
), GFP_KERNEL
,
333 cpu_to_node(c
->cpu
));
336 goto err_rq_wq_destroy
;
339 rq
->wqe_sz
= (priv
->params
.lro_en
) ? priv
->params
.lro_wqe_sz
:
340 MLX5E_SW2HW_MTU(priv
->netdev
->mtu
);
341 rq
->wqe_sz
= SKB_DATA_ALIGN(rq
->wqe_sz
+ MLX5E_NET_IP_ALIGN
);
343 for (i
= 0; i
< wq_sz
; i
++) {
344 struct mlx5e_rx_wqe
*wqe
= mlx5_wq_ll_get_wqe(&rq
->wq
, i
);
345 u32 byte_count
= rq
->wqe_sz
- MLX5E_NET_IP_ALIGN
;
347 wqe
->data
.lkey
= c
->mkey_be
;
348 wqe
->data
.byte_count
=
349 cpu_to_be32(byte_count
| MLX5_HW_START_PADDING
);
353 rq
->netdev
= c
->netdev
;
354 rq
->tstamp
= &priv
->tstamp
;
362 mlx5_wq_destroy(&rq
->wq_ctrl
);
367 static void mlx5e_destroy_rq(struct mlx5e_rq
*rq
)
370 mlx5_wq_destroy(&rq
->wq_ctrl
);
373 static int mlx5e_enable_rq(struct mlx5e_rq
*rq
, struct mlx5e_rq_param
*param
)
375 struct mlx5e_priv
*priv
= rq
->priv
;
376 struct mlx5_core_dev
*mdev
= priv
->mdev
;
384 inlen
= MLX5_ST_SZ_BYTES(create_rq_in
) +
385 sizeof(u64
) * rq
->wq_ctrl
.buf
.npages
;
386 in
= mlx5_vzalloc(inlen
);
390 rqc
= MLX5_ADDR_OF(create_rq_in
, in
, ctx
);
391 wq
= MLX5_ADDR_OF(rqc
, rqc
, wq
);
393 memcpy(rqc
, param
->rqc
, sizeof(param
->rqc
));
395 MLX5_SET(rqc
, rqc
, cqn
, rq
->cq
.mcq
.cqn
);
396 MLX5_SET(rqc
, rqc
, state
, MLX5_RQC_STATE_RST
);
397 MLX5_SET(rqc
, rqc
, flush_in_error_en
, 1);
398 MLX5_SET(wq
, wq
, log_wq_pg_sz
, rq
->wq_ctrl
.buf
.page_shift
-
399 MLX5_ADAPTER_PAGE_SHIFT
);
400 MLX5_SET64(wq
, wq
, dbr_addr
, rq
->wq_ctrl
.db
.dma
);
402 mlx5_fill_page_array(&rq
->wq_ctrl
.buf
,
403 (__be64
*)MLX5_ADDR_OF(wq
, wq
, pas
));
405 err
= mlx5_core_create_rq(mdev
, in
, inlen
, &rq
->rqn
);
412 static int mlx5e_modify_rq(struct mlx5e_rq
*rq
, int curr_state
, int next_state
)
414 struct mlx5e_channel
*c
= rq
->channel
;
415 struct mlx5e_priv
*priv
= c
->priv
;
416 struct mlx5_core_dev
*mdev
= priv
->mdev
;
423 inlen
= MLX5_ST_SZ_BYTES(modify_rq_in
);
424 in
= mlx5_vzalloc(inlen
);
428 rqc
= MLX5_ADDR_OF(modify_rq_in
, in
, ctx
);
430 MLX5_SET(modify_rq_in
, in
, rq_state
, curr_state
);
431 MLX5_SET(rqc
, rqc
, state
, next_state
);
433 err
= mlx5_core_modify_rq(mdev
, rq
->rqn
, in
, inlen
);
440 static void mlx5e_disable_rq(struct mlx5e_rq
*rq
)
442 mlx5_core_destroy_rq(rq
->priv
->mdev
, rq
->rqn
);
445 static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq
*rq
)
447 unsigned long exp_time
= jiffies
+ msecs_to_jiffies(20000);
448 struct mlx5e_channel
*c
= rq
->channel
;
449 struct mlx5e_priv
*priv
= c
->priv
;
450 struct mlx5_wq_ll
*wq
= &rq
->wq
;
452 while (time_before(jiffies
, exp_time
)) {
453 if (wq
->cur_sz
>= priv
->params
.min_rx_wqes
)
462 static int mlx5e_open_rq(struct mlx5e_channel
*c
,
463 struct mlx5e_rq_param
*param
,
468 err
= mlx5e_create_rq(c
, param
, rq
);
472 err
= mlx5e_enable_rq(rq
, param
);
476 err
= mlx5e_modify_rq(rq
, MLX5_RQC_STATE_RST
, MLX5_RQC_STATE_RDY
);
480 set_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE
, &rq
->state
);
481 mlx5e_send_nop(&c
->sq
[0], true); /* trigger mlx5e_post_rx_wqes() */
486 mlx5e_disable_rq(rq
);
488 mlx5e_destroy_rq(rq
);
493 static void mlx5e_close_rq(struct mlx5e_rq
*rq
)
495 clear_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE
, &rq
->state
);
496 napi_synchronize(&rq
->channel
->napi
); /* prevent mlx5e_post_rx_wqes */
498 mlx5e_modify_rq(rq
, MLX5_RQC_STATE_RDY
, MLX5_RQC_STATE_ERR
);
499 while (!mlx5_wq_ll_is_empty(&rq
->wq
))
502 /* avoid destroying rq before mlx5e_poll_rx_cq() is done with it */
503 napi_synchronize(&rq
->channel
->napi
);
505 mlx5e_disable_rq(rq
);
506 mlx5e_destroy_rq(rq
);
509 static void mlx5e_free_sq_db(struct mlx5e_sq
*sq
)
516 static int mlx5e_alloc_sq_db(struct mlx5e_sq
*sq
, int numa
)
518 int wq_sz
= mlx5_wq_cyc_get_size(&sq
->wq
);
519 int df_sz
= wq_sz
* MLX5_SEND_WQEBB_NUM_DS
;
521 sq
->skb
= kzalloc_node(wq_sz
* sizeof(*sq
->skb
), GFP_KERNEL
, numa
);
522 sq
->dma_fifo
= kzalloc_node(df_sz
* sizeof(*sq
->dma_fifo
), GFP_KERNEL
,
524 sq
->wqe_info
= kzalloc_node(wq_sz
* sizeof(*sq
->wqe_info
), GFP_KERNEL
,
527 if (!sq
->skb
|| !sq
->dma_fifo
|| !sq
->wqe_info
) {
528 mlx5e_free_sq_db(sq
);
532 sq
->dma_fifo_mask
= df_sz
- 1;
537 static int mlx5e_create_sq(struct mlx5e_channel
*c
,
539 struct mlx5e_sq_param
*param
,
542 struct mlx5e_priv
*priv
= c
->priv
;
543 struct mlx5_core_dev
*mdev
= priv
->mdev
;
545 void *sqc
= param
->sqc
;
546 void *sqc_wq
= MLX5_ADDR_OF(sqc
, sqc
, wq
);
550 err
= mlx5_alloc_map_uar(mdev
, &sq
->uar
);
554 param
->wq
.db_numa_node
= cpu_to_node(c
->cpu
);
556 err
= mlx5_wq_cyc_create(mdev
, ¶m
->wq
, sqc_wq
, &sq
->wq
,
559 goto err_unmap_free_uar
;
561 sq
->wq
.db
= &sq
->wq
.db
[MLX5_SND_DBR
];
562 sq
->uar_map
= sq
->uar
.map
;
563 sq
->uar_bf_map
= sq
->uar
.bf_map
;
564 sq
->bf_buf_size
= (1 << MLX5_CAP_GEN(mdev
, log_bf_reg_size
)) / 2;
565 sq
->max_inline
= param
->max_inline
;
567 err
= mlx5e_alloc_sq_db(sq
, cpu_to_node(c
->cpu
));
569 goto err_sq_wq_destroy
;
571 txq_ix
= c
->ix
+ tc
* priv
->params
.num_channels
;
572 sq
->txq
= netdev_get_tx_queue(priv
->netdev
, txq_ix
);
575 sq
->tstamp
= &priv
->tstamp
;
576 sq
->mkey_be
= c
->mkey_be
;
579 sq
->edge
= (sq
->wq
.sz_m1
+ 1) - MLX5_SEND_WQE_MAX_WQEBBS
;
580 sq
->bf_budget
= MLX5E_SQ_BF_BUDGET
;
581 priv
->txq_to_sq_map
[txq_ix
] = sq
;
586 mlx5_wq_destroy(&sq
->wq_ctrl
);
589 mlx5_unmap_free_uar(mdev
, &sq
->uar
);
594 static void mlx5e_destroy_sq(struct mlx5e_sq
*sq
)
596 struct mlx5e_channel
*c
= sq
->channel
;
597 struct mlx5e_priv
*priv
= c
->priv
;
599 mlx5e_free_sq_db(sq
);
600 mlx5_wq_destroy(&sq
->wq_ctrl
);
601 mlx5_unmap_free_uar(priv
->mdev
, &sq
->uar
);
604 static int mlx5e_enable_sq(struct mlx5e_sq
*sq
, struct mlx5e_sq_param
*param
)
606 struct mlx5e_channel
*c
= sq
->channel
;
607 struct mlx5e_priv
*priv
= c
->priv
;
608 struct mlx5_core_dev
*mdev
= priv
->mdev
;
616 inlen
= MLX5_ST_SZ_BYTES(create_sq_in
) +
617 sizeof(u64
) * sq
->wq_ctrl
.buf
.npages
;
618 in
= mlx5_vzalloc(inlen
);
622 sqc
= MLX5_ADDR_OF(create_sq_in
, in
, ctx
);
623 wq
= MLX5_ADDR_OF(sqc
, sqc
, wq
);
625 memcpy(sqc
, param
->sqc
, sizeof(param
->sqc
));
627 MLX5_SET(sqc
, sqc
, tis_num_0
, priv
->tisn
[sq
->tc
]);
628 MLX5_SET(sqc
, sqc
, cqn
, c
->sq
[sq
->tc
].cq
.mcq
.cqn
);
629 MLX5_SET(sqc
, sqc
, state
, MLX5_SQC_STATE_RST
);
630 MLX5_SET(sqc
, sqc
, tis_lst_sz
, 1);
631 MLX5_SET(sqc
, sqc
, flush_in_error_en
, 1);
633 MLX5_SET(wq
, wq
, wq_type
, MLX5_WQ_TYPE_CYCLIC
);
634 MLX5_SET(wq
, wq
, uar_page
, sq
->uar
.index
);
635 MLX5_SET(wq
, wq
, log_wq_pg_sz
, sq
->wq_ctrl
.buf
.page_shift
-
636 MLX5_ADAPTER_PAGE_SHIFT
);
637 MLX5_SET64(wq
, wq
, dbr_addr
, sq
->wq_ctrl
.db
.dma
);
639 mlx5_fill_page_array(&sq
->wq_ctrl
.buf
,
640 (__be64
*)MLX5_ADDR_OF(wq
, wq
, pas
));
642 err
= mlx5_core_create_sq(mdev
, in
, inlen
, &sq
->sqn
);
649 static int mlx5e_modify_sq(struct mlx5e_sq
*sq
, int curr_state
, int next_state
)
651 struct mlx5e_channel
*c
= sq
->channel
;
652 struct mlx5e_priv
*priv
= c
->priv
;
653 struct mlx5_core_dev
*mdev
= priv
->mdev
;
660 inlen
= MLX5_ST_SZ_BYTES(modify_sq_in
);
661 in
= mlx5_vzalloc(inlen
);
665 sqc
= MLX5_ADDR_OF(modify_sq_in
, in
, ctx
);
667 MLX5_SET(modify_sq_in
, in
, sq_state
, curr_state
);
668 MLX5_SET(sqc
, sqc
, state
, next_state
);
670 err
= mlx5_core_modify_sq(mdev
, sq
->sqn
, in
, inlen
);
677 static void mlx5e_disable_sq(struct mlx5e_sq
*sq
)
679 struct mlx5e_channel
*c
= sq
->channel
;
680 struct mlx5e_priv
*priv
= c
->priv
;
681 struct mlx5_core_dev
*mdev
= priv
->mdev
;
683 mlx5_core_destroy_sq(mdev
, sq
->sqn
);
686 static int mlx5e_open_sq(struct mlx5e_channel
*c
,
688 struct mlx5e_sq_param
*param
,
693 err
= mlx5e_create_sq(c
, tc
, param
, sq
);
697 err
= mlx5e_enable_sq(sq
, param
);
701 err
= mlx5e_modify_sq(sq
, MLX5_SQC_STATE_RST
, MLX5_SQC_STATE_RDY
);
705 set_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE
, &sq
->state
);
706 netdev_tx_reset_queue(sq
->txq
);
707 netif_tx_start_queue(sq
->txq
);
712 mlx5e_disable_sq(sq
);
714 mlx5e_destroy_sq(sq
);
719 static inline void netif_tx_disable_queue(struct netdev_queue
*txq
)
721 __netif_tx_lock_bh(txq
);
722 netif_tx_stop_queue(txq
);
723 __netif_tx_unlock_bh(txq
);
726 static void mlx5e_close_sq(struct mlx5e_sq
*sq
)
728 clear_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE
, &sq
->state
);
729 napi_synchronize(&sq
->channel
->napi
); /* prevent netif_tx_wake_queue */
730 netif_tx_disable_queue(sq
->txq
);
732 /* ensure hw is notified of all pending wqes */
733 if (mlx5e_sq_has_room_for(sq
, 1))
734 mlx5e_send_nop(sq
, true);
736 mlx5e_modify_sq(sq
, MLX5_SQC_STATE_RDY
, MLX5_SQC_STATE_ERR
);
737 while (sq
->cc
!= sq
->pc
) /* wait till sq is empty */
740 /* avoid destroying sq before mlx5e_poll_tx_cq() is done with it */
741 napi_synchronize(&sq
->channel
->napi
);
743 mlx5e_disable_sq(sq
);
744 mlx5e_destroy_sq(sq
);
747 static int mlx5e_create_cq(struct mlx5e_channel
*c
,
748 struct mlx5e_cq_param
*param
,
751 struct mlx5e_priv
*priv
= c
->priv
;
752 struct mlx5_core_dev
*mdev
= priv
->mdev
;
753 struct mlx5_core_cq
*mcq
= &cq
->mcq
;
759 param
->wq
.buf_numa_node
= cpu_to_node(c
->cpu
);
760 param
->wq
.db_numa_node
= cpu_to_node(c
->cpu
);
761 param
->eq_ix
= c
->ix
;
763 err
= mlx5_cqwq_create(mdev
, ¶m
->wq
, param
->cqc
, &cq
->wq
,
768 mlx5_vector2eqn(mdev
, param
->eq_ix
, &eqn_not_used
, &irqn
);
773 mcq
->set_ci_db
= cq
->wq_ctrl
.db
.db
;
774 mcq
->arm_db
= cq
->wq_ctrl
.db
.db
+ 1;
777 mcq
->vector
= param
->eq_ix
;
778 mcq
->comp
= mlx5e_completion_event
;
779 mcq
->event
= mlx5e_cq_error_event
;
781 mcq
->uar
= &priv
->cq_uar
;
783 for (i
= 0; i
< mlx5_cqwq_get_size(&cq
->wq
); i
++) {
784 struct mlx5_cqe64
*cqe
= mlx5_cqwq_get_wqe(&cq
->wq
, i
);
795 static void mlx5e_destroy_cq(struct mlx5e_cq
*cq
)
797 mlx5_wq_destroy(&cq
->wq_ctrl
);
800 static int mlx5e_enable_cq(struct mlx5e_cq
*cq
, struct mlx5e_cq_param
*param
)
802 struct mlx5e_priv
*priv
= cq
->priv
;
803 struct mlx5_core_dev
*mdev
= priv
->mdev
;
804 struct mlx5_core_cq
*mcq
= &cq
->mcq
;
809 unsigned int irqn_not_used
;
813 inlen
= MLX5_ST_SZ_BYTES(create_cq_in
) +
814 sizeof(u64
) * cq
->wq_ctrl
.buf
.npages
;
815 in
= mlx5_vzalloc(inlen
);
819 cqc
= MLX5_ADDR_OF(create_cq_in
, in
, cq_context
);
821 memcpy(cqc
, param
->cqc
, sizeof(param
->cqc
));
823 mlx5_fill_page_array(&cq
->wq_ctrl
.buf
,
824 (__be64
*)MLX5_ADDR_OF(create_cq_in
, in
, pas
));
826 mlx5_vector2eqn(mdev
, param
->eq_ix
, &eqn
, &irqn_not_used
);
828 MLX5_SET(cqc
, cqc
, c_eqn
, eqn
);
829 MLX5_SET(cqc
, cqc
, uar_page
, mcq
->uar
->index
);
830 MLX5_SET(cqc
, cqc
, log_page_size
, cq
->wq_ctrl
.buf
.page_shift
-
831 MLX5_ADAPTER_PAGE_SHIFT
);
832 MLX5_SET64(cqc
, cqc
, dbr_addr
, cq
->wq_ctrl
.db
.dma
);
834 err
= mlx5_core_create_cq(mdev
, mcq
, in
, inlen
);
846 static void mlx5e_disable_cq(struct mlx5e_cq
*cq
)
848 struct mlx5e_priv
*priv
= cq
->priv
;
849 struct mlx5_core_dev
*mdev
= priv
->mdev
;
851 mlx5_core_destroy_cq(mdev
, &cq
->mcq
);
854 static int mlx5e_open_cq(struct mlx5e_channel
*c
,
855 struct mlx5e_cq_param
*param
,
857 u16 moderation_usecs
,
858 u16 moderation_frames
)
861 struct mlx5e_priv
*priv
= c
->priv
;
862 struct mlx5_core_dev
*mdev
= priv
->mdev
;
864 err
= mlx5e_create_cq(c
, param
, cq
);
868 err
= mlx5e_enable_cq(cq
, param
);
872 err
= mlx5_core_modify_cq_moderation(mdev
, &cq
->mcq
,
881 mlx5e_destroy_cq(cq
);
886 static void mlx5e_close_cq(struct mlx5e_cq
*cq
)
888 mlx5e_disable_cq(cq
);
889 mlx5e_destroy_cq(cq
);
892 static int mlx5e_get_cpu(struct mlx5e_priv
*priv
, int ix
)
894 return cpumask_first(priv
->mdev
->priv
.irq_info
[ix
].mask
);
897 static int mlx5e_open_tx_cqs(struct mlx5e_channel
*c
,
898 struct mlx5e_channel_param
*cparam
)
900 struct mlx5e_priv
*priv
= c
->priv
;
904 for (tc
= 0; tc
< c
->num_tc
; tc
++) {
905 err
= mlx5e_open_cq(c
, &cparam
->tx_cq
, &c
->sq
[tc
].cq
,
906 priv
->params
.tx_cq_moderation_usec
,
907 priv
->params
.tx_cq_moderation_pkts
);
909 goto err_close_tx_cqs
;
915 for (tc
--; tc
>= 0; tc
--)
916 mlx5e_close_cq(&c
->sq
[tc
].cq
);
921 static void mlx5e_close_tx_cqs(struct mlx5e_channel
*c
)
925 for (tc
= 0; tc
< c
->num_tc
; tc
++)
926 mlx5e_close_cq(&c
->sq
[tc
].cq
);
929 static int mlx5e_open_sqs(struct mlx5e_channel
*c
,
930 struct mlx5e_channel_param
*cparam
)
935 for (tc
= 0; tc
< c
->num_tc
; tc
++) {
936 err
= mlx5e_open_sq(c
, tc
, &cparam
->sq
, &c
->sq
[tc
]);
944 for (tc
--; tc
>= 0; tc
--)
945 mlx5e_close_sq(&c
->sq
[tc
]);
950 static void mlx5e_close_sqs(struct mlx5e_channel
*c
)
954 for (tc
= 0; tc
< c
->num_tc
; tc
++)
955 mlx5e_close_sq(&c
->sq
[tc
]);
958 static void mlx5e_build_channeltc_to_txq_map(struct mlx5e_priv
*priv
, int ix
)
962 for (i
= 0; i
< MLX5E_MAX_NUM_TC
; i
++)
963 priv
->channeltc_to_txq_map
[ix
][i
] =
964 ix
+ i
* priv
->params
.num_channels
;
967 static int mlx5e_open_channel(struct mlx5e_priv
*priv
, int ix
,
968 struct mlx5e_channel_param
*cparam
,
969 struct mlx5e_channel
**cp
)
971 struct net_device
*netdev
= priv
->netdev
;
972 int cpu
= mlx5e_get_cpu(priv
, ix
);
973 struct mlx5e_channel
*c
;
976 c
= kzalloc_node(sizeof(*c
), GFP_KERNEL
, cpu_to_node(cpu
));
983 c
->pdev
= &priv
->mdev
->pdev
->dev
;
984 c
->netdev
= priv
->netdev
;
985 c
->mkey_be
= cpu_to_be32(priv
->mr
.key
);
986 c
->num_tc
= priv
->params
.num_tc
;
988 mlx5e_build_channeltc_to_txq_map(priv
, ix
);
990 netif_napi_add(netdev
, &c
->napi
, mlx5e_napi_poll
, 64);
992 err
= mlx5e_open_tx_cqs(c
, cparam
);
996 err
= mlx5e_open_cq(c
, &cparam
->rx_cq
, &c
->rq
.cq
,
997 priv
->params
.rx_cq_moderation_usec
,
998 priv
->params
.rx_cq_moderation_pkts
);
1000 goto err_close_tx_cqs
;
1002 napi_enable(&c
->napi
);
1004 err
= mlx5e_open_sqs(c
, cparam
);
1006 goto err_disable_napi
;
1008 err
= mlx5e_open_rq(c
, &cparam
->rq
, &c
->rq
);
1012 netif_set_xps_queue(netdev
, get_cpu_mask(c
->cpu
), ix
);
1021 napi_disable(&c
->napi
);
1022 mlx5e_close_cq(&c
->rq
.cq
);
1025 mlx5e_close_tx_cqs(c
);
1028 netif_napi_del(&c
->napi
);
1029 napi_hash_del(&c
->napi
);
1035 static void mlx5e_close_channel(struct mlx5e_channel
*c
)
1037 mlx5e_close_rq(&c
->rq
);
1039 napi_disable(&c
->napi
);
1040 mlx5e_close_cq(&c
->rq
.cq
);
1041 mlx5e_close_tx_cqs(c
);
1042 netif_napi_del(&c
->napi
);
1044 napi_hash_del(&c
->napi
);
1050 static void mlx5e_build_rq_param(struct mlx5e_priv
*priv
,
1051 struct mlx5e_rq_param
*param
)
1053 void *rqc
= param
->rqc
;
1054 void *wq
= MLX5_ADDR_OF(rqc
, rqc
, wq
);
1056 MLX5_SET(wq
, wq
, wq_type
, MLX5_WQ_TYPE_LINKED_LIST
);
1057 MLX5_SET(wq
, wq
, end_padding_mode
, MLX5_WQ_END_PAD_MODE_ALIGN
);
1058 MLX5_SET(wq
, wq
, log_wq_stride
, ilog2(sizeof(struct mlx5e_rx_wqe
)));
1059 MLX5_SET(wq
, wq
, log_wq_sz
, priv
->params
.log_rq_size
);
1060 MLX5_SET(wq
, wq
, pd
, priv
->pdn
);
1062 param
->wq
.buf_numa_node
= dev_to_node(&priv
->mdev
->pdev
->dev
);
1063 param
->wq
.linear
= 1;
1066 static void mlx5e_build_sq_param(struct mlx5e_priv
*priv
,
1067 struct mlx5e_sq_param
*param
)
1069 void *sqc
= param
->sqc
;
1070 void *wq
= MLX5_ADDR_OF(sqc
, sqc
, wq
);
1072 MLX5_SET(wq
, wq
, log_wq_sz
, priv
->params
.log_sq_size
);
1073 MLX5_SET(wq
, wq
, log_wq_stride
, ilog2(MLX5_SEND_WQE_BB
));
1074 MLX5_SET(wq
, wq
, pd
, priv
->pdn
);
1076 param
->wq
.buf_numa_node
= dev_to_node(&priv
->mdev
->pdev
->dev
);
1077 param
->max_inline
= priv
->params
.tx_max_inline
;
1080 static void mlx5e_build_common_cq_param(struct mlx5e_priv
*priv
,
1081 struct mlx5e_cq_param
*param
)
1083 void *cqc
= param
->cqc
;
1085 MLX5_SET(cqc
, cqc
, uar_page
, priv
->cq_uar
.index
);
1088 static void mlx5e_build_rx_cq_param(struct mlx5e_priv
*priv
,
1089 struct mlx5e_cq_param
*param
)
1091 void *cqc
= param
->cqc
;
1093 MLX5_SET(cqc
, cqc
, log_cq_size
, priv
->params
.log_rq_size
);
1095 mlx5e_build_common_cq_param(priv
, param
);
1098 static void mlx5e_build_tx_cq_param(struct mlx5e_priv
*priv
,
1099 struct mlx5e_cq_param
*param
)
1101 void *cqc
= param
->cqc
;
1103 MLX5_SET(cqc
, cqc
, log_cq_size
, priv
->params
.log_sq_size
);
1105 mlx5e_build_common_cq_param(priv
, param
);
1108 static void mlx5e_build_channel_param(struct mlx5e_priv
*priv
,
1109 struct mlx5e_channel_param
*cparam
)
1111 memset(cparam
, 0, sizeof(*cparam
));
1113 mlx5e_build_rq_param(priv
, &cparam
->rq
);
1114 mlx5e_build_sq_param(priv
, &cparam
->sq
);
1115 mlx5e_build_rx_cq_param(priv
, &cparam
->rx_cq
);
1116 mlx5e_build_tx_cq_param(priv
, &cparam
->tx_cq
);
1119 static int mlx5e_open_channels(struct mlx5e_priv
*priv
)
1121 struct mlx5e_channel_param cparam
;
1122 int nch
= priv
->params
.num_channels
;
1127 priv
->channel
= kcalloc(nch
, sizeof(struct mlx5e_channel
*),
1130 priv
->txq_to_sq_map
= kcalloc(nch
* priv
->params
.num_tc
,
1131 sizeof(struct mlx5e_sq
*), GFP_KERNEL
);
1133 if (!priv
->channel
|| !priv
->txq_to_sq_map
)
1134 goto err_free_txq_to_sq_map
;
1136 mlx5e_build_channel_param(priv
, &cparam
);
1137 for (i
= 0; i
< nch
; i
++) {
1138 err
= mlx5e_open_channel(priv
, i
, &cparam
, &priv
->channel
[i
]);
1140 goto err_close_channels
;
1143 for (j
= 0; j
< nch
; j
++) {
1144 err
= mlx5e_wait_for_min_rx_wqes(&priv
->channel
[j
]->rq
);
1146 goto err_close_channels
;
1152 for (i
--; i
>= 0; i
--)
1153 mlx5e_close_channel(priv
->channel
[i
]);
1155 err_free_txq_to_sq_map
:
1156 kfree(priv
->txq_to_sq_map
);
1157 kfree(priv
->channel
);
1162 static void mlx5e_close_channels(struct mlx5e_priv
*priv
)
1166 for (i
= 0; i
< priv
->params
.num_channels
; i
++)
1167 mlx5e_close_channel(priv
->channel
[i
]);
1169 kfree(priv
->txq_to_sq_map
);
1170 kfree(priv
->channel
);
1173 static int mlx5e_rx_hash_fn(int hfunc
)
1175 return (hfunc
== ETH_RSS_HASH_TOP
) ?
1176 MLX5_RX_HASH_FN_TOEPLITZ
:
1177 MLX5_RX_HASH_FN_INVERTED_XOR8
;
1180 static int mlx5e_bits_invert(unsigned long a
, int size
)
1185 for (i
= 0; i
< size
; i
++)
1186 inv
|= (test_bit(size
- i
- 1, &a
) ? 1 : 0) << i
;
1191 static void mlx5e_fill_indir_rqt_rqns(struct mlx5e_priv
*priv
, void *rqtc
)
1195 for (i
= 0; i
< MLX5E_INDIR_RQT_SIZE
; i
++) {
1198 if (priv
->params
.rss_hfunc
== ETH_RSS_HASH_XOR
)
1199 ix
= mlx5e_bits_invert(i
, MLX5E_LOG_INDIR_RQT_SIZE
);
1201 ix
= priv
->params
.indirection_rqt
[ix
];
1202 MLX5_SET(rqtc
, rqtc
, rq_num
[i
],
1203 test_bit(MLX5E_STATE_OPENED
, &priv
->state
) ?
1204 priv
->channel
[ix
]->rq
.rqn
:
1209 static void mlx5e_fill_rqt_rqns(struct mlx5e_priv
*priv
, void *rqtc
,
1210 enum mlx5e_rqt_ix rqt_ix
)
1214 case MLX5E_INDIRECTION_RQT
:
1215 mlx5e_fill_indir_rqt_rqns(priv
, rqtc
);
1219 default: /* MLX5E_SINGLE_RQ_RQT */
1220 MLX5_SET(rqtc
, rqtc
, rq_num
[0],
1221 test_bit(MLX5E_STATE_OPENED
, &priv
->state
) ?
1222 priv
->channel
[0]->rq
.rqn
:
1229 static int mlx5e_create_rqt(struct mlx5e_priv
*priv
, enum mlx5e_rqt_ix rqt_ix
)
1231 struct mlx5_core_dev
*mdev
= priv
->mdev
;
1238 sz
= (rqt_ix
== MLX5E_SINGLE_RQ_RQT
) ? 1 : MLX5E_INDIR_RQT_SIZE
;
1240 inlen
= MLX5_ST_SZ_BYTES(create_rqt_in
) + sizeof(u32
) * sz
;
1241 in
= mlx5_vzalloc(inlen
);
1245 rqtc
= MLX5_ADDR_OF(create_rqt_in
, in
, rqt_context
);
1247 MLX5_SET(rqtc
, rqtc
, rqt_actual_size
, sz
);
1248 MLX5_SET(rqtc
, rqtc
, rqt_max_size
, sz
);
1250 mlx5e_fill_rqt_rqns(priv
, rqtc
, rqt_ix
);
1252 err
= mlx5_core_create_rqt(mdev
, in
, inlen
, &priv
->rqtn
[rqt_ix
]);
1259 int mlx5e_redirect_rqt(struct mlx5e_priv
*priv
, enum mlx5e_rqt_ix rqt_ix
)
1261 struct mlx5_core_dev
*mdev
= priv
->mdev
;
1268 sz
= (rqt_ix
== MLX5E_SINGLE_RQ_RQT
) ? 1 : MLX5E_INDIR_RQT_SIZE
;
1270 inlen
= MLX5_ST_SZ_BYTES(modify_rqt_in
) + sizeof(u32
) * sz
;
1271 in
= mlx5_vzalloc(inlen
);
1275 rqtc
= MLX5_ADDR_OF(modify_rqt_in
, in
, ctx
);
1277 MLX5_SET(rqtc
, rqtc
, rqt_actual_size
, sz
);
1279 mlx5e_fill_rqt_rqns(priv
, rqtc
, rqt_ix
);
1281 MLX5_SET(modify_rqt_in
, in
, bitmask
.rqn_list
, 1);
1283 err
= mlx5_core_modify_rqt(mdev
, priv
->rqtn
[rqt_ix
], in
, inlen
);
1290 static void mlx5e_destroy_rqt(struct mlx5e_priv
*priv
, enum mlx5e_rqt_ix rqt_ix
)
1292 mlx5_core_destroy_rqt(priv
->mdev
, priv
->rqtn
[rqt_ix
]);
1295 static void mlx5e_redirect_rqts(struct mlx5e_priv
*priv
)
1297 mlx5e_redirect_rqt(priv
, MLX5E_INDIRECTION_RQT
);
1298 mlx5e_redirect_rqt(priv
, MLX5E_SINGLE_RQ_RQT
);
1301 static void mlx5e_build_tir_ctx_lro(void *tirc
, struct mlx5e_priv
*priv
)
1303 if (!priv
->params
.lro_en
)
1306 #define ROUGH_MAX_L2_L3_HDR_SZ 256
1308 MLX5_SET(tirc
, tirc
, lro_enable_mask
,
1309 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO
|
1310 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO
);
1311 MLX5_SET(tirc
, tirc
, lro_max_ip_payload_size
,
1312 (priv
->params
.lro_wqe_sz
-
1313 ROUGH_MAX_L2_L3_HDR_SZ
) >> 8);
1314 MLX5_SET(tirc
, tirc
, lro_timeout_period_usecs
,
1315 MLX5_CAP_ETH(priv
->mdev
,
1316 lro_timer_supported_periods
[2]));
1319 void mlx5e_build_tir_ctx_hash(void *tirc
, struct mlx5e_priv
*priv
)
1321 MLX5_SET(tirc
, tirc
, rx_hash_fn
,
1322 mlx5e_rx_hash_fn(priv
->params
.rss_hfunc
));
1323 if (priv
->params
.rss_hfunc
== ETH_RSS_HASH_TOP
) {
1324 void *rss_key
= MLX5_ADDR_OF(tirc
, tirc
,
1325 rx_hash_toeplitz_key
);
1326 size_t len
= MLX5_FLD_SZ_BYTES(tirc
,
1327 rx_hash_toeplitz_key
);
1329 MLX5_SET(tirc
, tirc
, rx_hash_symmetric
, 1);
1330 memcpy(rss_key
, priv
->params
.toeplitz_hash_key
, len
);
1334 static int mlx5e_modify_tirs_lro(struct mlx5e_priv
*priv
)
1336 struct mlx5_core_dev
*mdev
= priv
->mdev
;
1344 inlen
= MLX5_ST_SZ_BYTES(modify_tir_in
);
1345 in
= mlx5_vzalloc(inlen
);
1349 MLX5_SET(modify_tir_in
, in
, bitmask
.lro
, 1);
1350 tirc
= MLX5_ADDR_OF(modify_tir_in
, in
, ctx
);
1352 mlx5e_build_tir_ctx_lro(tirc
, priv
);
1354 for (tt
= 0; tt
< MLX5E_NUM_TT
; tt
++) {
1355 err
= mlx5_core_modify_tir(mdev
, priv
->tirn
[tt
], in
, inlen
);
1365 static int mlx5e_refresh_tir_self_loopback_enable(struct mlx5_core_dev
*mdev
,
1372 inlen
= MLX5_ST_SZ_BYTES(modify_tir_in
);
1373 in
= mlx5_vzalloc(inlen
);
1377 MLX5_SET(modify_tir_in
, in
, bitmask
.self_lb_en
, 1);
1379 err
= mlx5_core_modify_tir(mdev
, tirn
, in
, inlen
);
1386 static int mlx5e_refresh_tirs_self_loopback_enable(struct mlx5e_priv
*priv
)
1391 for (i
= 0; i
< MLX5E_NUM_TT
; i
++) {
1392 err
= mlx5e_refresh_tir_self_loopback_enable(priv
->mdev
,
1401 static int mlx5e_set_dev_port_mtu(struct net_device
*netdev
)
1403 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
1404 struct mlx5_core_dev
*mdev
= priv
->mdev
;
1408 err
= mlx5_set_port_mtu(mdev
, MLX5E_SW2HW_MTU(netdev
->mtu
), 1);
1412 mlx5_query_port_oper_mtu(mdev
, &hw_mtu
, 1);
1414 if (MLX5E_HW2SW_MTU(hw_mtu
) != netdev
->mtu
)
1415 netdev_warn(netdev
, "%s: Port MTU %d is different than netdev mtu %d\n",
1416 __func__
, MLX5E_HW2SW_MTU(hw_mtu
), netdev
->mtu
);
1418 netdev
->mtu
= MLX5E_HW2SW_MTU(hw_mtu
);
1422 int mlx5e_open_locked(struct net_device
*netdev
)
1424 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
1428 set_bit(MLX5E_STATE_OPENED
, &priv
->state
);
1430 num_txqs
= priv
->params
.num_channels
* priv
->params
.num_tc
;
1431 netif_set_real_num_tx_queues(netdev
, num_txqs
);
1432 netif_set_real_num_rx_queues(netdev
, priv
->params
.num_channels
);
1434 err
= mlx5e_set_dev_port_mtu(netdev
);
1436 goto err_clear_state_opened_flag
;
1438 err
= mlx5e_open_channels(priv
);
1440 netdev_err(netdev
, "%s: mlx5e_open_channels failed, %d\n",
1442 goto err_clear_state_opened_flag
;
1445 err
= mlx5e_refresh_tirs_self_loopback_enable(priv
);
1447 netdev_err(netdev
, "%s: mlx5e_refresh_tirs_self_loopback_enable failed, %d\n",
1449 goto err_close_channels
;
1452 mlx5e_update_carrier(priv
);
1453 mlx5e_redirect_rqts(priv
);
1454 mlx5e_timestamp_init(priv
);
1456 schedule_delayed_work(&priv
->update_stats_work
, 0);
1461 mlx5e_close_channels(priv
);
1462 err_clear_state_opened_flag
:
1463 clear_bit(MLX5E_STATE_OPENED
, &priv
->state
);
1467 static int mlx5e_open(struct net_device
*netdev
)
1469 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
1472 mutex_lock(&priv
->state_lock
);
1473 err
= mlx5e_open_locked(netdev
);
1474 mutex_unlock(&priv
->state_lock
);
1479 int mlx5e_close_locked(struct net_device
*netdev
)
1481 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
1483 /* May already be CLOSED in case a previous configuration operation
1484 * (e.g RX/TX queue size change) that involves close&open failed.
1486 if (!test_bit(MLX5E_STATE_OPENED
, &priv
->state
))
1489 clear_bit(MLX5E_STATE_OPENED
, &priv
->state
);
1491 mlx5e_timestamp_cleanup(priv
);
1492 mlx5e_redirect_rqts(priv
);
1493 netif_carrier_off(priv
->netdev
);
1494 mlx5e_close_channels(priv
);
1499 static int mlx5e_close(struct net_device
*netdev
)
1501 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
1504 mutex_lock(&priv
->state_lock
);
1505 err
= mlx5e_close_locked(netdev
);
1506 mutex_unlock(&priv
->state_lock
);
1511 static int mlx5e_create_drop_rq(struct mlx5e_priv
*priv
,
1512 struct mlx5e_rq
*rq
,
1513 struct mlx5e_rq_param
*param
)
1515 struct mlx5_core_dev
*mdev
= priv
->mdev
;
1516 void *rqc
= param
->rqc
;
1517 void *rqc_wq
= MLX5_ADDR_OF(rqc
, rqc
, wq
);
1520 param
->wq
.db_numa_node
= param
->wq
.buf_numa_node
;
1522 err
= mlx5_wq_ll_create(mdev
, ¶m
->wq
, rqc_wq
, &rq
->wq
,
1532 static int mlx5e_create_drop_cq(struct mlx5e_priv
*priv
,
1533 struct mlx5e_cq
*cq
,
1534 struct mlx5e_cq_param
*param
)
1536 struct mlx5_core_dev
*mdev
= priv
->mdev
;
1537 struct mlx5_core_cq
*mcq
= &cq
->mcq
;
1542 err
= mlx5_cqwq_create(mdev
, ¶m
->wq
, param
->cqc
, &cq
->wq
,
1547 mlx5_vector2eqn(mdev
, param
->eq_ix
, &eqn_not_used
, &irqn
);
1550 mcq
->set_ci_db
= cq
->wq_ctrl
.db
.db
;
1551 mcq
->arm_db
= cq
->wq_ctrl
.db
.db
+ 1;
1552 *mcq
->set_ci_db
= 0;
1554 mcq
->vector
= param
->eq_ix
;
1555 mcq
->comp
= mlx5e_completion_event
;
1556 mcq
->event
= mlx5e_cq_error_event
;
1558 mcq
->uar
= &priv
->cq_uar
;
1565 static int mlx5e_open_drop_rq(struct mlx5e_priv
*priv
)
1567 struct mlx5e_cq_param cq_param
;
1568 struct mlx5e_rq_param rq_param
;
1569 struct mlx5e_rq
*rq
= &priv
->drop_rq
;
1570 struct mlx5e_cq
*cq
= &priv
->drop_rq
.cq
;
1573 memset(&cq_param
, 0, sizeof(cq_param
));
1574 memset(&rq_param
, 0, sizeof(rq_param
));
1575 mlx5e_build_rx_cq_param(priv
, &cq_param
);
1576 mlx5e_build_rq_param(priv
, &rq_param
);
1578 err
= mlx5e_create_drop_cq(priv
, cq
, &cq_param
);
1582 err
= mlx5e_enable_cq(cq
, &cq_param
);
1584 goto err_destroy_cq
;
1586 err
= mlx5e_create_drop_rq(priv
, rq
, &rq_param
);
1588 goto err_disable_cq
;
1590 err
= mlx5e_enable_rq(rq
, &rq_param
);
1592 goto err_destroy_rq
;
1597 mlx5e_destroy_rq(&priv
->drop_rq
);
1600 mlx5e_disable_cq(&priv
->drop_rq
.cq
);
1603 mlx5e_destroy_cq(&priv
->drop_rq
.cq
);
1608 static void mlx5e_close_drop_rq(struct mlx5e_priv
*priv
)
1610 mlx5e_disable_rq(&priv
->drop_rq
);
1611 mlx5e_destroy_rq(&priv
->drop_rq
);
1612 mlx5e_disable_cq(&priv
->drop_rq
.cq
);
1613 mlx5e_destroy_cq(&priv
->drop_rq
.cq
);
1616 static int mlx5e_create_tis(struct mlx5e_priv
*priv
, int tc
)
1618 struct mlx5_core_dev
*mdev
= priv
->mdev
;
1619 u32 in
[MLX5_ST_SZ_DW(create_tis_in
)];
1620 void *tisc
= MLX5_ADDR_OF(create_tis_in
, in
, ctx
);
1622 memset(in
, 0, sizeof(in
));
1624 MLX5_SET(tisc
, tisc
, prio
, tc
);
1625 MLX5_SET(tisc
, tisc
, transport_domain
, priv
->tdn
);
1627 return mlx5_core_create_tis(mdev
, in
, sizeof(in
), &priv
->tisn
[tc
]);
1630 static void mlx5e_destroy_tis(struct mlx5e_priv
*priv
, int tc
)
1632 mlx5_core_destroy_tis(priv
->mdev
, priv
->tisn
[tc
]);
1635 static int mlx5e_create_tises(struct mlx5e_priv
*priv
)
1640 for (tc
= 0; tc
< priv
->params
.num_tc
; tc
++) {
1641 err
= mlx5e_create_tis(priv
, tc
);
1643 goto err_close_tises
;
1649 for (tc
--; tc
>= 0; tc
--)
1650 mlx5e_destroy_tis(priv
, tc
);
1655 static void mlx5e_destroy_tises(struct mlx5e_priv
*priv
)
1659 for (tc
= 0; tc
< priv
->params
.num_tc
; tc
++)
1660 mlx5e_destroy_tis(priv
, tc
);
1663 static void mlx5e_build_tir_ctx(struct mlx5e_priv
*priv
, u32
*tirc
, int tt
)
1665 void *hfso
= MLX5_ADDR_OF(tirc
, tirc
, rx_hash_field_selector_outer
);
1667 MLX5_SET(tirc
, tirc
, transport_domain
, priv
->tdn
);
1669 #define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\
1670 MLX5_HASH_FIELD_SEL_DST_IP)
1672 #define MLX5_HASH_IP_L4PORTS (MLX5_HASH_FIELD_SEL_SRC_IP |\
1673 MLX5_HASH_FIELD_SEL_DST_IP |\
1674 MLX5_HASH_FIELD_SEL_L4_SPORT |\
1675 MLX5_HASH_FIELD_SEL_L4_DPORT)
1677 #define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\
1678 MLX5_HASH_FIELD_SEL_DST_IP |\
1679 MLX5_HASH_FIELD_SEL_IPSEC_SPI)
1681 mlx5e_build_tir_ctx_lro(tirc
, priv
);
1683 MLX5_SET(tirc
, tirc
, disp_type
, MLX5_TIRC_DISP_TYPE_INDIRECT
);
1687 MLX5_SET(tirc
, tirc
, indirect_table
,
1688 priv
->rqtn
[MLX5E_SINGLE_RQ_RQT
]);
1689 MLX5_SET(tirc
, tirc
, rx_hash_fn
, MLX5_RX_HASH_FN_INVERTED_XOR8
);
1692 MLX5_SET(tirc
, tirc
, indirect_table
,
1693 priv
->rqtn
[MLX5E_INDIRECTION_RQT
]);
1694 mlx5e_build_tir_ctx_hash(tirc
, priv
);
1699 case MLX5E_TT_IPV4_TCP
:
1700 MLX5_SET(rx_hash_field_select
, hfso
, l3_prot_type
,
1701 MLX5_L3_PROT_TYPE_IPV4
);
1702 MLX5_SET(rx_hash_field_select
, hfso
, l4_prot_type
,
1703 MLX5_L4_PROT_TYPE_TCP
);
1704 MLX5_SET(rx_hash_field_select
, hfso
, selected_fields
,
1705 MLX5_HASH_IP_L4PORTS
);
1708 case MLX5E_TT_IPV6_TCP
:
1709 MLX5_SET(rx_hash_field_select
, hfso
, l3_prot_type
,
1710 MLX5_L3_PROT_TYPE_IPV6
);
1711 MLX5_SET(rx_hash_field_select
, hfso
, l4_prot_type
,
1712 MLX5_L4_PROT_TYPE_TCP
);
1713 MLX5_SET(rx_hash_field_select
, hfso
, selected_fields
,
1714 MLX5_HASH_IP_L4PORTS
);
1717 case MLX5E_TT_IPV4_UDP
:
1718 MLX5_SET(rx_hash_field_select
, hfso
, l3_prot_type
,
1719 MLX5_L3_PROT_TYPE_IPV4
);
1720 MLX5_SET(rx_hash_field_select
, hfso
, l4_prot_type
,
1721 MLX5_L4_PROT_TYPE_UDP
);
1722 MLX5_SET(rx_hash_field_select
, hfso
, selected_fields
,
1723 MLX5_HASH_IP_L4PORTS
);
1726 case MLX5E_TT_IPV6_UDP
:
1727 MLX5_SET(rx_hash_field_select
, hfso
, l3_prot_type
,
1728 MLX5_L3_PROT_TYPE_IPV6
);
1729 MLX5_SET(rx_hash_field_select
, hfso
, l4_prot_type
,
1730 MLX5_L4_PROT_TYPE_UDP
);
1731 MLX5_SET(rx_hash_field_select
, hfso
, selected_fields
,
1732 MLX5_HASH_IP_L4PORTS
);
1735 case MLX5E_TT_IPV4_IPSEC_AH
:
1736 MLX5_SET(rx_hash_field_select
, hfso
, l3_prot_type
,
1737 MLX5_L3_PROT_TYPE_IPV4
);
1738 MLX5_SET(rx_hash_field_select
, hfso
, selected_fields
,
1739 MLX5_HASH_IP_IPSEC_SPI
);
1742 case MLX5E_TT_IPV6_IPSEC_AH
:
1743 MLX5_SET(rx_hash_field_select
, hfso
, l3_prot_type
,
1744 MLX5_L3_PROT_TYPE_IPV6
);
1745 MLX5_SET(rx_hash_field_select
, hfso
, selected_fields
,
1746 MLX5_HASH_IP_IPSEC_SPI
);
1749 case MLX5E_TT_IPV4_IPSEC_ESP
:
1750 MLX5_SET(rx_hash_field_select
, hfso
, l3_prot_type
,
1751 MLX5_L3_PROT_TYPE_IPV4
);
1752 MLX5_SET(rx_hash_field_select
, hfso
, selected_fields
,
1753 MLX5_HASH_IP_IPSEC_SPI
);
1756 case MLX5E_TT_IPV6_IPSEC_ESP
:
1757 MLX5_SET(rx_hash_field_select
, hfso
, l3_prot_type
,
1758 MLX5_L3_PROT_TYPE_IPV6
);
1759 MLX5_SET(rx_hash_field_select
, hfso
, selected_fields
,
1760 MLX5_HASH_IP_IPSEC_SPI
);
1764 MLX5_SET(rx_hash_field_select
, hfso
, l3_prot_type
,
1765 MLX5_L3_PROT_TYPE_IPV4
);
1766 MLX5_SET(rx_hash_field_select
, hfso
, selected_fields
,
1771 MLX5_SET(rx_hash_field_select
, hfso
, l3_prot_type
,
1772 MLX5_L3_PROT_TYPE_IPV6
);
1773 MLX5_SET(rx_hash_field_select
, hfso
, selected_fields
,
1779 static int mlx5e_create_tir(struct mlx5e_priv
*priv
, int tt
)
1781 struct mlx5_core_dev
*mdev
= priv
->mdev
;
1787 inlen
= MLX5_ST_SZ_BYTES(create_tir_in
);
1788 in
= mlx5_vzalloc(inlen
);
1792 tirc
= MLX5_ADDR_OF(create_tir_in
, in
, ctx
);
1794 mlx5e_build_tir_ctx(priv
, tirc
, tt
);
1796 err
= mlx5_core_create_tir(mdev
, in
, inlen
, &priv
->tirn
[tt
]);
1803 static void mlx5e_destroy_tir(struct mlx5e_priv
*priv
, int tt
)
1805 mlx5_core_destroy_tir(priv
->mdev
, priv
->tirn
[tt
]);
1808 static int mlx5e_create_tirs(struct mlx5e_priv
*priv
)
1813 for (i
= 0; i
< MLX5E_NUM_TT
; i
++) {
1814 err
= mlx5e_create_tir(priv
, i
);
1816 goto err_destroy_tirs
;
1822 for (i
--; i
>= 0; i
--)
1823 mlx5e_destroy_tir(priv
, i
);
1828 static void mlx5e_destroy_tirs(struct mlx5e_priv
*priv
)
1832 for (i
= 0; i
< MLX5E_NUM_TT
; i
++)
1833 mlx5e_destroy_tir(priv
, i
);
1836 static struct rtnl_link_stats64
*
1837 mlx5e_get_stats(struct net_device
*dev
, struct rtnl_link_stats64
*stats
)
1839 struct mlx5e_priv
*priv
= netdev_priv(dev
);
1840 struct mlx5e_vport_stats
*vstats
= &priv
->stats
.vport
;
1842 stats
->rx_packets
= vstats
->rx_packets
;
1843 stats
->rx_bytes
= vstats
->rx_bytes
;
1844 stats
->tx_packets
= vstats
->tx_packets
;
1845 stats
->tx_bytes
= vstats
->tx_bytes
;
1846 stats
->multicast
= vstats
->rx_multicast_packets
+
1847 vstats
->tx_multicast_packets
;
1848 stats
->tx_errors
= vstats
->tx_error_packets
;
1849 stats
->rx_errors
= vstats
->rx_error_packets
;
1850 stats
->tx_dropped
= vstats
->tx_queue_dropped
;
1851 stats
->rx_crc_errors
= 0;
1852 stats
->rx_length_errors
= 0;
1857 static void mlx5e_set_rx_mode(struct net_device
*dev
)
1859 struct mlx5e_priv
*priv
= netdev_priv(dev
);
1861 schedule_work(&priv
->set_rx_mode_work
);
1864 static int mlx5e_set_mac(struct net_device
*netdev
, void *addr
)
1866 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
1867 struct sockaddr
*saddr
= addr
;
1869 if (!is_valid_ether_addr(saddr
->sa_data
))
1870 return -EADDRNOTAVAIL
;
1872 netif_addr_lock_bh(netdev
);
1873 ether_addr_copy(netdev
->dev_addr
, saddr
->sa_data
);
1874 netif_addr_unlock_bh(netdev
);
1876 schedule_work(&priv
->set_rx_mode_work
);
1881 static int mlx5e_set_features(struct net_device
*netdev
,
1882 netdev_features_t features
)
1884 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
1886 netdev_features_t changes
= features
^ netdev
->features
;
1888 mutex_lock(&priv
->state_lock
);
1890 if (changes
& NETIF_F_LRO
) {
1891 bool was_opened
= test_bit(MLX5E_STATE_OPENED
, &priv
->state
);
1894 mlx5e_close_locked(priv
->netdev
);
1896 priv
->params
.lro_en
= !!(features
& NETIF_F_LRO
);
1897 err
= mlx5e_modify_tirs_lro(priv
);
1899 mlx5_core_warn(priv
->mdev
, "lro modify failed, %d\n",
1903 err
= mlx5e_open_locked(priv
->netdev
);
1906 mutex_unlock(&priv
->state_lock
);
1908 if (changes
& NETIF_F_HW_VLAN_CTAG_FILTER
) {
1909 if (features
& NETIF_F_HW_VLAN_CTAG_FILTER
)
1910 mlx5e_enable_vlan_filter(priv
);
1912 mlx5e_disable_vlan_filter(priv
);
1918 static int mlx5e_change_mtu(struct net_device
*netdev
, int new_mtu
)
1920 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
1921 struct mlx5_core_dev
*mdev
= priv
->mdev
;
1926 mlx5_query_port_max_mtu(mdev
, &max_mtu
, 1);
1928 max_mtu
= MLX5E_HW2SW_MTU(max_mtu
);
1930 if (new_mtu
> max_mtu
) {
1932 "%s: Bad MTU (%d) > (%d) Max\n",
1933 __func__
, new_mtu
, max_mtu
);
1937 mutex_lock(&priv
->state_lock
);
1939 was_opened
= test_bit(MLX5E_STATE_OPENED
, &priv
->state
);
1941 mlx5e_close_locked(netdev
);
1943 netdev
->mtu
= new_mtu
;
1946 err
= mlx5e_open_locked(netdev
);
1948 mutex_unlock(&priv
->state_lock
);
1953 static int mlx5e_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
1957 return mlx5e_hwstamp_set(dev
, ifr
);
1959 return mlx5e_hwstamp_get(dev
, ifr
);
1965 static int mlx5e_set_vf_mac(struct net_device
*dev
, int vf
, u8
*mac
)
1967 struct mlx5e_priv
*priv
= netdev_priv(dev
);
1968 struct mlx5_core_dev
*mdev
= priv
->mdev
;
1970 return mlx5_eswitch_set_vport_mac(mdev
->priv
.eswitch
, vf
+ 1, mac
);
1973 static int mlx5e_set_vf_vlan(struct net_device
*dev
, int vf
, u16 vlan
, u8 qos
)
1975 struct mlx5e_priv
*priv
= netdev_priv(dev
);
1976 struct mlx5_core_dev
*mdev
= priv
->mdev
;
1978 return mlx5_eswitch_set_vport_vlan(mdev
->priv
.eswitch
, vf
+ 1,
1982 static int mlx5_vport_link2ifla(u8 esw_link
)
1985 case MLX5_ESW_VPORT_ADMIN_STATE_DOWN
:
1986 return IFLA_VF_LINK_STATE_DISABLE
;
1987 case MLX5_ESW_VPORT_ADMIN_STATE_UP
:
1988 return IFLA_VF_LINK_STATE_ENABLE
;
1990 return IFLA_VF_LINK_STATE_AUTO
;
1993 static int mlx5_ifla_link2vport(u8 ifla_link
)
1995 switch (ifla_link
) {
1996 case IFLA_VF_LINK_STATE_DISABLE
:
1997 return MLX5_ESW_VPORT_ADMIN_STATE_DOWN
;
1998 case IFLA_VF_LINK_STATE_ENABLE
:
1999 return MLX5_ESW_VPORT_ADMIN_STATE_UP
;
2001 return MLX5_ESW_VPORT_ADMIN_STATE_AUTO
;
2004 static int mlx5e_set_vf_link_state(struct net_device
*dev
, int vf
,
2007 struct mlx5e_priv
*priv
= netdev_priv(dev
);
2008 struct mlx5_core_dev
*mdev
= priv
->mdev
;
2010 return mlx5_eswitch_set_vport_state(mdev
->priv
.eswitch
, vf
+ 1,
2011 mlx5_ifla_link2vport(link_state
));
2014 static int mlx5e_get_vf_config(struct net_device
*dev
,
2015 int vf
, struct ifla_vf_info
*ivi
)
2017 struct mlx5e_priv
*priv
= netdev_priv(dev
);
2018 struct mlx5_core_dev
*mdev
= priv
->mdev
;
2021 err
= mlx5_eswitch_get_vport_config(mdev
->priv
.eswitch
, vf
+ 1, ivi
);
2024 ivi
->linkstate
= mlx5_vport_link2ifla(ivi
->linkstate
);
2028 static int mlx5e_get_vf_stats(struct net_device
*dev
,
2029 int vf
, struct ifla_vf_stats
*vf_stats
)
2031 struct mlx5e_priv
*priv
= netdev_priv(dev
);
2032 struct mlx5_core_dev
*mdev
= priv
->mdev
;
2034 return mlx5_eswitch_get_vport_stats(mdev
->priv
.eswitch
, vf
+ 1,
2038 static const struct net_device_ops mlx5e_netdev_ops_basic
= {
2039 .ndo_open
= mlx5e_open
,
2040 .ndo_stop
= mlx5e_close
,
2041 .ndo_start_xmit
= mlx5e_xmit
,
2042 .ndo_get_stats64
= mlx5e_get_stats
,
2043 .ndo_set_rx_mode
= mlx5e_set_rx_mode
,
2044 .ndo_set_mac_address
= mlx5e_set_mac
,
2045 .ndo_vlan_rx_add_vid
= mlx5e_vlan_rx_add_vid
,
2046 .ndo_vlan_rx_kill_vid
= mlx5e_vlan_rx_kill_vid
,
2047 .ndo_set_features
= mlx5e_set_features
,
2048 .ndo_change_mtu
= mlx5e_change_mtu
,
2049 .ndo_do_ioctl
= mlx5e_ioctl
,
2052 static const struct net_device_ops mlx5e_netdev_ops_sriov
= {
2053 .ndo_open
= mlx5e_open
,
2054 .ndo_stop
= mlx5e_close
,
2055 .ndo_start_xmit
= mlx5e_xmit
,
2056 .ndo_get_stats64
= mlx5e_get_stats
,
2057 .ndo_set_rx_mode
= mlx5e_set_rx_mode
,
2058 .ndo_set_mac_address
= mlx5e_set_mac
,
2059 .ndo_vlan_rx_add_vid
= mlx5e_vlan_rx_add_vid
,
2060 .ndo_vlan_rx_kill_vid
= mlx5e_vlan_rx_kill_vid
,
2061 .ndo_set_features
= mlx5e_set_features
,
2062 .ndo_change_mtu
= mlx5e_change_mtu
,
2063 .ndo_do_ioctl
= mlx5e_ioctl
,
2064 .ndo_set_vf_mac
= mlx5e_set_vf_mac
,
2065 .ndo_set_vf_vlan
= mlx5e_set_vf_vlan
,
2066 .ndo_get_vf_config
= mlx5e_get_vf_config
,
2067 .ndo_set_vf_link_state
= mlx5e_set_vf_link_state
,
2068 .ndo_get_vf_stats
= mlx5e_get_vf_stats
,
2071 static int mlx5e_check_required_hca_cap(struct mlx5_core_dev
*mdev
)
2073 if (MLX5_CAP_GEN(mdev
, port_type
) != MLX5_CAP_PORT_TYPE_ETH
)
2075 if (!MLX5_CAP_GEN(mdev
, eth_net_offloads
) ||
2076 !MLX5_CAP_GEN(mdev
, nic_flow_table
) ||
2077 !MLX5_CAP_ETH(mdev
, csum_cap
) ||
2078 !MLX5_CAP_ETH(mdev
, max_lso_cap
) ||
2079 !MLX5_CAP_ETH(mdev
, vlan_cap
) ||
2080 !MLX5_CAP_ETH(mdev
, rss_ind_tbl_cap
) ||
2081 MLX5_CAP_FLOWTABLE(mdev
,
2082 flow_table_properties_nic_receive
.max_ft_level
)
2084 mlx5_core_warn(mdev
,
2085 "Not creating net device, some required device capabilities are missing\n");
2088 if (!MLX5_CAP_ETH(mdev
, self_lb_en_modifiable
))
2089 mlx5_core_warn(mdev
, "Self loop back prevention is not supported\n");
2094 u16
mlx5e_get_max_inline_cap(struct mlx5_core_dev
*mdev
)
2096 int bf_buf_size
= (1 << MLX5_CAP_GEN(mdev
, log_bf_reg_size
)) / 2;
2098 return bf_buf_size
-
2099 sizeof(struct mlx5e_tx_wqe
) +
2100 2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/;
2103 void mlx5e_build_default_indir_rqt(u32
*indirection_rqt
, int len
,
2108 for (i
= 0; i
< len
; i
++)
2109 indirection_rqt
[i
] = i
% num_channels
;
2112 static void mlx5e_build_netdev_priv(struct mlx5_core_dev
*mdev
,
2113 struct net_device
*netdev
,
2116 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
2118 priv
->params
.log_sq_size
=
2119 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE
;
2120 priv
->params
.log_rq_size
=
2121 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE
;
2122 priv
->params
.rx_cq_moderation_usec
=
2123 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC
;
2124 priv
->params
.rx_cq_moderation_pkts
=
2125 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS
;
2126 priv
->params
.tx_cq_moderation_usec
=
2127 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC
;
2128 priv
->params
.tx_cq_moderation_pkts
=
2129 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS
;
2130 priv
->params
.tx_max_inline
= mlx5e_get_max_inline_cap(mdev
);
2131 priv
->params
.min_rx_wqes
=
2132 MLX5E_PARAMS_DEFAULT_MIN_RX_WQES
;
2133 priv
->params
.num_tc
= 1;
2134 priv
->params
.default_vlan_prio
= 0;
2135 priv
->params
.rss_hfunc
= ETH_RSS_HASH_XOR
;
2137 netdev_rss_key_fill(priv
->params
.toeplitz_hash_key
,
2138 sizeof(priv
->params
.toeplitz_hash_key
));
2140 mlx5e_build_default_indir_rqt(priv
->params
.indirection_rqt
,
2141 MLX5E_INDIR_RQT_SIZE
, num_channels
);
2143 priv
->params
.lro_wqe_sz
=
2144 MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ
;
2147 priv
->netdev
= netdev
;
2148 priv
->params
.num_channels
= num_channels
;
2149 priv
->default_vlan_prio
= priv
->params
.default_vlan_prio
;
2151 spin_lock_init(&priv
->async_events_spinlock
);
2152 mutex_init(&priv
->state_lock
);
2154 INIT_WORK(&priv
->update_carrier_work
, mlx5e_update_carrier_work
);
2155 INIT_WORK(&priv
->set_rx_mode_work
, mlx5e_set_rx_mode_work
);
2156 INIT_DELAYED_WORK(&priv
->update_stats_work
, mlx5e_update_stats_work
);
2159 static void mlx5e_set_netdev_dev_addr(struct net_device
*netdev
)
2161 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
2163 mlx5_query_nic_vport_mac_address(priv
->mdev
, 0, netdev
->dev_addr
);
2164 if (is_zero_ether_addr(netdev
->dev_addr
) &&
2165 !MLX5_CAP_GEN(priv
->mdev
, vport_group_manager
)) {
2166 eth_hw_addr_random(netdev
);
2167 mlx5_core_info(priv
->mdev
, "Assigned random MAC address %pM\n", netdev
->dev_addr
);
2171 static void mlx5e_build_netdev(struct net_device
*netdev
)
2173 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
2174 struct mlx5_core_dev
*mdev
= priv
->mdev
;
2176 SET_NETDEV_DEV(netdev
, &mdev
->pdev
->dev
);
2178 if (MLX5_CAP_GEN(mdev
, vport_group_manager
))
2179 netdev
->netdev_ops
= &mlx5e_netdev_ops_sriov
;
2181 netdev
->netdev_ops
= &mlx5e_netdev_ops_basic
;
2183 netdev
->watchdog_timeo
= 15 * HZ
;
2185 netdev
->ethtool_ops
= &mlx5e_ethtool_ops
;
2187 netdev
->vlan_features
|= NETIF_F_SG
;
2188 netdev
->vlan_features
|= NETIF_F_IP_CSUM
;
2189 netdev
->vlan_features
|= NETIF_F_IPV6_CSUM
;
2190 netdev
->vlan_features
|= NETIF_F_GRO
;
2191 netdev
->vlan_features
|= NETIF_F_TSO
;
2192 netdev
->vlan_features
|= NETIF_F_TSO6
;
2193 netdev
->vlan_features
|= NETIF_F_RXCSUM
;
2194 netdev
->vlan_features
|= NETIF_F_RXHASH
;
2196 if (!!MLX5_CAP_ETH(mdev
, lro_cap
))
2197 netdev
->vlan_features
|= NETIF_F_LRO
;
2199 netdev
->hw_features
= netdev
->vlan_features
;
2200 netdev
->hw_features
|= NETIF_F_HW_VLAN_CTAG_TX
;
2201 netdev
->hw_features
|= NETIF_F_HW_VLAN_CTAG_RX
;
2202 netdev
->hw_features
|= NETIF_F_HW_VLAN_CTAG_FILTER
;
2204 netdev
->features
= netdev
->hw_features
;
2205 if (!priv
->params
.lro_en
)
2206 netdev
->features
&= ~NETIF_F_LRO
;
2208 netdev
->features
|= NETIF_F_HIGHDMA
;
2210 netdev
->priv_flags
|= IFF_UNICAST_FLT
;
2212 mlx5e_set_netdev_dev_addr(netdev
);
2215 static int mlx5e_create_mkey(struct mlx5e_priv
*priv
, u32 pdn
,
2216 struct mlx5_core_mr
*mr
)
2218 struct mlx5_core_dev
*mdev
= priv
->mdev
;
2219 struct mlx5_create_mkey_mbox_in
*in
;
2222 in
= mlx5_vzalloc(sizeof(*in
));
2226 in
->seg
.flags
= MLX5_PERM_LOCAL_WRITE
|
2227 MLX5_PERM_LOCAL_READ
|
2228 MLX5_ACCESS_MODE_PA
;
2229 in
->seg
.flags_pd
= cpu_to_be32(pdn
| MLX5_MKEY_LEN64
);
2230 in
->seg
.qpn_mkey7_0
= cpu_to_be32(0xffffff << 8);
2232 err
= mlx5_core_create_mkey(mdev
, mr
, in
, sizeof(*in
), NULL
, NULL
,
2240 static void *mlx5e_create_netdev(struct mlx5_core_dev
*mdev
)
2242 struct net_device
*netdev
;
2243 struct mlx5e_priv
*priv
;
2244 int nch
= mlx5e_get_max_num_channels(mdev
);
2247 if (mlx5e_check_required_hca_cap(mdev
))
2250 netdev
= alloc_etherdev_mqs(sizeof(struct mlx5e_priv
), nch
, nch
);
2252 mlx5_core_err(mdev
, "alloc_etherdev_mqs() failed\n");
2256 mlx5e_build_netdev_priv(mdev
, netdev
, nch
);
2257 mlx5e_build_netdev(netdev
);
2259 netif_carrier_off(netdev
);
2261 priv
= netdev_priv(netdev
);
2263 err
= mlx5_alloc_map_uar(mdev
, &priv
->cq_uar
);
2265 mlx5_core_err(mdev
, "alloc_map uar failed, %d\n", err
);
2266 goto err_free_netdev
;
2269 err
= mlx5_core_alloc_pd(mdev
, &priv
->pdn
);
2271 mlx5_core_err(mdev
, "alloc pd failed, %d\n", err
);
2272 goto err_unmap_free_uar
;
2275 err
= mlx5_core_alloc_transport_domain(mdev
, &priv
->tdn
);
2277 mlx5_core_err(mdev
, "alloc td failed, %d\n", err
);
2278 goto err_dealloc_pd
;
2281 err
= mlx5e_create_mkey(priv
, priv
->pdn
, &priv
->mr
);
2283 mlx5_core_err(mdev
, "create mkey failed, %d\n", err
);
2284 goto err_dealloc_transport_domain
;
2287 err
= mlx5e_create_tises(priv
);
2289 mlx5_core_warn(mdev
, "create tises failed, %d\n", err
);
2290 goto err_destroy_mkey
;
2293 err
= mlx5e_open_drop_rq(priv
);
2295 mlx5_core_err(mdev
, "open drop rq failed, %d\n", err
);
2296 goto err_destroy_tises
;
2299 err
= mlx5e_create_rqt(priv
, MLX5E_INDIRECTION_RQT
);
2301 mlx5_core_warn(mdev
, "create rqt(INDIR) failed, %d\n", err
);
2302 goto err_close_drop_rq
;
2305 err
= mlx5e_create_rqt(priv
, MLX5E_SINGLE_RQ_RQT
);
2307 mlx5_core_warn(mdev
, "create rqt(SINGLE) failed, %d\n", err
);
2308 goto err_destroy_rqt_indir
;
2311 err
= mlx5e_create_tirs(priv
);
2313 mlx5_core_warn(mdev
, "create tirs failed, %d\n", err
);
2314 goto err_destroy_rqt_single
;
2317 err
= mlx5e_create_flow_tables(priv
);
2319 mlx5_core_warn(mdev
, "create flow tables failed, %d\n", err
);
2320 goto err_destroy_tirs
;
2323 mlx5e_init_eth_addr(priv
);
2325 err
= register_netdev(netdev
);
2327 mlx5_core_err(mdev
, "register_netdev failed, %d\n", err
);
2328 goto err_destroy_flow_tables
;
2331 mlx5e_enable_async_events(priv
);
2332 schedule_work(&priv
->set_rx_mode_work
);
2336 err_destroy_flow_tables
:
2337 mlx5e_destroy_flow_tables(priv
);
2340 mlx5e_destroy_tirs(priv
);
2342 err_destroy_rqt_single
:
2343 mlx5e_destroy_rqt(priv
, MLX5E_SINGLE_RQ_RQT
);
2345 err_destroy_rqt_indir
:
2346 mlx5e_destroy_rqt(priv
, MLX5E_INDIRECTION_RQT
);
2349 mlx5e_close_drop_rq(priv
);
2352 mlx5e_destroy_tises(priv
);
2355 mlx5_core_destroy_mkey(mdev
, &priv
->mr
);
2357 err_dealloc_transport_domain
:
2358 mlx5_core_dealloc_transport_domain(mdev
, priv
->tdn
);
2361 mlx5_core_dealloc_pd(mdev
, priv
->pdn
);
2364 mlx5_unmap_free_uar(mdev
, &priv
->cq_uar
);
2367 free_netdev(netdev
);
2372 static void mlx5e_destroy_netdev(struct mlx5_core_dev
*mdev
, void *vpriv
)
2374 struct mlx5e_priv
*priv
= vpriv
;
2375 struct net_device
*netdev
= priv
->netdev
;
2377 set_bit(MLX5E_STATE_DESTROYING
, &priv
->state
);
2379 schedule_work(&priv
->set_rx_mode_work
);
2380 mlx5e_disable_async_events(priv
);
2381 flush_scheduled_work();
2382 unregister_netdev(netdev
);
2383 mlx5e_destroy_flow_tables(priv
);
2384 mlx5e_destroy_tirs(priv
);
2385 mlx5e_destroy_rqt(priv
, MLX5E_SINGLE_RQ_RQT
);
2386 mlx5e_destroy_rqt(priv
, MLX5E_INDIRECTION_RQT
);
2387 mlx5e_close_drop_rq(priv
);
2388 mlx5e_destroy_tises(priv
);
2389 mlx5_core_destroy_mkey(priv
->mdev
, &priv
->mr
);
2390 mlx5_core_dealloc_transport_domain(priv
->mdev
, priv
->tdn
);
2391 mlx5_core_dealloc_pd(priv
->mdev
, priv
->pdn
);
2392 mlx5_unmap_free_uar(priv
->mdev
, &priv
->cq_uar
);
2393 free_netdev(netdev
);
2396 static void *mlx5e_get_netdev(void *vpriv
)
2398 struct mlx5e_priv
*priv
= vpriv
;
2400 return priv
->netdev
;
2403 static struct mlx5_interface mlx5e_interface
= {
2404 .add
= mlx5e_create_netdev
,
2405 .remove
= mlx5e_destroy_netdev
,
2406 .event
= mlx5e_async_event
,
2407 .protocol
= MLX5_INTERFACE_PROTOCOL_ETH
,
2408 .get_dev
= mlx5e_get_netdev
,
2411 void mlx5e_init(void)
2413 mlx5_register_interface(&mlx5e_interface
);
2416 void mlx5e_cleanup(void)
2418 mlx5_unregister_interface(&mlx5e_interface
);