drivers/net/ethernet/mellanox/mlx5/core/en_tx.c

   1 /*
   2  * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/tcp.h>
  34 #include <linux/if_vlan.h>
  35 #include "en.h"
  36
  37 #define MLX5E_SQ_NOPS_ROOM  MLX5_SEND_WQE_MAX_WQEBBS
  38 #define MLX5E_SQ_STOP_ROOM (MLX5_SEND_WQE_MAX_WQEBBS +\
  39                             MLX5E_SQ_NOPS_ROOM)
  40
  41 void mlx5e_send_nop(struct mlx5e_sq *sq, bool notify_hw)
  42 {
  43         struct mlx5_wq_cyc                *wq  = &sq->wq;
  44
  45         u16 pi = sq->pc & wq->sz_m1;
  46         struct mlx5e_tx_wqe              *wqe  = mlx5_wq_cyc_get_wqe(wq, pi);
  47
  48         struct mlx5_wqe_ctrl_seg         *cseg = &wqe->ctrl;
  49
  50         memset(cseg, 0, sizeof(*cseg));
  51
  52         cseg->opmod_idx_opcode = cpu_to_be32((sq->pc << 8) | MLX5_OPCODE_NOP);
  53         cseg->qpn_ds           = cpu_to_be32((sq->sqn << 8) | 0x01);
  54
  55         sq->skb[pi] = NULL;
  56         sq->pc++;
  57         sq->stats.nop++;
  58
  59         if (notify_hw) {
  60                 cseg->fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE;
  61                 mlx5e_tx_notify_hw(sq, &wqe->ctrl, 0);
  62         }
  63 }
  64
  65 static inline void mlx5e_tx_dma_unmap(struct device *pdev,
  66                                       struct mlx5e_sq_dma *dma)
  67 {
  68         switch (dma->type) {
  69         case MLX5E_DMA_MAP_SINGLE:
  70                 dma_unmap_single(pdev, dma->addr, dma->size, DMA_TO_DEVICE);
  71                 break;
  72         case MLX5E_DMA_MAP_PAGE:
  73                 dma_unmap_page(pdev, dma->addr, dma->size, DMA_TO_DEVICE);
  74                 break;
  75         default:
  76                 WARN_ONCE(true, "mlx5e_tx_dma_unmap unknown DMA type!\n");
  77         }
  78 }
  79
  80 static inline void mlx5e_dma_push(struct mlx5e_sq *sq,
  81                                   dma_addr_t addr,
  82                                   u32 size,
  83                                   enum mlx5e_dma_map_type map_type)
  84 {
  85         sq->dma_fifo[sq->dma_fifo_pc & sq->dma_fifo_mask].addr = addr;
  86         sq->dma_fifo[sq->dma_fifo_pc & sq->dma_fifo_mask].size = size;
  87         sq->dma_fifo[sq->dma_fifo_pc & sq->dma_fifo_mask].type = map_type;
  88         sq->dma_fifo_pc++;
  89 }
  90
  91 static inline struct mlx5e_sq_dma *mlx5e_dma_get(struct mlx5e_sq *sq, u32 i)
  92 {
  93         return &sq->dma_fifo[i & sq->dma_fifo_mask];
  94 }
  95
  96 static void mlx5e_dma_unmap_wqe_err(struct mlx5e_sq *sq, u8 num_dma)
  97 {
  98         int i;
  99
 100         for (i = 0; i < num_dma; i++) {
 101                 struct mlx5e_sq_dma *last_pushed_dma =
 102                         mlx5e_dma_get(sq, --sq->dma_fifo_pc);
 103
 104                 mlx5e_tx_dma_unmap(sq->pdev, last_pushed_dma);
 105         }
 106 }
 107
 108 u16 mlx5e_select_queue(struct net_device *dev, struct sk_buff *skb,
 109                        void *accel_priv, select_queue_fallback_t fallback)
 110 {
 111         struct mlx5e_priv *priv = netdev_priv(dev);
 112         int channel_ix = fallback(dev, skb);
 113         int up = (netdev_get_num_tc(dev) && skb_vlan_tag_present(skb)) ?
 114                  skb->vlan_tci >> VLAN_PRIO_SHIFT : 0;
 115
 116         return priv->channeltc_to_txq_map[channel_ix][up];
 117 }
 118
 119 static inline u16 mlx5e_get_inline_hdr_size(struct mlx5e_sq *sq,
 120                                             struct sk_buff *skb, bool bf)
 121 {
 122         /* Some NIC TX decisions, e.g loopback, are based on the packet
 123          * headers and occur before the data gather.
 124          * Therefore these headers must be copied into the WQE
 125          */
 126 #define MLX5E_MIN_INLINE ETH_HLEN
 127
 128         if (bf) {
 129                 u16 ihs = skb_headlen(skb);
 130
 131                 if (skb_vlan_tag_present(skb))
 132                         ihs += VLAN_HLEN;
 133
 134                 if (ihs <= sq->max_inline)
 135                         return skb_headlen(skb);
 136         }
 137
 138         return MLX5E_MIN_INLINE;
 139 }
 140
 141 static inline void mlx5e_tx_skb_pull_inline(unsigned char **skb_data,
 142                                             unsigned int *skb_len,
 143                                             unsigned int len)
 144 {
 145         *skb_len -= len;
 146         *skb_data += len;
 147 }
 148
 149 static inline void mlx5e_insert_vlan(void *start, struct sk_buff *skb, u16 ihs,
 150                                      unsigned char **skb_data,
 151                                      unsigned int *skb_len)
 152 {
 153         struct vlan_ethhdr *vhdr = (struct vlan_ethhdr *)start;
 154         int cpy1_sz = 2 * ETH_ALEN;
 155         int cpy2_sz = ihs - cpy1_sz;
 156
 157         memcpy(vhdr, *skb_data, cpy1_sz);
 158         mlx5e_tx_skb_pull_inline(skb_data, skb_len, cpy1_sz);
 159         vhdr->h_vlan_proto = skb->vlan_proto;
 160         vhdr->h_vlan_TCI = cpu_to_be16(skb_vlan_tag_get(skb));
 161         memcpy(&vhdr->h_vlan_encapsulated_proto, *skb_data, cpy2_sz);
 162         mlx5e_tx_skb_pull_inline(skb_data, skb_len, cpy2_sz);
 163 }
 164
 165 static netdev_tx_t mlx5e_sq_xmit(struct mlx5e_sq *sq, struct sk_buff *skb)
 166 {
 167         struct mlx5_wq_cyc       *wq   = &sq->wq;
 168
 169         u16 pi = sq->pc & wq->sz_m1;
 170         struct mlx5e_tx_wqe      *wqe  = mlx5_wq_cyc_get_wqe(wq, pi);
 171         struct mlx5e_tx_wqe_info *wi   = &sq->wqe_info[pi];
 172
 173         struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
 174         struct mlx5_wqe_eth_seg  *eseg = &wqe->eth;
 175         struct mlx5_wqe_data_seg *dseg;
 176
 177         unsigned char *skb_data = skb->data;
 178         unsigned int skb_len = skb->len;
 179         u8  opcode = MLX5_OPCODE_SEND;
 180         dma_addr_t dma_addr = 0;
 181         unsigned int num_bytes;
 182         bool bf = false;
 183         u16 headlen;
 184         u16 ds_cnt;
 185         u16 ihs;
 186         int i;
 187
 188         memset(wqe, 0, sizeof(*wqe));
 189
 190         if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
 191                 eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM;
 192                 if (skb->encapsulation) {
 193                         eseg->cs_flags |= MLX5_ETH_WQE_L3_INNER_CSUM |
 194                                           MLX5_ETH_WQE_L4_INNER_CSUM;
 195                         sq->stats.csum_offload_inner++;
 196                 } else {
 197                         eseg->cs_flags |= MLX5_ETH_WQE_L4_CSUM;
 198                 }
 199         } else
 200                 sq->stats.csum_offload_none++;
 201
 202         if (sq->cc != sq->prev_cc) {
 203                 sq->prev_cc = sq->cc;
 204                 sq->bf_budget = (sq->cc == sq->pc) ? MLX5E_SQ_BF_BUDGET : 0;
 205         }
 206
 207         if (skb_is_gso(skb)) {
 208                 eseg->mss    = cpu_to_be16(skb_shinfo(skb)->gso_size);
 209                 opcode       = MLX5_OPCODE_LSO;
 210
 211                 if (skb->encapsulation) {
 212                         ihs = skb_inner_transport_offset(skb) + inner_tcp_hdrlen(skb);
 213                         sq->stats.tso_inner_packets++;
 214                         sq->stats.tso_inner_bytes += skb->len - ihs;
 215                 } else {
 216                         ihs = skb_transport_offset(skb) + tcp_hdrlen(skb);
 217                         sq->stats.tso_packets++;
 218                         sq->stats.tso_bytes += skb->len - ihs;
 219                 }
 220
 221                 num_bytes = skb->len + (skb_shinfo(skb)->gso_segs - 1) * ihs;
 222         } else {
 223                 bf = sq->bf_budget &&
 224                      !skb->xmit_more &&
 225                      !skb_shinfo(skb)->nr_frags;
 226                 ihs = mlx5e_get_inline_hdr_size(sq, skb, bf);
 227                 num_bytes = max_t(unsigned int, skb->len, ETH_ZLEN);
 228         }
 229
 230         wi->num_bytes = num_bytes;
 231
 232         if (skb_vlan_tag_present(skb)) {
 233                 mlx5e_insert_vlan(eseg->inline_hdr_start, skb, ihs, &skb_data,
 234                                   &skb_len);
 235                 ihs += VLAN_HLEN;
 236         } else {
 237                 memcpy(eseg->inline_hdr_start, skb_data, ihs);
 238                 mlx5e_tx_skb_pull_inline(&skb_data, &skb_len, ihs);
 239         }
 240
 241         eseg->inline_hdr_sz = cpu_to_be16(ihs);
 242
 243         ds_cnt  = sizeof(*wqe) / MLX5_SEND_WQE_DS;
 244         ds_cnt += DIV_ROUND_UP(ihs - sizeof(eseg->inline_hdr_start),
 245                                MLX5_SEND_WQE_DS);
 246         dseg    = (struct mlx5_wqe_data_seg *)cseg + ds_cnt;
 247
 248         wi->num_dma = 0;
 249
 250         headlen = skb_len - skb->data_len;
 251         if (headlen) {
 252                 dma_addr = dma_map_single(sq->pdev, skb_data, headlen,
 253                                           DMA_TO_DEVICE);
 254                 if (unlikely(dma_mapping_error(sq->pdev, dma_addr)))
 255                         goto dma_unmap_wqe_err;
 256
 257                 dseg->addr       = cpu_to_be64(dma_addr);
 258                 dseg->lkey       = sq->mkey_be;
 259                 dseg->byte_count = cpu_to_be32(headlen);
 260
 261                 mlx5e_dma_push(sq, dma_addr, headlen, MLX5E_DMA_MAP_SINGLE);
 262                 wi->num_dma++;
 263
 264                 dseg++;
 265         }
 266
 267         for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
 268                 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i];
 269                 int fsz = skb_frag_size(frag);
 270
 271                 dma_addr = skb_frag_dma_map(sq->pdev, frag, 0, fsz,
 272                                             DMA_TO_DEVICE);
 273                 if (unlikely(dma_mapping_error(sq->pdev, dma_addr)))
 274                         goto dma_unmap_wqe_err;
 275
 276                 dseg->addr       = cpu_to_be64(dma_addr);
 277                 dseg->lkey       = sq->mkey_be;
 278                 dseg->byte_count = cpu_to_be32(fsz);
 279
 280                 mlx5e_dma_push(sq, dma_addr, fsz, MLX5E_DMA_MAP_PAGE);
 281                 wi->num_dma++;
 282
 283                 dseg++;
 284         }
 285
 286         ds_cnt += wi->num_dma;
 287
 288         cseg->opmod_idx_opcode = cpu_to_be32((sq->pc << 8) | opcode);
 289         cseg->qpn_ds           = cpu_to_be32((sq->sqn << 8) | ds_cnt);
 290
 291         sq->skb[pi] = skb;
 292
 293         wi->num_wqebbs = DIV_ROUND_UP(ds_cnt, MLX5_SEND_WQEBB_NUM_DS);
 294         sq->pc += wi->num_wqebbs;
 295
 296         netdev_tx_sent_queue(sq->txq, wi->num_bytes);
 297
 298         if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP))
 299                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
 300
 301         if (unlikely(!mlx5e_sq_has_room_for(sq, MLX5E_SQ_STOP_ROOM))) {
 302                 netif_tx_stop_queue(sq->txq);
 303                 sq->stats.stopped++;
 304         }
 305
 306         if (!skb->xmit_more || netif_xmit_stopped(sq->txq)) {
 307                 int bf_sz = 0;
 308
 309                 if (bf && test_bit(MLX5E_SQ_STATE_BF_ENABLE, &sq->state))
 310                         bf_sz = wi->num_wqebbs << 3;
 311
 312                 cseg->fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE;
 313                 mlx5e_tx_notify_hw(sq, &wqe->ctrl, bf_sz);
 314         }
 315
 316         /* fill sq edge with nops to avoid wqe wrap around */
 317         while ((sq->pc & wq->sz_m1) > sq->edge)
 318                 mlx5e_send_nop(sq, false);
 319
 320         if (bf)
 321                 sq->bf_budget--;
 322
 323         sq->stats.packets++;
 324         sq->stats.bytes += num_bytes;
 325         return NETDEV_TX_OK;
 326
 327 dma_unmap_wqe_err:
 328         sq->stats.dropped++;
 329         mlx5e_dma_unmap_wqe_err(sq, wi->num_dma);
 330
 331         dev_kfree_skb_any(skb);
 332
 333         return NETDEV_TX_OK;
 334 }
 335
 336 netdev_tx_t mlx5e_xmit(struct sk_buff *skb, struct net_device *dev)
 337 {
 338         struct mlx5e_priv *priv = netdev_priv(dev);
 339         struct mlx5e_sq *sq = priv->txq_to_sq_map[skb_get_queue_mapping(skb)];
 340
 341         return mlx5e_sq_xmit(sq, skb);
 342 }
 343
 344 bool mlx5e_poll_tx_cq(struct mlx5e_cq *cq, int napi_budget)
 345 {
 346         struct mlx5e_sq *sq;
 347         u32 dma_fifo_cc;
 348         u32 nbytes;
 349         u16 npkts;
 350         u16 sqcc;
 351         int i;
 352
 353         sq = container_of(cq, struct mlx5e_sq, cq);
 354
 355         npkts = 0;
 356         nbytes = 0;
 357
 358         /* sq->cc must be updated only after mlx5_cqwq_update_db_record(),
 359          * otherwise a cq overrun may occur
 360          */
 361         sqcc = sq->cc;
 362
 363         /* avoid dirtying sq cache line every cqe */
 364         dma_fifo_cc = sq->dma_fifo_cc;
 365
 366         for (i = 0; i < MLX5E_TX_CQ_POLL_BUDGET; i++) {
 367                 struct mlx5_cqe64 *cqe;
 368                 u16 wqe_counter;
 369                 bool last_wqe;
 370
 371                 cqe = mlx5e_get_cqe(cq);
 372                 if (!cqe)
 373                         break;
 374
 375                 mlx5_cqwq_pop(&cq->wq);
 376
 377                 wqe_counter = be16_to_cpu(cqe->wqe_counter);
 378
 379                 do {
 380                         struct mlx5e_tx_wqe_info *wi;
 381                         struct sk_buff *skb;
 382                         u16 ci;
 383                         int j;
 384
 385                         last_wqe = (sqcc == wqe_counter);
 386
 387                         ci = sqcc & sq->wq.sz_m1;
 388                         skb = sq->skb[ci];
 389                         wi = &sq->wqe_info[ci];
 390
 391                         if (unlikely(!skb)) { /* nop */
 392                                 sqcc++;
 393                                 continue;
 394                         }
 395
 396                         if (unlikely(skb_shinfo(skb)->tx_flags &
 397                                      SKBTX_HW_TSTAMP)) {
 398                                 struct skb_shared_hwtstamps hwts = {};
 399
 400                                 mlx5e_fill_hwstamp(sq->tstamp,
 401                                                    get_cqe_ts(cqe), &hwts);
 402                                 skb_tstamp_tx(skb, &hwts);
 403                         }
 404
 405                         for (j = 0; j < wi->num_dma; j++) {
 406                                 struct mlx5e_sq_dma *dma =
 407                                         mlx5e_dma_get(sq, dma_fifo_cc++);
 408
 409                                 mlx5e_tx_dma_unmap(sq->pdev, dma);
 410                         }
 411
 412                         npkts++;
 413                         nbytes += wi->num_bytes;
 414                         sqcc += wi->num_wqebbs;
 415                         napi_consume_skb(skb, napi_budget);
 416                 } while (!last_wqe);
 417         }
 418
 419         mlx5_cqwq_update_db_record(&cq->wq);
 420
 421         /* ensure cq space is freed before enabling more cqes */
 422         wmb();
 423
 424         sq->dma_fifo_cc = dma_fifo_cc;
 425         sq->cc = sqcc;
 426
 427         netdev_tx_completed_queue(sq->txq, npkts, nbytes);
 428
 429         if (netif_tx_queue_stopped(sq->txq) &&
 430             mlx5e_sq_has_room_for(sq, MLX5E_SQ_STOP_ROOM) &&
 431             likely(test_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state))) {
 432                                 netif_tx_wake_queue(sq->txq);
 433                                 sq->stats.wake++;
 434         }
 435
 436         return (i == MLX5E_TX_CQ_POLL_BUDGET);
 437 }