drivers/net/ethernet/mellanox/mlx5/core/eq.c

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/interrupt.h>
  34 #include <linux/module.h>
  35 #include <linux/mlx5/driver.h>
  36 #include <linux/mlx5/cmd.h>
  37 #include "mlx5_core.h"
  38 #ifdef CONFIG_MLX5_CORE_EN
  39 #include "eswitch.h"
  40 #endif
  41
  42 enum {
  43         MLX5_EQE_SIZE           = sizeof(struct mlx5_eqe),
  44         MLX5_EQE_OWNER_INIT_VAL = 0x1,
  45 };
  46
  47 enum {
  48         MLX5_EQ_STATE_ARMED             = 0x9,
  49         MLX5_EQ_STATE_FIRED             = 0xa,
  50         MLX5_EQ_STATE_ALWAYS_ARMED      = 0xb,
  51 };
  52
  53 enum {
  54         MLX5_NUM_SPARE_EQE      = 0x80,
  55         MLX5_NUM_ASYNC_EQE      = 0x100,
  56         MLX5_NUM_CMD_EQE        = 32,
  57 };
  58
  59 enum {
  60         MLX5_EQ_DOORBEL_OFFSET  = 0x40,
  61 };
  62
  63 #define MLX5_ASYNC_EVENT_MASK ((1ull << MLX5_EVENT_TYPE_PATH_MIG)           | \
  64                                (1ull << MLX5_EVENT_TYPE_COMM_EST)           | \
  65                                (1ull << MLX5_EVENT_TYPE_SQ_DRAINED)         | \
  66                                (1ull << MLX5_EVENT_TYPE_CQ_ERROR)           | \
  67                                (1ull << MLX5_EVENT_TYPE_WQ_CATAS_ERROR)     | \
  68                                (1ull << MLX5_EVENT_TYPE_PATH_MIG_FAILED)    | \
  69                                (1ull << MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR) | \
  70                                (1ull << MLX5_EVENT_TYPE_WQ_ACCESS_ERROR)    | \
  71                                (1ull << MLX5_EVENT_TYPE_PORT_CHANGE)        | \
  72                                (1ull << MLX5_EVENT_TYPE_SRQ_CATAS_ERROR)    | \
  73                                (1ull << MLX5_EVENT_TYPE_SRQ_LAST_WQE)       | \
  74                                (1ull << MLX5_EVENT_TYPE_SRQ_RQ_LIMIT))
  75
  76 struct map_eq_in {
  77         u64     mask;
  78         u32     reserved;
  79         u32     unmap_eqn;
  80 };
  81
  82 struct cre_des_eq {
  83         u8      reserved[15];
  84         u8      eqn;
  85 };
  86
  87 static int mlx5_cmd_destroy_eq(struct mlx5_core_dev *dev, u8 eqn)
  88 {
  89         struct mlx5_destroy_eq_mbox_in in;
  90         struct mlx5_destroy_eq_mbox_out out;
  91         int err;
  92
  93         memset(&in, 0, sizeof(in));
  94         memset(&out, 0, sizeof(out));
  95         in.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_DESTROY_EQ);
  96         in.eqn = eqn;
  97         err = mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
  98         if (!err)
  99                 goto ex;
 100
 101         if (out.hdr.status)
 102                 err = mlx5_cmd_status_to_err(&out.hdr);
 103
 104 ex:
 105         return err;
 106 }
 107
 108 static struct mlx5_eqe *get_eqe(struct mlx5_eq *eq, u32 entry)
 109 {
 110         return mlx5_buf_offset(&eq->buf, entry * MLX5_EQE_SIZE);
 111 }
 112
 113 static struct mlx5_eqe *next_eqe_sw(struct mlx5_eq *eq)
 114 {
 115         struct mlx5_eqe *eqe = get_eqe(eq, eq->cons_index & (eq->nent - 1));
 116
 117         return ((eqe->owner & 1) ^ !!(eq->cons_index & eq->nent)) ? NULL : eqe;
 118 }
 119
 120 static const char *eqe_type_str(u8 type)
 121 {
 122         switch (type) {
 123         case MLX5_EVENT_TYPE_COMP:
 124                 return "MLX5_EVENT_TYPE_COMP";
 125         case MLX5_EVENT_TYPE_PATH_MIG:
 126                 return "MLX5_EVENT_TYPE_PATH_MIG";
 127         case MLX5_EVENT_TYPE_COMM_EST:
 128                 return "MLX5_EVENT_TYPE_COMM_EST";
 129         case MLX5_EVENT_TYPE_SQ_DRAINED:
 130                 return "MLX5_EVENT_TYPE_SQ_DRAINED";
 131         case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
 132                 return "MLX5_EVENT_TYPE_SRQ_LAST_WQE";
 133         case MLX5_EVENT_TYPE_SRQ_RQ_LIMIT:
 134                 return "MLX5_EVENT_TYPE_SRQ_RQ_LIMIT";
 135         case MLX5_EVENT_TYPE_CQ_ERROR:
 136                 return "MLX5_EVENT_TYPE_CQ_ERROR";
 137         case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
 138                 return "MLX5_EVENT_TYPE_WQ_CATAS_ERROR";
 139         case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
 140                 return "MLX5_EVENT_TYPE_PATH_MIG_FAILED";
 141         case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
 142                 return "MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR";
 143         case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
 144                 return "MLX5_EVENT_TYPE_WQ_ACCESS_ERROR";
 145         case MLX5_EVENT_TYPE_SRQ_CATAS_ERROR:
 146                 return "MLX5_EVENT_TYPE_SRQ_CATAS_ERROR";
 147         case MLX5_EVENT_TYPE_INTERNAL_ERROR:
 148                 return "MLX5_EVENT_TYPE_INTERNAL_ERROR";
 149         case MLX5_EVENT_TYPE_PORT_CHANGE:
 150                 return "MLX5_EVENT_TYPE_PORT_CHANGE";
 151         case MLX5_EVENT_TYPE_GPIO_EVENT:
 152                 return "MLX5_EVENT_TYPE_GPIO_EVENT";
 153         case MLX5_EVENT_TYPE_REMOTE_CONFIG:
 154                 return "MLX5_EVENT_TYPE_REMOTE_CONFIG";
 155         case MLX5_EVENT_TYPE_DB_BF_CONGESTION:
 156                 return "MLX5_EVENT_TYPE_DB_BF_CONGESTION";
 157         case MLX5_EVENT_TYPE_STALL_EVENT:
 158                 return "MLX5_EVENT_TYPE_STALL_EVENT";
 159         case MLX5_EVENT_TYPE_CMD:
 160                 return "MLX5_EVENT_TYPE_CMD";
 161         case MLX5_EVENT_TYPE_PAGE_REQUEST:
 162                 return "MLX5_EVENT_TYPE_PAGE_REQUEST";
 163         case MLX5_EVENT_TYPE_PAGE_FAULT:
 164                 return "MLX5_EVENT_TYPE_PAGE_FAULT";
 165         default:
 166                 return "Unrecognized event";
 167         }
 168 }
 169
 170 static enum mlx5_dev_event port_subtype_event(u8 subtype)
 171 {
 172         switch (subtype) {
 173         case MLX5_PORT_CHANGE_SUBTYPE_DOWN:
 174                 return MLX5_DEV_EVENT_PORT_DOWN;
 175         case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE:
 176                 return MLX5_DEV_EVENT_PORT_UP;
 177         case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED:
 178                 return MLX5_DEV_EVENT_PORT_INITIALIZED;
 179         case MLX5_PORT_CHANGE_SUBTYPE_LID:
 180                 return MLX5_DEV_EVENT_LID_CHANGE;
 181         case MLX5_PORT_CHANGE_SUBTYPE_PKEY:
 182                 return MLX5_DEV_EVENT_PKEY_CHANGE;
 183         case MLX5_PORT_CHANGE_SUBTYPE_GUID:
 184                 return MLX5_DEV_EVENT_GUID_CHANGE;
 185         case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG:
 186                 return MLX5_DEV_EVENT_CLIENT_REREG;
 187         }
 188         return -1;
 189 }
 190
 191 static void eq_update_ci(struct mlx5_eq *eq, int arm)
 192 {
 193         __be32 __iomem *addr = eq->doorbell + (arm ? 0 : 2);
 194         u32 val = (eq->cons_index & 0xffffff) | (eq->eqn << 24);
 195         __raw_writel((__force u32) cpu_to_be32(val), addr);
 196         /* We still want ordering, just not swabbing, so add a barrier */
 197         mb();
 198 }
 199
 200 static int mlx5_eq_int(struct mlx5_core_dev *dev, struct mlx5_eq *eq)
 201 {
 202         struct mlx5_eqe *eqe;
 203         int eqes_found = 0;
 204         int set_ci = 0;
 205         u32 cqn;
 206         u32 rsn;
 207         u8 port;
 208
 209         while ((eqe = next_eqe_sw(eq))) {
 210                 /*
 211                  * Make sure we read EQ entry contents after we've
 212                  * checked the ownership bit.
 213                  */
 214                 dma_rmb();
 215
 216                 mlx5_core_dbg(eq->dev, "eqn %d, eqe type %s\n",
 217                               eq->eqn, eqe_type_str(eqe->type));
 218                 switch (eqe->type) {
 219                 case MLX5_EVENT_TYPE_COMP:
 220                         cqn = be32_to_cpu(eqe->data.comp.cqn) & 0xffffff;
 221                         mlx5_cq_completion(dev, cqn);
 222                         break;
 223
 224                 case MLX5_EVENT_TYPE_PATH_MIG:
 225                 case MLX5_EVENT_TYPE_COMM_EST:
 226                 case MLX5_EVENT_TYPE_SQ_DRAINED:
 227                 case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
 228                 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
 229                 case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
 230                 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
 231                 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
 232                         rsn = be32_to_cpu(eqe->data.qp_srq.qp_srq_n) & 0xffffff;
 233                         mlx5_core_dbg(dev, "event %s(%d) arrived on resource 0x%x\n",
 234                                       eqe_type_str(eqe->type), eqe->type, rsn);
 235                         mlx5_rsc_event(dev, rsn, eqe->type);
 236                         break;
 237
 238                 case MLX5_EVENT_TYPE_SRQ_RQ_LIMIT:
 239                 case MLX5_EVENT_TYPE_SRQ_CATAS_ERROR:
 240                         rsn = be32_to_cpu(eqe->data.qp_srq.qp_srq_n) & 0xffffff;
 241                         mlx5_core_dbg(dev, "SRQ event %s(%d): srqn 0x%x\n",
 242                                       eqe_type_str(eqe->type), eqe->type, rsn);
 243                         mlx5_srq_event(dev, rsn, eqe->type);
 244                         break;
 245
 246                 case MLX5_EVENT_TYPE_CMD:
 247                         mlx5_cmd_comp_handler(dev, be32_to_cpu(eqe->data.cmd.vector));
 248                         break;
 249
 250                 case MLX5_EVENT_TYPE_PORT_CHANGE:
 251                         port = (eqe->data.port.port >> 4) & 0xf;
 252                         switch (eqe->sub_type) {
 253                         case MLX5_PORT_CHANGE_SUBTYPE_DOWN:
 254                         case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE:
 255                         case MLX5_PORT_CHANGE_SUBTYPE_LID:
 256                         case MLX5_PORT_CHANGE_SUBTYPE_PKEY:
 257                         case MLX5_PORT_CHANGE_SUBTYPE_GUID:
 258                         case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG:
 259                         case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED:
 260                                 if (dev->event)
 261                                         dev->event(dev, port_subtype_event(eqe->sub_type),
 262                                                    (unsigned long)port);
 263                                 break;
 264                         default:
 265                                 mlx5_core_warn(dev, "Port event with unrecognized subtype: port %d, sub_type %d\n",
 266                                                port, eqe->sub_type);
 267                         }
 268                         break;
 269                 case MLX5_EVENT_TYPE_CQ_ERROR:
 270                         cqn = be32_to_cpu(eqe->data.cq_err.cqn) & 0xffffff;
 271                         mlx5_core_warn(dev, "CQ error on CQN 0x%x, syndrom 0x%x\n",
 272                                        cqn, eqe->data.cq_err.syndrome);
 273                         mlx5_cq_event(dev, cqn, eqe->type);
 274                         break;
 275
 276                 case MLX5_EVENT_TYPE_PAGE_REQUEST:
 277                         {
 278                                 u16 func_id = be16_to_cpu(eqe->data.req_pages.func_id);
 279                                 s32 npages = be32_to_cpu(eqe->data.req_pages.num_pages);
 280
 281                                 mlx5_core_dbg(dev, "page request for func 0x%x, npages %d\n",
 282                                               func_id, npages);
 283                                 mlx5_core_req_pages_handler(dev, func_id, npages);
 284                         }
 285                         break;
 286
 287 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
 288                 case MLX5_EVENT_TYPE_PAGE_FAULT:
 289                         mlx5_eq_pagefault(dev, eqe);
 290                         break;
 291 #endif
 292
 293 #ifdef CONFIG_MLX5_CORE_EN
 294                 case MLX5_EVENT_TYPE_NIC_VPORT_CHANGE:
 295                         mlx5_eswitch_vport_event(dev->priv.eswitch, eqe);
 296                         break;
 297 #endif
 298                 default:
 299                         mlx5_core_warn(dev, "Unhandled event 0x%x on EQ 0x%x\n",
 300                                        eqe->type, eq->eqn);
 301                         break;
 302                 }
 303
 304                 ++eq->cons_index;
 305                 eqes_found = 1;
 306                 ++set_ci;
 307
 308                 /* The HCA will think the queue has overflowed if we
 309                  * don't tell it we've been processing events.  We
 310                  * create our EQs with MLX5_NUM_SPARE_EQE extra
 311                  * entries, so we must update our consumer index at
 312                  * least that often.
 313                  */
 314                 if (unlikely(set_ci >= MLX5_NUM_SPARE_EQE)) {
 315                         eq_update_ci(eq, 0);
 316                         set_ci = 0;
 317                 }
 318         }
 319
 320         eq_update_ci(eq, 1);
 321
 322         return eqes_found;
 323 }
 324
 325 static irqreturn_t mlx5_msix_handler(int irq, void *eq_ptr)
 326 {
 327         struct mlx5_eq *eq = eq_ptr;
 328         struct mlx5_core_dev *dev = eq->dev;
 329
 330         mlx5_eq_int(dev, eq);
 331
 332         /* MSI-X vectors always belong to us */
 333         return IRQ_HANDLED;
 334 }
 335
 336 static void init_eq_buf(struct mlx5_eq *eq)
 337 {
 338         struct mlx5_eqe *eqe;
 339         int i;
 340
 341         for (i = 0; i < eq->nent; i++) {
 342                 eqe = get_eqe(eq, i);
 343                 eqe->owner = MLX5_EQE_OWNER_INIT_VAL;
 344         }
 345 }
 346
 347 int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx,
 348                        int nent, u64 mask, const char *name, struct mlx5_uar *uar)
 349 {
 350         struct mlx5_priv *priv = &dev->priv;
 351         struct mlx5_create_eq_mbox_in *in;
 352         struct mlx5_create_eq_mbox_out out;
 353         int err;
 354         int inlen;
 355
 356         eq->nent = roundup_pow_of_two(nent + MLX5_NUM_SPARE_EQE);
 357         eq->cons_index = 0;
 358         err = mlx5_buf_alloc(dev, eq->nent * MLX5_EQE_SIZE, &eq->buf);
 359         if (err)
 360                 return err;
 361
 362         init_eq_buf(eq);
 363
 364         inlen = sizeof(*in) + sizeof(in->pas[0]) * eq->buf.npages;
 365         in = mlx5_vzalloc(inlen);
 366         if (!in) {
 367                 err = -ENOMEM;
 368                 goto err_buf;
 369         }
 370         memset(&out, 0, sizeof(out));
 371
 372         mlx5_fill_page_array(&eq->buf, in->pas);
 373
 374         in->hdr.opcode = cpu_to_be16(MLX5_CMD_OP_CREATE_EQ);
 375         in->ctx.log_sz_usr_page = cpu_to_be32(ilog2(eq->nent) << 24 | uar->index);
 376         in->ctx.intr = vecidx;
 377         in->ctx.log_page_size = eq->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT;
 378         in->events_mask = cpu_to_be64(mask);
 379
 380         err = mlx5_cmd_exec(dev, in, inlen, &out, sizeof(out));
 381         if (err)
 382                 goto err_in;
 383
 384         if (out.hdr.status) {
 385                 err = mlx5_cmd_status_to_err(&out.hdr);
 386                 goto err_in;
 387         }
 388
 389         snprintf(priv->irq_info[vecidx].name, MLX5_MAX_IRQ_NAME, "%s@pci:%s",
 390                  name, pci_name(dev->pdev));
 391
 392         eq->eqn = out.eq_number;
 393         eq->irqn = priv->msix_arr[vecidx].vector;
 394         eq->dev = dev;
 395         eq->doorbell = uar->map + MLX5_EQ_DOORBEL_OFFSET;
 396         err = request_irq(eq->irqn, mlx5_msix_handler, 0,
 397                           priv->irq_info[vecidx].name, eq);
 398         if (err)
 399                 goto err_eq;
 400
 401         err = mlx5_debug_eq_add(dev, eq);
 402         if (err)
 403                 goto err_irq;
 404
 405         /* EQs are created in ARMED state
 406          */
 407         eq_update_ci(eq, 1);
 408
 409         kvfree(in);
 410         return 0;
 411
 412 err_irq:
 413         free_irq(priv->msix_arr[vecidx].vector, eq);
 414
 415 err_eq:
 416         mlx5_cmd_destroy_eq(dev, eq->eqn);
 417
 418 err_in:
 419         kvfree(in);
 420
 421 err_buf:
 422         mlx5_buf_free(dev, &eq->buf);
 423         return err;
 424 }
 425 EXPORT_SYMBOL_GPL(mlx5_create_map_eq);
 426
 427 int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq)
 428 {
 429         int err;
 430
 431         mlx5_debug_eq_remove(dev, eq);
 432         free_irq(eq->irqn, eq);
 433         err = mlx5_cmd_destroy_eq(dev, eq->eqn);
 434         if (err)
 435                 mlx5_core_warn(dev, "failed to destroy a previously created eq: eqn %d\n",
 436                                eq->eqn);
 437         synchronize_irq(eq->irqn);
 438         mlx5_buf_free(dev, &eq->buf);
 439
 440         return err;
 441 }
 442 EXPORT_SYMBOL_GPL(mlx5_destroy_unmap_eq);
 443
 444 int mlx5_eq_init(struct mlx5_core_dev *dev)
 445 {
 446         int err;
 447
 448         spin_lock_init(&dev->priv.eq_table.lock);
 449
 450         err = mlx5_eq_debugfs_init(dev);
 451
 452         return err;
 453 }
 454
 455
 456 void mlx5_eq_cleanup(struct mlx5_core_dev *dev)
 457 {
 458         mlx5_eq_debugfs_cleanup(dev);
 459 }
 460
 461 int mlx5_start_eqs(struct mlx5_core_dev *dev)
 462 {
 463         struct mlx5_eq_table *table = &dev->priv.eq_table;
 464         u32 async_event_mask = MLX5_ASYNC_EVENT_MASK;
 465         int err;
 466
 467         if (MLX5_CAP_GEN(dev, pg))
 468                 async_event_mask |= (1ull << MLX5_EVENT_TYPE_PAGE_FAULT);
 469
 470         if (MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH &&
 471             MLX5_CAP_GEN(dev, vport_group_manager) &&
 472             mlx5_core_is_pf(dev))
 473                 async_event_mask |= (1ull << MLX5_EVENT_TYPE_NIC_VPORT_CHANGE);
 474
 475         err = mlx5_create_map_eq(dev, &table->cmd_eq, MLX5_EQ_VEC_CMD,
 476                                  MLX5_NUM_CMD_EQE, 1ull << MLX5_EVENT_TYPE_CMD,
 477                                  "mlx5_cmd_eq", &dev->priv.uuari.uars[0]);
 478         if (err) {
 479                 mlx5_core_warn(dev, "failed to create cmd EQ %d\n", err);
 480                 return err;
 481         }
 482
 483         mlx5_cmd_use_events(dev);
 484
 485         err = mlx5_create_map_eq(dev, &table->async_eq, MLX5_EQ_VEC_ASYNC,
 486                                  MLX5_NUM_ASYNC_EQE, async_event_mask,
 487                                  "mlx5_async_eq", &dev->priv.uuari.uars[0]);
 488         if (err) {
 489                 mlx5_core_warn(dev, "failed to create async EQ %d\n", err);
 490                 goto err1;
 491         }
 492
 493         err = mlx5_create_map_eq(dev, &table->pages_eq,
 494                                  MLX5_EQ_VEC_PAGES,
 495                                  /* TODO: sriov max_vf + */ 1,
 496                                  1 << MLX5_EVENT_TYPE_PAGE_REQUEST, "mlx5_pages_eq",
 497                                  &dev->priv.uuari.uars[0]);
 498         if (err) {
 499                 mlx5_core_warn(dev, "failed to create pages EQ %d\n", err);
 500                 goto err2;
 501         }
 502
 503         return err;
 504
 505 err2:
 506         mlx5_destroy_unmap_eq(dev, &table->async_eq);
 507
 508 err1:
 509         mlx5_cmd_use_polling(dev);
 510         mlx5_destroy_unmap_eq(dev, &table->cmd_eq);
 511         return err;
 512 }
 513
 514 int mlx5_stop_eqs(struct mlx5_core_dev *dev)
 515 {
 516         struct mlx5_eq_table *table = &dev->priv.eq_table;
 517         int err;
 518
 519         err = mlx5_destroy_unmap_eq(dev, &table->pages_eq);
 520         if (err)
 521                 return err;
 522
 523         mlx5_destroy_unmap_eq(dev, &table->async_eq);
 524         mlx5_cmd_use_polling(dev);
 525
 526         err = mlx5_destroy_unmap_eq(dev, &table->cmd_eq);
 527         if (err)
 528                 mlx5_cmd_use_events(dev);
 529
 530         return err;
 531 }
 532
 533 int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq,
 534                        struct mlx5_query_eq_mbox_out *out, int outlen)
 535 {
 536         struct mlx5_query_eq_mbox_in in;
 537         int err;
 538
 539         memset(&in, 0, sizeof(in));
 540         memset(out, 0, outlen);
 541         in.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_QUERY_EQ);
 542         in.eqn = eq->eqn;
 543         err = mlx5_cmd_exec(dev, &in, sizeof(in), out, outlen);
 544         if (err)
 545                 return err;
 546
 547         if (out->hdr.status)
 548                 err = mlx5_cmd_status_to_err(&out->hdr);
 549
 550         return err;
 551 }
 552 EXPORT_SYMBOL_GPL(mlx5_core_eq_query);