drivers/net/ethernet/mellanox/mlx5/core/eq.c

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/interrupt.h>
  34 #include <linux/module.h>
  35 #include <linux/mlx5/driver.h>
  36 #include <linux/mlx5/cmd.h>
  37 #include "mlx5_core.h"
  38
  39 enum {
  40         MLX5_EQE_SIZE           = sizeof(struct mlx5_eqe),
  41         MLX5_EQE_OWNER_INIT_VAL = 0x1,
  42 };
  43
  44 enum {
  45         MLX5_EQ_STATE_ARMED             = 0x9,
  46         MLX5_EQ_STATE_FIRED             = 0xa,
  47         MLX5_EQ_STATE_ALWAYS_ARMED      = 0xb,
  48 };
  49
  50 enum {
  51         MLX5_NUM_SPARE_EQE      = 0x80,
  52         MLX5_NUM_ASYNC_EQE      = 0x100,
  53         MLX5_NUM_CMD_EQE        = 32,
  54 };
  55
  56 enum {
  57         MLX5_EQ_DOORBEL_OFFSET  = 0x40,
  58 };
  59
  60 #define MLX5_ASYNC_EVENT_MASK ((1ull << MLX5_EVENT_TYPE_PATH_MIG)           | \
  61                                (1ull << MLX5_EVENT_TYPE_COMM_EST)           | \
  62                                (1ull << MLX5_EVENT_TYPE_SQ_DRAINED)         | \
  63                                (1ull << MLX5_EVENT_TYPE_CQ_ERROR)           | \
  64                                (1ull << MLX5_EVENT_TYPE_WQ_CATAS_ERROR)     | \
  65                                (1ull << MLX5_EVENT_TYPE_PATH_MIG_FAILED)    | \
  66                                (1ull << MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR) | \
  67                                (1ull << MLX5_EVENT_TYPE_WQ_ACCESS_ERROR)    | \
  68                                (1ull << MLX5_EVENT_TYPE_PORT_CHANGE)        | \
  69                                (1ull << MLX5_EVENT_TYPE_SRQ_CATAS_ERROR)    | \
  70                                (1ull << MLX5_EVENT_TYPE_SRQ_LAST_WQE)       | \
  71                                (1ull << MLX5_EVENT_TYPE_SRQ_RQ_LIMIT))
  72
  73 struct map_eq_in {
  74         u64     mask;
  75         u32     reserved;
  76         u32     unmap_eqn;
  77 };
  78
  79 struct cre_des_eq {
  80         u8      reserved[15];
  81         u8      eqn;
  82 };
  83
  84 static int mlx5_cmd_destroy_eq(struct mlx5_core_dev *dev, u8 eqn)
  85 {
  86         struct mlx5_destroy_eq_mbox_in in;
  87         struct mlx5_destroy_eq_mbox_out out;
  88         int err;
  89
  90         memset(&in, 0, sizeof(in));
  91         memset(&out, 0, sizeof(out));
  92         in.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_DESTROY_EQ);
  93         in.eqn = eqn;
  94         err = mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
  95         if (!err)
  96                 goto ex;
  97
  98         if (out.hdr.status)
  99                 err = mlx5_cmd_status_to_err(&out.hdr);
 100
 101 ex:
 102         return err;
 103 }
 104
 105 static struct mlx5_eqe *get_eqe(struct mlx5_eq *eq, u32 entry)
 106 {
 107         return mlx5_buf_offset(&eq->buf, entry * MLX5_EQE_SIZE);
 108 }
 109
 110 static struct mlx5_eqe *next_eqe_sw(struct mlx5_eq *eq)
 111 {
 112         struct mlx5_eqe *eqe = get_eqe(eq, eq->cons_index & (eq->nent - 1));
 113
 114         return ((eqe->owner & 1) ^ !!(eq->cons_index & eq->nent)) ? NULL : eqe;
 115 }
 116
 117 static const char *eqe_type_str(u8 type)
 118 {
 119         switch (type) {
 120         case MLX5_EVENT_TYPE_COMP:
 121                 return "MLX5_EVENT_TYPE_COMP";
 122         case MLX5_EVENT_TYPE_PATH_MIG:
 123                 return "MLX5_EVENT_TYPE_PATH_MIG";
 124         case MLX5_EVENT_TYPE_COMM_EST:
 125                 return "MLX5_EVENT_TYPE_COMM_EST";
 126         case MLX5_EVENT_TYPE_SQ_DRAINED:
 127                 return "MLX5_EVENT_TYPE_SQ_DRAINED";
 128         case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
 129                 return "MLX5_EVENT_TYPE_SRQ_LAST_WQE";
 130         case MLX5_EVENT_TYPE_SRQ_RQ_LIMIT:
 131                 return "MLX5_EVENT_TYPE_SRQ_RQ_LIMIT";
 132         case MLX5_EVENT_TYPE_CQ_ERROR:
 133                 return "MLX5_EVENT_TYPE_CQ_ERROR";
 134         case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
 135                 return "MLX5_EVENT_TYPE_WQ_CATAS_ERROR";
 136         case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
 137                 return "MLX5_EVENT_TYPE_PATH_MIG_FAILED";
 138         case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
 139                 return "MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR";
 140         case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
 141                 return "MLX5_EVENT_TYPE_WQ_ACCESS_ERROR";
 142         case MLX5_EVENT_TYPE_SRQ_CATAS_ERROR:
 143                 return "MLX5_EVENT_TYPE_SRQ_CATAS_ERROR";
 144         case MLX5_EVENT_TYPE_INTERNAL_ERROR:
 145                 return "MLX5_EVENT_TYPE_INTERNAL_ERROR";
 146         case MLX5_EVENT_TYPE_PORT_CHANGE:
 147                 return "MLX5_EVENT_TYPE_PORT_CHANGE";
 148         case MLX5_EVENT_TYPE_GPIO_EVENT:
 149                 return "MLX5_EVENT_TYPE_GPIO_EVENT";
 150         case MLX5_EVENT_TYPE_REMOTE_CONFIG:
 151                 return "MLX5_EVENT_TYPE_REMOTE_CONFIG";
 152         case MLX5_EVENT_TYPE_DB_BF_CONGESTION:
 153                 return "MLX5_EVENT_TYPE_DB_BF_CONGESTION";
 154         case MLX5_EVENT_TYPE_STALL_EVENT:
 155                 return "MLX5_EVENT_TYPE_STALL_EVENT";
 156         case MLX5_EVENT_TYPE_CMD:
 157                 return "MLX5_EVENT_TYPE_CMD";
 158         case MLX5_EVENT_TYPE_PAGE_REQUEST:
 159                 return "MLX5_EVENT_TYPE_PAGE_REQUEST";
 160         case MLX5_EVENT_TYPE_PAGE_FAULT:
 161                 return "MLX5_EVENT_TYPE_PAGE_FAULT";
 162         default:
 163                 return "Unrecognized event";
 164         }
 165 }
 166
 167 static enum mlx5_dev_event port_subtype_event(u8 subtype)
 168 {
 169         switch (subtype) {
 170         case MLX5_PORT_CHANGE_SUBTYPE_DOWN:
 171                 return MLX5_DEV_EVENT_PORT_DOWN;
 172         case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE:
 173                 return MLX5_DEV_EVENT_PORT_UP;
 174         case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED:
 175                 return MLX5_DEV_EVENT_PORT_INITIALIZED;
 176         case MLX5_PORT_CHANGE_SUBTYPE_LID:
 177                 return MLX5_DEV_EVENT_LID_CHANGE;
 178         case MLX5_PORT_CHANGE_SUBTYPE_PKEY:
 179                 return MLX5_DEV_EVENT_PKEY_CHANGE;
 180         case MLX5_PORT_CHANGE_SUBTYPE_GUID:
 181                 return MLX5_DEV_EVENT_GUID_CHANGE;
 182         case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG:
 183                 return MLX5_DEV_EVENT_CLIENT_REREG;
 184         }
 185         return -1;
 186 }
 187
 188 static void eq_update_ci(struct mlx5_eq *eq, int arm)
 189 {
 190         __be32 __iomem *addr = eq->doorbell + (arm ? 0 : 2);
 191         u32 val = (eq->cons_index & 0xffffff) | (eq->eqn << 24);
 192         __raw_writel((__force u32) cpu_to_be32(val), addr);
 193         /* We still want ordering, just not swabbing, so add a barrier */
 194         mb();
 195 }
 196
 197 static int mlx5_eq_int(struct mlx5_core_dev *dev, struct mlx5_eq *eq)
 198 {
 199         struct mlx5_eqe *eqe;
 200         int eqes_found = 0;
 201         int set_ci = 0;
 202         u32 cqn;
 203         u32 rsn;
 204         u8 port;
 205
 206         while ((eqe = next_eqe_sw(eq))) {
 207                 /*
 208                  * Make sure we read EQ entry contents after we've
 209                  * checked the ownership bit.
 210                  */
 211                 dma_rmb();
 212
 213                 mlx5_core_dbg(eq->dev, "eqn %d, eqe type %s\n",
 214                               eq->eqn, eqe_type_str(eqe->type));
 215                 switch (eqe->type) {
 216                 case MLX5_EVENT_TYPE_COMP:
 217                         cqn = be32_to_cpu(eqe->data.comp.cqn) & 0xffffff;
 218                         mlx5_cq_completion(dev, cqn);
 219                         break;
 220
 221                 case MLX5_EVENT_TYPE_PATH_MIG:
 222                 case MLX5_EVENT_TYPE_COMM_EST:
 223                 case MLX5_EVENT_TYPE_SQ_DRAINED:
 224                 case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
 225                 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
 226                 case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
 227                 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
 228                 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
 229                         rsn = be32_to_cpu(eqe->data.qp_srq.qp_srq_n) & 0xffffff;
 230                         rsn |= (eqe->data.qp_srq.type << MLX5_USER_INDEX_LEN);
 231                         mlx5_core_dbg(dev, "event %s(%d) arrived on resource 0x%x\n",
 232                                       eqe_type_str(eqe->type), eqe->type, rsn);
 233                         mlx5_rsc_event(dev, rsn, eqe->type);
 234                         break;
 235
 236                 case MLX5_EVENT_TYPE_SRQ_RQ_LIMIT:
 237                 case MLX5_EVENT_TYPE_SRQ_CATAS_ERROR:
 238                         rsn = be32_to_cpu(eqe->data.qp_srq.qp_srq_n) & 0xffffff;
 239                         mlx5_core_dbg(dev, "SRQ event %s(%d): srqn 0x%x\n",
 240                                       eqe_type_str(eqe->type), eqe->type, rsn);
 241                         mlx5_srq_event(dev, rsn, eqe->type);
 242                         break;
 243
 244                 case MLX5_EVENT_TYPE_CMD:
 245                         mlx5_cmd_comp_handler(dev, be32_to_cpu(eqe->data.cmd.vector));
 246                         break;
 247
 248                 case MLX5_EVENT_TYPE_PORT_CHANGE:
 249                         port = (eqe->data.port.port >> 4) & 0xf;
 250                         switch (eqe->sub_type) {
 251                         case MLX5_PORT_CHANGE_SUBTYPE_DOWN:
 252                         case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE:
 253                         case MLX5_PORT_CHANGE_SUBTYPE_LID:
 254                         case MLX5_PORT_CHANGE_SUBTYPE_PKEY:
 255                         case MLX5_PORT_CHANGE_SUBTYPE_GUID:
 256                         case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG:
 257                         case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED:
 258                                 if (dev->event)
 259                                         dev->event(dev, port_subtype_event(eqe->sub_type),
 260                                                    (unsigned long)port);
 261                                 break;
 262                         default:
 263                                 mlx5_core_warn(dev, "Port event with unrecognized subtype: port %d, sub_type %d\n",
 264                                                port, eqe->sub_type);
 265                         }
 266                         break;
 267                 case MLX5_EVENT_TYPE_CQ_ERROR:
 268                         cqn = be32_to_cpu(eqe->data.cq_err.cqn) & 0xffffff;
 269                         mlx5_core_warn(dev, "CQ error on CQN 0x%x, syndrom 0x%x\n",
 270                                        cqn, eqe->data.cq_err.syndrome);
 271                         mlx5_cq_event(dev, cqn, eqe->type);
 272                         break;
 273
 274                 case MLX5_EVENT_TYPE_PAGE_REQUEST:
 275                         {
 276                                 u16 func_id = be16_to_cpu(eqe->data.req_pages.func_id);
 277                                 s32 npages = be32_to_cpu(eqe->data.req_pages.num_pages);
 278
 279                                 mlx5_core_dbg(dev, "page request for func 0x%x, npages %d\n",
 280                                               func_id, npages);
 281                                 mlx5_core_req_pages_handler(dev, func_id, npages);
 282                         }
 283                         break;
 284
 285 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
 286                 case MLX5_EVENT_TYPE_PAGE_FAULT:
 287                         mlx5_eq_pagefault(dev, eqe);
 288                         break;
 289 #endif
 290
 291                 default:
 292                         mlx5_core_warn(dev, "Unhandled event 0x%x on EQ 0x%x\n",
 293                                        eqe->type, eq->eqn);
 294                         break;
 295                 }
 296
 297                 ++eq->cons_index;
 298                 eqes_found = 1;
 299                 ++set_ci;
 300
 301                 /* The HCA will think the queue has overflowed if we
 302                  * don't tell it we've been processing events.  We
 303                  * create our EQs with MLX5_NUM_SPARE_EQE extra
 304                  * entries, so we must update our consumer index at
 305                  * least that often.
 306                  */
 307                 if (unlikely(set_ci >= MLX5_NUM_SPARE_EQE)) {
 308                         eq_update_ci(eq, 0);
 309                         set_ci = 0;
 310                 }
 311         }
 312
 313         eq_update_ci(eq, 1);
 314
 315         return eqes_found;
 316 }
 317
 318 static irqreturn_t mlx5_msix_handler(int irq, void *eq_ptr)
 319 {
 320         struct mlx5_eq *eq = eq_ptr;
 321         struct mlx5_core_dev *dev = eq->dev;
 322
 323         mlx5_eq_int(dev, eq);
 324
 325         /* MSI-X vectors always belong to us */
 326         return IRQ_HANDLED;
 327 }
 328
 329 static void init_eq_buf(struct mlx5_eq *eq)
 330 {
 331         struct mlx5_eqe *eqe;
 332         int i;
 333
 334         for (i = 0; i < eq->nent; i++) {
 335                 eqe = get_eqe(eq, i);
 336                 eqe->owner = MLX5_EQE_OWNER_INIT_VAL;
 337         }
 338 }
 339
 340 int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx,
 341                        int nent, u64 mask, const char *name, struct mlx5_uar *uar)
 342 {
 343         struct mlx5_priv *priv = &dev->priv;
 344         struct mlx5_create_eq_mbox_in *in;
 345         struct mlx5_create_eq_mbox_out out;
 346         int err;
 347         int inlen;
 348
 349         eq->nent = roundup_pow_of_two(nent + MLX5_NUM_SPARE_EQE);
 350         eq->cons_index = 0;
 351         err = mlx5_buf_alloc(dev, eq->nent * MLX5_EQE_SIZE, &eq->buf);
 352         if (err)
 353                 return err;
 354
 355         init_eq_buf(eq);
 356
 357         inlen = sizeof(*in) + sizeof(in->pas[0]) * eq->buf.npages;
 358         in = mlx5_vzalloc(inlen);
 359         if (!in) {
 360                 err = -ENOMEM;
 361                 goto err_buf;
 362         }
 363         memset(&out, 0, sizeof(out));
 364
 365         mlx5_fill_page_array(&eq->buf, in->pas);
 366
 367         in->hdr.opcode = cpu_to_be16(MLX5_CMD_OP_CREATE_EQ);
 368         in->ctx.log_sz_usr_page = cpu_to_be32(ilog2(eq->nent) << 24 | uar->index);
 369         in->ctx.intr = vecidx;
 370         in->ctx.log_page_size = eq->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT;
 371         in->events_mask = cpu_to_be64(mask);
 372
 373         err = mlx5_cmd_exec(dev, in, inlen, &out, sizeof(out));
 374         if (err)
 375                 goto err_in;
 376
 377         if (out.hdr.status) {
 378                 err = mlx5_cmd_status_to_err(&out.hdr);
 379                 goto err_in;
 380         }
 381
 382         snprintf(priv->irq_info[vecidx].name, MLX5_MAX_IRQ_NAME, "%s@pci:%s",
 383                  name, pci_name(dev->pdev));
 384
 385         eq->eqn = out.eq_number;
 386         eq->irqn = priv->msix_arr[vecidx].vector;
 387         eq->dev = dev;
 388         eq->doorbell = uar->map + MLX5_EQ_DOORBEL_OFFSET;
 389         err = request_irq(eq->irqn, mlx5_msix_handler, 0,
 390                           priv->irq_info[vecidx].name, eq);
 391         if (err)
 392                 goto err_eq;
 393
 394         err = mlx5_debug_eq_add(dev, eq);
 395         if (err)
 396                 goto err_irq;
 397
 398         /* EQs are created in ARMED state
 399          */
 400         eq_update_ci(eq, 1);
 401
 402         kvfree(in);
 403         return 0;
 404
 405 err_irq:
 406         free_irq(priv->msix_arr[vecidx].vector, eq);
 407
 408 err_eq:
 409         mlx5_cmd_destroy_eq(dev, eq->eqn);
 410
 411 err_in:
 412         kvfree(in);
 413
 414 err_buf:
 415         mlx5_buf_free(dev, &eq->buf);
 416         return err;
 417 }
 418 EXPORT_SYMBOL_GPL(mlx5_create_map_eq);
 419
 420 int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq)
 421 {
 422         int err;
 423
 424         mlx5_debug_eq_remove(dev, eq);
 425         free_irq(eq->irqn, eq);
 426         err = mlx5_cmd_destroy_eq(dev, eq->eqn);
 427         if (err)
 428                 mlx5_core_warn(dev, "failed to destroy a previously created eq: eqn %d\n",
 429                                eq->eqn);
 430         synchronize_irq(eq->irqn);
 431         mlx5_buf_free(dev, &eq->buf);
 432
 433         return err;
 434 }
 435 EXPORT_SYMBOL_GPL(mlx5_destroy_unmap_eq);
 436
 437 int mlx5_eq_init(struct mlx5_core_dev *dev)
 438 {
 439         int err;
 440
 441         spin_lock_init(&dev->priv.eq_table.lock);
 442
 443         err = mlx5_eq_debugfs_init(dev);
 444
 445         return err;
 446 }
 447
 448
 449 void mlx5_eq_cleanup(struct mlx5_core_dev *dev)
 450 {
 451         mlx5_eq_debugfs_cleanup(dev);
 452 }
 453
 454 int mlx5_start_eqs(struct mlx5_core_dev *dev)
 455 {
 456         struct mlx5_eq_table *table = &dev->priv.eq_table;
 457         u32 async_event_mask = MLX5_ASYNC_EVENT_MASK;
 458         int err;
 459
 460         if (MLX5_CAP_GEN(dev, pg))
 461                 async_event_mask |= (1ull << MLX5_EVENT_TYPE_PAGE_FAULT);
 462
 463         err = mlx5_create_map_eq(dev, &table->cmd_eq, MLX5_EQ_VEC_CMD,
 464                                  MLX5_NUM_CMD_EQE, 1ull << MLX5_EVENT_TYPE_CMD,
 465                                  "mlx5_cmd_eq", &dev->priv.uuari.uars[0]);
 466         if (err) {
 467                 mlx5_core_warn(dev, "failed to create cmd EQ %d\n", err);
 468                 return err;
 469         }
 470
 471         mlx5_cmd_use_events(dev);
 472
 473         err = mlx5_create_map_eq(dev, &table->async_eq, MLX5_EQ_VEC_ASYNC,
 474                                  MLX5_NUM_ASYNC_EQE, async_event_mask,
 475                                  "mlx5_async_eq", &dev->priv.uuari.uars[0]);
 476         if (err) {
 477                 mlx5_core_warn(dev, "failed to create async EQ %d\n", err);
 478                 goto err1;
 479         }
 480
 481         err = mlx5_create_map_eq(dev, &table->pages_eq,
 482                                  MLX5_EQ_VEC_PAGES,
 483                                  /* TODO: sriov max_vf + */ 1,
 484                                  1 << MLX5_EVENT_TYPE_PAGE_REQUEST, "mlx5_pages_eq",
 485                                  &dev->priv.uuari.uars[0]);
 486         if (err) {
 487                 mlx5_core_warn(dev, "failed to create pages EQ %d\n", err);
 488                 goto err2;
 489         }
 490
 491         return err;
 492
 493 err2:
 494         mlx5_destroy_unmap_eq(dev, &table->async_eq);
 495
 496 err1:
 497         mlx5_cmd_use_polling(dev);
 498         mlx5_destroy_unmap_eq(dev, &table->cmd_eq);
 499         return err;
 500 }
 501
 502 int mlx5_stop_eqs(struct mlx5_core_dev *dev)
 503 {
 504         struct mlx5_eq_table *table = &dev->priv.eq_table;
 505         int err;
 506
 507         err = mlx5_destroy_unmap_eq(dev, &table->pages_eq);
 508         if (err)
 509                 return err;
 510
 511         mlx5_destroy_unmap_eq(dev, &table->async_eq);
 512         mlx5_cmd_use_polling(dev);
 513
 514         err = mlx5_destroy_unmap_eq(dev, &table->cmd_eq);
 515         if (err)
 516                 mlx5_cmd_use_events(dev);
 517
 518         return err;
 519 }
 520
 521 int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq,
 522                        struct mlx5_query_eq_mbox_out *out, int outlen)
 523 {
 524         struct mlx5_query_eq_mbox_in in;
 525         int err;
 526
 527         memset(&in, 0, sizeof(in));
 528         memset(out, 0, outlen);
 529         in.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_QUERY_EQ);
 530         in.eqn = eq->eqn;
 531         err = mlx5_cmd_exec(dev, &in, sizeof(in), out, outlen);
 532         if (err)
 533                 return err;
 534
 535         if (out->hdr.status)
 536                 err = mlx5_cmd_status_to_err(&out->hdr);
 537
 538         return err;
 539 }
 540 EXPORT_SYMBOL_GPL(mlx5_core_eq_query);