2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <asm-generic/kmap_types.h>
34 #include <linux/module.h>
35 #include <linux/init.h>
36 #include <linux/errno.h>
37 #include <linux/pci.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/slab.h>
40 #include <linux/io-mapping.h>
41 #include <linux/interrupt.h>
42 #include <linux/mlx5/driver.h>
43 #include <linux/mlx5/cq.h>
44 #include <linux/mlx5/qp.h>
45 #include <linux/mlx5/srq.h>
46 #include <linux/debugfs.h>
47 #include <linux/kmod.h>
48 #include <linux/mlx5/mlx5_ifc.h>
49 #include "mlx5_core.h"
51 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
52 MODULE_DESCRIPTION("Mellanox Connect-IB, ConnectX-4 core driver");
53 MODULE_LICENSE("Dual BSD/GPL");
54 MODULE_VERSION(DRIVER_VERSION
);
56 int mlx5_core_debug_mask
;
57 module_param_named(debug_mask
, mlx5_core_debug_mask
, int, 0644);
58 MODULE_PARM_DESC(debug_mask
, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0");
60 #define MLX5_DEFAULT_PROF 2
61 static int prof_sel
= MLX5_DEFAULT_PROF
;
62 module_param_named(prof_sel
, prof_sel
, int, 0444);
63 MODULE_PARM_DESC(prof_sel
, "profile selector. Valid range 0 - 2");
65 struct workqueue_struct
*mlx5_core_wq
;
66 static LIST_HEAD(intf_list
);
67 static LIST_HEAD(dev_list
);
68 static DEFINE_MUTEX(intf_mutex
);
70 struct mlx5_device_context
{
71 struct list_head list
;
72 struct mlx5_interface
*intf
;
76 static struct mlx5_profile profile
[] = {
81 .mask
= MLX5_PROF_MASK_QP_SIZE
,
85 .mask
= MLX5_PROF_MASK_QP_SIZE
|
86 MLX5_PROF_MASK_MR_CACHE
,
155 static int set_dma_caps(struct pci_dev
*pdev
)
159 err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(64));
161 dev_warn(&pdev
->dev
, "Warning: couldn't set 64-bit PCI DMA mask\n");
162 err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
164 dev_err(&pdev
->dev
, "Can't set PCI DMA mask, aborting\n");
169 err
= pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(64));
172 "Warning: couldn't set 64-bit consistent PCI DMA mask\n");
173 err
= pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(32));
176 "Can't set consistent PCI DMA mask, aborting\n");
181 dma_set_max_seg_size(&pdev
->dev
, 2u * 1024 * 1024 * 1024);
185 static int request_bar(struct pci_dev
*pdev
)
189 if (!(pci_resource_flags(pdev
, 0) & IORESOURCE_MEM
)) {
190 dev_err(&pdev
->dev
, "Missing registers BAR, aborting\n");
194 err
= pci_request_regions(pdev
, DRIVER_NAME
);
196 dev_err(&pdev
->dev
, "Couldn't get PCI resources, aborting\n");
201 static void release_bar(struct pci_dev
*pdev
)
203 pci_release_regions(pdev
);
206 static int mlx5_enable_msix(struct mlx5_core_dev
*dev
)
208 struct mlx5_priv
*priv
= &dev
->priv
;
209 struct mlx5_eq_table
*table
= &priv
->eq_table
;
210 int num_eqs
= 1 << MLX5_CAP_GEN(dev
, log_max_eq
);
214 nvec
= MLX5_CAP_GEN(dev
, num_ports
) * num_online_cpus() +
215 MLX5_EQ_VEC_COMP_BASE
;
216 nvec
= min_t(int, nvec
, num_eqs
);
217 if (nvec
<= MLX5_EQ_VEC_COMP_BASE
)
220 priv
->msix_arr
= kcalloc(nvec
, sizeof(*priv
->msix_arr
), GFP_KERNEL
);
222 priv
->irq_info
= kcalloc(nvec
, sizeof(*priv
->irq_info
), GFP_KERNEL
);
223 if (!priv
->msix_arr
|| !priv
->irq_info
)
226 for (i
= 0; i
< nvec
; i
++)
227 priv
->msix_arr
[i
].entry
= i
;
229 nvec
= pci_enable_msix_range(dev
->pdev
, priv
->msix_arr
,
230 MLX5_EQ_VEC_COMP_BASE
+ 1, nvec
);
234 table
->num_comp_vectors
= nvec
- MLX5_EQ_VEC_COMP_BASE
;
239 kfree(priv
->irq_info
);
240 kfree(priv
->msix_arr
);
244 static void mlx5_disable_msix(struct mlx5_core_dev
*dev
)
246 struct mlx5_priv
*priv
= &dev
->priv
;
248 pci_disable_msix(dev
->pdev
);
249 kfree(priv
->irq_info
);
250 kfree(priv
->msix_arr
);
253 struct mlx5_reg_host_endianess
{
259 #define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos))
262 MLX5_CAP_BITS_RW_MASK
= CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM
, 2) |
263 MLX5_DEV_CAP_FLAG_DCT
,
266 static u16
to_fw_pkey_sz(u32 size
)
282 pr_warn("invalid pkey table size %d\n", size
);
287 static u16
to_sw_pkey_sz(int pkey_sz
)
289 if (pkey_sz
> MLX5_MAX_LOG_PKEY_TABLE
)
292 return MLX5_MIN_PKEY_TABLE_SIZE
<< pkey_sz
;
295 int mlx5_core_get_caps(struct mlx5_core_dev
*dev
, enum mlx5_cap_type cap_type
,
296 enum mlx5_cap_mode cap_mode
)
298 u8 in
[MLX5_ST_SZ_BYTES(query_hca_cap_in
)];
299 int out_sz
= MLX5_ST_SZ_BYTES(query_hca_cap_out
);
300 void *out
, *hca_caps
;
301 u16 opmod
= (cap_type
<< 1) | (cap_mode
& 0x01);
304 memset(in
, 0, sizeof(in
));
305 out
= kzalloc(out_sz
, GFP_KERNEL
);
309 MLX5_SET(query_hca_cap_in
, in
, opcode
, MLX5_CMD_OP_QUERY_HCA_CAP
);
310 MLX5_SET(query_hca_cap_in
, in
, op_mod
, opmod
);
311 err
= mlx5_cmd_exec(dev
, in
, sizeof(in
), out
, out_sz
);
315 err
= mlx5_cmd_status_to_err_v2(out
);
318 "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n",
319 cap_type
, cap_mode
, err
);
323 hca_caps
= MLX5_ADDR_OF(query_hca_cap_out
, out
, capability
);
326 case HCA_CAP_OPMOD_GET_MAX
:
327 memcpy(dev
->hca_caps_max
[cap_type
], hca_caps
,
328 MLX5_UN_SZ_BYTES(hca_cap_union
));
330 case HCA_CAP_OPMOD_GET_CUR
:
331 memcpy(dev
->hca_caps_cur
[cap_type
], hca_caps
,
332 MLX5_UN_SZ_BYTES(hca_cap_union
));
336 "Tried to query dev cap type(%x) with wrong opmode(%x)\n",
346 static int set_caps(struct mlx5_core_dev
*dev
, void *in
, int in_sz
)
348 u32 out
[MLX5_ST_SZ_DW(set_hca_cap_out
)];
351 memset(out
, 0, sizeof(out
));
353 MLX5_SET(set_hca_cap_in
, in
, opcode
, MLX5_CMD_OP_SET_HCA_CAP
);
354 err
= mlx5_cmd_exec(dev
, in
, in_sz
, out
, sizeof(out
));
358 err
= mlx5_cmd_status_to_err_v2(out
);
363 static int handle_hca_cap(struct mlx5_core_dev
*dev
)
365 void *set_ctx
= NULL
;
366 struct mlx5_profile
*prof
= dev
->profile
;
368 int set_sz
= MLX5_ST_SZ_BYTES(set_hca_cap_in
);
371 set_ctx
= kzalloc(set_sz
, GFP_KERNEL
);
375 err
= mlx5_core_get_caps(dev
, MLX5_CAP_GENERAL
, HCA_CAP_OPMOD_GET_MAX
);
379 err
= mlx5_core_get_caps(dev
, MLX5_CAP_GENERAL
, HCA_CAP_OPMOD_GET_CUR
);
383 set_hca_cap
= MLX5_ADDR_OF(set_hca_cap_in
, set_ctx
,
385 memcpy(set_hca_cap
, dev
->hca_caps_cur
[MLX5_CAP_GENERAL
],
386 MLX5_ST_SZ_BYTES(cmd_hca_cap
));
388 mlx5_core_dbg(dev
, "Current Pkey table size %d Setting new size %d\n",
389 to_sw_pkey_sz(MLX5_CAP_GEN(dev
, pkey_table_size
)),
391 /* we limit the size of the pkey table to 128 entries for now */
392 MLX5_SET(cmd_hca_cap
, set_hca_cap
, pkey_table_size
,
395 if (prof
->mask
& MLX5_PROF_MASK_QP_SIZE
)
396 MLX5_SET(cmd_hca_cap
, set_hca_cap
, log_max_qp
,
399 /* disable cmdif checksum */
400 MLX5_SET(cmd_hca_cap
, set_hca_cap
, cmdif_checksum
, 0);
402 err
= set_caps(dev
, set_ctx
, set_sz
);
409 static int set_hca_ctrl(struct mlx5_core_dev
*dev
)
411 struct mlx5_reg_host_endianess he_in
;
412 struct mlx5_reg_host_endianess he_out
;
415 memset(&he_in
, 0, sizeof(he_in
));
416 he_in
.he
= MLX5_SET_HOST_ENDIANNESS
;
417 err
= mlx5_core_access_reg(dev
, &he_in
, sizeof(he_in
),
418 &he_out
, sizeof(he_out
),
419 MLX5_REG_HOST_ENDIANNESS
, 0, 1);
423 static int mlx5_core_enable_hca(struct mlx5_core_dev
*dev
)
426 struct mlx5_enable_hca_mbox_in in
;
427 struct mlx5_enable_hca_mbox_out out
;
429 memset(&in
, 0, sizeof(in
));
430 memset(&out
, 0, sizeof(out
));
431 in
.hdr
.opcode
= cpu_to_be16(MLX5_CMD_OP_ENABLE_HCA
);
432 err
= mlx5_cmd_exec(dev
, &in
, sizeof(in
), &out
, sizeof(out
));
437 return mlx5_cmd_status_to_err(&out
.hdr
);
442 static int mlx5_core_disable_hca(struct mlx5_core_dev
*dev
)
445 struct mlx5_disable_hca_mbox_in in
;
446 struct mlx5_disable_hca_mbox_out out
;
448 memset(&in
, 0, sizeof(in
));
449 memset(&out
, 0, sizeof(out
));
450 in
.hdr
.opcode
= cpu_to_be16(MLX5_CMD_OP_DISABLE_HCA
);
451 err
= mlx5_cmd_exec(dev
, &in
, sizeof(in
), &out
, sizeof(out
));
456 return mlx5_cmd_status_to_err(&out
.hdr
);
461 static int mlx5_irq_set_affinity_hint(struct mlx5_core_dev
*mdev
, int i
)
463 struct mlx5_priv
*priv
= &mdev
->priv
;
464 struct msix_entry
*msix
= priv
->msix_arr
;
465 int irq
= msix
[i
+ MLX5_EQ_VEC_COMP_BASE
].vector
;
466 int numa_node
= dev_to_node(&mdev
->pdev
->dev
);
469 if (!zalloc_cpumask_var(&priv
->irq_info
[i
].mask
, GFP_KERNEL
)) {
470 mlx5_core_warn(mdev
, "zalloc_cpumask_var failed");
474 err
= cpumask_set_cpu_local_first(i
, numa_node
, priv
->irq_info
[i
].mask
);
476 mlx5_core_warn(mdev
, "cpumask_set_cpu_local_first failed");
480 err
= irq_set_affinity_hint(irq
, priv
->irq_info
[i
].mask
);
482 mlx5_core_warn(mdev
, "irq_set_affinity_hint failed,irq 0x%.4x",
490 free_cpumask_var(priv
->irq_info
[i
].mask
);
494 static void mlx5_irq_clear_affinity_hint(struct mlx5_core_dev
*mdev
, int i
)
496 struct mlx5_priv
*priv
= &mdev
->priv
;
497 struct msix_entry
*msix
= priv
->msix_arr
;
498 int irq
= msix
[i
+ MLX5_EQ_VEC_COMP_BASE
].vector
;
500 irq_set_affinity_hint(irq
, NULL
);
501 free_cpumask_var(priv
->irq_info
[i
].mask
);
504 static int mlx5_irq_set_affinity_hints(struct mlx5_core_dev
*mdev
)
509 for (i
= 0; i
< mdev
->priv
.eq_table
.num_comp_vectors
; i
++) {
510 err
= mlx5_irq_set_affinity_hint(mdev
, i
);
518 for (i
--; i
>= 0; i
--)
519 mlx5_irq_clear_affinity_hint(mdev
, i
);
524 static void mlx5_irq_clear_affinity_hints(struct mlx5_core_dev
*mdev
)
528 for (i
= 0; i
< mdev
->priv
.eq_table
.num_comp_vectors
; i
++)
529 mlx5_irq_clear_affinity_hint(mdev
, i
);
532 int mlx5_vector2eqn(struct mlx5_core_dev
*dev
, int vector
, int *eqn
, int *irqn
)
534 struct mlx5_eq_table
*table
= &dev
->priv
.eq_table
;
535 struct mlx5_eq
*eq
, *n
;
538 spin_lock(&table
->lock
);
539 list_for_each_entry_safe(eq
, n
, &table
->comp_eqs_list
, list
) {
540 if (eq
->index
== vector
) {
547 spin_unlock(&table
->lock
);
551 EXPORT_SYMBOL(mlx5_vector2eqn
);
553 static void free_comp_eqs(struct mlx5_core_dev
*dev
)
555 struct mlx5_eq_table
*table
= &dev
->priv
.eq_table
;
556 struct mlx5_eq
*eq
, *n
;
558 spin_lock(&table
->lock
);
559 list_for_each_entry_safe(eq
, n
, &table
->comp_eqs_list
, list
) {
561 spin_unlock(&table
->lock
);
562 if (mlx5_destroy_unmap_eq(dev
, eq
))
563 mlx5_core_warn(dev
, "failed to destroy EQ 0x%x\n",
566 spin_lock(&table
->lock
);
568 spin_unlock(&table
->lock
);
571 static int alloc_comp_eqs(struct mlx5_core_dev
*dev
)
573 struct mlx5_eq_table
*table
= &dev
->priv
.eq_table
;
574 char name
[MLX5_MAX_IRQ_NAME
];
581 INIT_LIST_HEAD(&table
->comp_eqs_list
);
582 ncomp_vec
= table
->num_comp_vectors
;
583 nent
= MLX5_COMP_EQ_SIZE
;
584 for (i
= 0; i
< ncomp_vec
; i
++) {
585 eq
= kzalloc(sizeof(*eq
), GFP_KERNEL
);
591 snprintf(name
, MLX5_MAX_IRQ_NAME
, "mlx5_comp%d", i
);
592 err
= mlx5_create_map_eq(dev
, eq
,
593 i
+ MLX5_EQ_VEC_COMP_BASE
, nent
, 0,
594 name
, &dev
->priv
.uuari
.uars
[0]);
599 mlx5_core_dbg(dev
, "allocated completion EQN %d\n", eq
->eqn
);
601 spin_lock(&table
->lock
);
602 list_add_tail(&eq
->list
, &table
->comp_eqs_list
);
603 spin_unlock(&table
->lock
);
613 #ifdef CONFIG_MLX5_CORE_EN
614 static int mlx5_core_set_issi(struct mlx5_core_dev
*dev
)
616 u32 query_in
[MLX5_ST_SZ_DW(query_issi_in
)];
617 u32 query_out
[MLX5_ST_SZ_DW(query_issi_out
)];
618 u32 set_in
[MLX5_ST_SZ_DW(set_issi_in
)];
619 u32 set_out
[MLX5_ST_SZ_DW(set_issi_out
)];
623 memset(query_in
, 0, sizeof(query_in
));
624 memset(query_out
, 0, sizeof(query_out
));
626 MLX5_SET(query_issi_in
, query_in
, opcode
, MLX5_CMD_OP_QUERY_ISSI
);
628 err
= mlx5_cmd_exec_check_status(dev
, query_in
, sizeof(query_in
),
629 query_out
, sizeof(query_out
));
631 if (((struct mlx5_outbox_hdr
*)query_out
)->status
==
632 MLX5_CMD_STAT_BAD_OP_ERR
) {
633 pr_debug("Only ISSI 0 is supported\n");
637 pr_err("failed to query ISSI\n");
641 sup_issi
= MLX5_GET(query_issi_out
, query_out
, supported_issi_dw0
);
643 if (sup_issi
& (1 << 1)) {
644 memset(set_in
, 0, sizeof(set_in
));
645 memset(set_out
, 0, sizeof(set_out
));
647 MLX5_SET(set_issi_in
, set_in
, opcode
, MLX5_CMD_OP_SET_ISSI
);
648 MLX5_SET(set_issi_in
, set_in
, current_issi
, 1);
650 err
= mlx5_cmd_exec_check_status(dev
, set_in
, sizeof(set_in
),
651 set_out
, sizeof(set_out
));
653 pr_err("failed to set ISSI=1\n");
660 } else if (sup_issi
& (1 << 0)) {
668 static int mlx5_dev_init(struct mlx5_core_dev
*dev
, struct pci_dev
*pdev
)
670 struct mlx5_priv
*priv
= &dev
->priv
;
674 pci_set_drvdata(dev
->pdev
, dev
);
675 strncpy(priv
->name
, dev_name(&pdev
->dev
), MLX5_MAX_NAME_LEN
);
676 priv
->name
[MLX5_MAX_NAME_LEN
- 1] = 0;
678 mutex_init(&priv
->pgdir_mutex
);
679 INIT_LIST_HEAD(&priv
->pgdir_list
);
680 spin_lock_init(&priv
->mkey_lock
);
682 priv
->dbg_root
= debugfs_create_dir(dev_name(&pdev
->dev
), mlx5_debugfs_root
);
686 err
= pci_enable_device(pdev
);
688 dev_err(&pdev
->dev
, "Cannot enable PCI device, aborting\n");
692 err
= request_bar(pdev
);
694 dev_err(&pdev
->dev
, "error requesting BARs, aborting\n");
698 pci_set_master(pdev
);
700 err
= set_dma_caps(pdev
);
702 dev_err(&pdev
->dev
, "Failed setting DMA capabilities mask, aborting\n");
706 dev
->iseg_base
= pci_resource_start(dev
->pdev
, 0);
707 dev
->iseg
= ioremap(dev
->iseg_base
, sizeof(*dev
->iseg
));
710 dev_err(&pdev
->dev
, "Failed mapping initialization segment, aborting\n");
713 dev_info(&pdev
->dev
, "firmware version: %d.%d.%d\n", fw_rev_maj(dev
),
714 fw_rev_min(dev
), fw_rev_sub(dev
));
716 err
= mlx5_cmd_init(dev
);
718 dev_err(&pdev
->dev
, "Failed initializing command interface, aborting\n");
722 mlx5_pagealloc_init(dev
);
724 err
= mlx5_core_enable_hca(dev
);
726 dev_err(&pdev
->dev
, "enable hca failed\n");
727 goto err_pagealloc_cleanup
;
730 #ifdef CONFIG_MLX5_CORE_EN
731 err
= mlx5_core_set_issi(dev
);
733 dev_err(&pdev
->dev
, "failed to set issi\n");
734 goto err_disable_hca
;
738 err
= mlx5_satisfy_startup_pages(dev
, 1);
740 dev_err(&pdev
->dev
, "failed to allocate boot pages\n");
741 goto err_disable_hca
;
744 err
= set_hca_ctrl(dev
);
746 dev_err(&pdev
->dev
, "set_hca_ctrl failed\n");
747 goto reclaim_boot_pages
;
750 err
= handle_hca_cap(dev
);
752 dev_err(&pdev
->dev
, "handle_hca_cap failed\n");
753 goto reclaim_boot_pages
;
756 err
= mlx5_satisfy_startup_pages(dev
, 0);
758 dev_err(&pdev
->dev
, "failed to allocate init pages\n");
759 goto reclaim_boot_pages
;
762 err
= mlx5_pagealloc_start(dev
);
764 dev_err(&pdev
->dev
, "mlx5_pagealloc_start failed\n");
765 goto reclaim_boot_pages
;
768 err
= mlx5_cmd_init_hca(dev
);
770 dev_err(&pdev
->dev
, "init hca failed\n");
771 goto err_pagealloc_stop
;
774 mlx5_start_health_poll(dev
);
776 err
= mlx5_query_hca_caps(dev
);
778 dev_err(&pdev
->dev
, "query hca failed\n");
782 err
= mlx5_cmd_query_adapter(dev
);
784 dev_err(&pdev
->dev
, "query adapter failed\n");
788 err
= mlx5_enable_msix(dev
);
790 dev_err(&pdev
->dev
, "enable msix failed\n");
794 err
= mlx5_eq_init(dev
);
796 dev_err(&pdev
->dev
, "failed to initialize eq\n");
800 err
= mlx5_alloc_uuars(dev
, &priv
->uuari
);
802 dev_err(&pdev
->dev
, "Failed allocating uar, aborting\n");
806 err
= mlx5_start_eqs(dev
);
808 dev_err(&pdev
->dev
, "Failed to start pages and async EQs\n");
812 err
= alloc_comp_eqs(dev
);
814 dev_err(&pdev
->dev
, "Failed to alloc completion EQs\n");
818 err
= mlx5_irq_set_affinity_hints(dev
);
820 dev_err(&pdev
->dev
, "Failed to alloc affinity hint cpumask\n");
821 goto err_free_comp_eqs
;
824 MLX5_INIT_DOORBELL_LOCK(&priv
->cq_uar_lock
);
826 mlx5_init_cq_table(dev
);
827 mlx5_init_qp_table(dev
);
828 mlx5_init_srq_table(dev
);
829 mlx5_init_mr_table(dev
);
840 mlx5_free_uuars(dev
, &priv
->uuari
);
843 mlx5_eq_cleanup(dev
);
846 mlx5_disable_msix(dev
);
849 mlx5_stop_health_poll(dev
);
850 if (mlx5_cmd_teardown_hca(dev
)) {
851 dev_err(&dev
->pdev
->dev
, "tear_down_hca failed, skip cleanup\n");
856 mlx5_pagealloc_stop(dev
);
859 mlx5_reclaim_startup_pages(dev
);
862 mlx5_core_disable_hca(dev
);
864 err_pagealloc_cleanup
:
865 mlx5_pagealloc_cleanup(dev
);
866 mlx5_cmd_cleanup(dev
);
872 pci_clear_master(dev
->pdev
);
873 release_bar(dev
->pdev
);
876 pci_disable_device(dev
->pdev
);
879 debugfs_remove(priv
->dbg_root
);
883 static void mlx5_dev_cleanup(struct mlx5_core_dev
*dev
)
885 struct mlx5_priv
*priv
= &dev
->priv
;
887 mlx5_cleanup_srq_table(dev
);
888 mlx5_cleanup_qp_table(dev
);
889 mlx5_cleanup_cq_table(dev
);
890 mlx5_irq_clear_affinity_hints(dev
);
893 mlx5_free_uuars(dev
, &priv
->uuari
);
894 mlx5_eq_cleanup(dev
);
895 mlx5_disable_msix(dev
);
896 mlx5_stop_health_poll(dev
);
897 if (mlx5_cmd_teardown_hca(dev
)) {
898 dev_err(&dev
->pdev
->dev
, "tear_down_hca failed, skip cleanup\n");
901 mlx5_pagealloc_stop(dev
);
902 mlx5_reclaim_startup_pages(dev
);
903 mlx5_core_disable_hca(dev
);
904 mlx5_pagealloc_cleanup(dev
);
905 mlx5_cmd_cleanup(dev
);
907 pci_clear_master(dev
->pdev
);
908 release_bar(dev
->pdev
);
909 pci_disable_device(dev
->pdev
);
910 debugfs_remove(priv
->dbg_root
);
913 static void mlx5_add_device(struct mlx5_interface
*intf
, struct mlx5_priv
*priv
)
915 struct mlx5_device_context
*dev_ctx
;
916 struct mlx5_core_dev
*dev
= container_of(priv
, struct mlx5_core_dev
, priv
);
918 dev_ctx
= kmalloc(sizeof(*dev_ctx
), GFP_KERNEL
);
920 pr_warn("mlx5_add_device: alloc context failed\n");
924 dev_ctx
->intf
= intf
;
925 dev_ctx
->context
= intf
->add(dev
);
927 if (dev_ctx
->context
) {
928 spin_lock_irq(&priv
->ctx_lock
);
929 list_add_tail(&dev_ctx
->list
, &priv
->ctx_list
);
930 spin_unlock_irq(&priv
->ctx_lock
);
936 static void mlx5_remove_device(struct mlx5_interface
*intf
, struct mlx5_priv
*priv
)
938 struct mlx5_device_context
*dev_ctx
;
939 struct mlx5_core_dev
*dev
= container_of(priv
, struct mlx5_core_dev
, priv
);
941 list_for_each_entry(dev_ctx
, &priv
->ctx_list
, list
)
942 if (dev_ctx
->intf
== intf
) {
943 spin_lock_irq(&priv
->ctx_lock
);
944 list_del(&dev_ctx
->list
);
945 spin_unlock_irq(&priv
->ctx_lock
);
947 intf
->remove(dev
, dev_ctx
->context
);
952 static int mlx5_register_device(struct mlx5_core_dev
*dev
)
954 struct mlx5_priv
*priv
= &dev
->priv
;
955 struct mlx5_interface
*intf
;
957 mutex_lock(&intf_mutex
);
958 list_add_tail(&priv
->dev_list
, &dev_list
);
959 list_for_each_entry(intf
, &intf_list
, list
)
960 mlx5_add_device(intf
, priv
);
961 mutex_unlock(&intf_mutex
);
965 static void mlx5_unregister_device(struct mlx5_core_dev
*dev
)
967 struct mlx5_priv
*priv
= &dev
->priv
;
968 struct mlx5_interface
*intf
;
970 mutex_lock(&intf_mutex
);
971 list_for_each_entry(intf
, &intf_list
, list
)
972 mlx5_remove_device(intf
, priv
);
973 list_del(&priv
->dev_list
);
974 mutex_unlock(&intf_mutex
);
977 int mlx5_register_interface(struct mlx5_interface
*intf
)
979 struct mlx5_priv
*priv
;
981 if (!intf
->add
|| !intf
->remove
)
984 mutex_lock(&intf_mutex
);
985 list_add_tail(&intf
->list
, &intf_list
);
986 list_for_each_entry(priv
, &dev_list
, dev_list
)
987 mlx5_add_device(intf
, priv
);
988 mutex_unlock(&intf_mutex
);
992 EXPORT_SYMBOL(mlx5_register_interface
);
994 void mlx5_unregister_interface(struct mlx5_interface
*intf
)
996 struct mlx5_priv
*priv
;
998 mutex_lock(&intf_mutex
);
999 list_for_each_entry(priv
, &dev_list
, dev_list
)
1000 mlx5_remove_device(intf
, priv
);
1001 list_del(&intf
->list
);
1002 mutex_unlock(&intf_mutex
);
1004 EXPORT_SYMBOL(mlx5_unregister_interface
);
1006 void *mlx5_get_protocol_dev(struct mlx5_core_dev
*mdev
, int protocol
)
1008 struct mlx5_priv
*priv
= &mdev
->priv
;
1009 struct mlx5_device_context
*dev_ctx
;
1010 unsigned long flags
;
1011 void *result
= NULL
;
1013 spin_lock_irqsave(&priv
->ctx_lock
, flags
);
1015 list_for_each_entry(dev_ctx
, &mdev
->priv
.ctx_list
, list
)
1016 if ((dev_ctx
->intf
->protocol
== protocol
) &&
1017 dev_ctx
->intf
->get_dev
) {
1018 result
= dev_ctx
->intf
->get_dev(dev_ctx
->context
);
1022 spin_unlock_irqrestore(&priv
->ctx_lock
, flags
);
1026 EXPORT_SYMBOL(mlx5_get_protocol_dev
);
1028 static void mlx5_core_event(struct mlx5_core_dev
*dev
, enum mlx5_dev_event event
,
1029 unsigned long param
)
1031 struct mlx5_priv
*priv
= &dev
->priv
;
1032 struct mlx5_device_context
*dev_ctx
;
1033 unsigned long flags
;
1035 spin_lock_irqsave(&priv
->ctx_lock
, flags
);
1037 list_for_each_entry(dev_ctx
, &priv
->ctx_list
, list
)
1038 if (dev_ctx
->intf
->event
)
1039 dev_ctx
->intf
->event(dev
, dev_ctx
->context
, event
, param
);
1041 spin_unlock_irqrestore(&priv
->ctx_lock
, flags
);
1044 struct mlx5_core_event_handler
{
1045 void (*event
)(struct mlx5_core_dev
*dev
,
1046 enum mlx5_dev_event event
,
1050 #define MLX5_IB_MOD "mlx5_ib"
1052 static int init_one(struct pci_dev
*pdev
,
1053 const struct pci_device_id
*id
)
1055 struct mlx5_core_dev
*dev
;
1056 struct mlx5_priv
*priv
;
1059 dev
= kzalloc(sizeof(*dev
), GFP_KERNEL
);
1061 dev_err(&pdev
->dev
, "kzalloc failed\n");
1066 pci_set_drvdata(pdev
, dev
);
1068 if (prof_sel
< 0 || prof_sel
>= ARRAY_SIZE(profile
)) {
1069 pr_warn("selected profile out of range, selecting default (%d)\n",
1071 prof_sel
= MLX5_DEFAULT_PROF
;
1073 dev
->profile
= &profile
[prof_sel
];
1074 dev
->event
= mlx5_core_event
;
1076 INIT_LIST_HEAD(&priv
->ctx_list
);
1077 spin_lock_init(&priv
->ctx_lock
);
1078 err
= mlx5_dev_init(dev
, pdev
);
1080 dev_err(&pdev
->dev
, "mlx5_dev_init failed %d\n", err
);
1084 err
= mlx5_register_device(dev
);
1086 dev_err(&pdev
->dev
, "mlx5_register_device failed %d\n", err
);
1090 err
= request_module_nowait(MLX5_IB_MOD
);
1092 pr_info("failed request module on %s\n", MLX5_IB_MOD
);
1097 mlx5_dev_cleanup(dev
);
1102 static void remove_one(struct pci_dev
*pdev
)
1104 struct mlx5_core_dev
*dev
= pci_get_drvdata(pdev
);
1106 mlx5_unregister_device(dev
);
1107 mlx5_dev_cleanup(dev
);
1111 static const struct pci_device_id mlx5_core_pci_table
[] = {
1112 { PCI_VDEVICE(MELLANOX
, 0x1011) }, /* Connect-IB */
1113 { PCI_VDEVICE(MELLANOX
, 0x1012) }, /* Connect-IB VF */
1114 { PCI_VDEVICE(MELLANOX
, 0x1013) }, /* ConnectX-4 */
1115 { PCI_VDEVICE(MELLANOX
, 0x1014) }, /* ConnectX-4 VF */
1116 { PCI_VDEVICE(MELLANOX
, 0x1015) }, /* ConnectX-4LX */
1117 { PCI_VDEVICE(MELLANOX
, 0x1016) }, /* ConnectX-4LX VF */
1121 MODULE_DEVICE_TABLE(pci
, mlx5_core_pci_table
);
1123 static struct pci_driver mlx5_core_driver
= {
1124 .name
= DRIVER_NAME
,
1125 .id_table
= mlx5_core_pci_table
,
1127 .remove
= remove_one
1130 static int __init
init(void)
1134 mlx5_register_debugfs();
1135 mlx5_core_wq
= create_singlethread_workqueue("mlx5_core_wq");
1136 if (!mlx5_core_wq
) {
1142 err
= pci_register_driver(&mlx5_core_driver
);
1146 #ifdef CONFIG_MLX5_CORE_EN
1153 mlx5_health_cleanup();
1154 destroy_workqueue(mlx5_core_wq
);
1156 mlx5_unregister_debugfs();
1160 static void __exit
cleanup(void)
1162 #ifdef CONFIG_MLX5_CORE_EN
1165 pci_unregister_driver(&mlx5_core_driver
);
1166 mlx5_health_cleanup();
1167 destroy_workqueue(mlx5_core_wq
);
1168 mlx5_unregister_debugfs();
1172 module_exit(cleanup
);