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Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next
[deliverable/linux.git] / drivers / net / ethernet / mellanox / mlx5 / core / main.c
1 /*
2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <linux/highmem.h>
34 #include <linux/module.h>
35 #include <linux/init.h>
36 #include <linux/errno.h>
37 #include <linux/pci.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/slab.h>
40 #include <linux/io-mapping.h>
41 #include <linux/interrupt.h>
42 #include <linux/delay.h>
43 #include <linux/mlx5/driver.h>
44 #include <linux/mlx5/cq.h>
45 #include <linux/mlx5/qp.h>
46 #include <linux/mlx5/srq.h>
47 #include <linux/debugfs.h>
48 #include <linux/kmod.h>
49 #include <linux/delay.h>
50 #include <linux/mlx5/mlx5_ifc.h>
51 #include "mlx5_core.h"
52 #include "fs_core.h"
53 #ifdef CONFIG_MLX5_CORE_EN
54 #include "eswitch.h"
55 #endif
56
57 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
58 MODULE_DESCRIPTION("Mellanox Connect-IB, ConnectX-4 core driver");
59 MODULE_LICENSE("Dual BSD/GPL");
60 MODULE_VERSION(DRIVER_VERSION);
61
62 int mlx5_core_debug_mask;
63 module_param_named(debug_mask, mlx5_core_debug_mask, int, 0644);
64 MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0");
65
66 #define MLX5_DEFAULT_PROF 2
67 static int prof_sel = MLX5_DEFAULT_PROF;
68 module_param_named(prof_sel, prof_sel, int, 0444);
69 MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2");
70
71 static LIST_HEAD(intf_list);
72 static LIST_HEAD(dev_list);
73 static DEFINE_MUTEX(intf_mutex);
74
75 struct mlx5_device_context {
76 struct list_head list;
77 struct mlx5_interface *intf;
78 void *context;
79 };
80
81 enum {
82 MLX5_ATOMIC_REQ_MODE_BE = 0x0,
83 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1,
84 };
85
86 static struct mlx5_profile profile[] = {
87 [0] = {
88 .mask = 0,
89 },
90 [1] = {
91 .mask = MLX5_PROF_MASK_QP_SIZE,
92 .log_max_qp = 12,
93 },
94 [2] = {
95 .mask = MLX5_PROF_MASK_QP_SIZE |
96 MLX5_PROF_MASK_MR_CACHE,
97 .log_max_qp = 17,
98 .mr_cache[0] = {
99 .size = 500,
100 .limit = 250
101 },
102 .mr_cache[1] = {
103 .size = 500,
104 .limit = 250
105 },
106 .mr_cache[2] = {
107 .size = 500,
108 .limit = 250
109 },
110 .mr_cache[3] = {
111 .size = 500,
112 .limit = 250
113 },
114 .mr_cache[4] = {
115 .size = 500,
116 .limit = 250
117 },
118 .mr_cache[5] = {
119 .size = 500,
120 .limit = 250
121 },
122 .mr_cache[6] = {
123 .size = 500,
124 .limit = 250
125 },
126 .mr_cache[7] = {
127 .size = 500,
128 .limit = 250
129 },
130 .mr_cache[8] = {
131 .size = 500,
132 .limit = 250
133 },
134 .mr_cache[9] = {
135 .size = 500,
136 .limit = 250
137 },
138 .mr_cache[10] = {
139 .size = 500,
140 .limit = 250
141 },
142 .mr_cache[11] = {
143 .size = 500,
144 .limit = 250
145 },
146 .mr_cache[12] = {
147 .size = 64,
148 .limit = 32
149 },
150 .mr_cache[13] = {
151 .size = 32,
152 .limit = 16
153 },
154 .mr_cache[14] = {
155 .size = 16,
156 .limit = 8
157 },
158 .mr_cache[15] = {
159 .size = 8,
160 .limit = 4
161 },
162 },
163 };
164
165 #define FW_INIT_TIMEOUT_MILI 2000
166 #define FW_INIT_WAIT_MS 2
167
168 static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili)
169 {
170 unsigned long end = jiffies + msecs_to_jiffies(max_wait_mili);
171 int err = 0;
172
173 while (fw_initializing(dev)) {
174 if (time_after(jiffies, end)) {
175 err = -EBUSY;
176 break;
177 }
178 msleep(FW_INIT_WAIT_MS);
179 }
180
181 return err;
182 }
183
184 static int set_dma_caps(struct pci_dev *pdev)
185 {
186 int err;
187
188 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
189 if (err) {
190 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n");
191 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
192 if (err) {
193 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n");
194 return err;
195 }
196 }
197
198 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
199 if (err) {
200 dev_warn(&pdev->dev,
201 "Warning: couldn't set 64-bit consistent PCI DMA mask\n");
202 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
203 if (err) {
204 dev_err(&pdev->dev,
205 "Can't set consistent PCI DMA mask, aborting\n");
206 return err;
207 }
208 }
209
210 dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024);
211 return err;
212 }
213
214 static int mlx5_pci_enable_device(struct mlx5_core_dev *dev)
215 {
216 struct pci_dev *pdev = dev->pdev;
217 int err = 0;
218
219 mutex_lock(&dev->pci_status_mutex);
220 if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) {
221 err = pci_enable_device(pdev);
222 if (!err)
223 dev->pci_status = MLX5_PCI_STATUS_ENABLED;
224 }
225 mutex_unlock(&dev->pci_status_mutex);
226
227 return err;
228 }
229
230 static void mlx5_pci_disable_device(struct mlx5_core_dev *dev)
231 {
232 struct pci_dev *pdev = dev->pdev;
233
234 mutex_lock(&dev->pci_status_mutex);
235 if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) {
236 pci_disable_device(pdev);
237 dev->pci_status = MLX5_PCI_STATUS_DISABLED;
238 }
239 mutex_unlock(&dev->pci_status_mutex);
240 }
241
242 static int request_bar(struct pci_dev *pdev)
243 {
244 int err = 0;
245
246 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
247 dev_err(&pdev->dev, "Missing registers BAR, aborting\n");
248 return -ENODEV;
249 }
250
251 err = pci_request_regions(pdev, DRIVER_NAME);
252 if (err)
253 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
254
255 return err;
256 }
257
258 static void release_bar(struct pci_dev *pdev)
259 {
260 pci_release_regions(pdev);
261 }
262
263 static int mlx5_enable_msix(struct mlx5_core_dev *dev)
264 {
265 struct mlx5_priv *priv = &dev->priv;
266 struct mlx5_eq_table *table = &priv->eq_table;
267 int num_eqs = 1 << MLX5_CAP_GEN(dev, log_max_eq);
268 int nvec;
269 int i;
270
271 nvec = MLX5_CAP_GEN(dev, num_ports) * num_online_cpus() +
272 MLX5_EQ_VEC_COMP_BASE;
273 nvec = min_t(int, nvec, num_eqs);
274 if (nvec <= MLX5_EQ_VEC_COMP_BASE)
275 return -ENOMEM;
276
277 priv->msix_arr = kcalloc(nvec, sizeof(*priv->msix_arr), GFP_KERNEL);
278
279 priv->irq_info = kcalloc(nvec, sizeof(*priv->irq_info), GFP_KERNEL);
280 if (!priv->msix_arr || !priv->irq_info)
281 goto err_free_msix;
282
283 for (i = 0; i < nvec; i++)
284 priv->msix_arr[i].entry = i;
285
286 nvec = pci_enable_msix_range(dev->pdev, priv->msix_arr,
287 MLX5_EQ_VEC_COMP_BASE + 1, nvec);
288 if (nvec < 0)
289 return nvec;
290
291 table->num_comp_vectors = nvec - MLX5_EQ_VEC_COMP_BASE;
292
293 return 0;
294
295 err_free_msix:
296 kfree(priv->irq_info);
297 kfree(priv->msix_arr);
298 return -ENOMEM;
299 }
300
301 static void mlx5_disable_msix(struct mlx5_core_dev *dev)
302 {
303 struct mlx5_priv *priv = &dev->priv;
304
305 pci_disable_msix(dev->pdev);
306 kfree(priv->irq_info);
307 kfree(priv->msix_arr);
308 }
309
310 struct mlx5_reg_host_endianess {
311 u8 he;
312 u8 rsvd[15];
313 };
314
315
316 #define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos))
317
318 enum {
319 MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) |
320 MLX5_DEV_CAP_FLAG_DCT,
321 };
322
323 static u16 to_fw_pkey_sz(u32 size)
324 {
325 switch (size) {
326 case 128:
327 return 0;
328 case 256:
329 return 1;
330 case 512:
331 return 2;
332 case 1024:
333 return 3;
334 case 2048:
335 return 4;
336 case 4096:
337 return 5;
338 default:
339 pr_warn("invalid pkey table size %d\n", size);
340 return 0;
341 }
342 }
343
344 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type,
345 enum mlx5_cap_mode cap_mode)
346 {
347 u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)];
348 int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
349 void *out, *hca_caps;
350 u16 opmod = (cap_type << 1) | (cap_mode & 0x01);
351 int err;
352
353 memset(in, 0, sizeof(in));
354 out = kzalloc(out_sz, GFP_KERNEL);
355 if (!out)
356 return -ENOMEM;
357
358 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
359 MLX5_SET(query_hca_cap_in, in, op_mod, opmod);
360 err = mlx5_cmd_exec(dev, in, sizeof(in), out, out_sz);
361 if (err)
362 goto query_ex;
363
364 err = mlx5_cmd_status_to_err_v2(out);
365 if (err) {
366 mlx5_core_warn(dev,
367 "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n",
368 cap_type, cap_mode, err);
369 goto query_ex;
370 }
371
372 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
373
374 switch (cap_mode) {
375 case HCA_CAP_OPMOD_GET_MAX:
376 memcpy(dev->hca_caps_max[cap_type], hca_caps,
377 MLX5_UN_SZ_BYTES(hca_cap_union));
378 break;
379 case HCA_CAP_OPMOD_GET_CUR:
380 memcpy(dev->hca_caps_cur[cap_type], hca_caps,
381 MLX5_UN_SZ_BYTES(hca_cap_union));
382 break;
383 default:
384 mlx5_core_warn(dev,
385 "Tried to query dev cap type(%x) with wrong opmode(%x)\n",
386 cap_type, cap_mode);
387 err = -EINVAL;
388 break;
389 }
390 query_ex:
391 kfree(out);
392 return err;
393 }
394
395 static int set_caps(struct mlx5_core_dev *dev, void *in, int in_sz, int opmod)
396 {
397 u32 out[MLX5_ST_SZ_DW(set_hca_cap_out)];
398 int err;
399
400 memset(out, 0, sizeof(out));
401
402 MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP);
403 MLX5_SET(set_hca_cap_in, in, op_mod, opmod << 1);
404 err = mlx5_cmd_exec(dev, in, in_sz, out, sizeof(out));
405 if (err)
406 return err;
407
408 err = mlx5_cmd_status_to_err_v2(out);
409
410 return err;
411 }
412
413 static int handle_hca_cap_atomic(struct mlx5_core_dev *dev)
414 {
415 void *set_ctx;
416 void *set_hca_cap;
417 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
418 int req_endianness;
419 int err;
420
421 if (MLX5_CAP_GEN(dev, atomic)) {
422 err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC,
423 HCA_CAP_OPMOD_GET_CUR);
424 if (err)
425 return err;
426 } else {
427 return 0;
428 }
429
430 req_endianness =
431 MLX5_CAP_ATOMIC(dev,
432 supported_atomic_req_8B_endianess_mode_1);
433
434 if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS)
435 return 0;
436
437 set_ctx = kzalloc(set_sz, GFP_KERNEL);
438 if (!set_ctx)
439 return -ENOMEM;
440
441 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
442
443 /* Set requestor to host endianness */
444 MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianess_mode,
445 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS);
446
447 err = set_caps(dev, set_ctx, set_sz, MLX5_SET_HCA_CAP_OP_MOD_ATOMIC);
448
449 kfree(set_ctx);
450 return err;
451 }
452
453 static int handle_hca_cap(struct mlx5_core_dev *dev)
454 {
455 void *set_ctx = NULL;
456 struct mlx5_profile *prof = dev->profile;
457 int err = -ENOMEM;
458 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
459 void *set_hca_cap;
460
461 set_ctx = kzalloc(set_sz, GFP_KERNEL);
462 if (!set_ctx)
463 goto query_ex;
464
465 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL, HCA_CAP_OPMOD_GET_MAX);
466 if (err)
467 goto query_ex;
468
469 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL, HCA_CAP_OPMOD_GET_CUR);
470 if (err)
471 goto query_ex;
472
473 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx,
474 capability);
475 memcpy(set_hca_cap, dev->hca_caps_cur[MLX5_CAP_GENERAL],
476 MLX5_ST_SZ_BYTES(cmd_hca_cap));
477
478 mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n",
479 mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)),
480 128);
481 /* we limit the size of the pkey table to 128 entries for now */
482 MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size,
483 to_fw_pkey_sz(128));
484
485 if (prof->mask & MLX5_PROF_MASK_QP_SIZE)
486 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp,
487 prof->log_max_qp);
488
489 /* disable cmdif checksum */
490 MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0);
491
492 MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12);
493
494 err = set_caps(dev, set_ctx, set_sz,
495 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE);
496
497 query_ex:
498 kfree(set_ctx);
499 return err;
500 }
501
502 static int set_hca_ctrl(struct mlx5_core_dev *dev)
503 {
504 struct mlx5_reg_host_endianess he_in;
505 struct mlx5_reg_host_endianess he_out;
506 int err;
507
508 if (!mlx5_core_is_pf(dev))
509 return 0;
510
511 memset(&he_in, 0, sizeof(he_in));
512 he_in.he = MLX5_SET_HOST_ENDIANNESS;
513 err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in),
514 &he_out, sizeof(he_out),
515 MLX5_REG_HOST_ENDIANNESS, 0, 1);
516 return err;
517 }
518
519 int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id)
520 {
521 u32 out[MLX5_ST_SZ_DW(enable_hca_out)];
522 u32 in[MLX5_ST_SZ_DW(enable_hca_in)];
523 int err;
524
525 memset(in, 0, sizeof(in));
526 MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA);
527 MLX5_SET(enable_hca_in, in, function_id, func_id);
528 memset(out, 0, sizeof(out));
529
530 err = mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
531 if (err)
532 return err;
533
534 return mlx5_cmd_status_to_err_v2(out);
535 }
536
537 int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id)
538 {
539 u32 out[MLX5_ST_SZ_DW(disable_hca_out)];
540 u32 in[MLX5_ST_SZ_DW(disable_hca_in)];
541 int err;
542
543 memset(in, 0, sizeof(in));
544 MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA);
545 MLX5_SET(disable_hca_in, in, function_id, func_id);
546 memset(out, 0, sizeof(out));
547 err = mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
548 if (err)
549 return err;
550
551 return mlx5_cmd_status_to_err_v2(out);
552 }
553
554 cycle_t mlx5_read_internal_timer(struct mlx5_core_dev *dev)
555 {
556 u32 timer_h, timer_h1, timer_l;
557
558 timer_h = ioread32be(&dev->iseg->internal_timer_h);
559 timer_l = ioread32be(&dev->iseg->internal_timer_l);
560 timer_h1 = ioread32be(&dev->iseg->internal_timer_h);
561 if (timer_h != timer_h1) /* wrap around */
562 timer_l = ioread32be(&dev->iseg->internal_timer_l);
563
564 return (cycle_t)timer_l | (cycle_t)timer_h1 << 32;
565 }
566
567 static int mlx5_irq_set_affinity_hint(struct mlx5_core_dev *mdev, int i)
568 {
569 struct mlx5_priv *priv = &mdev->priv;
570 struct msix_entry *msix = priv->msix_arr;
571 int irq = msix[i + MLX5_EQ_VEC_COMP_BASE].vector;
572 int numa_node = priv->numa_node;
573 int err;
574
575 if (!zalloc_cpumask_var(&priv->irq_info[i].mask, GFP_KERNEL)) {
576 mlx5_core_warn(mdev, "zalloc_cpumask_var failed");
577 return -ENOMEM;
578 }
579
580 cpumask_set_cpu(cpumask_local_spread(i, numa_node),
581 priv->irq_info[i].mask);
582
583 err = irq_set_affinity_hint(irq, priv->irq_info[i].mask);
584 if (err) {
585 mlx5_core_warn(mdev, "irq_set_affinity_hint failed,irq 0x%.4x",
586 irq);
587 goto err_clear_mask;
588 }
589
590 return 0;
591
592 err_clear_mask:
593 free_cpumask_var(priv->irq_info[i].mask);
594 return err;
595 }
596
597 static void mlx5_irq_clear_affinity_hint(struct mlx5_core_dev *mdev, int i)
598 {
599 struct mlx5_priv *priv = &mdev->priv;
600 struct msix_entry *msix = priv->msix_arr;
601 int irq = msix[i + MLX5_EQ_VEC_COMP_BASE].vector;
602
603 irq_set_affinity_hint(irq, NULL);
604 free_cpumask_var(priv->irq_info[i].mask);
605 }
606
607 static int mlx5_irq_set_affinity_hints(struct mlx5_core_dev *mdev)
608 {
609 int err;
610 int i;
611
612 for (i = 0; i < mdev->priv.eq_table.num_comp_vectors; i++) {
613 err = mlx5_irq_set_affinity_hint(mdev, i);
614 if (err)
615 goto err_out;
616 }
617
618 return 0;
619
620 err_out:
621 for (i--; i >= 0; i--)
622 mlx5_irq_clear_affinity_hint(mdev, i);
623
624 return err;
625 }
626
627 static void mlx5_irq_clear_affinity_hints(struct mlx5_core_dev *mdev)
628 {
629 int i;
630
631 for (i = 0; i < mdev->priv.eq_table.num_comp_vectors; i++)
632 mlx5_irq_clear_affinity_hint(mdev, i);
633 }
634
635 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn,
636 unsigned int *irqn)
637 {
638 struct mlx5_eq_table *table = &dev->priv.eq_table;
639 struct mlx5_eq *eq, *n;
640 int err = -ENOENT;
641
642 spin_lock(&table->lock);
643 list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) {
644 if (eq->index == vector) {
645 *eqn = eq->eqn;
646 *irqn = eq->irqn;
647 err = 0;
648 break;
649 }
650 }
651 spin_unlock(&table->lock);
652
653 return err;
654 }
655 EXPORT_SYMBOL(mlx5_vector2eqn);
656
657 static void free_comp_eqs(struct mlx5_core_dev *dev)
658 {
659 struct mlx5_eq_table *table = &dev->priv.eq_table;
660 struct mlx5_eq *eq, *n;
661
662 spin_lock(&table->lock);
663 list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) {
664 list_del(&eq->list);
665 spin_unlock(&table->lock);
666 if (mlx5_destroy_unmap_eq(dev, eq))
667 mlx5_core_warn(dev, "failed to destroy EQ 0x%x\n",
668 eq->eqn);
669 kfree(eq);
670 spin_lock(&table->lock);
671 }
672 spin_unlock(&table->lock);
673 }
674
675 static int alloc_comp_eqs(struct mlx5_core_dev *dev)
676 {
677 struct mlx5_eq_table *table = &dev->priv.eq_table;
678 char name[MLX5_MAX_IRQ_NAME];
679 struct mlx5_eq *eq;
680 int ncomp_vec;
681 int nent;
682 int err;
683 int i;
684
685 INIT_LIST_HEAD(&table->comp_eqs_list);
686 ncomp_vec = table->num_comp_vectors;
687 nent = MLX5_COMP_EQ_SIZE;
688 for (i = 0; i < ncomp_vec; i++) {
689 eq = kzalloc(sizeof(*eq), GFP_KERNEL);
690 if (!eq) {
691 err = -ENOMEM;
692 goto clean;
693 }
694
695 snprintf(name, MLX5_MAX_IRQ_NAME, "mlx5_comp%d", i);
696 err = mlx5_create_map_eq(dev, eq,
697 i + MLX5_EQ_VEC_COMP_BASE, nent, 0,
698 name, &dev->priv.uuari.uars[0]);
699 if (err) {
700 kfree(eq);
701 goto clean;
702 }
703 mlx5_core_dbg(dev, "allocated completion EQN %d\n", eq->eqn);
704 eq->index = i;
705 spin_lock(&table->lock);
706 list_add_tail(&eq->list, &table->comp_eqs_list);
707 spin_unlock(&table->lock);
708 }
709
710 return 0;
711
712 clean:
713 free_comp_eqs(dev);
714 return err;
715 }
716
717 static int mlx5_core_set_issi(struct mlx5_core_dev *dev)
718 {
719 u32 query_in[MLX5_ST_SZ_DW(query_issi_in)];
720 u32 query_out[MLX5_ST_SZ_DW(query_issi_out)];
721 u32 set_in[MLX5_ST_SZ_DW(set_issi_in)];
722 u32 set_out[MLX5_ST_SZ_DW(set_issi_out)];
723 int err;
724 u32 sup_issi;
725
726 memset(query_in, 0, sizeof(query_in));
727 memset(query_out, 0, sizeof(query_out));
728
729 MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI);
730
731 err = mlx5_cmd_exec_check_status(dev, query_in, sizeof(query_in),
732 query_out, sizeof(query_out));
733 if (err) {
734 if (((struct mlx5_outbox_hdr *)query_out)->status ==
735 MLX5_CMD_STAT_BAD_OP_ERR) {
736 pr_debug("Only ISSI 0 is supported\n");
737 return 0;
738 }
739
740 pr_err("failed to query ISSI\n");
741 return err;
742 }
743
744 sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0);
745
746 if (sup_issi & (1 << 1)) {
747 memset(set_in, 0, sizeof(set_in));
748 memset(set_out, 0, sizeof(set_out));
749
750 MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI);
751 MLX5_SET(set_issi_in, set_in, current_issi, 1);
752
753 err = mlx5_cmd_exec_check_status(dev, set_in, sizeof(set_in),
754 set_out, sizeof(set_out));
755 if (err) {
756 pr_err("failed to set ISSI=1\n");
757 return err;
758 }
759
760 dev->issi = 1;
761
762 return 0;
763 } else if (sup_issi & (1 << 0) || !sup_issi) {
764 return 0;
765 }
766
767 return -ENOTSUPP;
768 }
769
770 static void mlx5_add_device(struct mlx5_interface *intf, struct mlx5_priv *priv)
771 {
772 struct mlx5_device_context *dev_ctx;
773 struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv);
774
775 dev_ctx = kmalloc(sizeof(*dev_ctx), GFP_KERNEL);
776 if (!dev_ctx)
777 return;
778
779 dev_ctx->intf = intf;
780 dev_ctx->context = intf->add(dev);
781
782 if (dev_ctx->context) {
783 spin_lock_irq(&priv->ctx_lock);
784 list_add_tail(&dev_ctx->list, &priv->ctx_list);
785 spin_unlock_irq(&priv->ctx_lock);
786 } else {
787 kfree(dev_ctx);
788 }
789 }
790
791 static void mlx5_remove_device(struct mlx5_interface *intf, struct mlx5_priv *priv)
792 {
793 struct mlx5_device_context *dev_ctx;
794 struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv);
795
796 list_for_each_entry(dev_ctx, &priv->ctx_list, list)
797 if (dev_ctx->intf == intf) {
798 spin_lock_irq(&priv->ctx_lock);
799 list_del(&dev_ctx->list);
800 spin_unlock_irq(&priv->ctx_lock);
801
802 intf->remove(dev, dev_ctx->context);
803 kfree(dev_ctx);
804 return;
805 }
806 }
807
808 static int mlx5_register_device(struct mlx5_core_dev *dev)
809 {
810 struct mlx5_priv *priv = &dev->priv;
811 struct mlx5_interface *intf;
812
813 mutex_lock(&intf_mutex);
814 list_add_tail(&priv->dev_list, &dev_list);
815 list_for_each_entry(intf, &intf_list, list)
816 mlx5_add_device(intf, priv);
817 mutex_unlock(&intf_mutex);
818
819 return 0;
820 }
821
822 static void mlx5_unregister_device(struct mlx5_core_dev *dev)
823 {
824 struct mlx5_priv *priv = &dev->priv;
825 struct mlx5_interface *intf;
826
827 mutex_lock(&intf_mutex);
828 list_for_each_entry(intf, &intf_list, list)
829 mlx5_remove_device(intf, priv);
830 list_del(&priv->dev_list);
831 mutex_unlock(&intf_mutex);
832 }
833
834 int mlx5_register_interface(struct mlx5_interface *intf)
835 {
836 struct mlx5_priv *priv;
837
838 if (!intf->add || !intf->remove)
839 return -EINVAL;
840
841 mutex_lock(&intf_mutex);
842 list_add_tail(&intf->list, &intf_list);
843 list_for_each_entry(priv, &dev_list, dev_list)
844 mlx5_add_device(intf, priv);
845 mutex_unlock(&intf_mutex);
846
847 return 0;
848 }
849 EXPORT_SYMBOL(mlx5_register_interface);
850
851 void mlx5_unregister_interface(struct mlx5_interface *intf)
852 {
853 struct mlx5_priv *priv;
854
855 mutex_lock(&intf_mutex);
856 list_for_each_entry(priv, &dev_list, dev_list)
857 mlx5_remove_device(intf, priv);
858 list_del(&intf->list);
859 mutex_unlock(&intf_mutex);
860 }
861 EXPORT_SYMBOL(mlx5_unregister_interface);
862
863 void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol)
864 {
865 struct mlx5_priv *priv = &mdev->priv;
866 struct mlx5_device_context *dev_ctx;
867 unsigned long flags;
868 void *result = NULL;
869
870 spin_lock_irqsave(&priv->ctx_lock, flags);
871
872 list_for_each_entry(dev_ctx, &mdev->priv.ctx_list, list)
873 if ((dev_ctx->intf->protocol == protocol) &&
874 dev_ctx->intf->get_dev) {
875 result = dev_ctx->intf->get_dev(dev_ctx->context);
876 break;
877 }
878
879 spin_unlock_irqrestore(&priv->ctx_lock, flags);
880
881 return result;
882 }
883 EXPORT_SYMBOL(mlx5_get_protocol_dev);
884
885 static int mlx5_pci_init(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
886 {
887 struct pci_dev *pdev = dev->pdev;
888 int err = 0;
889
890 pci_set_drvdata(dev->pdev, dev);
891 strncpy(priv->name, dev_name(&pdev->dev), MLX5_MAX_NAME_LEN);
892 priv->name[MLX5_MAX_NAME_LEN - 1] = 0;
893
894 mutex_init(&priv->pgdir_mutex);
895 INIT_LIST_HEAD(&priv->pgdir_list);
896 spin_lock_init(&priv->mkey_lock);
897
898 mutex_init(&priv->alloc_mutex);
899
900 priv->numa_node = dev_to_node(&dev->pdev->dev);
901
902 priv->dbg_root = debugfs_create_dir(dev_name(&pdev->dev), mlx5_debugfs_root);
903 if (!priv->dbg_root)
904 return -ENOMEM;
905
906 err = mlx5_pci_enable_device(dev);
907 if (err) {
908 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
909 goto err_dbg;
910 }
911
912 err = request_bar(pdev);
913 if (err) {
914 dev_err(&pdev->dev, "error requesting BARs, aborting\n");
915 goto err_disable;
916 }
917
918 pci_set_master(pdev);
919
920 err = set_dma_caps(pdev);
921 if (err) {
922 dev_err(&pdev->dev, "Failed setting DMA capabilities mask, aborting\n");
923 goto err_clr_master;
924 }
925
926 dev->iseg_base = pci_resource_start(dev->pdev, 0);
927 dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg));
928 if (!dev->iseg) {
929 err = -ENOMEM;
930 dev_err(&pdev->dev, "Failed mapping initialization segment, aborting\n");
931 goto err_clr_master;
932 }
933
934 return 0;
935
936 err_clr_master:
937 pci_clear_master(dev->pdev);
938 release_bar(dev->pdev);
939 err_disable:
940 mlx5_pci_disable_device(dev);
941
942 err_dbg:
943 debugfs_remove(priv->dbg_root);
944 return err;
945 }
946
947 static void mlx5_pci_close(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
948 {
949 iounmap(dev->iseg);
950 pci_clear_master(dev->pdev);
951 release_bar(dev->pdev);
952 mlx5_pci_disable_device(dev);
953 debugfs_remove(priv->dbg_root);
954 }
955
956 #define MLX5_IB_MOD "mlx5_ib"
957 static int mlx5_load_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
958 {
959 struct pci_dev *pdev = dev->pdev;
960 int err;
961
962 mutex_lock(&dev->intf_state_mutex);
963 if (dev->interface_state == MLX5_INTERFACE_STATE_UP) {
964 dev_warn(&dev->pdev->dev, "%s: interface is up, NOP\n",
965 __func__);
966 goto out;
967 }
968
969 dev_info(&pdev->dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev),
970 fw_rev_min(dev), fw_rev_sub(dev));
971
972 /* on load removing any previous indication of internal error, device is
973 * up
974 */
975 dev->state = MLX5_DEVICE_STATE_UP;
976
977 err = mlx5_cmd_init(dev);
978 if (err) {
979 dev_err(&pdev->dev, "Failed initializing command interface, aborting\n");
980 goto out_err;
981 }
982
983 err = wait_fw_init(dev, FW_INIT_TIMEOUT_MILI);
984 if (err) {
985 dev_err(&dev->pdev->dev, "Firmware over %d MS in initializing state, aborting\n",
986 FW_INIT_TIMEOUT_MILI);
987 goto out_err;
988 }
989
990 mlx5_pagealloc_init(dev);
991
992 err = mlx5_core_enable_hca(dev, 0);
993 if (err) {
994 dev_err(&pdev->dev, "enable hca failed\n");
995 goto err_pagealloc_cleanup;
996 }
997
998 err = mlx5_core_set_issi(dev);
999 if (err) {
1000 dev_err(&pdev->dev, "failed to set issi\n");
1001 goto err_disable_hca;
1002 }
1003
1004 err = mlx5_satisfy_startup_pages(dev, 1);
1005 if (err) {
1006 dev_err(&pdev->dev, "failed to allocate boot pages\n");
1007 goto err_disable_hca;
1008 }
1009
1010 err = set_hca_ctrl(dev);
1011 if (err) {
1012 dev_err(&pdev->dev, "set_hca_ctrl failed\n");
1013 goto reclaim_boot_pages;
1014 }
1015
1016 err = handle_hca_cap(dev);
1017 if (err) {
1018 dev_err(&pdev->dev, "handle_hca_cap failed\n");
1019 goto reclaim_boot_pages;
1020 }
1021
1022 err = handle_hca_cap_atomic(dev);
1023 if (err) {
1024 dev_err(&pdev->dev, "handle_hca_cap_atomic failed\n");
1025 goto reclaim_boot_pages;
1026 }
1027
1028 err = mlx5_satisfy_startup_pages(dev, 0);
1029 if (err) {
1030 dev_err(&pdev->dev, "failed to allocate init pages\n");
1031 goto reclaim_boot_pages;
1032 }
1033
1034 err = mlx5_pagealloc_start(dev);
1035 if (err) {
1036 dev_err(&pdev->dev, "mlx5_pagealloc_start failed\n");
1037 goto reclaim_boot_pages;
1038 }
1039
1040 err = mlx5_cmd_init_hca(dev);
1041 if (err) {
1042 dev_err(&pdev->dev, "init hca failed\n");
1043 goto err_pagealloc_stop;
1044 }
1045
1046 mlx5_start_health_poll(dev);
1047
1048 err = mlx5_query_hca_caps(dev);
1049 if (err) {
1050 dev_err(&pdev->dev, "query hca failed\n");
1051 goto err_stop_poll;
1052 }
1053
1054 err = mlx5_query_board_id(dev);
1055 if (err) {
1056 dev_err(&pdev->dev, "query board id failed\n");
1057 goto err_stop_poll;
1058 }
1059
1060 err = mlx5_enable_msix(dev);
1061 if (err) {
1062 dev_err(&pdev->dev, "enable msix failed\n");
1063 goto err_stop_poll;
1064 }
1065
1066 err = mlx5_eq_init(dev);
1067 if (err) {
1068 dev_err(&pdev->dev, "failed to initialize eq\n");
1069 goto disable_msix;
1070 }
1071
1072 err = mlx5_alloc_uuars(dev, &priv->uuari);
1073 if (err) {
1074 dev_err(&pdev->dev, "Failed allocating uar, aborting\n");
1075 goto err_eq_cleanup;
1076 }
1077
1078 err = mlx5_start_eqs(dev);
1079 if (err) {
1080 dev_err(&pdev->dev, "Failed to start pages and async EQs\n");
1081 goto err_free_uar;
1082 }
1083
1084 err = alloc_comp_eqs(dev);
1085 if (err) {
1086 dev_err(&pdev->dev, "Failed to alloc completion EQs\n");
1087 goto err_stop_eqs;
1088 }
1089
1090 err = mlx5_irq_set_affinity_hints(dev);
1091 if (err)
1092 dev_err(&pdev->dev, "Failed to alloc affinity hint cpumask\n");
1093
1094 MLX5_INIT_DOORBELL_LOCK(&priv->cq_uar_lock);
1095
1096 mlx5_init_cq_table(dev);
1097 mlx5_init_qp_table(dev);
1098 mlx5_init_srq_table(dev);
1099 mlx5_init_mkey_table(dev);
1100
1101 err = mlx5_init_fs(dev);
1102 if (err) {
1103 dev_err(&pdev->dev, "Failed to init flow steering\n");
1104 goto err_fs;
1105 }
1106 #ifdef CONFIG_MLX5_CORE_EN
1107 err = mlx5_eswitch_init(dev);
1108 if (err) {
1109 dev_err(&pdev->dev, "eswitch init failed %d\n", err);
1110 goto err_reg_dev;
1111 }
1112 #endif
1113
1114 err = mlx5_sriov_init(dev);
1115 if (err) {
1116 dev_err(&pdev->dev, "sriov init failed %d\n", err);
1117 goto err_sriov;
1118 }
1119
1120 err = mlx5_register_device(dev);
1121 if (err) {
1122 dev_err(&pdev->dev, "mlx5_register_device failed %d\n", err);
1123 goto err_reg_dev;
1124 }
1125
1126 err = request_module_nowait(MLX5_IB_MOD);
1127 if (err)
1128 pr_info("failed request module on %s\n", MLX5_IB_MOD);
1129
1130 dev->interface_state = MLX5_INTERFACE_STATE_UP;
1131 out:
1132 mutex_unlock(&dev->intf_state_mutex);
1133
1134 return 0;
1135
1136 err_sriov:
1137 if (mlx5_sriov_cleanup(dev))
1138 dev_err(&dev->pdev->dev, "sriov cleanup failed\n");
1139
1140 #ifdef CONFIG_MLX5_CORE_EN
1141 mlx5_eswitch_cleanup(dev->priv.eswitch);
1142 #endif
1143 err_reg_dev:
1144 mlx5_cleanup_fs(dev);
1145 err_fs:
1146 mlx5_cleanup_mkey_table(dev);
1147 mlx5_cleanup_srq_table(dev);
1148 mlx5_cleanup_qp_table(dev);
1149 mlx5_cleanup_cq_table(dev);
1150 mlx5_irq_clear_affinity_hints(dev);
1151 free_comp_eqs(dev);
1152
1153 err_stop_eqs:
1154 mlx5_stop_eqs(dev);
1155
1156 err_free_uar:
1157 mlx5_free_uuars(dev, &priv->uuari);
1158
1159 err_eq_cleanup:
1160 mlx5_eq_cleanup(dev);
1161
1162 disable_msix:
1163 mlx5_disable_msix(dev);
1164
1165 err_stop_poll:
1166 mlx5_stop_health_poll(dev);
1167 if (mlx5_cmd_teardown_hca(dev)) {
1168 dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n");
1169 goto out_err;
1170 }
1171
1172 err_pagealloc_stop:
1173 mlx5_pagealloc_stop(dev);
1174
1175 reclaim_boot_pages:
1176 mlx5_reclaim_startup_pages(dev);
1177
1178 err_disable_hca:
1179 mlx5_core_disable_hca(dev, 0);
1180
1181 err_pagealloc_cleanup:
1182 mlx5_pagealloc_cleanup(dev);
1183 mlx5_cmd_cleanup(dev);
1184
1185 out_err:
1186 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
1187 mutex_unlock(&dev->intf_state_mutex);
1188
1189 return err;
1190 }
1191
1192 static int mlx5_unload_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
1193 {
1194 int err = 0;
1195
1196 err = mlx5_sriov_cleanup(dev);
1197 if (err) {
1198 dev_warn(&dev->pdev->dev, "%s: sriov cleanup failed - abort\n",
1199 __func__);
1200 return err;
1201 }
1202
1203 mutex_lock(&dev->intf_state_mutex);
1204 if (dev->interface_state == MLX5_INTERFACE_STATE_DOWN) {
1205 dev_warn(&dev->pdev->dev, "%s: interface is down, NOP\n",
1206 __func__);
1207 goto out;
1208 }
1209 mlx5_unregister_device(dev);
1210 #ifdef CONFIG_MLX5_CORE_EN
1211 mlx5_eswitch_cleanup(dev->priv.eswitch);
1212 #endif
1213
1214 mlx5_cleanup_fs(dev);
1215 mlx5_cleanup_mkey_table(dev);
1216 mlx5_cleanup_srq_table(dev);
1217 mlx5_cleanup_qp_table(dev);
1218 mlx5_cleanup_cq_table(dev);
1219 mlx5_irq_clear_affinity_hints(dev);
1220 free_comp_eqs(dev);
1221 mlx5_stop_eqs(dev);
1222 mlx5_free_uuars(dev, &priv->uuari);
1223 mlx5_eq_cleanup(dev);
1224 mlx5_disable_msix(dev);
1225 mlx5_stop_health_poll(dev);
1226 err = mlx5_cmd_teardown_hca(dev);
1227 if (err) {
1228 dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n");
1229 goto out;
1230 }
1231 mlx5_pagealloc_stop(dev);
1232 mlx5_reclaim_startup_pages(dev);
1233 mlx5_core_disable_hca(dev, 0);
1234 mlx5_pagealloc_cleanup(dev);
1235 mlx5_cmd_cleanup(dev);
1236
1237 out:
1238 dev->interface_state = MLX5_INTERFACE_STATE_DOWN;
1239 mutex_unlock(&dev->intf_state_mutex);
1240 return err;
1241 }
1242
1243 void mlx5_core_event(struct mlx5_core_dev *dev, enum mlx5_dev_event event,
1244 unsigned long param)
1245 {
1246 struct mlx5_priv *priv = &dev->priv;
1247 struct mlx5_device_context *dev_ctx;
1248 unsigned long flags;
1249
1250 spin_lock_irqsave(&priv->ctx_lock, flags);
1251
1252 list_for_each_entry(dev_ctx, &priv->ctx_list, list)
1253 if (dev_ctx->intf->event)
1254 dev_ctx->intf->event(dev, dev_ctx->context, event, param);
1255
1256 spin_unlock_irqrestore(&priv->ctx_lock, flags);
1257 }
1258
1259 struct mlx5_core_event_handler {
1260 void (*event)(struct mlx5_core_dev *dev,
1261 enum mlx5_dev_event event,
1262 void *data);
1263 };
1264
1265
1266 static int init_one(struct pci_dev *pdev,
1267 const struct pci_device_id *id)
1268 {
1269 struct mlx5_core_dev *dev;
1270 struct mlx5_priv *priv;
1271 int err;
1272
1273 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1274 if (!dev) {
1275 dev_err(&pdev->dev, "kzalloc failed\n");
1276 return -ENOMEM;
1277 }
1278 priv = &dev->priv;
1279 priv->pci_dev_data = id->driver_data;
1280
1281 pci_set_drvdata(pdev, dev);
1282
1283 if (prof_sel < 0 || prof_sel >= ARRAY_SIZE(profile)) {
1284 pr_warn("selected profile out of range, selecting default (%d)\n",
1285 MLX5_DEFAULT_PROF);
1286 prof_sel = MLX5_DEFAULT_PROF;
1287 }
1288 dev->profile = &profile[prof_sel];
1289 dev->pdev = pdev;
1290 dev->event = mlx5_core_event;
1291
1292 INIT_LIST_HEAD(&priv->ctx_list);
1293 spin_lock_init(&priv->ctx_lock);
1294 mutex_init(&dev->pci_status_mutex);
1295 mutex_init(&dev->intf_state_mutex);
1296 err = mlx5_pci_init(dev, priv);
1297 if (err) {
1298 dev_err(&pdev->dev, "mlx5_pci_init failed with error code %d\n", err);
1299 goto clean_dev;
1300 }
1301
1302 err = mlx5_health_init(dev);
1303 if (err) {
1304 dev_err(&pdev->dev, "mlx5_health_init failed with error code %d\n", err);
1305 goto close_pci;
1306 }
1307
1308 err = mlx5_load_one(dev, priv);
1309 if (err) {
1310 dev_err(&pdev->dev, "mlx5_load_one failed with error code %d\n", err);
1311 goto clean_health;
1312 }
1313
1314 return 0;
1315
1316 clean_health:
1317 mlx5_health_cleanup(dev);
1318 close_pci:
1319 mlx5_pci_close(dev, priv);
1320 clean_dev:
1321 pci_set_drvdata(pdev, NULL);
1322 kfree(dev);
1323
1324 return err;
1325 }
1326
1327 static void remove_one(struct pci_dev *pdev)
1328 {
1329 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1330 struct mlx5_priv *priv = &dev->priv;
1331
1332 if (mlx5_unload_one(dev, priv)) {
1333 dev_err(&dev->pdev->dev, "mlx5_unload_one failed\n");
1334 mlx5_health_cleanup(dev);
1335 return;
1336 }
1337 mlx5_health_cleanup(dev);
1338 mlx5_pci_close(dev, priv);
1339 pci_set_drvdata(pdev, NULL);
1340 kfree(dev);
1341 }
1342
1343 static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev,
1344 pci_channel_state_t state)
1345 {
1346 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1347 struct mlx5_priv *priv = &dev->priv;
1348
1349 dev_info(&pdev->dev, "%s was called\n", __func__);
1350 mlx5_enter_error_state(dev);
1351 mlx5_unload_one(dev, priv);
1352 mlx5_pci_disable_device(dev);
1353 return state == pci_channel_io_perm_failure ?
1354 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
1355 }
1356
1357 static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev)
1358 {
1359 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1360 int err = 0;
1361
1362 dev_info(&pdev->dev, "%s was called\n", __func__);
1363
1364 err = mlx5_pci_enable_device(dev);
1365 if (err) {
1366 dev_err(&pdev->dev, "%s: mlx5_pci_enable_device failed with error code: %d\n"
1367 , __func__, err);
1368 return PCI_ERS_RESULT_DISCONNECT;
1369 }
1370 pci_set_master(pdev);
1371 pci_set_power_state(pdev, PCI_D0);
1372 pci_restore_state(pdev);
1373
1374 return err ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED;
1375 }
1376
1377 void mlx5_disable_device(struct mlx5_core_dev *dev)
1378 {
1379 mlx5_pci_err_detected(dev->pdev, 0);
1380 }
1381
1382 /* wait for the device to show vital signs. For now we check
1383 * that we can read the device ID and that the health buffer
1384 * shows a non zero value which is different than 0xffffffff
1385 */
1386 static void wait_vital(struct pci_dev *pdev)
1387 {
1388 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1389 struct mlx5_core_health *health = &dev->priv.health;
1390 const int niter = 100;
1391 u32 count;
1392 u16 did;
1393 int i;
1394
1395 /* Wait for firmware to be ready after reset */
1396 msleep(1000);
1397 for (i = 0; i < niter; i++) {
1398 if (pci_read_config_word(pdev, 2, &did)) {
1399 dev_warn(&pdev->dev, "failed reading config word\n");
1400 break;
1401 }
1402 if (did == pdev->device) {
1403 dev_info(&pdev->dev, "device ID correctly read after %d iterations\n", i);
1404 break;
1405 }
1406 msleep(50);
1407 }
1408 if (i == niter)
1409 dev_warn(&pdev->dev, "%s-%d: could not read device ID\n", __func__, __LINE__);
1410
1411 for (i = 0; i < niter; i++) {
1412 count = ioread32be(health->health_counter);
1413 if (count && count != 0xffffffff) {
1414 dev_info(&pdev->dev, "Counter value 0x%x after %d iterations\n", count, i);
1415 break;
1416 }
1417 msleep(50);
1418 }
1419
1420 if (i == niter)
1421 dev_warn(&pdev->dev, "%s-%d: could not read device ID\n", __func__, __LINE__);
1422 }
1423
1424 static void mlx5_pci_resume(struct pci_dev *pdev)
1425 {
1426 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1427 struct mlx5_priv *priv = &dev->priv;
1428 int err;
1429
1430 dev_info(&pdev->dev, "%s was called\n", __func__);
1431
1432 pci_save_state(pdev);
1433 wait_vital(pdev);
1434
1435 err = mlx5_load_one(dev, priv);
1436 if (err)
1437 dev_err(&pdev->dev, "%s: mlx5_load_one failed with error code: %d\n"
1438 , __func__, err);
1439 else
1440 dev_info(&pdev->dev, "%s: device recovered\n", __func__);
1441 }
1442
1443 static const struct pci_error_handlers mlx5_err_handler = {
1444 .error_detected = mlx5_pci_err_detected,
1445 .slot_reset = mlx5_pci_slot_reset,
1446 .resume = mlx5_pci_resume
1447 };
1448
1449 static const struct pci_device_id mlx5_core_pci_table[] = {
1450 { PCI_VDEVICE(MELLANOX, 0x1011) }, /* Connect-IB */
1451 { PCI_VDEVICE(MELLANOX, 0x1012), MLX5_PCI_DEV_IS_VF}, /* Connect-IB VF */
1452 { PCI_VDEVICE(MELLANOX, 0x1013) }, /* ConnectX-4 */
1453 { PCI_VDEVICE(MELLANOX, 0x1014), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4 VF */
1454 { PCI_VDEVICE(MELLANOX, 0x1015) }, /* ConnectX-4LX */
1455 { PCI_VDEVICE(MELLANOX, 0x1016), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4LX VF */
1456 { 0, }
1457 };
1458
1459 MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table);
1460
1461 static struct pci_driver mlx5_core_driver = {
1462 .name = DRIVER_NAME,
1463 .id_table = mlx5_core_pci_table,
1464 .probe = init_one,
1465 .remove = remove_one,
1466 .err_handler = &mlx5_err_handler,
1467 .sriov_configure = mlx5_core_sriov_configure,
1468 };
1469
1470 static int __init init(void)
1471 {
1472 int err;
1473
1474 mlx5_register_debugfs();
1475
1476 err = pci_register_driver(&mlx5_core_driver);
1477 if (err)
1478 goto err_debug;
1479
1480 #ifdef CONFIG_MLX5_CORE_EN
1481 mlx5e_init();
1482 #endif
1483
1484 return 0;
1485
1486 err_debug:
1487 mlx5_unregister_debugfs();
1488 return err;
1489 }
1490
1491 static void __exit cleanup(void)
1492 {
1493 #ifdef CONFIG_MLX5_CORE_EN
1494 mlx5e_cleanup();
1495 #endif
1496 pci_unregister_driver(&mlx5_core_driver);
1497 mlx5_unregister_debugfs();
1498 }
1499
1500 module_init(init);
1501 module_exit(cleanup);
Linux kernel - Deliverables
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