2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/highmem.h>
34 #include <linux/module.h>
35 #include <linux/init.h>
36 #include <linux/errno.h>
37 #include <linux/pci.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/slab.h>
40 #include <linux/io-mapping.h>
41 #include <linux/interrupt.h>
42 #include <linux/delay.h>
43 #include <linux/mlx5/driver.h>
44 #include <linux/mlx5/cq.h>
45 #include <linux/mlx5/qp.h>
46 #include <linux/mlx5/srq.h>
47 #include <linux/debugfs.h>
48 #include <linux/kmod.h>
49 #include <linux/delay.h>
50 #include <linux/mlx5/mlx5_ifc.h>
51 #ifdef CONFIG_RFS_ACCEL
52 #include <linux/cpu_rmap.h>
54 #include "mlx5_core.h"
56 #ifdef CONFIG_MLX5_CORE_EN
60 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
61 MODULE_DESCRIPTION("Mellanox Connect-IB, ConnectX-4 core driver");
62 MODULE_LICENSE("Dual BSD/GPL");
63 MODULE_VERSION(DRIVER_VERSION
);
65 int mlx5_core_debug_mask
;
66 module_param_named(debug_mask
, mlx5_core_debug_mask
, int, 0644);
67 MODULE_PARM_DESC(debug_mask
, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0");
69 #define MLX5_DEFAULT_PROF 2
70 static int prof_sel
= MLX5_DEFAULT_PROF
;
71 module_param_named(prof_sel
, prof_sel
, int, 0444);
72 MODULE_PARM_DESC(prof_sel
, "profile selector. Valid range 0 - 2");
74 static LIST_HEAD(intf_list
);
75 static LIST_HEAD(dev_list
);
76 static DEFINE_MUTEX(intf_mutex
);
78 struct mlx5_device_context
{
79 struct list_head list
;
80 struct mlx5_interface
*intf
;
85 MLX5_ATOMIC_REQ_MODE_BE
= 0x0,
86 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS
= 0x1,
89 static struct mlx5_profile profile
[] = {
94 .mask
= MLX5_PROF_MASK_QP_SIZE
,
98 .mask
= MLX5_PROF_MASK_QP_SIZE
|
99 MLX5_PROF_MASK_MR_CACHE
,
168 #define FW_INIT_TIMEOUT_MILI 2000
169 #define FW_INIT_WAIT_MS 2
171 static int wait_fw_init(struct mlx5_core_dev
*dev
, u32 max_wait_mili
)
173 unsigned long end
= jiffies
+ msecs_to_jiffies(max_wait_mili
);
176 while (fw_initializing(dev
)) {
177 if (time_after(jiffies
, end
)) {
181 msleep(FW_INIT_WAIT_MS
);
187 static int set_dma_caps(struct pci_dev
*pdev
)
191 err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(64));
193 dev_warn(&pdev
->dev
, "Warning: couldn't set 64-bit PCI DMA mask\n");
194 err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
196 dev_err(&pdev
->dev
, "Can't set PCI DMA mask, aborting\n");
201 err
= pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(64));
204 "Warning: couldn't set 64-bit consistent PCI DMA mask\n");
205 err
= pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(32));
208 "Can't set consistent PCI DMA mask, aborting\n");
213 dma_set_max_seg_size(&pdev
->dev
, 2u * 1024 * 1024 * 1024);
217 static int mlx5_pci_enable_device(struct mlx5_core_dev
*dev
)
219 struct pci_dev
*pdev
= dev
->pdev
;
222 mutex_lock(&dev
->pci_status_mutex
);
223 if (dev
->pci_status
== MLX5_PCI_STATUS_DISABLED
) {
224 err
= pci_enable_device(pdev
);
226 dev
->pci_status
= MLX5_PCI_STATUS_ENABLED
;
228 mutex_unlock(&dev
->pci_status_mutex
);
233 static void mlx5_pci_disable_device(struct mlx5_core_dev
*dev
)
235 struct pci_dev
*pdev
= dev
->pdev
;
237 mutex_lock(&dev
->pci_status_mutex
);
238 if (dev
->pci_status
== MLX5_PCI_STATUS_ENABLED
) {
239 pci_disable_device(pdev
);
240 dev
->pci_status
= MLX5_PCI_STATUS_DISABLED
;
242 mutex_unlock(&dev
->pci_status_mutex
);
245 static int request_bar(struct pci_dev
*pdev
)
249 if (!(pci_resource_flags(pdev
, 0) & IORESOURCE_MEM
)) {
250 dev_err(&pdev
->dev
, "Missing registers BAR, aborting\n");
254 err
= pci_request_regions(pdev
, DRIVER_NAME
);
256 dev_err(&pdev
->dev
, "Couldn't get PCI resources, aborting\n");
261 static void release_bar(struct pci_dev
*pdev
)
263 pci_release_regions(pdev
);
266 static int mlx5_enable_msix(struct mlx5_core_dev
*dev
)
268 struct mlx5_priv
*priv
= &dev
->priv
;
269 struct mlx5_eq_table
*table
= &priv
->eq_table
;
270 int num_eqs
= 1 << MLX5_CAP_GEN(dev
, log_max_eq
);
274 nvec
= MLX5_CAP_GEN(dev
, num_ports
) * num_online_cpus() +
275 MLX5_EQ_VEC_COMP_BASE
;
276 nvec
= min_t(int, nvec
, num_eqs
);
277 if (nvec
<= MLX5_EQ_VEC_COMP_BASE
)
280 priv
->msix_arr
= kcalloc(nvec
, sizeof(*priv
->msix_arr
), GFP_KERNEL
);
282 priv
->irq_info
= kcalloc(nvec
, sizeof(*priv
->irq_info
), GFP_KERNEL
);
283 if (!priv
->msix_arr
|| !priv
->irq_info
)
286 for (i
= 0; i
< nvec
; i
++)
287 priv
->msix_arr
[i
].entry
= i
;
289 nvec
= pci_enable_msix_range(dev
->pdev
, priv
->msix_arr
,
290 MLX5_EQ_VEC_COMP_BASE
+ 1, nvec
);
294 table
->num_comp_vectors
= nvec
- MLX5_EQ_VEC_COMP_BASE
;
299 kfree(priv
->irq_info
);
300 kfree(priv
->msix_arr
);
304 static void mlx5_disable_msix(struct mlx5_core_dev
*dev
)
306 struct mlx5_priv
*priv
= &dev
->priv
;
308 pci_disable_msix(dev
->pdev
);
309 kfree(priv
->irq_info
);
310 kfree(priv
->msix_arr
);
313 struct mlx5_reg_host_endianess
{
319 #define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos))
322 MLX5_CAP_BITS_RW_MASK
= CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM
, 2) |
323 MLX5_DEV_CAP_FLAG_DCT
,
326 static u16
to_fw_pkey_sz(u32 size
)
342 pr_warn("invalid pkey table size %d\n", size
);
347 static int mlx5_core_get_caps_mode(struct mlx5_core_dev
*dev
,
348 enum mlx5_cap_type cap_type
,
349 enum mlx5_cap_mode cap_mode
)
351 u8 in
[MLX5_ST_SZ_BYTES(query_hca_cap_in
)];
352 int out_sz
= MLX5_ST_SZ_BYTES(query_hca_cap_out
);
353 void *out
, *hca_caps
;
354 u16 opmod
= (cap_type
<< 1) | (cap_mode
& 0x01);
357 memset(in
, 0, sizeof(in
));
358 out
= kzalloc(out_sz
, GFP_KERNEL
);
362 MLX5_SET(query_hca_cap_in
, in
, opcode
, MLX5_CMD_OP_QUERY_HCA_CAP
);
363 MLX5_SET(query_hca_cap_in
, in
, op_mod
, opmod
);
364 err
= mlx5_cmd_exec(dev
, in
, sizeof(in
), out
, out_sz
);
368 err
= mlx5_cmd_status_to_err_v2(out
);
371 "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n",
372 cap_type
, cap_mode
, err
);
376 hca_caps
= MLX5_ADDR_OF(query_hca_cap_out
, out
, capability
);
379 case HCA_CAP_OPMOD_GET_MAX
:
380 memcpy(dev
->hca_caps_max
[cap_type
], hca_caps
,
381 MLX5_UN_SZ_BYTES(hca_cap_union
));
383 case HCA_CAP_OPMOD_GET_CUR
:
384 memcpy(dev
->hca_caps_cur
[cap_type
], hca_caps
,
385 MLX5_UN_SZ_BYTES(hca_cap_union
));
389 "Tried to query dev cap type(%x) with wrong opmode(%x)\n",
399 int mlx5_core_get_caps(struct mlx5_core_dev
*dev
, enum mlx5_cap_type cap_type
)
403 ret
= mlx5_core_get_caps_mode(dev
, cap_type
, HCA_CAP_OPMOD_GET_CUR
);
406 return mlx5_core_get_caps_mode(dev
, cap_type
, HCA_CAP_OPMOD_GET_MAX
);
409 static int set_caps(struct mlx5_core_dev
*dev
, void *in
, int in_sz
, int opmod
)
411 u32 out
[MLX5_ST_SZ_DW(set_hca_cap_out
)];
414 memset(out
, 0, sizeof(out
));
416 MLX5_SET(set_hca_cap_in
, in
, opcode
, MLX5_CMD_OP_SET_HCA_CAP
);
417 MLX5_SET(set_hca_cap_in
, in
, op_mod
, opmod
<< 1);
418 err
= mlx5_cmd_exec(dev
, in
, in_sz
, out
, sizeof(out
));
422 err
= mlx5_cmd_status_to_err_v2(out
);
427 static int handle_hca_cap_atomic(struct mlx5_core_dev
*dev
)
431 int set_sz
= MLX5_ST_SZ_BYTES(set_hca_cap_in
);
435 if (MLX5_CAP_GEN(dev
, atomic
)) {
436 err
= mlx5_core_get_caps(dev
, MLX5_CAP_ATOMIC
);
445 supported_atomic_req_8B_endianess_mode_1
);
447 if (req_endianness
!= MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS
)
450 set_ctx
= kzalloc(set_sz
, GFP_KERNEL
);
454 set_hca_cap
= MLX5_ADDR_OF(set_hca_cap_in
, set_ctx
, capability
);
456 /* Set requestor to host endianness */
457 MLX5_SET(atomic_caps
, set_hca_cap
, atomic_req_8B_endianess_mode
,
458 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS
);
460 err
= set_caps(dev
, set_ctx
, set_sz
, MLX5_SET_HCA_CAP_OP_MOD_ATOMIC
);
466 static int handle_hca_cap(struct mlx5_core_dev
*dev
)
468 void *set_ctx
= NULL
;
469 struct mlx5_profile
*prof
= dev
->profile
;
471 int set_sz
= MLX5_ST_SZ_BYTES(set_hca_cap_in
);
474 set_ctx
= kzalloc(set_sz
, GFP_KERNEL
);
478 err
= mlx5_core_get_caps(dev
, MLX5_CAP_GENERAL
);
482 set_hca_cap
= MLX5_ADDR_OF(set_hca_cap_in
, set_ctx
,
484 memcpy(set_hca_cap
, dev
->hca_caps_cur
[MLX5_CAP_GENERAL
],
485 MLX5_ST_SZ_BYTES(cmd_hca_cap
));
487 mlx5_core_dbg(dev
, "Current Pkey table size %d Setting new size %d\n",
488 mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev
, pkey_table_size
)),
490 /* we limit the size of the pkey table to 128 entries for now */
491 MLX5_SET(cmd_hca_cap
, set_hca_cap
, pkey_table_size
,
494 if (prof
->mask
& MLX5_PROF_MASK_QP_SIZE
)
495 MLX5_SET(cmd_hca_cap
, set_hca_cap
, log_max_qp
,
498 /* disable cmdif checksum */
499 MLX5_SET(cmd_hca_cap
, set_hca_cap
, cmdif_checksum
, 0);
501 MLX5_SET(cmd_hca_cap
, set_hca_cap
, log_uar_page_sz
, PAGE_SHIFT
- 12);
503 err
= set_caps(dev
, set_ctx
, set_sz
,
504 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE
);
511 static int set_hca_ctrl(struct mlx5_core_dev
*dev
)
513 struct mlx5_reg_host_endianess he_in
;
514 struct mlx5_reg_host_endianess he_out
;
517 if (!mlx5_core_is_pf(dev
))
520 memset(&he_in
, 0, sizeof(he_in
));
521 he_in
.he
= MLX5_SET_HOST_ENDIANNESS
;
522 err
= mlx5_core_access_reg(dev
, &he_in
, sizeof(he_in
),
523 &he_out
, sizeof(he_out
),
524 MLX5_REG_HOST_ENDIANNESS
, 0, 1);
528 int mlx5_core_enable_hca(struct mlx5_core_dev
*dev
, u16 func_id
)
530 u32 out
[MLX5_ST_SZ_DW(enable_hca_out
)];
531 u32 in
[MLX5_ST_SZ_DW(enable_hca_in
)];
534 memset(in
, 0, sizeof(in
));
535 MLX5_SET(enable_hca_in
, in
, opcode
, MLX5_CMD_OP_ENABLE_HCA
);
536 MLX5_SET(enable_hca_in
, in
, function_id
, func_id
);
537 memset(out
, 0, sizeof(out
));
539 err
= mlx5_cmd_exec(dev
, &in
, sizeof(in
), &out
, sizeof(out
));
543 return mlx5_cmd_status_to_err_v2(out
);
546 int mlx5_core_disable_hca(struct mlx5_core_dev
*dev
, u16 func_id
)
548 u32 out
[MLX5_ST_SZ_DW(disable_hca_out
)];
549 u32 in
[MLX5_ST_SZ_DW(disable_hca_in
)];
552 memset(in
, 0, sizeof(in
));
553 MLX5_SET(disable_hca_in
, in
, opcode
, MLX5_CMD_OP_DISABLE_HCA
);
554 MLX5_SET(disable_hca_in
, in
, function_id
, func_id
);
555 memset(out
, 0, sizeof(out
));
556 err
= mlx5_cmd_exec(dev
, in
, sizeof(in
), out
, sizeof(out
));
560 return mlx5_cmd_status_to_err_v2(out
);
563 cycle_t
mlx5_read_internal_timer(struct mlx5_core_dev
*dev
)
565 u32 timer_h
, timer_h1
, timer_l
;
567 timer_h
= ioread32be(&dev
->iseg
->internal_timer_h
);
568 timer_l
= ioread32be(&dev
->iseg
->internal_timer_l
);
569 timer_h1
= ioread32be(&dev
->iseg
->internal_timer_h
);
570 if (timer_h
!= timer_h1
) /* wrap around */
571 timer_l
= ioread32be(&dev
->iseg
->internal_timer_l
);
573 return (cycle_t
)timer_l
| (cycle_t
)timer_h1
<< 32;
576 static int mlx5_irq_set_affinity_hint(struct mlx5_core_dev
*mdev
, int i
)
578 struct mlx5_priv
*priv
= &mdev
->priv
;
579 struct msix_entry
*msix
= priv
->msix_arr
;
580 int irq
= msix
[i
+ MLX5_EQ_VEC_COMP_BASE
].vector
;
581 int numa_node
= priv
->numa_node
;
584 if (!zalloc_cpumask_var(&priv
->irq_info
[i
].mask
, GFP_KERNEL
)) {
585 mlx5_core_warn(mdev
, "zalloc_cpumask_var failed");
589 cpumask_set_cpu(cpumask_local_spread(i
, numa_node
),
590 priv
->irq_info
[i
].mask
);
592 err
= irq_set_affinity_hint(irq
, priv
->irq_info
[i
].mask
);
594 mlx5_core_warn(mdev
, "irq_set_affinity_hint failed,irq 0x%.4x",
602 free_cpumask_var(priv
->irq_info
[i
].mask
);
606 static void mlx5_irq_clear_affinity_hint(struct mlx5_core_dev
*mdev
, int i
)
608 struct mlx5_priv
*priv
= &mdev
->priv
;
609 struct msix_entry
*msix
= priv
->msix_arr
;
610 int irq
= msix
[i
+ MLX5_EQ_VEC_COMP_BASE
].vector
;
612 irq_set_affinity_hint(irq
, NULL
);
613 free_cpumask_var(priv
->irq_info
[i
].mask
);
616 static int mlx5_irq_set_affinity_hints(struct mlx5_core_dev
*mdev
)
621 for (i
= 0; i
< mdev
->priv
.eq_table
.num_comp_vectors
; i
++) {
622 err
= mlx5_irq_set_affinity_hint(mdev
, i
);
630 for (i
--; i
>= 0; i
--)
631 mlx5_irq_clear_affinity_hint(mdev
, i
);
636 static void mlx5_irq_clear_affinity_hints(struct mlx5_core_dev
*mdev
)
640 for (i
= 0; i
< mdev
->priv
.eq_table
.num_comp_vectors
; i
++)
641 mlx5_irq_clear_affinity_hint(mdev
, i
);
644 int mlx5_vector2eqn(struct mlx5_core_dev
*dev
, int vector
, int *eqn
,
647 struct mlx5_eq_table
*table
= &dev
->priv
.eq_table
;
648 struct mlx5_eq
*eq
, *n
;
651 spin_lock(&table
->lock
);
652 list_for_each_entry_safe(eq
, n
, &table
->comp_eqs_list
, list
) {
653 if (eq
->index
== vector
) {
660 spin_unlock(&table
->lock
);
664 EXPORT_SYMBOL(mlx5_vector2eqn
);
666 struct mlx5_eq
*mlx5_eqn2eq(struct mlx5_core_dev
*dev
, int eqn
)
668 struct mlx5_eq_table
*table
= &dev
->priv
.eq_table
;
671 spin_lock(&table
->lock
);
672 list_for_each_entry(eq
, &table
->comp_eqs_list
, list
)
673 if (eq
->eqn
== eqn
) {
674 spin_unlock(&table
->lock
);
678 spin_unlock(&table
->lock
);
680 return ERR_PTR(-ENOENT
);
683 static void free_comp_eqs(struct mlx5_core_dev
*dev
)
685 struct mlx5_eq_table
*table
= &dev
->priv
.eq_table
;
686 struct mlx5_eq
*eq
, *n
;
688 #ifdef CONFIG_RFS_ACCEL
690 free_irq_cpu_rmap(dev
->rmap
);
694 spin_lock(&table
->lock
);
695 list_for_each_entry_safe(eq
, n
, &table
->comp_eqs_list
, list
) {
697 spin_unlock(&table
->lock
);
698 if (mlx5_destroy_unmap_eq(dev
, eq
))
699 mlx5_core_warn(dev
, "failed to destroy EQ 0x%x\n",
702 spin_lock(&table
->lock
);
704 spin_unlock(&table
->lock
);
707 static int alloc_comp_eqs(struct mlx5_core_dev
*dev
)
709 struct mlx5_eq_table
*table
= &dev
->priv
.eq_table
;
710 char name
[MLX5_MAX_IRQ_NAME
];
717 INIT_LIST_HEAD(&table
->comp_eqs_list
);
718 ncomp_vec
= table
->num_comp_vectors
;
719 nent
= MLX5_COMP_EQ_SIZE
;
720 #ifdef CONFIG_RFS_ACCEL
721 dev
->rmap
= alloc_irq_cpu_rmap(ncomp_vec
);
725 for (i
= 0; i
< ncomp_vec
; i
++) {
726 eq
= kzalloc(sizeof(*eq
), GFP_KERNEL
);
732 #ifdef CONFIG_RFS_ACCEL
733 irq_cpu_rmap_add(dev
->rmap
,
734 dev
->priv
.msix_arr
[i
+ MLX5_EQ_VEC_COMP_BASE
].vector
);
736 snprintf(name
, MLX5_MAX_IRQ_NAME
, "mlx5_comp%d", i
);
737 err
= mlx5_create_map_eq(dev
, eq
,
738 i
+ MLX5_EQ_VEC_COMP_BASE
, nent
, 0,
739 name
, &dev
->priv
.uuari
.uars
[0]);
744 mlx5_core_dbg(dev
, "allocated completion EQN %d\n", eq
->eqn
);
746 spin_lock(&table
->lock
);
747 list_add_tail(&eq
->list
, &table
->comp_eqs_list
);
748 spin_unlock(&table
->lock
);
758 static int mlx5_core_set_issi(struct mlx5_core_dev
*dev
)
760 u32 query_in
[MLX5_ST_SZ_DW(query_issi_in
)];
761 u32 query_out
[MLX5_ST_SZ_DW(query_issi_out
)];
762 u32 set_in
[MLX5_ST_SZ_DW(set_issi_in
)];
763 u32 set_out
[MLX5_ST_SZ_DW(set_issi_out
)];
767 memset(query_in
, 0, sizeof(query_in
));
768 memset(query_out
, 0, sizeof(query_out
));
770 MLX5_SET(query_issi_in
, query_in
, opcode
, MLX5_CMD_OP_QUERY_ISSI
);
772 err
= mlx5_cmd_exec_check_status(dev
, query_in
, sizeof(query_in
),
773 query_out
, sizeof(query_out
));
775 if (((struct mlx5_outbox_hdr
*)query_out
)->status
==
776 MLX5_CMD_STAT_BAD_OP_ERR
) {
777 pr_debug("Only ISSI 0 is supported\n");
781 pr_err("failed to query ISSI\n");
785 sup_issi
= MLX5_GET(query_issi_out
, query_out
, supported_issi_dw0
);
787 if (sup_issi
& (1 << 1)) {
788 memset(set_in
, 0, sizeof(set_in
));
789 memset(set_out
, 0, sizeof(set_out
));
791 MLX5_SET(set_issi_in
, set_in
, opcode
, MLX5_CMD_OP_SET_ISSI
);
792 MLX5_SET(set_issi_in
, set_in
, current_issi
, 1);
794 err
= mlx5_cmd_exec_check_status(dev
, set_in
, sizeof(set_in
),
795 set_out
, sizeof(set_out
));
797 pr_err("failed to set ISSI=1\n");
804 } else if (sup_issi
& (1 << 0) || !sup_issi
) {
811 static void mlx5_add_device(struct mlx5_interface
*intf
, struct mlx5_priv
*priv
)
813 struct mlx5_device_context
*dev_ctx
;
814 struct mlx5_core_dev
*dev
= container_of(priv
, struct mlx5_core_dev
, priv
);
816 dev_ctx
= kmalloc(sizeof(*dev_ctx
), GFP_KERNEL
);
820 dev_ctx
->intf
= intf
;
821 dev_ctx
->context
= intf
->add(dev
);
823 if (dev_ctx
->context
) {
824 spin_lock_irq(&priv
->ctx_lock
);
825 list_add_tail(&dev_ctx
->list
, &priv
->ctx_list
);
826 spin_unlock_irq(&priv
->ctx_lock
);
832 static void mlx5_remove_device(struct mlx5_interface
*intf
, struct mlx5_priv
*priv
)
834 struct mlx5_device_context
*dev_ctx
;
835 struct mlx5_core_dev
*dev
= container_of(priv
, struct mlx5_core_dev
, priv
);
837 list_for_each_entry(dev_ctx
, &priv
->ctx_list
, list
)
838 if (dev_ctx
->intf
== intf
) {
839 spin_lock_irq(&priv
->ctx_lock
);
840 list_del(&dev_ctx
->list
);
841 spin_unlock_irq(&priv
->ctx_lock
);
843 intf
->remove(dev
, dev_ctx
->context
);
849 static int mlx5_register_device(struct mlx5_core_dev
*dev
)
851 struct mlx5_priv
*priv
= &dev
->priv
;
852 struct mlx5_interface
*intf
;
854 mutex_lock(&intf_mutex
);
855 list_add_tail(&priv
->dev_list
, &dev_list
);
856 list_for_each_entry(intf
, &intf_list
, list
)
857 mlx5_add_device(intf
, priv
);
858 mutex_unlock(&intf_mutex
);
863 static void mlx5_unregister_device(struct mlx5_core_dev
*dev
)
865 struct mlx5_priv
*priv
= &dev
->priv
;
866 struct mlx5_interface
*intf
;
868 mutex_lock(&intf_mutex
);
869 list_for_each_entry(intf
, &intf_list
, list
)
870 mlx5_remove_device(intf
, priv
);
871 list_del(&priv
->dev_list
);
872 mutex_unlock(&intf_mutex
);
875 int mlx5_register_interface(struct mlx5_interface
*intf
)
877 struct mlx5_priv
*priv
;
879 if (!intf
->add
|| !intf
->remove
)
882 mutex_lock(&intf_mutex
);
883 list_add_tail(&intf
->list
, &intf_list
);
884 list_for_each_entry(priv
, &dev_list
, dev_list
)
885 mlx5_add_device(intf
, priv
);
886 mutex_unlock(&intf_mutex
);
890 EXPORT_SYMBOL(mlx5_register_interface
);
892 void mlx5_unregister_interface(struct mlx5_interface
*intf
)
894 struct mlx5_priv
*priv
;
896 mutex_lock(&intf_mutex
);
897 list_for_each_entry(priv
, &dev_list
, dev_list
)
898 mlx5_remove_device(intf
, priv
);
899 list_del(&intf
->list
);
900 mutex_unlock(&intf_mutex
);
902 EXPORT_SYMBOL(mlx5_unregister_interface
);
904 void *mlx5_get_protocol_dev(struct mlx5_core_dev
*mdev
, int protocol
)
906 struct mlx5_priv
*priv
= &mdev
->priv
;
907 struct mlx5_device_context
*dev_ctx
;
911 spin_lock_irqsave(&priv
->ctx_lock
, flags
);
913 list_for_each_entry(dev_ctx
, &mdev
->priv
.ctx_list
, list
)
914 if ((dev_ctx
->intf
->protocol
== protocol
) &&
915 dev_ctx
->intf
->get_dev
) {
916 result
= dev_ctx
->intf
->get_dev(dev_ctx
->context
);
920 spin_unlock_irqrestore(&priv
->ctx_lock
, flags
);
924 EXPORT_SYMBOL(mlx5_get_protocol_dev
);
926 static int mlx5_pci_init(struct mlx5_core_dev
*dev
, struct mlx5_priv
*priv
)
928 struct pci_dev
*pdev
= dev
->pdev
;
931 pci_set_drvdata(dev
->pdev
, dev
);
932 strncpy(priv
->name
, dev_name(&pdev
->dev
), MLX5_MAX_NAME_LEN
);
933 priv
->name
[MLX5_MAX_NAME_LEN
- 1] = 0;
935 mutex_init(&priv
->pgdir_mutex
);
936 INIT_LIST_HEAD(&priv
->pgdir_list
);
937 spin_lock_init(&priv
->mkey_lock
);
939 mutex_init(&priv
->alloc_mutex
);
941 priv
->numa_node
= dev_to_node(&dev
->pdev
->dev
);
943 priv
->dbg_root
= debugfs_create_dir(dev_name(&pdev
->dev
), mlx5_debugfs_root
);
947 err
= mlx5_pci_enable_device(dev
);
949 dev_err(&pdev
->dev
, "Cannot enable PCI device, aborting\n");
953 err
= request_bar(pdev
);
955 dev_err(&pdev
->dev
, "error requesting BARs, aborting\n");
959 pci_set_master(pdev
);
961 err
= set_dma_caps(pdev
);
963 dev_err(&pdev
->dev
, "Failed setting DMA capabilities mask, aborting\n");
967 dev
->iseg_base
= pci_resource_start(dev
->pdev
, 0);
968 dev
->iseg
= ioremap(dev
->iseg_base
, sizeof(*dev
->iseg
));
971 dev_err(&pdev
->dev
, "Failed mapping initialization segment, aborting\n");
978 pci_clear_master(dev
->pdev
);
979 release_bar(dev
->pdev
);
981 mlx5_pci_disable_device(dev
);
984 debugfs_remove(priv
->dbg_root
);
988 static void mlx5_pci_close(struct mlx5_core_dev
*dev
, struct mlx5_priv
*priv
)
991 pci_clear_master(dev
->pdev
);
992 release_bar(dev
->pdev
);
993 mlx5_pci_disable_device(dev
);
994 debugfs_remove(priv
->dbg_root
);
997 #define MLX5_IB_MOD "mlx5_ib"
998 static int mlx5_load_one(struct mlx5_core_dev
*dev
, struct mlx5_priv
*priv
)
1000 struct pci_dev
*pdev
= dev
->pdev
;
1003 mutex_lock(&dev
->intf_state_mutex
);
1004 if (test_bit(MLX5_INTERFACE_STATE_UP
, &dev
->intf_state
)) {
1005 dev_warn(&dev
->pdev
->dev
, "%s: interface is up, NOP\n",
1010 dev_info(&pdev
->dev
, "firmware version: %d.%d.%d\n", fw_rev_maj(dev
),
1011 fw_rev_min(dev
), fw_rev_sub(dev
));
1013 /* on load removing any previous indication of internal error, device is
1016 dev
->state
= MLX5_DEVICE_STATE_UP
;
1018 err
= mlx5_cmd_init(dev
);
1020 dev_err(&pdev
->dev
, "Failed initializing command interface, aborting\n");
1024 err
= wait_fw_init(dev
, FW_INIT_TIMEOUT_MILI
);
1026 dev_err(&dev
->pdev
->dev
, "Firmware over %d MS in initializing state, aborting\n",
1027 FW_INIT_TIMEOUT_MILI
);
1031 mlx5_pagealloc_init(dev
);
1033 err
= mlx5_core_enable_hca(dev
, 0);
1035 dev_err(&pdev
->dev
, "enable hca failed\n");
1036 goto err_pagealloc_cleanup
;
1039 err
= mlx5_core_set_issi(dev
);
1041 dev_err(&pdev
->dev
, "failed to set issi\n");
1042 goto err_disable_hca
;
1045 err
= mlx5_satisfy_startup_pages(dev
, 1);
1047 dev_err(&pdev
->dev
, "failed to allocate boot pages\n");
1048 goto err_disable_hca
;
1051 err
= set_hca_ctrl(dev
);
1053 dev_err(&pdev
->dev
, "set_hca_ctrl failed\n");
1054 goto reclaim_boot_pages
;
1057 err
= handle_hca_cap(dev
);
1059 dev_err(&pdev
->dev
, "handle_hca_cap failed\n");
1060 goto reclaim_boot_pages
;
1063 err
= handle_hca_cap_atomic(dev
);
1065 dev_err(&pdev
->dev
, "handle_hca_cap_atomic failed\n");
1066 goto reclaim_boot_pages
;
1069 err
= mlx5_satisfy_startup_pages(dev
, 0);
1071 dev_err(&pdev
->dev
, "failed to allocate init pages\n");
1072 goto reclaim_boot_pages
;
1075 err
= mlx5_pagealloc_start(dev
);
1077 dev_err(&pdev
->dev
, "mlx5_pagealloc_start failed\n");
1078 goto reclaim_boot_pages
;
1081 err
= mlx5_cmd_init_hca(dev
);
1083 dev_err(&pdev
->dev
, "init hca failed\n");
1084 goto err_pagealloc_stop
;
1087 mlx5_start_health_poll(dev
);
1089 err
= mlx5_query_hca_caps(dev
);
1091 dev_err(&pdev
->dev
, "query hca failed\n");
1095 err
= mlx5_query_board_id(dev
);
1097 dev_err(&pdev
->dev
, "query board id failed\n");
1101 err
= mlx5_enable_msix(dev
);
1103 dev_err(&pdev
->dev
, "enable msix failed\n");
1107 err
= mlx5_eq_init(dev
);
1109 dev_err(&pdev
->dev
, "failed to initialize eq\n");
1113 err
= mlx5_alloc_uuars(dev
, &priv
->uuari
);
1115 dev_err(&pdev
->dev
, "Failed allocating uar, aborting\n");
1116 goto err_eq_cleanup
;
1119 err
= mlx5_start_eqs(dev
);
1121 dev_err(&pdev
->dev
, "Failed to start pages and async EQs\n");
1125 err
= alloc_comp_eqs(dev
);
1127 dev_err(&pdev
->dev
, "Failed to alloc completion EQs\n");
1131 err
= mlx5_irq_set_affinity_hints(dev
);
1133 dev_err(&pdev
->dev
, "Failed to alloc affinity hint cpumask\n");
1135 MLX5_INIT_DOORBELL_LOCK(&priv
->cq_uar_lock
);
1137 mlx5_init_cq_table(dev
);
1138 mlx5_init_qp_table(dev
);
1139 mlx5_init_srq_table(dev
);
1140 mlx5_init_mkey_table(dev
);
1142 err
= mlx5_init_fs(dev
);
1144 dev_err(&pdev
->dev
, "Failed to init flow steering\n");
1147 #ifdef CONFIG_MLX5_CORE_EN
1148 err
= mlx5_eswitch_init(dev
);
1150 dev_err(&pdev
->dev
, "eswitch init failed %d\n", err
);
1155 err
= mlx5_sriov_init(dev
);
1157 dev_err(&pdev
->dev
, "sriov init failed %d\n", err
);
1161 err
= mlx5_register_device(dev
);
1163 dev_err(&pdev
->dev
, "mlx5_register_device failed %d\n", err
);
1167 err
= request_module_nowait(MLX5_IB_MOD
);
1169 pr_info("failed request module on %s\n", MLX5_IB_MOD
);
1171 clear_bit(MLX5_INTERFACE_STATE_DOWN
, &dev
->intf_state
);
1172 set_bit(MLX5_INTERFACE_STATE_UP
, &dev
->intf_state
);
1174 mutex_unlock(&dev
->intf_state_mutex
);
1179 if (mlx5_sriov_cleanup(dev
))
1180 dev_err(&dev
->pdev
->dev
, "sriov cleanup failed\n");
1182 #ifdef CONFIG_MLX5_CORE_EN
1183 mlx5_eswitch_cleanup(dev
->priv
.eswitch
);
1186 mlx5_cleanup_fs(dev
);
1188 mlx5_cleanup_mkey_table(dev
);
1189 mlx5_cleanup_srq_table(dev
);
1190 mlx5_cleanup_qp_table(dev
);
1191 mlx5_cleanup_cq_table(dev
);
1192 mlx5_irq_clear_affinity_hints(dev
);
1199 mlx5_free_uuars(dev
, &priv
->uuari
);
1202 mlx5_eq_cleanup(dev
);
1205 mlx5_disable_msix(dev
);
1208 mlx5_stop_health_poll(dev
);
1209 if (mlx5_cmd_teardown_hca(dev
)) {
1210 dev_err(&dev
->pdev
->dev
, "tear_down_hca failed, skip cleanup\n");
1215 mlx5_pagealloc_stop(dev
);
1218 mlx5_reclaim_startup_pages(dev
);
1221 mlx5_core_disable_hca(dev
, 0);
1223 err_pagealloc_cleanup
:
1224 mlx5_pagealloc_cleanup(dev
);
1225 mlx5_cmd_cleanup(dev
);
1228 dev
->state
= MLX5_DEVICE_STATE_INTERNAL_ERROR
;
1229 mutex_unlock(&dev
->intf_state_mutex
);
1234 static int mlx5_unload_one(struct mlx5_core_dev
*dev
, struct mlx5_priv
*priv
)
1238 err
= mlx5_sriov_cleanup(dev
);
1240 dev_warn(&dev
->pdev
->dev
, "%s: sriov cleanup failed - abort\n",
1245 mutex_lock(&dev
->intf_state_mutex
);
1246 if (test_bit(MLX5_INTERFACE_STATE_DOWN
, &dev
->intf_state
)) {
1247 dev_warn(&dev
->pdev
->dev
, "%s: interface is down, NOP\n",
1251 mlx5_unregister_device(dev
);
1252 #ifdef CONFIG_MLX5_CORE_EN
1253 mlx5_eswitch_cleanup(dev
->priv
.eswitch
);
1256 mlx5_cleanup_fs(dev
);
1257 mlx5_cleanup_mkey_table(dev
);
1258 mlx5_cleanup_srq_table(dev
);
1259 mlx5_cleanup_qp_table(dev
);
1260 mlx5_cleanup_cq_table(dev
);
1261 mlx5_irq_clear_affinity_hints(dev
);
1264 mlx5_free_uuars(dev
, &priv
->uuari
);
1265 mlx5_eq_cleanup(dev
);
1266 mlx5_disable_msix(dev
);
1267 mlx5_stop_health_poll(dev
);
1268 err
= mlx5_cmd_teardown_hca(dev
);
1270 dev_err(&dev
->pdev
->dev
, "tear_down_hca failed, skip cleanup\n");
1273 mlx5_pagealloc_stop(dev
);
1274 mlx5_reclaim_startup_pages(dev
);
1275 mlx5_core_disable_hca(dev
, 0);
1276 mlx5_pagealloc_cleanup(dev
);
1277 mlx5_cmd_cleanup(dev
);
1280 clear_bit(MLX5_INTERFACE_STATE_UP
, &dev
->intf_state
);
1281 set_bit(MLX5_INTERFACE_STATE_DOWN
, &dev
->intf_state
);
1282 mutex_unlock(&dev
->intf_state_mutex
);
1286 void mlx5_core_event(struct mlx5_core_dev
*dev
, enum mlx5_dev_event event
,
1287 unsigned long param
)
1289 struct mlx5_priv
*priv
= &dev
->priv
;
1290 struct mlx5_device_context
*dev_ctx
;
1291 unsigned long flags
;
1293 spin_lock_irqsave(&priv
->ctx_lock
, flags
);
1295 list_for_each_entry(dev_ctx
, &priv
->ctx_list
, list
)
1296 if (dev_ctx
->intf
->event
)
1297 dev_ctx
->intf
->event(dev
, dev_ctx
->context
, event
, param
);
1299 spin_unlock_irqrestore(&priv
->ctx_lock
, flags
);
1302 struct mlx5_core_event_handler
{
1303 void (*event
)(struct mlx5_core_dev
*dev
,
1304 enum mlx5_dev_event event
,
1309 static int init_one(struct pci_dev
*pdev
,
1310 const struct pci_device_id
*id
)
1312 struct mlx5_core_dev
*dev
;
1313 struct mlx5_priv
*priv
;
1316 dev
= kzalloc(sizeof(*dev
), GFP_KERNEL
);
1318 dev_err(&pdev
->dev
, "kzalloc failed\n");
1322 priv
->pci_dev_data
= id
->driver_data
;
1324 pci_set_drvdata(pdev
, dev
);
1326 if (prof_sel
< 0 || prof_sel
>= ARRAY_SIZE(profile
)) {
1327 pr_warn("selected profile out of range, selecting default (%d)\n",
1329 prof_sel
= MLX5_DEFAULT_PROF
;
1331 dev
->profile
= &profile
[prof_sel
];
1333 dev
->event
= mlx5_core_event
;
1335 INIT_LIST_HEAD(&priv
->ctx_list
);
1336 spin_lock_init(&priv
->ctx_lock
);
1337 mutex_init(&dev
->pci_status_mutex
);
1338 mutex_init(&dev
->intf_state_mutex
);
1339 err
= mlx5_pci_init(dev
, priv
);
1341 dev_err(&pdev
->dev
, "mlx5_pci_init failed with error code %d\n", err
);
1345 err
= mlx5_health_init(dev
);
1347 dev_err(&pdev
->dev
, "mlx5_health_init failed with error code %d\n", err
);
1351 err
= mlx5_load_one(dev
, priv
);
1353 dev_err(&pdev
->dev
, "mlx5_load_one failed with error code %d\n", err
);
1360 mlx5_health_cleanup(dev
);
1362 mlx5_pci_close(dev
, priv
);
1364 pci_set_drvdata(pdev
, NULL
);
1370 static void remove_one(struct pci_dev
*pdev
)
1372 struct mlx5_core_dev
*dev
= pci_get_drvdata(pdev
);
1373 struct mlx5_priv
*priv
= &dev
->priv
;
1375 if (mlx5_unload_one(dev
, priv
)) {
1376 dev_err(&dev
->pdev
->dev
, "mlx5_unload_one failed\n");
1377 mlx5_health_cleanup(dev
);
1380 mlx5_health_cleanup(dev
);
1381 mlx5_pci_close(dev
, priv
);
1382 pci_set_drvdata(pdev
, NULL
);
1386 static pci_ers_result_t
mlx5_pci_err_detected(struct pci_dev
*pdev
,
1387 pci_channel_state_t state
)
1389 struct mlx5_core_dev
*dev
= pci_get_drvdata(pdev
);
1390 struct mlx5_priv
*priv
= &dev
->priv
;
1392 dev_info(&pdev
->dev
, "%s was called\n", __func__
);
1393 mlx5_enter_error_state(dev
);
1394 mlx5_unload_one(dev
, priv
);
1395 mlx5_pci_disable_device(dev
);
1396 return state
== pci_channel_io_perm_failure
?
1397 PCI_ERS_RESULT_DISCONNECT
: PCI_ERS_RESULT_NEED_RESET
;
1400 static pci_ers_result_t
mlx5_pci_slot_reset(struct pci_dev
*pdev
)
1402 struct mlx5_core_dev
*dev
= pci_get_drvdata(pdev
);
1405 dev_info(&pdev
->dev
, "%s was called\n", __func__
);
1407 err
= mlx5_pci_enable_device(dev
);
1409 dev_err(&pdev
->dev
, "%s: mlx5_pci_enable_device failed with error code: %d\n"
1411 return PCI_ERS_RESULT_DISCONNECT
;
1413 pci_set_master(pdev
);
1414 pci_set_power_state(pdev
, PCI_D0
);
1415 pci_restore_state(pdev
);
1417 return err
? PCI_ERS_RESULT_DISCONNECT
: PCI_ERS_RESULT_RECOVERED
;
1420 void mlx5_disable_device(struct mlx5_core_dev
*dev
)
1422 mlx5_pci_err_detected(dev
->pdev
, 0);
1425 /* wait for the device to show vital signs. For now we check
1426 * that we can read the device ID and that the health buffer
1427 * shows a non zero value which is different than 0xffffffff
1429 static void wait_vital(struct pci_dev
*pdev
)
1431 struct mlx5_core_dev
*dev
= pci_get_drvdata(pdev
);
1432 struct mlx5_core_health
*health
= &dev
->priv
.health
;
1433 const int niter
= 100;
1438 /* Wait for firmware to be ready after reset */
1440 for (i
= 0; i
< niter
; i
++) {
1441 if (pci_read_config_word(pdev
, 2, &did
)) {
1442 dev_warn(&pdev
->dev
, "failed reading config word\n");
1445 if (did
== pdev
->device
) {
1446 dev_info(&pdev
->dev
, "device ID correctly read after %d iterations\n", i
);
1452 dev_warn(&pdev
->dev
, "%s-%d: could not read device ID\n", __func__
, __LINE__
);
1454 for (i
= 0; i
< niter
; i
++) {
1455 count
= ioread32be(health
->health_counter
);
1456 if (count
&& count
!= 0xffffffff) {
1457 dev_info(&pdev
->dev
, "Counter value 0x%x after %d iterations\n", count
, i
);
1464 dev_warn(&pdev
->dev
, "%s-%d: could not read device ID\n", __func__
, __LINE__
);
1467 static void mlx5_pci_resume(struct pci_dev
*pdev
)
1469 struct mlx5_core_dev
*dev
= pci_get_drvdata(pdev
);
1470 struct mlx5_priv
*priv
= &dev
->priv
;
1473 dev_info(&pdev
->dev
, "%s was called\n", __func__
);
1475 pci_save_state(pdev
);
1478 err
= mlx5_load_one(dev
, priv
);
1480 dev_err(&pdev
->dev
, "%s: mlx5_load_one failed with error code: %d\n"
1483 dev_info(&pdev
->dev
, "%s: device recovered\n", __func__
);
1486 static const struct pci_error_handlers mlx5_err_handler
= {
1487 .error_detected
= mlx5_pci_err_detected
,
1488 .slot_reset
= mlx5_pci_slot_reset
,
1489 .resume
= mlx5_pci_resume
1492 static void shutdown(struct pci_dev
*pdev
)
1494 struct mlx5_core_dev
*dev
= pci_get_drvdata(pdev
);
1495 struct mlx5_priv
*priv
= &dev
->priv
;
1497 dev_info(&pdev
->dev
, "Shutdown was called\n");
1498 /* Notify mlx5 clients that the kernel is being shut down */
1499 set_bit(MLX5_INTERFACE_STATE_SHUTDOWN
, &dev
->intf_state
);
1500 mlx5_unload_one(dev
, priv
);
1501 mlx5_pci_disable_device(dev
);
1504 static const struct pci_device_id mlx5_core_pci_table
[] = {
1505 { PCI_VDEVICE(MELLANOX
, 0x1011) }, /* Connect-IB */
1506 { PCI_VDEVICE(MELLANOX
, 0x1012), MLX5_PCI_DEV_IS_VF
}, /* Connect-IB VF */
1507 { PCI_VDEVICE(MELLANOX
, 0x1013) }, /* ConnectX-4 */
1508 { PCI_VDEVICE(MELLANOX
, 0x1014), MLX5_PCI_DEV_IS_VF
}, /* ConnectX-4 VF */
1509 { PCI_VDEVICE(MELLANOX
, 0x1015) }, /* ConnectX-4LX */
1510 { PCI_VDEVICE(MELLANOX
, 0x1016), MLX5_PCI_DEV_IS_VF
}, /* ConnectX-4LX VF */
1511 { PCI_VDEVICE(MELLANOX
, 0x1017) }, /* ConnectX-5 */
1512 { PCI_VDEVICE(MELLANOX
, 0x1018), MLX5_PCI_DEV_IS_VF
}, /* ConnectX-5 VF */
1516 MODULE_DEVICE_TABLE(pci
, mlx5_core_pci_table
);
1518 static struct pci_driver mlx5_core_driver
= {
1519 .name
= DRIVER_NAME
,
1520 .id_table
= mlx5_core_pci_table
,
1522 .remove
= remove_one
,
1523 .shutdown
= shutdown
,
1524 .err_handler
= &mlx5_err_handler
,
1525 .sriov_configure
= mlx5_core_sriov_configure
,
1528 static int __init
init(void)
1532 mlx5_register_debugfs();
1534 err
= pci_register_driver(&mlx5_core_driver
);
1538 #ifdef CONFIG_MLX5_CORE_EN
1545 mlx5_unregister_debugfs();
1549 static void __exit
cleanup(void)
1551 #ifdef CONFIG_MLX5_CORE_EN
1554 pci_unregister_driver(&mlx5_core_driver
);
1555 mlx5_unregister_debugfs();
1559 module_exit(cleanup
);