2 * Copyright (c) 2013, Mellanox Technologies inc. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <asm-generic/kmap_types.h>
34 #include <linux/module.h>
35 #include <linux/init.h>
36 #include <linux/errno.h>
37 #include <linux/pci.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/slab.h>
40 #include <linux/io-mapping.h>
41 #include <linux/mlx5/driver.h>
42 #include <linux/mlx5/cq.h>
43 #include <linux/mlx5/qp.h>
44 #include <linux/mlx5/srq.h>
45 #include <linux/debugfs.h>
46 #include "mlx5_core.h"
48 #define DRIVER_NAME "mlx5_core"
49 #define DRIVER_VERSION "1.0"
50 #define DRIVER_RELDATE "June 2013"
52 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
53 MODULE_DESCRIPTION("Mellanox ConnectX-IB HCA core library");
54 MODULE_LICENSE("Dual BSD/GPL");
55 MODULE_VERSION(DRIVER_VERSION
);
57 int mlx5_core_debug_mask
;
58 module_param_named(debug_mask
, mlx5_core_debug_mask
, int, 0644);
59 MODULE_PARM_DESC(debug_mask
, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0");
61 struct workqueue_struct
*mlx5_core_wq
;
63 static int set_dma_caps(struct pci_dev
*pdev
)
67 err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(64));
69 dev_warn(&pdev
->dev
, "Warning: couldn't set 64-bit PCI DMA mask.\n");
70 err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
72 dev_err(&pdev
->dev
, "Can't set PCI DMA mask, aborting.\n");
77 err
= pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(64));
80 "Warning: couldn't set 64-bit consistent PCI DMA mask.\n");
81 err
= pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(32));
84 "Can't set consistent PCI DMA mask, aborting.\n");
89 dma_set_max_seg_size(&pdev
->dev
, 2u * 1024 * 1024 * 1024);
93 static int request_bar(struct pci_dev
*pdev
)
97 if (!(pci_resource_flags(pdev
, 0) & IORESOURCE_MEM
)) {
98 dev_err(&pdev
->dev
, "Missing registers BAR, aborting.\n");
102 err
= pci_request_regions(pdev
, DRIVER_NAME
);
104 dev_err(&pdev
->dev
, "Couldn't get PCI resources, aborting\n");
109 static void release_bar(struct pci_dev
*pdev
)
111 pci_release_regions(pdev
);
114 static int mlx5_enable_msix(struct mlx5_core_dev
*dev
)
116 struct mlx5_eq_table
*table
= &dev
->priv
.eq_table
;
117 int num_eqs
= 1 << dev
->caps
.log_max_eq
;
122 nvec
= dev
->caps
.num_ports
* num_online_cpus() + MLX5_EQ_VEC_COMP_BASE
;
123 nvec
= min_t(int, nvec
, num_eqs
);
124 if (nvec
<= MLX5_EQ_VEC_COMP_BASE
)
127 table
->msix_arr
= kzalloc(nvec
* sizeof(*table
->msix_arr
), GFP_KERNEL
);
128 if (!table
->msix_arr
)
131 for (i
= 0; i
< nvec
; i
++)
132 table
->msix_arr
[i
].entry
= i
;
135 table
->num_comp_vectors
= nvec
- MLX5_EQ_VEC_COMP_BASE
;
136 err
= pci_enable_msix(dev
->pdev
, table
->msix_arr
, nvec
);
139 } else if (err
> 2) {
144 mlx5_core_dbg(dev
, "received %d MSI vectors out of %d requested\n", err
, nvec
);
149 static void mlx5_disable_msix(struct mlx5_core_dev
*dev
)
151 struct mlx5_eq_table
*table
= &dev
->priv
.eq_table
;
153 pci_disable_msix(dev
->pdev
);
154 kfree(table
->msix_arr
);
157 struct mlx5_reg_host_endianess
{
162 static int handle_hca_cap(struct mlx5_core_dev
*dev
)
164 struct mlx5_cmd_query_hca_cap_mbox_out
*query_out
= NULL
;
165 struct mlx5_cmd_set_hca_cap_mbox_in
*set_ctx
= NULL
;
166 struct mlx5_cmd_query_hca_cap_mbox_in query_ctx
;
167 struct mlx5_cmd_set_hca_cap_mbox_out set_out
;
171 memset(&query_ctx
, 0, sizeof(query_ctx
));
172 query_out
= kzalloc(sizeof(*query_out
), GFP_KERNEL
);
176 set_ctx
= kzalloc(sizeof(*set_ctx
), GFP_KERNEL
);
182 query_ctx
.hdr
.opcode
= cpu_to_be16(MLX5_CMD_OP_QUERY_HCA_CAP
);
183 query_ctx
.hdr
.opmod
= cpu_to_be16(0x1);
184 err
= mlx5_cmd_exec(dev
, &query_ctx
, sizeof(query_ctx
),
185 query_out
, sizeof(*query_out
));
189 err
= mlx5_cmd_status_to_err(&query_out
->hdr
);
191 mlx5_core_warn(dev
, "query hca cap failed, %d\n", err
);
195 memcpy(&set_ctx
->hca_cap
, &query_out
->hca_cap
,
196 sizeof(set_ctx
->hca_cap
));
198 if (dev
->profile
->mask
& MLX5_PROF_MASK_QP_SIZE
)
199 set_ctx
->hca_cap
.log_max_qp
= dev
->profile
->log_max_qp
;
201 flags
= be64_to_cpu(query_out
->hca_cap
.flags
);
202 /* disable checksum */
203 flags
&= ~MLX5_DEV_CAP_FLAG_CMDIF_CSUM
;
205 set_ctx
->hca_cap
.flags
= cpu_to_be64(flags
);
206 memset(&set_out
, 0, sizeof(set_out
));
207 set_ctx
->hca_cap
.log_uar_page_sz
= cpu_to_be16(PAGE_SHIFT
- 12);
208 set_ctx
->hdr
.opcode
= cpu_to_be16(MLX5_CMD_OP_SET_HCA_CAP
);
209 err
= mlx5_cmd_exec(dev
, set_ctx
, sizeof(*set_ctx
),
210 &set_out
, sizeof(set_out
));
212 mlx5_core_warn(dev
, "set hca cap failed, %d\n", err
);
216 err
= mlx5_cmd_status_to_err(&set_out
.hdr
);
227 static int set_hca_ctrl(struct mlx5_core_dev
*dev
)
229 struct mlx5_reg_host_endianess he_in
;
230 struct mlx5_reg_host_endianess he_out
;
233 memset(&he_in
, 0, sizeof(he_in
));
234 he_in
.he
= MLX5_SET_HOST_ENDIANNESS
;
235 err
= mlx5_core_access_reg(dev
, &he_in
, sizeof(he_in
),
236 &he_out
, sizeof(he_out
),
237 MLX5_REG_HOST_ENDIANNESS
, 0, 1);
241 static int mlx5_core_enable_hca(struct mlx5_core_dev
*dev
)
244 struct mlx5_enable_hca_mbox_in in
;
245 struct mlx5_enable_hca_mbox_out out
;
247 memset(&in
, 0, sizeof(in
));
248 memset(&out
, 0, sizeof(out
));
249 in
.hdr
.opcode
= cpu_to_be16(MLX5_CMD_OP_ENABLE_HCA
);
250 err
= mlx5_cmd_exec(dev
, &in
, sizeof(in
), &out
, sizeof(out
));
255 return mlx5_cmd_status_to_err(&out
.hdr
);
260 static int mlx5_core_disable_hca(struct mlx5_core_dev
*dev
)
263 struct mlx5_disable_hca_mbox_in in
;
264 struct mlx5_disable_hca_mbox_out out
;
266 memset(&in
, 0, sizeof(in
));
267 memset(&out
, 0, sizeof(out
));
268 in
.hdr
.opcode
= cpu_to_be16(MLX5_CMD_OP_DISABLE_HCA
);
269 err
= mlx5_cmd_exec(dev
, &in
, sizeof(in
), &out
, sizeof(out
));
274 return mlx5_cmd_status_to_err(&out
.hdr
);
279 int mlx5_dev_init(struct mlx5_core_dev
*dev
, struct pci_dev
*pdev
)
281 struct mlx5_priv
*priv
= &dev
->priv
;
285 pci_set_drvdata(dev
->pdev
, dev
);
286 strncpy(priv
->name
, dev_name(&pdev
->dev
), MLX5_MAX_NAME_LEN
);
287 priv
->name
[MLX5_MAX_NAME_LEN
- 1] = 0;
289 mutex_init(&priv
->pgdir_mutex
);
290 INIT_LIST_HEAD(&priv
->pgdir_list
);
291 spin_lock_init(&priv
->mkey_lock
);
293 priv
->dbg_root
= debugfs_create_dir(dev_name(&pdev
->dev
), mlx5_debugfs_root
);
297 err
= pci_enable_device(pdev
);
299 dev_err(&pdev
->dev
, "Cannot enable PCI device, aborting.\n");
303 err
= request_bar(pdev
);
305 dev_err(&pdev
->dev
, "error requesting BARs, aborting.\n");
309 pci_set_master(pdev
);
311 err
= set_dma_caps(pdev
);
313 dev_err(&pdev
->dev
, "Failed setting DMA capabilities mask, aborting\n");
317 dev
->iseg_base
= pci_resource_start(dev
->pdev
, 0);
318 dev
->iseg
= ioremap(dev
->iseg_base
, sizeof(*dev
->iseg
));
321 dev_err(&pdev
->dev
, "Failed mapping initialization segment, aborting\n");
324 dev_info(&pdev
->dev
, "firmware version: %d.%d.%d\n", fw_rev_maj(dev
),
325 fw_rev_min(dev
), fw_rev_sub(dev
));
327 err
= mlx5_cmd_init(dev
);
329 dev_err(&pdev
->dev
, "Failed initializing command interface, aborting\n");
333 mlx5_pagealloc_init(dev
);
335 err
= mlx5_core_enable_hca(dev
);
337 dev_err(&pdev
->dev
, "enable hca failed\n");
338 goto err_pagealloc_cleanup
;
341 err
= mlx5_satisfy_startup_pages(dev
, 1);
343 dev_err(&pdev
->dev
, "failed to allocate boot pages\n");
344 goto err_disable_hca
;
347 err
= set_hca_ctrl(dev
);
349 dev_err(&pdev
->dev
, "set_hca_ctrl failed\n");
350 goto reclaim_boot_pages
;
353 err
= handle_hca_cap(dev
);
355 dev_err(&pdev
->dev
, "handle_hca_cap failed\n");
356 goto reclaim_boot_pages
;
359 err
= mlx5_satisfy_startup_pages(dev
, 0);
361 dev_err(&pdev
->dev
, "failed to allocate init pages\n");
362 goto reclaim_boot_pages
;
365 err
= mlx5_pagealloc_start(dev
);
367 dev_err(&pdev
->dev
, "mlx5_pagealloc_start failed\n");
368 goto reclaim_boot_pages
;
371 err
= mlx5_cmd_init_hca(dev
);
373 dev_err(&pdev
->dev
, "init hca failed\n");
374 goto err_pagealloc_stop
;
377 mlx5_start_health_poll(dev
);
379 err
= mlx5_cmd_query_hca_cap(dev
, &dev
->caps
);
381 dev_err(&pdev
->dev
, "query hca failed\n");
385 err
= mlx5_cmd_query_adapter(dev
);
387 dev_err(&pdev
->dev
, "query adapter failed\n");
391 err
= mlx5_enable_msix(dev
);
393 dev_err(&pdev
->dev
, "enable msix failed\n");
397 err
= mlx5_eq_init(dev
);
399 dev_err(&pdev
->dev
, "failed to initialize eq\n");
403 err
= mlx5_alloc_uuars(dev
, &priv
->uuari
);
405 dev_err(&pdev
->dev
, "Failed allocating uar, aborting\n");
409 err
= mlx5_start_eqs(dev
);
411 dev_err(&pdev
->dev
, "Failed to start pages and async EQs\n");
415 MLX5_INIT_DOORBELL_LOCK(&priv
->cq_uar_lock
);
417 mlx5_init_cq_table(dev
);
418 mlx5_init_qp_table(dev
);
419 mlx5_init_srq_table(dev
);
424 mlx5_free_uuars(dev
, &priv
->uuari
);
427 mlx5_eq_cleanup(dev
);
430 mlx5_disable_msix(dev
);
433 mlx5_stop_health_poll(dev
);
434 mlx5_cmd_teardown_hca(dev
);
437 mlx5_pagealloc_stop(dev
);
440 mlx5_reclaim_startup_pages(dev
);
443 mlx5_core_disable_hca(dev
);
445 err_pagealloc_cleanup
:
446 mlx5_pagealloc_cleanup(dev
);
447 mlx5_cmd_cleanup(dev
);
453 pci_clear_master(dev
->pdev
);
454 release_bar(dev
->pdev
);
457 pci_disable_device(dev
->pdev
);
460 debugfs_remove(priv
->dbg_root
);
463 EXPORT_SYMBOL(mlx5_dev_init
);
465 void mlx5_dev_cleanup(struct mlx5_core_dev
*dev
)
467 struct mlx5_priv
*priv
= &dev
->priv
;
469 mlx5_cleanup_srq_table(dev
);
470 mlx5_cleanup_qp_table(dev
);
471 mlx5_cleanup_cq_table(dev
);
473 mlx5_free_uuars(dev
, &priv
->uuari
);
474 mlx5_eq_cleanup(dev
);
475 mlx5_disable_msix(dev
);
476 mlx5_stop_health_poll(dev
);
477 mlx5_cmd_teardown_hca(dev
);
478 mlx5_pagealloc_stop(dev
);
479 mlx5_reclaim_startup_pages(dev
);
480 mlx5_core_disable_hca(dev
);
481 mlx5_pagealloc_cleanup(dev
);
482 mlx5_cmd_cleanup(dev
);
484 pci_clear_master(dev
->pdev
);
485 release_bar(dev
->pdev
);
486 pci_disable_device(dev
->pdev
);
487 debugfs_remove(priv
->dbg_root
);
489 EXPORT_SYMBOL(mlx5_dev_cleanup
);
491 static int __init
init(void)
495 mlx5_register_debugfs();
496 mlx5_core_wq
= create_singlethread_workqueue("mlx5_core_wq");
505 mlx5_health_cleanup();
507 mlx5_unregister_debugfs();
511 static void __exit
cleanup(void)
513 mlx5_health_cleanup();
514 destroy_workqueue(mlx5_core_wq
);
515 mlx5_unregister_debugfs();
519 module_exit(cleanup
);