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Merge tag 'qcom-soc-for-4.7-2' into net-next
[deliverable/linux.git] / drivers / net / ethernet / mellanox / mlx5 / core / main.c
1 /*
2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <linux/highmem.h>
34 #include <linux/module.h>
35 #include <linux/init.h>
36 #include <linux/errno.h>
37 #include <linux/pci.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/slab.h>
40 #include <linux/io-mapping.h>
41 #include <linux/interrupt.h>
42 #include <linux/delay.h>
43 #include <linux/mlx5/driver.h>
44 #include <linux/mlx5/cq.h>
45 #include <linux/mlx5/qp.h>
46 #include <linux/mlx5/srq.h>
47 #include <linux/debugfs.h>
48 #include <linux/kmod.h>
49 #include <linux/delay.h>
50 #include <linux/mlx5/mlx5_ifc.h>
51 #ifdef CONFIG_RFS_ACCEL
52 #include <linux/cpu_rmap.h>
53 #endif
54 #include "mlx5_core.h"
55 #include "fs_core.h"
56 #ifdef CONFIG_MLX5_CORE_EN
57 #include "eswitch.h"
58 #endif
59
60 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
61 MODULE_DESCRIPTION("Mellanox Connect-IB, ConnectX-4 core driver");
62 MODULE_LICENSE("Dual BSD/GPL");
63 MODULE_VERSION(DRIVER_VERSION);
64
65 int mlx5_core_debug_mask;
66 module_param_named(debug_mask, mlx5_core_debug_mask, int, 0644);
67 MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0");
68
69 #define MLX5_DEFAULT_PROF 2
70 static int prof_sel = MLX5_DEFAULT_PROF;
71 module_param_named(prof_sel, prof_sel, int, 0444);
72 MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2");
73
74 static LIST_HEAD(intf_list);
75 static LIST_HEAD(dev_list);
76 static DEFINE_MUTEX(intf_mutex);
77
78 struct mlx5_device_context {
79 struct list_head list;
80 struct mlx5_interface *intf;
81 void *context;
82 };
83
84 enum {
85 MLX5_ATOMIC_REQ_MODE_BE = 0x0,
86 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1,
87 };
88
89 static struct mlx5_profile profile[] = {
90 [0] = {
91 .mask = 0,
92 },
93 [1] = {
94 .mask = MLX5_PROF_MASK_QP_SIZE,
95 .log_max_qp = 12,
96 },
97 [2] = {
98 .mask = MLX5_PROF_MASK_QP_SIZE |
99 MLX5_PROF_MASK_MR_CACHE,
100 .log_max_qp = 17,
101 .mr_cache[0] = {
102 .size = 500,
103 .limit = 250
104 },
105 .mr_cache[1] = {
106 .size = 500,
107 .limit = 250
108 },
109 .mr_cache[2] = {
110 .size = 500,
111 .limit = 250
112 },
113 .mr_cache[3] = {
114 .size = 500,
115 .limit = 250
116 },
117 .mr_cache[4] = {
118 .size = 500,
119 .limit = 250
120 },
121 .mr_cache[5] = {
122 .size = 500,
123 .limit = 250
124 },
125 .mr_cache[6] = {
126 .size = 500,
127 .limit = 250
128 },
129 .mr_cache[7] = {
130 .size = 500,
131 .limit = 250
132 },
133 .mr_cache[8] = {
134 .size = 500,
135 .limit = 250
136 },
137 .mr_cache[9] = {
138 .size = 500,
139 .limit = 250
140 },
141 .mr_cache[10] = {
142 .size = 500,
143 .limit = 250
144 },
145 .mr_cache[11] = {
146 .size = 500,
147 .limit = 250
148 },
149 .mr_cache[12] = {
150 .size = 64,
151 .limit = 32
152 },
153 .mr_cache[13] = {
154 .size = 32,
155 .limit = 16
156 },
157 .mr_cache[14] = {
158 .size = 16,
159 .limit = 8
160 },
161 .mr_cache[15] = {
162 .size = 8,
163 .limit = 4
164 },
165 },
166 };
167
168 #define FW_INIT_TIMEOUT_MILI 2000
169 #define FW_INIT_WAIT_MS 2
170
171 static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili)
172 {
173 unsigned long end = jiffies + msecs_to_jiffies(max_wait_mili);
174 int err = 0;
175
176 while (fw_initializing(dev)) {
177 if (time_after(jiffies, end)) {
178 err = -EBUSY;
179 break;
180 }
181 msleep(FW_INIT_WAIT_MS);
182 }
183
184 return err;
185 }
186
187 static int set_dma_caps(struct pci_dev *pdev)
188 {
189 int err;
190
191 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
192 if (err) {
193 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n");
194 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
195 if (err) {
196 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n");
197 return err;
198 }
199 }
200
201 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
202 if (err) {
203 dev_warn(&pdev->dev,
204 "Warning: couldn't set 64-bit consistent PCI DMA mask\n");
205 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
206 if (err) {
207 dev_err(&pdev->dev,
208 "Can't set consistent PCI DMA mask, aborting\n");
209 return err;
210 }
211 }
212
213 dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024);
214 return err;
215 }
216
217 static int mlx5_pci_enable_device(struct mlx5_core_dev *dev)
218 {
219 struct pci_dev *pdev = dev->pdev;
220 int err = 0;
221
222 mutex_lock(&dev->pci_status_mutex);
223 if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) {
224 err = pci_enable_device(pdev);
225 if (!err)
226 dev->pci_status = MLX5_PCI_STATUS_ENABLED;
227 }
228 mutex_unlock(&dev->pci_status_mutex);
229
230 return err;
231 }
232
233 static void mlx5_pci_disable_device(struct mlx5_core_dev *dev)
234 {
235 struct pci_dev *pdev = dev->pdev;
236
237 mutex_lock(&dev->pci_status_mutex);
238 if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) {
239 pci_disable_device(pdev);
240 dev->pci_status = MLX5_PCI_STATUS_DISABLED;
241 }
242 mutex_unlock(&dev->pci_status_mutex);
243 }
244
245 static int request_bar(struct pci_dev *pdev)
246 {
247 int err = 0;
248
249 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
250 dev_err(&pdev->dev, "Missing registers BAR, aborting\n");
251 return -ENODEV;
252 }
253
254 err = pci_request_regions(pdev, DRIVER_NAME);
255 if (err)
256 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
257
258 return err;
259 }
260
261 static void release_bar(struct pci_dev *pdev)
262 {
263 pci_release_regions(pdev);
264 }
265
266 static int mlx5_enable_msix(struct mlx5_core_dev *dev)
267 {
268 struct mlx5_priv *priv = &dev->priv;
269 struct mlx5_eq_table *table = &priv->eq_table;
270 int num_eqs = 1 << MLX5_CAP_GEN(dev, log_max_eq);
271 int nvec;
272 int i;
273
274 nvec = MLX5_CAP_GEN(dev, num_ports) * num_online_cpus() +
275 MLX5_EQ_VEC_COMP_BASE;
276 nvec = min_t(int, nvec, num_eqs);
277 if (nvec <= MLX5_EQ_VEC_COMP_BASE)
278 return -ENOMEM;
279
280 priv->msix_arr = kcalloc(nvec, sizeof(*priv->msix_arr), GFP_KERNEL);
281
282 priv->irq_info = kcalloc(nvec, sizeof(*priv->irq_info), GFP_KERNEL);
283 if (!priv->msix_arr || !priv->irq_info)
284 goto err_free_msix;
285
286 for (i = 0; i < nvec; i++)
287 priv->msix_arr[i].entry = i;
288
289 nvec = pci_enable_msix_range(dev->pdev, priv->msix_arr,
290 MLX5_EQ_VEC_COMP_BASE + 1, nvec);
291 if (nvec < 0)
292 return nvec;
293
294 table->num_comp_vectors = nvec - MLX5_EQ_VEC_COMP_BASE;
295
296 return 0;
297
298 err_free_msix:
299 kfree(priv->irq_info);
300 kfree(priv->msix_arr);
301 return -ENOMEM;
302 }
303
304 static void mlx5_disable_msix(struct mlx5_core_dev *dev)
305 {
306 struct mlx5_priv *priv = &dev->priv;
307
308 pci_disable_msix(dev->pdev);
309 kfree(priv->irq_info);
310 kfree(priv->msix_arr);
311 }
312
313 struct mlx5_reg_host_endianess {
314 u8 he;
315 u8 rsvd[15];
316 };
317
318
319 #define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos))
320
321 enum {
322 MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) |
323 MLX5_DEV_CAP_FLAG_DCT,
324 };
325
326 static u16 to_fw_pkey_sz(u32 size)
327 {
328 switch (size) {
329 case 128:
330 return 0;
331 case 256:
332 return 1;
333 case 512:
334 return 2;
335 case 1024:
336 return 3;
337 case 2048:
338 return 4;
339 case 4096:
340 return 5;
341 default:
342 pr_warn("invalid pkey table size %d\n", size);
343 return 0;
344 }
345 }
346
347 static int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev,
348 enum mlx5_cap_type cap_type,
349 enum mlx5_cap_mode cap_mode)
350 {
351 u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)];
352 int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
353 void *out, *hca_caps;
354 u16 opmod = (cap_type << 1) | (cap_mode & 0x01);
355 int err;
356
357 memset(in, 0, sizeof(in));
358 out = kzalloc(out_sz, GFP_KERNEL);
359 if (!out)
360 return -ENOMEM;
361
362 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
363 MLX5_SET(query_hca_cap_in, in, op_mod, opmod);
364 err = mlx5_cmd_exec(dev, in, sizeof(in), out, out_sz);
365 if (err)
366 goto query_ex;
367
368 err = mlx5_cmd_status_to_err_v2(out);
369 if (err) {
370 mlx5_core_warn(dev,
371 "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n",
372 cap_type, cap_mode, err);
373 goto query_ex;
374 }
375
376 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
377
378 switch (cap_mode) {
379 case HCA_CAP_OPMOD_GET_MAX:
380 memcpy(dev->hca_caps_max[cap_type], hca_caps,
381 MLX5_UN_SZ_BYTES(hca_cap_union));
382 break;
383 case HCA_CAP_OPMOD_GET_CUR:
384 memcpy(dev->hca_caps_cur[cap_type], hca_caps,
385 MLX5_UN_SZ_BYTES(hca_cap_union));
386 break;
387 default:
388 mlx5_core_warn(dev,
389 "Tried to query dev cap type(%x) with wrong opmode(%x)\n",
390 cap_type, cap_mode);
391 err = -EINVAL;
392 break;
393 }
394 query_ex:
395 kfree(out);
396 return err;
397 }
398
399 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type)
400 {
401 int ret;
402
403 ret = mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_CUR);
404 if (ret)
405 return ret;
406 return mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_MAX);
407 }
408
409 static int set_caps(struct mlx5_core_dev *dev, void *in, int in_sz, int opmod)
410 {
411 u32 out[MLX5_ST_SZ_DW(set_hca_cap_out)];
412 int err;
413
414 memset(out, 0, sizeof(out));
415
416 MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP);
417 MLX5_SET(set_hca_cap_in, in, op_mod, opmod << 1);
418 err = mlx5_cmd_exec(dev, in, in_sz, out, sizeof(out));
419 if (err)
420 return err;
421
422 err = mlx5_cmd_status_to_err_v2(out);
423
424 return err;
425 }
426
427 static int handle_hca_cap_atomic(struct mlx5_core_dev *dev)
428 {
429 void *set_ctx;
430 void *set_hca_cap;
431 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
432 int req_endianness;
433 int err;
434
435 if (MLX5_CAP_GEN(dev, atomic)) {
436 err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC);
437 if (err)
438 return err;
439 } else {
440 return 0;
441 }
442
443 req_endianness =
444 MLX5_CAP_ATOMIC(dev,
445 supported_atomic_req_8B_endianess_mode_1);
446
447 if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS)
448 return 0;
449
450 set_ctx = kzalloc(set_sz, GFP_KERNEL);
451 if (!set_ctx)
452 return -ENOMEM;
453
454 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
455
456 /* Set requestor to host endianness */
457 MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianess_mode,
458 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS);
459
460 err = set_caps(dev, set_ctx, set_sz, MLX5_SET_HCA_CAP_OP_MOD_ATOMIC);
461
462 kfree(set_ctx);
463 return err;
464 }
465
466 static int handle_hca_cap(struct mlx5_core_dev *dev)
467 {
468 void *set_ctx = NULL;
469 struct mlx5_profile *prof = dev->profile;
470 int err = -ENOMEM;
471 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
472 void *set_hca_cap;
473
474 set_ctx = kzalloc(set_sz, GFP_KERNEL);
475 if (!set_ctx)
476 goto query_ex;
477
478 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL);
479 if (err)
480 goto query_ex;
481
482 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx,
483 capability);
484 memcpy(set_hca_cap, dev->hca_caps_cur[MLX5_CAP_GENERAL],
485 MLX5_ST_SZ_BYTES(cmd_hca_cap));
486
487 mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n",
488 mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)),
489 128);
490 /* we limit the size of the pkey table to 128 entries for now */
491 MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size,
492 to_fw_pkey_sz(128));
493
494 if (prof->mask & MLX5_PROF_MASK_QP_SIZE)
495 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp,
496 prof->log_max_qp);
497
498 /* disable cmdif checksum */
499 MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0);
500
501 MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12);
502
503 err = set_caps(dev, set_ctx, set_sz,
504 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE);
505
506 query_ex:
507 kfree(set_ctx);
508 return err;
509 }
510
511 static int set_hca_ctrl(struct mlx5_core_dev *dev)
512 {
513 struct mlx5_reg_host_endianess he_in;
514 struct mlx5_reg_host_endianess he_out;
515 int err;
516
517 if (!mlx5_core_is_pf(dev))
518 return 0;
519
520 memset(&he_in, 0, sizeof(he_in));
521 he_in.he = MLX5_SET_HOST_ENDIANNESS;
522 err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in),
523 &he_out, sizeof(he_out),
524 MLX5_REG_HOST_ENDIANNESS, 0, 1);
525 return err;
526 }
527
528 int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id)
529 {
530 u32 out[MLX5_ST_SZ_DW(enable_hca_out)];
531 u32 in[MLX5_ST_SZ_DW(enable_hca_in)];
532 int err;
533
534 memset(in, 0, sizeof(in));
535 MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA);
536 MLX5_SET(enable_hca_in, in, function_id, func_id);
537 memset(out, 0, sizeof(out));
538
539 err = mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
540 if (err)
541 return err;
542
543 return mlx5_cmd_status_to_err_v2(out);
544 }
545
546 int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id)
547 {
548 u32 out[MLX5_ST_SZ_DW(disable_hca_out)];
549 u32 in[MLX5_ST_SZ_DW(disable_hca_in)];
550 int err;
551
552 memset(in, 0, sizeof(in));
553 MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA);
554 MLX5_SET(disable_hca_in, in, function_id, func_id);
555 memset(out, 0, sizeof(out));
556 err = mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
557 if (err)
558 return err;
559
560 return mlx5_cmd_status_to_err_v2(out);
561 }
562
563 cycle_t mlx5_read_internal_timer(struct mlx5_core_dev *dev)
564 {
565 u32 timer_h, timer_h1, timer_l;
566
567 timer_h = ioread32be(&dev->iseg->internal_timer_h);
568 timer_l = ioread32be(&dev->iseg->internal_timer_l);
569 timer_h1 = ioread32be(&dev->iseg->internal_timer_h);
570 if (timer_h != timer_h1) /* wrap around */
571 timer_l = ioread32be(&dev->iseg->internal_timer_l);
572
573 return (cycle_t)timer_l | (cycle_t)timer_h1 << 32;
574 }
575
576 static int mlx5_irq_set_affinity_hint(struct mlx5_core_dev *mdev, int i)
577 {
578 struct mlx5_priv *priv = &mdev->priv;
579 struct msix_entry *msix = priv->msix_arr;
580 int irq = msix[i + MLX5_EQ_VEC_COMP_BASE].vector;
581 int numa_node = priv->numa_node;
582 int err;
583
584 if (!zalloc_cpumask_var(&priv->irq_info[i].mask, GFP_KERNEL)) {
585 mlx5_core_warn(mdev, "zalloc_cpumask_var failed");
586 return -ENOMEM;
587 }
588
589 cpumask_set_cpu(cpumask_local_spread(i, numa_node),
590 priv->irq_info[i].mask);
591
592 err = irq_set_affinity_hint(irq, priv->irq_info[i].mask);
593 if (err) {
594 mlx5_core_warn(mdev, "irq_set_affinity_hint failed,irq 0x%.4x",
595 irq);
596 goto err_clear_mask;
597 }
598
599 return 0;
600
601 err_clear_mask:
602 free_cpumask_var(priv->irq_info[i].mask);
603 return err;
604 }
605
606 static void mlx5_irq_clear_affinity_hint(struct mlx5_core_dev *mdev, int i)
607 {
608 struct mlx5_priv *priv = &mdev->priv;
609 struct msix_entry *msix = priv->msix_arr;
610 int irq = msix[i + MLX5_EQ_VEC_COMP_BASE].vector;
611
612 irq_set_affinity_hint(irq, NULL);
613 free_cpumask_var(priv->irq_info[i].mask);
614 }
615
616 static int mlx5_irq_set_affinity_hints(struct mlx5_core_dev *mdev)
617 {
618 int err;
619 int i;
620
621 for (i = 0; i < mdev->priv.eq_table.num_comp_vectors; i++) {
622 err = mlx5_irq_set_affinity_hint(mdev, i);
623 if (err)
624 goto err_out;
625 }
626
627 return 0;
628
629 err_out:
630 for (i--; i >= 0; i--)
631 mlx5_irq_clear_affinity_hint(mdev, i);
632
633 return err;
634 }
635
636 static void mlx5_irq_clear_affinity_hints(struct mlx5_core_dev *mdev)
637 {
638 int i;
639
640 for (i = 0; i < mdev->priv.eq_table.num_comp_vectors; i++)
641 mlx5_irq_clear_affinity_hint(mdev, i);
642 }
643
644 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn,
645 unsigned int *irqn)
646 {
647 struct mlx5_eq_table *table = &dev->priv.eq_table;
648 struct mlx5_eq *eq, *n;
649 int err = -ENOENT;
650
651 spin_lock(&table->lock);
652 list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) {
653 if (eq->index == vector) {
654 *eqn = eq->eqn;
655 *irqn = eq->irqn;
656 err = 0;
657 break;
658 }
659 }
660 spin_unlock(&table->lock);
661
662 return err;
663 }
664 EXPORT_SYMBOL(mlx5_vector2eqn);
665
666 static void free_comp_eqs(struct mlx5_core_dev *dev)
667 {
668 struct mlx5_eq_table *table = &dev->priv.eq_table;
669 struct mlx5_eq *eq, *n;
670
671 #ifdef CONFIG_RFS_ACCEL
672 if (dev->rmap) {
673 free_irq_cpu_rmap(dev->rmap);
674 dev->rmap = NULL;
675 }
676 #endif
677 spin_lock(&table->lock);
678 list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) {
679 list_del(&eq->list);
680 spin_unlock(&table->lock);
681 if (mlx5_destroy_unmap_eq(dev, eq))
682 mlx5_core_warn(dev, "failed to destroy EQ 0x%x\n",
683 eq->eqn);
684 kfree(eq);
685 spin_lock(&table->lock);
686 }
687 spin_unlock(&table->lock);
688 }
689
690 static int alloc_comp_eqs(struct mlx5_core_dev *dev)
691 {
692 struct mlx5_eq_table *table = &dev->priv.eq_table;
693 char name[MLX5_MAX_IRQ_NAME];
694 struct mlx5_eq *eq;
695 int ncomp_vec;
696 int nent;
697 int err;
698 int i;
699
700 INIT_LIST_HEAD(&table->comp_eqs_list);
701 ncomp_vec = table->num_comp_vectors;
702 nent = MLX5_COMP_EQ_SIZE;
703 #ifdef CONFIG_RFS_ACCEL
704 dev->rmap = alloc_irq_cpu_rmap(ncomp_vec);
705 if (!dev->rmap)
706 return -ENOMEM;
707 #endif
708 for (i = 0; i < ncomp_vec; i++) {
709 eq = kzalloc(sizeof(*eq), GFP_KERNEL);
710 if (!eq) {
711 err = -ENOMEM;
712 goto clean;
713 }
714
715 #ifdef CONFIG_RFS_ACCEL
716 irq_cpu_rmap_add(dev->rmap,
717 dev->priv.msix_arr[i + MLX5_EQ_VEC_COMP_BASE].vector);
718 #endif
719 snprintf(name, MLX5_MAX_IRQ_NAME, "mlx5_comp%d", i);
720 err = mlx5_create_map_eq(dev, eq,
721 i + MLX5_EQ_VEC_COMP_BASE, nent, 0,
722 name, &dev->priv.uuari.uars[0]);
723 if (err) {
724 kfree(eq);
725 goto clean;
726 }
727 mlx5_core_dbg(dev, "allocated completion EQN %d\n", eq->eqn);
728 eq->index = i;
729 spin_lock(&table->lock);
730 list_add_tail(&eq->list, &table->comp_eqs_list);
731 spin_unlock(&table->lock);
732 }
733
734 return 0;
735
736 clean:
737 free_comp_eqs(dev);
738 return err;
739 }
740
741 static int mlx5_core_set_issi(struct mlx5_core_dev *dev)
742 {
743 u32 query_in[MLX5_ST_SZ_DW(query_issi_in)];
744 u32 query_out[MLX5_ST_SZ_DW(query_issi_out)];
745 u32 set_in[MLX5_ST_SZ_DW(set_issi_in)];
746 u32 set_out[MLX5_ST_SZ_DW(set_issi_out)];
747 int err;
748 u32 sup_issi;
749
750 memset(query_in, 0, sizeof(query_in));
751 memset(query_out, 0, sizeof(query_out));
752
753 MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI);
754
755 err = mlx5_cmd_exec_check_status(dev, query_in, sizeof(query_in),
756 query_out, sizeof(query_out));
757 if (err) {
758 if (((struct mlx5_outbox_hdr *)query_out)->status ==
759 MLX5_CMD_STAT_BAD_OP_ERR) {
760 pr_debug("Only ISSI 0 is supported\n");
761 return 0;
762 }
763
764 pr_err("failed to query ISSI\n");
765 return err;
766 }
767
768 sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0);
769
770 if (sup_issi & (1 << 1)) {
771 memset(set_in, 0, sizeof(set_in));
772 memset(set_out, 0, sizeof(set_out));
773
774 MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI);
775 MLX5_SET(set_issi_in, set_in, current_issi, 1);
776
777 err = mlx5_cmd_exec_check_status(dev, set_in, sizeof(set_in),
778 set_out, sizeof(set_out));
779 if (err) {
780 pr_err("failed to set ISSI=1\n");
781 return err;
782 }
783
784 dev->issi = 1;
785
786 return 0;
787 } else if (sup_issi & (1 << 0) || !sup_issi) {
788 return 0;
789 }
790
791 return -ENOTSUPP;
792 }
793
794 static void mlx5_add_device(struct mlx5_interface *intf, struct mlx5_priv *priv)
795 {
796 struct mlx5_device_context *dev_ctx;
797 struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv);
798
799 dev_ctx = kmalloc(sizeof(*dev_ctx), GFP_KERNEL);
800 if (!dev_ctx)
801 return;
802
803 dev_ctx->intf = intf;
804 dev_ctx->context = intf->add(dev);
805
806 if (dev_ctx->context) {
807 spin_lock_irq(&priv->ctx_lock);
808 list_add_tail(&dev_ctx->list, &priv->ctx_list);
809 spin_unlock_irq(&priv->ctx_lock);
810 } else {
811 kfree(dev_ctx);
812 }
813 }
814
815 static void mlx5_remove_device(struct mlx5_interface *intf, struct mlx5_priv *priv)
816 {
817 struct mlx5_device_context *dev_ctx;
818 struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv);
819
820 list_for_each_entry(dev_ctx, &priv->ctx_list, list)
821 if (dev_ctx->intf == intf) {
822 spin_lock_irq(&priv->ctx_lock);
823 list_del(&dev_ctx->list);
824 spin_unlock_irq(&priv->ctx_lock);
825
826 intf->remove(dev, dev_ctx->context);
827 kfree(dev_ctx);
828 return;
829 }
830 }
831
832 static int mlx5_register_device(struct mlx5_core_dev *dev)
833 {
834 struct mlx5_priv *priv = &dev->priv;
835 struct mlx5_interface *intf;
836
837 mutex_lock(&intf_mutex);
838 list_add_tail(&priv->dev_list, &dev_list);
839 list_for_each_entry(intf, &intf_list, list)
840 mlx5_add_device(intf, priv);
841 mutex_unlock(&intf_mutex);
842
843 return 0;
844 }
845
846 static void mlx5_unregister_device(struct mlx5_core_dev *dev)
847 {
848 struct mlx5_priv *priv = &dev->priv;
849 struct mlx5_interface *intf;
850
851 mutex_lock(&intf_mutex);
852 list_for_each_entry(intf, &intf_list, list)
853 mlx5_remove_device(intf, priv);
854 list_del(&priv->dev_list);
855 mutex_unlock(&intf_mutex);
856 }
857
858 int mlx5_register_interface(struct mlx5_interface *intf)
859 {
860 struct mlx5_priv *priv;
861
862 if (!intf->add || !intf->remove)
863 return -EINVAL;
864
865 mutex_lock(&intf_mutex);
866 list_add_tail(&intf->list, &intf_list);
867 list_for_each_entry(priv, &dev_list, dev_list)
868 mlx5_add_device(intf, priv);
869 mutex_unlock(&intf_mutex);
870
871 return 0;
872 }
873 EXPORT_SYMBOL(mlx5_register_interface);
874
875 void mlx5_unregister_interface(struct mlx5_interface *intf)
876 {
877 struct mlx5_priv *priv;
878
879 mutex_lock(&intf_mutex);
880 list_for_each_entry(priv, &dev_list, dev_list)
881 mlx5_remove_device(intf, priv);
882 list_del(&intf->list);
883 mutex_unlock(&intf_mutex);
884 }
885 EXPORT_SYMBOL(mlx5_unregister_interface);
886
887 void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol)
888 {
889 struct mlx5_priv *priv = &mdev->priv;
890 struct mlx5_device_context *dev_ctx;
891 unsigned long flags;
892 void *result = NULL;
893
894 spin_lock_irqsave(&priv->ctx_lock, flags);
895
896 list_for_each_entry(dev_ctx, &mdev->priv.ctx_list, list)
897 if ((dev_ctx->intf->protocol == protocol) &&
898 dev_ctx->intf->get_dev) {
899 result = dev_ctx->intf->get_dev(dev_ctx->context);
900 break;
901 }
902
903 spin_unlock_irqrestore(&priv->ctx_lock, flags);
904
905 return result;
906 }
907 EXPORT_SYMBOL(mlx5_get_protocol_dev);
908
909 static int mlx5_pci_init(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
910 {
911 struct pci_dev *pdev = dev->pdev;
912 int err = 0;
913
914 pci_set_drvdata(dev->pdev, dev);
915 strncpy(priv->name, dev_name(&pdev->dev), MLX5_MAX_NAME_LEN);
916 priv->name[MLX5_MAX_NAME_LEN - 1] = 0;
917
918 mutex_init(&priv->pgdir_mutex);
919 INIT_LIST_HEAD(&priv->pgdir_list);
920 spin_lock_init(&priv->mkey_lock);
921
922 mutex_init(&priv->alloc_mutex);
923
924 priv->numa_node = dev_to_node(&dev->pdev->dev);
925
926 priv->dbg_root = debugfs_create_dir(dev_name(&pdev->dev), mlx5_debugfs_root);
927 if (!priv->dbg_root)
928 return -ENOMEM;
929
930 err = mlx5_pci_enable_device(dev);
931 if (err) {
932 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
933 goto err_dbg;
934 }
935
936 err = request_bar(pdev);
937 if (err) {
938 dev_err(&pdev->dev, "error requesting BARs, aborting\n");
939 goto err_disable;
940 }
941
942 pci_set_master(pdev);
943
944 err = set_dma_caps(pdev);
945 if (err) {
946 dev_err(&pdev->dev, "Failed setting DMA capabilities mask, aborting\n");
947 goto err_clr_master;
948 }
949
950 dev->iseg_base = pci_resource_start(dev->pdev, 0);
951 dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg));
952 if (!dev->iseg) {
953 err = -ENOMEM;
954 dev_err(&pdev->dev, "Failed mapping initialization segment, aborting\n");
955 goto err_clr_master;
956 }
957
958 return 0;
959
960 err_clr_master:
961 pci_clear_master(dev->pdev);
962 release_bar(dev->pdev);
963 err_disable:
964 mlx5_pci_disable_device(dev);
965
966 err_dbg:
967 debugfs_remove(priv->dbg_root);
968 return err;
969 }
970
971 static void mlx5_pci_close(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
972 {
973 iounmap(dev->iseg);
974 pci_clear_master(dev->pdev);
975 release_bar(dev->pdev);
976 mlx5_pci_disable_device(dev);
977 debugfs_remove(priv->dbg_root);
978 }
979
980 #define MLX5_IB_MOD "mlx5_ib"
981 static int mlx5_load_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
982 {
983 struct pci_dev *pdev = dev->pdev;
984 int err;
985
986 mutex_lock(&dev->intf_state_mutex);
987 if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
988 dev_warn(&dev->pdev->dev, "%s: interface is up, NOP\n",
989 __func__);
990 goto out;
991 }
992
993 dev_info(&pdev->dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev),
994 fw_rev_min(dev), fw_rev_sub(dev));
995
996 /* on load removing any previous indication of internal error, device is
997 * up
998 */
999 dev->state = MLX5_DEVICE_STATE_UP;
1000
1001 err = mlx5_cmd_init(dev);
1002 if (err) {
1003 dev_err(&pdev->dev, "Failed initializing command interface, aborting\n");
1004 goto out_err;
1005 }
1006
1007 err = wait_fw_init(dev, FW_INIT_TIMEOUT_MILI);
1008 if (err) {
1009 dev_err(&dev->pdev->dev, "Firmware over %d MS in initializing state, aborting\n",
1010 FW_INIT_TIMEOUT_MILI);
1011 goto out_err;
1012 }
1013
1014 mlx5_pagealloc_init(dev);
1015
1016 err = mlx5_core_enable_hca(dev, 0);
1017 if (err) {
1018 dev_err(&pdev->dev, "enable hca failed\n");
1019 goto err_pagealloc_cleanup;
1020 }
1021
1022 err = mlx5_core_set_issi(dev);
1023 if (err) {
1024 dev_err(&pdev->dev, "failed to set issi\n");
1025 goto err_disable_hca;
1026 }
1027
1028 err = mlx5_satisfy_startup_pages(dev, 1);
1029 if (err) {
1030 dev_err(&pdev->dev, "failed to allocate boot pages\n");
1031 goto err_disable_hca;
1032 }
1033
1034 err = set_hca_ctrl(dev);
1035 if (err) {
1036 dev_err(&pdev->dev, "set_hca_ctrl failed\n");
1037 goto reclaim_boot_pages;
1038 }
1039
1040 err = handle_hca_cap(dev);
1041 if (err) {
1042 dev_err(&pdev->dev, "handle_hca_cap failed\n");
1043 goto reclaim_boot_pages;
1044 }
1045
1046 err = handle_hca_cap_atomic(dev);
1047 if (err) {
1048 dev_err(&pdev->dev, "handle_hca_cap_atomic failed\n");
1049 goto reclaim_boot_pages;
1050 }
1051
1052 err = mlx5_satisfy_startup_pages(dev, 0);
1053 if (err) {
1054 dev_err(&pdev->dev, "failed to allocate init pages\n");
1055 goto reclaim_boot_pages;
1056 }
1057
1058 err = mlx5_pagealloc_start(dev);
1059 if (err) {
1060 dev_err(&pdev->dev, "mlx5_pagealloc_start failed\n");
1061 goto reclaim_boot_pages;
1062 }
1063
1064 err = mlx5_cmd_init_hca(dev);
1065 if (err) {
1066 dev_err(&pdev->dev, "init hca failed\n");
1067 goto err_pagealloc_stop;
1068 }
1069
1070 mlx5_start_health_poll(dev);
1071
1072 err = mlx5_query_hca_caps(dev);
1073 if (err) {
1074 dev_err(&pdev->dev, "query hca failed\n");
1075 goto err_stop_poll;
1076 }
1077
1078 err = mlx5_query_board_id(dev);
1079 if (err) {
1080 dev_err(&pdev->dev, "query board id failed\n");
1081 goto err_stop_poll;
1082 }
1083
1084 err = mlx5_enable_msix(dev);
1085 if (err) {
1086 dev_err(&pdev->dev, "enable msix failed\n");
1087 goto err_stop_poll;
1088 }
1089
1090 err = mlx5_eq_init(dev);
1091 if (err) {
1092 dev_err(&pdev->dev, "failed to initialize eq\n");
1093 goto disable_msix;
1094 }
1095
1096 err = mlx5_alloc_uuars(dev, &priv->uuari);
1097 if (err) {
1098 dev_err(&pdev->dev, "Failed allocating uar, aborting\n");
1099 goto err_eq_cleanup;
1100 }
1101
1102 err = mlx5_start_eqs(dev);
1103 if (err) {
1104 dev_err(&pdev->dev, "Failed to start pages and async EQs\n");
1105 goto err_free_uar;
1106 }
1107
1108 err = alloc_comp_eqs(dev);
1109 if (err) {
1110 dev_err(&pdev->dev, "Failed to alloc completion EQs\n");
1111 goto err_stop_eqs;
1112 }
1113
1114 err = mlx5_irq_set_affinity_hints(dev);
1115 if (err)
1116 dev_err(&pdev->dev, "Failed to alloc affinity hint cpumask\n");
1117
1118 MLX5_INIT_DOORBELL_LOCK(&priv->cq_uar_lock);
1119
1120 mlx5_init_cq_table(dev);
1121 mlx5_init_qp_table(dev);
1122 mlx5_init_srq_table(dev);
1123 mlx5_init_mkey_table(dev);
1124
1125 err = mlx5_init_fs(dev);
1126 if (err) {
1127 dev_err(&pdev->dev, "Failed to init flow steering\n");
1128 goto err_fs;
1129 }
1130 #ifdef CONFIG_MLX5_CORE_EN
1131 err = mlx5_eswitch_init(dev);
1132 if (err) {
1133 dev_err(&pdev->dev, "eswitch init failed %d\n", err);
1134 goto err_reg_dev;
1135 }
1136 #endif
1137
1138 err = mlx5_sriov_init(dev);
1139 if (err) {
1140 dev_err(&pdev->dev, "sriov init failed %d\n", err);
1141 goto err_sriov;
1142 }
1143
1144 err = mlx5_register_device(dev);
1145 if (err) {
1146 dev_err(&pdev->dev, "mlx5_register_device failed %d\n", err);
1147 goto err_reg_dev;
1148 }
1149
1150 err = request_module_nowait(MLX5_IB_MOD);
1151 if (err)
1152 pr_info("failed request module on %s\n", MLX5_IB_MOD);
1153
1154 clear_bit(MLX5_INTERFACE_STATE_DOWN, &dev->intf_state);
1155 set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1156 out:
1157 mutex_unlock(&dev->intf_state_mutex);
1158
1159 return 0;
1160
1161 err_sriov:
1162 if (mlx5_sriov_cleanup(dev))
1163 dev_err(&dev->pdev->dev, "sriov cleanup failed\n");
1164
1165 #ifdef CONFIG_MLX5_CORE_EN
1166 mlx5_eswitch_cleanup(dev->priv.eswitch);
1167 #endif
1168 err_reg_dev:
1169 mlx5_cleanup_fs(dev);
1170 err_fs:
1171 mlx5_cleanup_mkey_table(dev);
1172 mlx5_cleanup_srq_table(dev);
1173 mlx5_cleanup_qp_table(dev);
1174 mlx5_cleanup_cq_table(dev);
1175 mlx5_irq_clear_affinity_hints(dev);
1176 free_comp_eqs(dev);
1177
1178 err_stop_eqs:
1179 mlx5_stop_eqs(dev);
1180
1181 err_free_uar:
1182 mlx5_free_uuars(dev, &priv->uuari);
1183
1184 err_eq_cleanup:
1185 mlx5_eq_cleanup(dev);
1186
1187 disable_msix:
1188 mlx5_disable_msix(dev);
1189
1190 err_stop_poll:
1191 mlx5_stop_health_poll(dev);
1192 if (mlx5_cmd_teardown_hca(dev)) {
1193 dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n");
1194 goto out_err;
1195 }
1196
1197 err_pagealloc_stop:
1198 mlx5_pagealloc_stop(dev);
1199
1200 reclaim_boot_pages:
1201 mlx5_reclaim_startup_pages(dev);
1202
1203 err_disable_hca:
1204 mlx5_core_disable_hca(dev, 0);
1205
1206 err_pagealloc_cleanup:
1207 mlx5_pagealloc_cleanup(dev);
1208 mlx5_cmd_cleanup(dev);
1209
1210 out_err:
1211 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
1212 mutex_unlock(&dev->intf_state_mutex);
1213
1214 return err;
1215 }
1216
1217 static int mlx5_unload_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
1218 {
1219 int err = 0;
1220
1221 err = mlx5_sriov_cleanup(dev);
1222 if (err) {
1223 dev_warn(&dev->pdev->dev, "%s: sriov cleanup failed - abort\n",
1224 __func__);
1225 return err;
1226 }
1227
1228 mutex_lock(&dev->intf_state_mutex);
1229 if (test_bit(MLX5_INTERFACE_STATE_DOWN, &dev->intf_state)) {
1230 dev_warn(&dev->pdev->dev, "%s: interface is down, NOP\n",
1231 __func__);
1232 goto out;
1233 }
1234 mlx5_unregister_device(dev);
1235 #ifdef CONFIG_MLX5_CORE_EN
1236 mlx5_eswitch_cleanup(dev->priv.eswitch);
1237 #endif
1238
1239 mlx5_cleanup_fs(dev);
1240 mlx5_cleanup_mkey_table(dev);
1241 mlx5_cleanup_srq_table(dev);
1242 mlx5_cleanup_qp_table(dev);
1243 mlx5_cleanup_cq_table(dev);
1244 mlx5_irq_clear_affinity_hints(dev);
1245 free_comp_eqs(dev);
1246 mlx5_stop_eqs(dev);
1247 mlx5_free_uuars(dev, &priv->uuari);
1248 mlx5_eq_cleanup(dev);
1249 mlx5_disable_msix(dev);
1250 mlx5_stop_health_poll(dev);
1251 err = mlx5_cmd_teardown_hca(dev);
1252 if (err) {
1253 dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n");
1254 goto out;
1255 }
1256 mlx5_pagealloc_stop(dev);
1257 mlx5_reclaim_startup_pages(dev);
1258 mlx5_core_disable_hca(dev, 0);
1259 mlx5_pagealloc_cleanup(dev);
1260 mlx5_cmd_cleanup(dev);
1261
1262 out:
1263 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1264 set_bit(MLX5_INTERFACE_STATE_DOWN, &dev->intf_state);
1265 mutex_unlock(&dev->intf_state_mutex);
1266 return err;
1267 }
1268
1269 void mlx5_core_event(struct mlx5_core_dev *dev, enum mlx5_dev_event event,
1270 unsigned long param)
1271 {
1272 struct mlx5_priv *priv = &dev->priv;
1273 struct mlx5_device_context *dev_ctx;
1274 unsigned long flags;
1275
1276 spin_lock_irqsave(&priv->ctx_lock, flags);
1277
1278 list_for_each_entry(dev_ctx, &priv->ctx_list, list)
1279 if (dev_ctx->intf->event)
1280 dev_ctx->intf->event(dev, dev_ctx->context, event, param);
1281
1282 spin_unlock_irqrestore(&priv->ctx_lock, flags);
1283 }
1284
1285 struct mlx5_core_event_handler {
1286 void (*event)(struct mlx5_core_dev *dev,
1287 enum mlx5_dev_event event,
1288 void *data);
1289 };
1290
1291
1292 static int init_one(struct pci_dev *pdev,
1293 const struct pci_device_id *id)
1294 {
1295 struct mlx5_core_dev *dev;
1296 struct mlx5_priv *priv;
1297 int err;
1298
1299 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1300 if (!dev) {
1301 dev_err(&pdev->dev, "kzalloc failed\n");
1302 return -ENOMEM;
1303 }
1304 priv = &dev->priv;
1305 priv->pci_dev_data = id->driver_data;
1306
1307 pci_set_drvdata(pdev, dev);
1308
1309 if (prof_sel < 0 || prof_sel >= ARRAY_SIZE(profile)) {
1310 pr_warn("selected profile out of range, selecting default (%d)\n",
1311 MLX5_DEFAULT_PROF);
1312 prof_sel = MLX5_DEFAULT_PROF;
1313 }
1314 dev->profile = &profile[prof_sel];
1315 dev->pdev = pdev;
1316 dev->event = mlx5_core_event;
1317
1318 INIT_LIST_HEAD(&priv->ctx_list);
1319 spin_lock_init(&priv->ctx_lock);
1320 mutex_init(&dev->pci_status_mutex);
1321 mutex_init(&dev->intf_state_mutex);
1322 err = mlx5_pci_init(dev, priv);
1323 if (err) {
1324 dev_err(&pdev->dev, "mlx5_pci_init failed with error code %d\n", err);
1325 goto clean_dev;
1326 }
1327
1328 err = mlx5_health_init(dev);
1329 if (err) {
1330 dev_err(&pdev->dev, "mlx5_health_init failed with error code %d\n", err);
1331 goto close_pci;
1332 }
1333
1334 err = mlx5_load_one(dev, priv);
1335 if (err) {
1336 dev_err(&pdev->dev, "mlx5_load_one failed with error code %d\n", err);
1337 goto clean_health;
1338 }
1339
1340 return 0;
1341
1342 clean_health:
1343 mlx5_health_cleanup(dev);
1344 close_pci:
1345 mlx5_pci_close(dev, priv);
1346 clean_dev:
1347 pci_set_drvdata(pdev, NULL);
1348 kfree(dev);
1349
1350 return err;
1351 }
1352
1353 static void remove_one(struct pci_dev *pdev)
1354 {
1355 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1356 struct mlx5_priv *priv = &dev->priv;
1357
1358 if (mlx5_unload_one(dev, priv)) {
1359 dev_err(&dev->pdev->dev, "mlx5_unload_one failed\n");
1360 mlx5_health_cleanup(dev);
1361 return;
1362 }
1363 mlx5_health_cleanup(dev);
1364 mlx5_pci_close(dev, priv);
1365 pci_set_drvdata(pdev, NULL);
1366 kfree(dev);
1367 }
1368
1369 static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev,
1370 pci_channel_state_t state)
1371 {
1372 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1373 struct mlx5_priv *priv = &dev->priv;
1374
1375 dev_info(&pdev->dev, "%s was called\n", __func__);
1376 mlx5_enter_error_state(dev);
1377 mlx5_unload_one(dev, priv);
1378 mlx5_pci_disable_device(dev);
1379 return state == pci_channel_io_perm_failure ?
1380 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
1381 }
1382
1383 static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev)
1384 {
1385 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1386 int err = 0;
1387
1388 dev_info(&pdev->dev, "%s was called\n", __func__);
1389
1390 err = mlx5_pci_enable_device(dev);
1391 if (err) {
1392 dev_err(&pdev->dev, "%s: mlx5_pci_enable_device failed with error code: %d\n"
1393 , __func__, err);
1394 return PCI_ERS_RESULT_DISCONNECT;
1395 }
1396 pci_set_master(pdev);
1397 pci_set_power_state(pdev, PCI_D0);
1398 pci_restore_state(pdev);
1399
1400 return err ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED;
1401 }
1402
1403 void mlx5_disable_device(struct mlx5_core_dev *dev)
1404 {
1405 mlx5_pci_err_detected(dev->pdev, 0);
1406 }
1407
1408 /* wait for the device to show vital signs. For now we check
1409 * that we can read the device ID and that the health buffer
1410 * shows a non zero value which is different than 0xffffffff
1411 */
1412 static void wait_vital(struct pci_dev *pdev)
1413 {
1414 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1415 struct mlx5_core_health *health = &dev->priv.health;
1416 const int niter = 100;
1417 u32 count;
1418 u16 did;
1419 int i;
1420
1421 /* Wait for firmware to be ready after reset */
1422 msleep(1000);
1423 for (i = 0; i < niter; i++) {
1424 if (pci_read_config_word(pdev, 2, &did)) {
1425 dev_warn(&pdev->dev, "failed reading config word\n");
1426 break;
1427 }
1428 if (did == pdev->device) {
1429 dev_info(&pdev->dev, "device ID correctly read after %d iterations\n", i);
1430 break;
1431 }
1432 msleep(50);
1433 }
1434 if (i == niter)
1435 dev_warn(&pdev->dev, "%s-%d: could not read device ID\n", __func__, __LINE__);
1436
1437 for (i = 0; i < niter; i++) {
1438 count = ioread32be(health->health_counter);
1439 if (count && count != 0xffffffff) {
1440 dev_info(&pdev->dev, "Counter value 0x%x after %d iterations\n", count, i);
1441 break;
1442 }
1443 msleep(50);
1444 }
1445
1446 if (i == niter)
1447 dev_warn(&pdev->dev, "%s-%d: could not read device ID\n", __func__, __LINE__);
1448 }
1449
1450 static void mlx5_pci_resume(struct pci_dev *pdev)
1451 {
1452 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1453 struct mlx5_priv *priv = &dev->priv;
1454 int err;
1455
1456 dev_info(&pdev->dev, "%s was called\n", __func__);
1457
1458 pci_save_state(pdev);
1459 wait_vital(pdev);
1460
1461 err = mlx5_load_one(dev, priv);
1462 if (err)
1463 dev_err(&pdev->dev, "%s: mlx5_load_one failed with error code: %d\n"
1464 , __func__, err);
1465 else
1466 dev_info(&pdev->dev, "%s: device recovered\n", __func__);
1467 }
1468
1469 static const struct pci_error_handlers mlx5_err_handler = {
1470 .error_detected = mlx5_pci_err_detected,
1471 .slot_reset = mlx5_pci_slot_reset,
1472 .resume = mlx5_pci_resume
1473 };
1474
1475 static void shutdown(struct pci_dev *pdev)
1476 {
1477 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1478 struct mlx5_priv *priv = &dev->priv;
1479
1480 dev_info(&pdev->dev, "Shutdown was called\n");
1481 /* Notify mlx5 clients that the kernel is being shut down */
1482 set_bit(MLX5_INTERFACE_STATE_SHUTDOWN, &dev->intf_state);
1483 mlx5_unload_one(dev, priv);
1484 mlx5_pci_disable_device(dev);
1485 }
1486
1487 static const struct pci_device_id mlx5_core_pci_table[] = {
1488 { PCI_VDEVICE(MELLANOX, 0x1011) }, /* Connect-IB */
1489 { PCI_VDEVICE(MELLANOX, 0x1012), MLX5_PCI_DEV_IS_VF}, /* Connect-IB VF */
1490 { PCI_VDEVICE(MELLANOX, 0x1013) }, /* ConnectX-4 */
1491 { PCI_VDEVICE(MELLANOX, 0x1014), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4 VF */
1492 { PCI_VDEVICE(MELLANOX, 0x1015) }, /* ConnectX-4LX */
1493 { PCI_VDEVICE(MELLANOX, 0x1016), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4LX VF */
1494 { PCI_VDEVICE(MELLANOX, 0x1017) }, /* ConnectX-5 */
1495 { PCI_VDEVICE(MELLANOX, 0x1018), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 VF */
1496 { 0, }
1497 };
1498
1499 MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table);
1500
1501 static struct pci_driver mlx5_core_driver = {
1502 .name = DRIVER_NAME,
1503 .id_table = mlx5_core_pci_table,
1504 .probe = init_one,
1505 .remove = remove_one,
1506 .shutdown = shutdown,
1507 .err_handler = &mlx5_err_handler,
1508 .sriov_configure = mlx5_core_sriov_configure,
1509 };
1510
1511 static int __init init(void)
1512 {
1513 int err;
1514
1515 mlx5_register_debugfs();
1516
1517 err = pci_register_driver(&mlx5_core_driver);
1518 if (err)
1519 goto err_debug;
1520
1521 #ifdef CONFIG_MLX5_CORE_EN
1522 mlx5e_init();
1523 #endif
1524
1525 return 0;
1526
1527 err_debug:
1528 mlx5_unregister_debugfs();
1529 return err;
1530 }
1531
1532 static void __exit cleanup(void)
1533 {
1534 #ifdef CONFIG_MLX5_CORE_EN
1535 mlx5e_cleanup();
1536 #endif
1537 pci_unregister_driver(&mlx5_core_driver);
1538 mlx5_unregister_debugfs();
1539 }
1540
1541 module_init(init);
1542 module_exit(cleanup);
Linux kernel - Deliverables
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