drivers/net/ethernet/mellanox/mlx5/core/port.c

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/module.h>
  34 #include <linux/mlx5/driver.h>
  35 #include <linux/mlx5/port.h>
  36 #include <linux/mlx5/cmd.h>
  37 #include "mlx5_core.h"
  38
  39 int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in,
  40                          int size_in, void *data_out, int size_out,
  41                          u16 reg_num, int arg, int write)
  42 {
  43         struct mlx5_access_reg_mbox_in *in = NULL;
  44         struct mlx5_access_reg_mbox_out *out = NULL;
  45         int err = -ENOMEM;
  46
  47         in = mlx5_vzalloc(sizeof(*in) + size_in);
  48         if (!in)
  49                 return -ENOMEM;
  50
  51         out = mlx5_vzalloc(sizeof(*out) + size_out);
  52         if (!out)
  53                 goto ex1;
  54
  55         memcpy(in->data, data_in, size_in);
  56         in->hdr.opcode = cpu_to_be16(MLX5_CMD_OP_ACCESS_REG);
  57         in->hdr.opmod = cpu_to_be16(!write);
  58         in->arg = cpu_to_be32(arg);
  59         in->register_id = cpu_to_be16(reg_num);
  60         err = mlx5_cmd_exec(dev, in, sizeof(*in) + size_in, out,
  61                             sizeof(*out) + size_out);
  62         if (err)
  63                 goto ex2;
  64
  65         if (out->hdr.status)
  66                 err = mlx5_cmd_status_to_err(&out->hdr);
  67
  68         if (!err)
  69                 memcpy(data_out, out->data, size_out);
  70
  71 ex2:
  72         kvfree(out);
  73 ex1:
  74         kvfree(in);
  75         return err;
  76 }
  77 EXPORT_SYMBOL_GPL(mlx5_core_access_reg);
  78
  79
  80 struct mlx5_reg_pcap {
  81         u8                      rsvd0;
  82         u8                      port_num;
  83         u8                      rsvd1[2];
  84         __be32                  caps_127_96;
  85         __be32                  caps_95_64;
  86         __be32                  caps_63_32;
  87         __be32                  caps_31_0;
  88 };
  89
  90 int mlx5_set_port_caps(struct mlx5_core_dev *dev, u8 port_num, u32 caps)
  91 {
  92         struct mlx5_reg_pcap in;
  93         struct mlx5_reg_pcap out;
  94
  95         memset(&in, 0, sizeof(in));
  96         in.caps_127_96 = cpu_to_be32(caps);
  97         in.port_num = port_num;
  98
  99         return mlx5_core_access_reg(dev, &in, sizeof(in), &out,
 100                                     sizeof(out), MLX5_REG_PCAP, 0, 1);
 101 }
 102 EXPORT_SYMBOL_GPL(mlx5_set_port_caps);
 103
 104 int mlx5_query_port_ptys(struct mlx5_core_dev *dev, u32 *ptys,
 105                          int ptys_size, int proto_mask, u8 local_port)
 106 {
 107         u32 in[MLX5_ST_SZ_DW(ptys_reg)];
 108
 109         memset(in, 0, sizeof(in));
 110         MLX5_SET(ptys_reg, in, local_port, local_port);
 111         MLX5_SET(ptys_reg, in, proto_mask, proto_mask);
 112
 113         return mlx5_core_access_reg(dev, in, sizeof(in), ptys,
 114                                     ptys_size, MLX5_REG_PTYS, 0, 0);
 115 }
 116 EXPORT_SYMBOL_GPL(mlx5_query_port_ptys);
 117
 118 int mlx5_query_port_proto_cap(struct mlx5_core_dev *dev,
 119                               u32 *proto_cap, int proto_mask)
 120 {
 121         u32 out[MLX5_ST_SZ_DW(ptys_reg)];
 122         int err;
 123
 124         err = mlx5_query_port_ptys(dev, out, sizeof(out), proto_mask, 1);
 125         if (err)
 126                 return err;
 127
 128         if (proto_mask == MLX5_PTYS_EN)
 129                 *proto_cap = MLX5_GET(ptys_reg, out, eth_proto_capability);
 130         else
 131                 *proto_cap = MLX5_GET(ptys_reg, out, ib_proto_capability);
 132
 133         return 0;
 134 }
 135 EXPORT_SYMBOL_GPL(mlx5_query_port_proto_cap);
 136
 137 int mlx5_query_port_proto_admin(struct mlx5_core_dev *dev,
 138                                 u32 *proto_admin, int proto_mask)
 139 {
 140         u32 out[MLX5_ST_SZ_DW(ptys_reg)];
 141         int err;
 142
 143         err = mlx5_query_port_ptys(dev, out, sizeof(out), proto_mask, 1);
 144         if (err)
 145                 return err;
 146
 147         if (proto_mask == MLX5_PTYS_EN)
 148                 *proto_admin = MLX5_GET(ptys_reg, out, eth_proto_admin);
 149         else
 150                 *proto_admin = MLX5_GET(ptys_reg, out, ib_proto_admin);
 151
 152         return 0;
 153 }
 154 EXPORT_SYMBOL_GPL(mlx5_query_port_proto_admin);
 155
 156 int mlx5_query_port_link_width_oper(struct mlx5_core_dev *dev,
 157                                     u8 *link_width_oper, u8 local_port)
 158 {
 159         u32 out[MLX5_ST_SZ_DW(ptys_reg)];
 160         int err;
 161
 162         err = mlx5_query_port_ptys(dev, out, sizeof(out), MLX5_PTYS_IB, local_port);
 163         if (err)
 164                 return err;
 165
 166         *link_width_oper = MLX5_GET(ptys_reg, out, ib_link_width_oper);
 167
 168         return 0;
 169 }
 170 EXPORT_SYMBOL_GPL(mlx5_query_port_link_width_oper);
 171
 172 int mlx5_query_port_proto_oper(struct mlx5_core_dev *dev,
 173                                u8 *proto_oper, int proto_mask,
 174                                u8 local_port)
 175 {
 176         u32 out[MLX5_ST_SZ_DW(ptys_reg)];
 177         int err;
 178
 179         err = mlx5_query_port_ptys(dev, out, sizeof(out), proto_mask, local_port);
 180         if (err)
 181                 return err;
 182
 183         if (proto_mask == MLX5_PTYS_EN)
 184                 *proto_oper = MLX5_GET(ptys_reg, out, eth_proto_oper);
 185         else
 186                 *proto_oper = MLX5_GET(ptys_reg, out, ib_proto_oper);
 187
 188         return 0;
 189 }
 190 EXPORT_SYMBOL_GPL(mlx5_query_port_proto_oper);
 191
 192 int mlx5_set_port_proto(struct mlx5_core_dev *dev, u32 proto_admin,
 193                         int proto_mask)
 194 {
 195         u32 in[MLX5_ST_SZ_DW(ptys_reg)];
 196         u32 out[MLX5_ST_SZ_DW(ptys_reg)];
 197
 198         memset(in, 0, sizeof(in));
 199
 200         MLX5_SET(ptys_reg, in, local_port, 1);
 201         MLX5_SET(ptys_reg, in, proto_mask, proto_mask);
 202         if (proto_mask == MLX5_PTYS_EN)
 203                 MLX5_SET(ptys_reg, in, eth_proto_admin, proto_admin);
 204         else
 205                 MLX5_SET(ptys_reg, in, ib_proto_admin, proto_admin);
 206
 207         return mlx5_core_access_reg(dev, in, sizeof(in), out,
 208                                     sizeof(out), MLX5_REG_PTYS, 0, 1);
 209 }
 210 EXPORT_SYMBOL_GPL(mlx5_set_port_proto);
 211
 212 int mlx5_set_port_admin_status(struct mlx5_core_dev *dev,
 213                                enum mlx5_port_status status)
 214 {
 215         u32 in[MLX5_ST_SZ_DW(paos_reg)];
 216         u32 out[MLX5_ST_SZ_DW(paos_reg)];
 217
 218         memset(in, 0, sizeof(in));
 219
 220         MLX5_SET(paos_reg, in, local_port, 1);
 221         MLX5_SET(paos_reg, in, admin_status, status);
 222         MLX5_SET(paos_reg, in, ase, 1);
 223
 224         return mlx5_core_access_reg(dev, in, sizeof(in), out,
 225                                     sizeof(out), MLX5_REG_PAOS, 0, 1);
 226 }
 227 EXPORT_SYMBOL_GPL(mlx5_set_port_admin_status);
 228
 229 int mlx5_query_port_admin_status(struct mlx5_core_dev *dev,
 230                                  enum mlx5_port_status *status)
 231 {
 232         u32 in[MLX5_ST_SZ_DW(paos_reg)];
 233         u32 out[MLX5_ST_SZ_DW(paos_reg)];
 234         int err;
 235
 236         memset(in, 0, sizeof(in));
 237
 238         MLX5_SET(paos_reg, in, local_port, 1);
 239
 240         err = mlx5_core_access_reg(dev, in, sizeof(in), out,
 241                                    sizeof(out), MLX5_REG_PAOS, 0, 0);
 242         if (err)
 243                 return err;
 244
 245         *status = MLX5_GET(paos_reg, out, admin_status);
 246         return 0;
 247 }
 248 EXPORT_SYMBOL_GPL(mlx5_query_port_admin_status);
 249
 250 static void mlx5_query_port_mtu(struct mlx5_core_dev *dev, int *admin_mtu,
 251                                 int *max_mtu, int *oper_mtu, u8 port)
 252 {
 253         u32 in[MLX5_ST_SZ_DW(pmtu_reg)];
 254         u32 out[MLX5_ST_SZ_DW(pmtu_reg)];
 255
 256         memset(in, 0, sizeof(in));
 257
 258         MLX5_SET(pmtu_reg, in, local_port, port);
 259
 260         mlx5_core_access_reg(dev, in, sizeof(in), out,
 261                              sizeof(out), MLX5_REG_PMTU, 0, 0);
 262
 263         if (max_mtu)
 264                 *max_mtu  = MLX5_GET(pmtu_reg, out, max_mtu);
 265         if (oper_mtu)
 266                 *oper_mtu = MLX5_GET(pmtu_reg, out, oper_mtu);
 267         if (admin_mtu)
 268                 *admin_mtu = MLX5_GET(pmtu_reg, out, admin_mtu);
 269 }
 270
 271 int mlx5_set_port_mtu(struct mlx5_core_dev *dev, int mtu, u8 port)
 272 {
 273         u32 in[MLX5_ST_SZ_DW(pmtu_reg)];
 274         u32 out[MLX5_ST_SZ_DW(pmtu_reg)];
 275
 276         memset(in, 0, sizeof(in));
 277
 278         MLX5_SET(pmtu_reg, in, admin_mtu, mtu);
 279         MLX5_SET(pmtu_reg, in, local_port, port);
 280
 281         return mlx5_core_access_reg(dev, in, sizeof(in), out,
 282                                    sizeof(out), MLX5_REG_PMTU, 0, 1);
 283 }
 284 EXPORT_SYMBOL_GPL(mlx5_set_port_mtu);
 285
 286 void mlx5_query_port_max_mtu(struct mlx5_core_dev *dev, int *max_mtu,
 287                              u8 port)
 288 {
 289         mlx5_query_port_mtu(dev, NULL, max_mtu, NULL, port);
 290 }
 291 EXPORT_SYMBOL_GPL(mlx5_query_port_max_mtu);
 292
 293 void mlx5_query_port_oper_mtu(struct mlx5_core_dev *dev, int *oper_mtu,
 294                               u8 port)
 295 {
 296         mlx5_query_port_mtu(dev, NULL, NULL, oper_mtu, port);
 297 }
 298 EXPORT_SYMBOL_GPL(mlx5_query_port_oper_mtu);
 299
 300 static int mlx5_query_port_pvlc(struct mlx5_core_dev *dev, u32 *pvlc,
 301                                 int pvlc_size,  u8 local_port)
 302 {
 303         u32 in[MLX5_ST_SZ_DW(pvlc_reg)];
 304
 305         memset(in, 0, sizeof(in));
 306         MLX5_SET(pvlc_reg, in, local_port, local_port);
 307
 308         return mlx5_core_access_reg(dev, in, sizeof(in), pvlc,
 309                                     pvlc_size, MLX5_REG_PVLC, 0, 0);
 310 }
 311
 312 int mlx5_query_port_vl_hw_cap(struct mlx5_core_dev *dev,
 313                               u8 *vl_hw_cap, u8 local_port)
 314 {
 315         u32 out[MLX5_ST_SZ_DW(pvlc_reg)];
 316         int err;
 317
 318         err = mlx5_query_port_pvlc(dev, out, sizeof(out), local_port);
 319         if (err)
 320                 return err;
 321
 322         *vl_hw_cap = MLX5_GET(pvlc_reg, out, vl_hw_cap);
 323
 324         return 0;
 325 }
 326 EXPORT_SYMBOL_GPL(mlx5_query_port_vl_hw_cap);
 327
 328 int mlx5_set_port_pause(struct mlx5_core_dev *dev, u32 rx_pause, u32 tx_pause)
 329 {
 330         u32 in[MLX5_ST_SZ_DW(pfcc_reg)];
 331         u32 out[MLX5_ST_SZ_DW(pfcc_reg)];
 332
 333         memset(in, 0, sizeof(in));
 334         MLX5_SET(pfcc_reg, in, local_port, 1);
 335         MLX5_SET(pfcc_reg, in, pptx, tx_pause);
 336         MLX5_SET(pfcc_reg, in, pprx, rx_pause);
 337
 338         return mlx5_core_access_reg(dev, in, sizeof(in), out,
 339                                     sizeof(out), MLX5_REG_PFCC, 0, 1);
 340 }
 341 EXPORT_SYMBOL_GPL(mlx5_set_port_pause);
 342
 343 int mlx5_query_port_pause(struct mlx5_core_dev *dev,
 344                           u32 *rx_pause, u32 *tx_pause)
 345 {
 346         u32 in[MLX5_ST_SZ_DW(pfcc_reg)];
 347         u32 out[MLX5_ST_SZ_DW(pfcc_reg)];
 348         int err;
 349
 350         memset(in, 0, sizeof(in));
 351         MLX5_SET(pfcc_reg, in, local_port, 1);
 352
 353         err = mlx5_core_access_reg(dev, in, sizeof(in), out,
 354                                    sizeof(out), MLX5_REG_PFCC, 0, 0);
 355         if (err)
 356                 return err;
 357
 358         if (rx_pause)
 359                 *rx_pause = MLX5_GET(pfcc_reg, out, pprx);
 360
 361         if (tx_pause)
 362                 *tx_pause = MLX5_GET(pfcc_reg, out, pptx);
 363
 364         return 0;
 365 }
 366 EXPORT_SYMBOL_GPL(mlx5_query_port_pause);
 367
 368 int mlx5_set_port_pfc(struct mlx5_core_dev *dev, u8 pfc_en_tx, u8 pfc_en_rx)
 369 {
 370         u32 in[MLX5_ST_SZ_DW(pfcc_reg)];
 371         u32 out[MLX5_ST_SZ_DW(pfcc_reg)];
 372
 373         memset(in, 0, sizeof(in));
 374         MLX5_SET(pfcc_reg, in, local_port, 1);
 375         MLX5_SET(pfcc_reg, in, pfctx, pfc_en_tx);
 376         MLX5_SET(pfcc_reg, in, pfcrx, pfc_en_rx);
 377         MLX5_SET_TO_ONES(pfcc_reg, in, prio_mask_tx);
 378         MLX5_SET_TO_ONES(pfcc_reg, in, prio_mask_rx);
 379
 380         return mlx5_core_access_reg(dev, in, sizeof(in), out,
 381                                     sizeof(out), MLX5_REG_PFCC, 0, 1);
 382 }
 383 EXPORT_SYMBOL_GPL(mlx5_set_port_pfc);
 384
 385 int mlx5_query_port_pfc(struct mlx5_core_dev *dev, u8 *pfc_en_tx, u8 *pfc_en_rx)
 386 {
 387         u32 in[MLX5_ST_SZ_DW(pfcc_reg)];
 388         u32 out[MLX5_ST_SZ_DW(pfcc_reg)];
 389         int err;
 390
 391         memset(in, 0, sizeof(in));
 392         MLX5_SET(pfcc_reg, in, local_port, 1);
 393
 394         err = mlx5_core_access_reg(dev, in, sizeof(in), out,
 395                                    sizeof(out), MLX5_REG_PFCC, 0, 0);
 396         if (err)
 397                 return err;
 398
 399         if (pfc_en_tx)
 400                 *pfc_en_tx = MLX5_GET(pfcc_reg, out, pfctx);
 401
 402         if (pfc_en_rx)
 403                 *pfc_en_rx = MLX5_GET(pfcc_reg, out, pfcrx);
 404
 405         return 0;
 406 }
 407 EXPORT_SYMBOL_GPL(mlx5_query_port_pfc);
 408
 409 int mlx5_max_tc(struct mlx5_core_dev *mdev)
 410 {
 411         u8 num_tc = MLX5_CAP_GEN(mdev, max_tc) ? : 8;
 412
 413         return num_tc - 1;
 414 }
 415
 416 int mlx5_set_port_prio_tc(struct mlx5_core_dev *mdev, u8 *prio_tc)
 417 {
 418         u32 in[MLX5_ST_SZ_DW(qtct_reg)];
 419         u32 out[MLX5_ST_SZ_DW(qtct_reg)];
 420         int err;
 421         int i;
 422
 423         memset(in, 0, sizeof(in));
 424         for (i = 0; i < 8; i++) {
 425                 if (prio_tc[i] > mlx5_max_tc(mdev))
 426                         return -EINVAL;
 427
 428                 MLX5_SET(qtct_reg, in, prio, i);
 429                 MLX5_SET(qtct_reg, in, tclass, prio_tc[i]);
 430
 431                 err = mlx5_core_access_reg(mdev, in, sizeof(in), out,
 432                                            sizeof(out), MLX5_REG_QTCT, 0, 1);
 433                 if (err)
 434                         return err;
 435         }
 436
 437         return 0;
 438 }
 439 EXPORT_SYMBOL_GPL(mlx5_set_port_prio_tc);
 440
 441 static int mlx5_set_port_qetcr_reg(struct mlx5_core_dev *mdev, u32 *in,
 442                                    int inlen)
 443 {
 444         u32 out[MLX5_ST_SZ_DW(qtct_reg)];
 445
 446         if (!MLX5_CAP_GEN(mdev, ets))
 447                 return -ENOTSUPP;
 448
 449         return mlx5_core_access_reg(mdev, in, inlen, out, sizeof(out),
 450                                     MLX5_REG_QETCR, 0, 1);
 451 }
 452
 453 int mlx5_set_port_tc_group(struct mlx5_core_dev *mdev, u8 *tc_group)
 454 {
 455         u32 in[MLX5_ST_SZ_DW(qetc_reg)];
 456         int i;
 457
 458         memset(in, 0, sizeof(in));
 459
 460         for (i = 0; i <= mlx5_max_tc(mdev); i++) {
 461                 MLX5_SET(qetc_reg, in, tc_configuration[i].g, 1);
 462                 MLX5_SET(qetc_reg, in, tc_configuration[i].group, tc_group[i]);
 463         }
 464
 465         return mlx5_set_port_qetcr_reg(mdev, in, sizeof(in));
 466 }
 467 EXPORT_SYMBOL_GPL(mlx5_set_port_tc_group);
 468
 469 int mlx5_set_port_tc_bw_alloc(struct mlx5_core_dev *mdev, u8 *tc_bw)
 470 {
 471         u32 in[MLX5_ST_SZ_DW(qetc_reg)];
 472         int i;
 473
 474         memset(in, 0, sizeof(in));
 475
 476         for (i = 0; i <= mlx5_max_tc(mdev); i++) {
 477                 MLX5_SET(qetc_reg, in, tc_configuration[i].b, 1);
 478                 MLX5_SET(qetc_reg, in, tc_configuration[i].bw_allocation, tc_bw[i]);
 479         }
 480
 481         return mlx5_set_port_qetcr_reg(mdev, in, sizeof(in));
 482 }
 483 EXPORT_SYMBOL_GPL(mlx5_set_port_tc_bw_alloc);