drivers/net/ethernet/mellanox/mlx5/core/port.c

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/module.h>
  34 #include <linux/mlx5/driver.h>
  35 #include <linux/mlx5/cmd.h>
  36 #include "mlx5_core.h"
  37
  38 int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in,
  39                          int size_in, void *data_out, int size_out,
  40                          u16 reg_num, int arg, int write)
  41 {
  42         struct mlx5_access_reg_mbox_in *in = NULL;
  43         struct mlx5_access_reg_mbox_out *out = NULL;
  44         int err = -ENOMEM;
  45
  46         in = mlx5_vzalloc(sizeof(*in) + size_in);
  47         if (!in)
  48                 return -ENOMEM;
  49
  50         out = mlx5_vzalloc(sizeof(*out) + size_out);
  51         if (!out)
  52                 goto ex1;
  53
  54         memcpy(in->data, data_in, size_in);
  55         in->hdr.opcode = cpu_to_be16(MLX5_CMD_OP_ACCESS_REG);
  56         in->hdr.opmod = cpu_to_be16(!write);
  57         in->arg = cpu_to_be32(arg);
  58         in->register_id = cpu_to_be16(reg_num);
  59         err = mlx5_cmd_exec(dev, in, sizeof(*in) + size_in, out,
  60                             sizeof(*out) + size_out);
  61         if (err)
  62                 goto ex2;
  63
  64         if (out->hdr.status)
  65                 err = mlx5_cmd_status_to_err(&out->hdr);
  66
  67         if (!err)
  68                 memcpy(data_out, out->data, size_out);
  69
  70 ex2:
  71         kvfree(out);
  72 ex1:
  73         kvfree(in);
  74         return err;
  75 }
  76 EXPORT_SYMBOL_GPL(mlx5_core_access_reg);
  77
  78
  79 struct mlx5_reg_pcap {
  80         u8                      rsvd0;
  81         u8                      port_num;
  82         u8                      rsvd1[2];
  83         __be32                  caps_127_96;
  84         __be32                  caps_95_64;
  85         __be32                  caps_63_32;
  86         __be32                  caps_31_0;
  87 };
  88
  89 int mlx5_set_port_caps(struct mlx5_core_dev *dev, u8 port_num, u32 caps)
  90 {
  91         struct mlx5_reg_pcap in;
  92         struct mlx5_reg_pcap out;
  93         int err;
  94
  95         memset(&in, 0, sizeof(in));
  96         in.caps_127_96 = cpu_to_be32(caps);
  97         in.port_num = port_num;
  98
  99         err = mlx5_core_access_reg(dev, &in, sizeof(in), &out,
 100                                    sizeof(out), MLX5_REG_PCAP, 0, 1);
 101
 102         return err;
 103 }
 104 EXPORT_SYMBOL_GPL(mlx5_set_port_caps);
 105
 106 int mlx5_query_port_ptys(struct mlx5_core_dev *dev, u32 *ptys,
 107                          int ptys_size, int proto_mask)
 108 {
 109         u32 in[MLX5_ST_SZ_DW(ptys_reg)];
 110         int err;
 111
 112         memset(in, 0, sizeof(in));
 113         MLX5_SET(ptys_reg, in, local_port, 1);
 114         MLX5_SET(ptys_reg, in, proto_mask, proto_mask);
 115
 116         err = mlx5_core_access_reg(dev, in, sizeof(in), ptys,
 117                                    ptys_size, MLX5_REG_PTYS, 0, 0);
 118
 119         return err;
 120 }
 121 EXPORT_SYMBOL_GPL(mlx5_query_port_ptys);
 122
 123 int mlx5_query_port_proto_cap(struct mlx5_core_dev *dev,
 124                               u32 *proto_cap, int proto_mask)
 125 {
 126         u32 out[MLX5_ST_SZ_DW(ptys_reg)];
 127         int err;
 128
 129         err = mlx5_query_port_ptys(dev, out, sizeof(out), proto_mask);
 130         if (err)
 131                 return err;
 132
 133         if (proto_mask == MLX5_PTYS_EN)
 134                 *proto_cap = MLX5_GET(ptys_reg, out, eth_proto_capability);
 135         else
 136                 *proto_cap = MLX5_GET(ptys_reg, out, ib_proto_capability);
 137
 138         return 0;
 139 }
 140 EXPORT_SYMBOL_GPL(mlx5_query_port_proto_cap);
 141
 142 int mlx5_query_port_proto_admin(struct mlx5_core_dev *dev,
 143                                 u32 *proto_admin, int proto_mask)
 144 {
 145         u32 out[MLX5_ST_SZ_DW(ptys_reg)];
 146         int err;
 147
 148         err = mlx5_query_port_ptys(dev, out, sizeof(out), proto_mask);
 149         if (err)
 150                 return err;
 151
 152         if (proto_mask == MLX5_PTYS_EN)
 153                 *proto_admin = MLX5_GET(ptys_reg, out, eth_proto_admin);
 154         else
 155                 *proto_admin = MLX5_GET(ptys_reg, out, ib_proto_admin);
 156
 157         return 0;
 158 }
 159 EXPORT_SYMBOL_GPL(mlx5_query_port_proto_admin);
 160
 161 int mlx5_set_port_proto(struct mlx5_core_dev *dev, u32 proto_admin,
 162                         int proto_mask)
 163 {
 164         u32 in[MLX5_ST_SZ_DW(ptys_reg)];
 165         u32 out[MLX5_ST_SZ_DW(ptys_reg)];
 166         int err;
 167
 168         memset(in, 0, sizeof(in));
 169
 170         MLX5_SET(ptys_reg, in, local_port, 1);
 171         MLX5_SET(ptys_reg, in, proto_mask, proto_mask);
 172         if (proto_mask == MLX5_PTYS_EN)
 173                 MLX5_SET(ptys_reg, in, eth_proto_admin, proto_admin);
 174         else
 175                 MLX5_SET(ptys_reg, in, ib_proto_admin, proto_admin);
 176
 177         err = mlx5_core_access_reg(dev, in, sizeof(in), out,
 178                                    sizeof(out), MLX5_REG_PTYS, 0, 1);
 179         return err;
 180 }
 181 EXPORT_SYMBOL_GPL(mlx5_set_port_proto);
 182
 183 int mlx5_set_port_status(struct mlx5_core_dev *dev,
 184                          enum mlx5_port_status status)
 185 {
 186         u32 in[MLX5_ST_SZ_DW(paos_reg)];
 187         u32 out[MLX5_ST_SZ_DW(paos_reg)];
 188
 189         memset(in, 0, sizeof(in));
 190
 191         MLX5_SET(paos_reg, in, admin_status, status);
 192         MLX5_SET(paos_reg, in, ase, 1);
 193
 194         return mlx5_core_access_reg(dev, in, sizeof(in), out,
 195                                     sizeof(out), MLX5_REG_PAOS, 0, 1);
 196 }
 197
 198 int mlx5_query_port_status(struct mlx5_core_dev *dev, u8 *status)
 199 {
 200         u32 in[MLX5_ST_SZ_DW(paos_reg)];
 201         u32 out[MLX5_ST_SZ_DW(paos_reg)];
 202         int err;
 203
 204         memset(in, 0, sizeof(in));
 205
 206         err = mlx5_core_access_reg(dev, in, sizeof(in), out,
 207                                    sizeof(out), MLX5_REG_PAOS, 0, 0);
 208         if (err)
 209                 return err;
 210
 211         *status = MLX5_GET(paos_reg, out, oper_status);
 212         return err;
 213 }
 214
 215 static int mlx5_query_port_mtu(struct mlx5_core_dev *dev,
 216                                int *admin_mtu, int *max_mtu, int *oper_mtu)
 217 {
 218         u32 in[MLX5_ST_SZ_DW(pmtu_reg)];
 219         u32 out[MLX5_ST_SZ_DW(pmtu_reg)];
 220         int err;
 221
 222         memset(in, 0, sizeof(in));
 223
 224         MLX5_SET(pmtu_reg, in, local_port, 1);
 225
 226         err = mlx5_core_access_reg(dev, in, sizeof(in), out,
 227                                    sizeof(out), MLX5_REG_PMTU, 0, 0);
 228         if (err)
 229                 return err;
 230
 231         if (max_mtu)
 232                 *max_mtu  = MLX5_GET(pmtu_reg, out, max_mtu);
 233         if (oper_mtu)
 234                 *oper_mtu = MLX5_GET(pmtu_reg, out, oper_mtu);
 235         if (admin_mtu)
 236                 *admin_mtu = MLX5_GET(pmtu_reg, out, admin_mtu);
 237
 238         return 0;
 239 }
 240
 241 int mlx5_set_port_mtu(struct mlx5_core_dev *dev, int mtu)
 242 {
 243         u32 in[MLX5_ST_SZ_DW(pmtu_reg)];
 244         u32 out[MLX5_ST_SZ_DW(pmtu_reg)];
 245
 246         memset(in, 0, sizeof(in));
 247
 248         MLX5_SET(pmtu_reg, in, admin_mtu, mtu);
 249         MLX5_SET(pmtu_reg, in, local_port, 1);
 250
 251         return mlx5_core_access_reg(dev, in, sizeof(in), out, sizeof(out),
 252                                     MLX5_REG_PMTU, 0, 1);
 253 }
 254 EXPORT_SYMBOL_GPL(mlx5_set_port_mtu);
 255
 256 int mlx5_query_port_max_mtu(struct mlx5_core_dev *dev, int *max_mtu)
 257 {
 258         return mlx5_query_port_mtu(dev, NULL, max_mtu, NULL);
 259 }
 260 EXPORT_SYMBOL_GPL(mlx5_query_port_max_mtu);
 261
 262 int mlx5_query_port_oper_mtu(struct mlx5_core_dev *dev, int *oper_mtu)
 263 {
 264         return mlx5_query_port_mtu(dev, NULL, NULL, oper_mtu);
 265 }
 266 EXPORT_SYMBOL_GPL(mlx5_query_port_oper_mtu);