drivers/net/ethernet/mellanox/mlx5/core/port.c

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/module.h>
  34 #include <linux/mlx5/driver.h>
  35 #include <linux/mlx5/cmd.h>
  36 #include "mlx5_core.h"
  37
  38 int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in,
  39                          int size_in, void *data_out, int size_out,
  40                          u16 reg_num, int arg, int write)
  41 {
  42         struct mlx5_access_reg_mbox_in *in = NULL;
  43         struct mlx5_access_reg_mbox_out *out = NULL;
  44         int err = -ENOMEM;
  45
  46         in = mlx5_vzalloc(sizeof(*in) + size_in);
  47         if (!in)
  48                 return -ENOMEM;
  49
  50         out = mlx5_vzalloc(sizeof(*out) + size_out);
  51         if (!out)
  52                 goto ex1;
  53
  54         memcpy(in->data, data_in, size_in);
  55         in->hdr.opcode = cpu_to_be16(MLX5_CMD_OP_ACCESS_REG);
  56         in->hdr.opmod = cpu_to_be16(!write);
  57         in->arg = cpu_to_be32(arg);
  58         in->register_id = cpu_to_be16(reg_num);
  59         err = mlx5_cmd_exec(dev, in, sizeof(*in) + size_in, out,
  60                             sizeof(*out) + size_out);
  61         if (err)
  62                 goto ex2;
  63
  64         if (out->hdr.status)
  65                 err = mlx5_cmd_status_to_err(&out->hdr);
  66
  67         if (!err)
  68                 memcpy(data_out, out->data, size_out);
  69
  70 ex2:
  71         kvfree(out);
  72 ex1:
  73         kvfree(in);
  74         return err;
  75 }
  76 EXPORT_SYMBOL_GPL(mlx5_core_access_reg);
  77
  78
  79 struct mlx5_reg_pcap {
  80         u8                      rsvd0;
  81         u8                      port_num;
  82         u8                      rsvd1[2];
  83         __be32                  caps_127_96;
  84         __be32                  caps_95_64;
  85         __be32                  caps_63_32;
  86         __be32                  caps_31_0;
  87 };
  88
  89 int mlx5_set_port_caps(struct mlx5_core_dev *dev, u8 port_num, u32 caps)
  90 {
  91         struct mlx5_reg_pcap in;
  92         struct mlx5_reg_pcap out;
  93
  94         memset(&in, 0, sizeof(in));
  95         in.caps_127_96 = cpu_to_be32(caps);
  96         in.port_num = port_num;
  97
  98         return mlx5_core_access_reg(dev, &in, sizeof(in), &out,
  99                                     sizeof(out), MLX5_REG_PCAP, 0, 1);
 100 }
 101 EXPORT_SYMBOL_GPL(mlx5_set_port_caps);
 102
 103 int mlx5_query_port_ptys(struct mlx5_core_dev *dev, u32 *ptys,
 104                          int ptys_size, int proto_mask, u8 local_port)
 105 {
 106         u32 in[MLX5_ST_SZ_DW(ptys_reg)];
 107
 108         memset(in, 0, sizeof(in));
 109         MLX5_SET(ptys_reg, in, local_port, local_port);
 110         MLX5_SET(ptys_reg, in, proto_mask, proto_mask);
 111
 112         return mlx5_core_access_reg(dev, in, sizeof(in), ptys,
 113                                     ptys_size, MLX5_REG_PTYS, 0, 0);
 114 }
 115 EXPORT_SYMBOL_GPL(mlx5_query_port_ptys);
 116
 117 int mlx5_query_port_proto_cap(struct mlx5_core_dev *dev,
 118                               u32 *proto_cap, int proto_mask)
 119 {
 120         u32 out[MLX5_ST_SZ_DW(ptys_reg)];
 121         int err;
 122
 123         err = mlx5_query_port_ptys(dev, out, sizeof(out), proto_mask, 1);
 124         if (err)
 125                 return err;
 126
 127         if (proto_mask == MLX5_PTYS_EN)
 128                 *proto_cap = MLX5_GET(ptys_reg, out, eth_proto_capability);
 129         else
 130                 *proto_cap = MLX5_GET(ptys_reg, out, ib_proto_capability);
 131
 132         return 0;
 133 }
 134 EXPORT_SYMBOL_GPL(mlx5_query_port_proto_cap);
 135
 136 int mlx5_query_port_proto_admin(struct mlx5_core_dev *dev,
 137                                 u32 *proto_admin, int proto_mask)
 138 {
 139         u32 out[MLX5_ST_SZ_DW(ptys_reg)];
 140         int err;
 141
 142         err = mlx5_query_port_ptys(dev, out, sizeof(out), proto_mask, 1);
 143         if (err)
 144                 return err;
 145
 146         if (proto_mask == MLX5_PTYS_EN)
 147                 *proto_admin = MLX5_GET(ptys_reg, out, eth_proto_admin);
 148         else
 149                 *proto_admin = MLX5_GET(ptys_reg, out, ib_proto_admin);
 150
 151         return 0;
 152 }
 153 EXPORT_SYMBOL_GPL(mlx5_query_port_proto_admin);
 154
 155 int mlx5_query_port_link_width_oper(struct mlx5_core_dev *dev,
 156                                     u8 *link_width_oper, u8 local_port)
 157 {
 158         u32 out[MLX5_ST_SZ_DW(ptys_reg)];
 159         int err;
 160
 161         err = mlx5_query_port_ptys(dev, out, sizeof(out), MLX5_PTYS_IB, local_port);
 162         if (err)
 163                 return err;
 164
 165         *link_width_oper = MLX5_GET(ptys_reg, out, ib_link_width_oper);
 166
 167         return 0;
 168 }
 169 EXPORT_SYMBOL_GPL(mlx5_query_port_link_width_oper);
 170
 171 int mlx5_query_port_proto_oper(struct mlx5_core_dev *dev,
 172                                u8 *proto_oper, int proto_mask,
 173                                u8 local_port)
 174 {
 175         u32 out[MLX5_ST_SZ_DW(ptys_reg)];
 176         int err;
 177
 178         err = mlx5_query_port_ptys(dev, out, sizeof(out), proto_mask, local_port);
 179         if (err)
 180                 return err;
 181
 182         if (proto_mask == MLX5_PTYS_EN)
 183                 *proto_oper = MLX5_GET(ptys_reg, out, eth_proto_oper);
 184         else
 185                 *proto_oper = MLX5_GET(ptys_reg, out, ib_proto_oper);
 186
 187         return 0;
 188 }
 189 EXPORT_SYMBOL_GPL(mlx5_query_port_proto_oper);
 190
 191 int mlx5_set_port_proto(struct mlx5_core_dev *dev, u32 proto_admin,
 192                         int proto_mask)
 193 {
 194         u32 in[MLX5_ST_SZ_DW(ptys_reg)];
 195         u32 out[MLX5_ST_SZ_DW(ptys_reg)];
 196
 197         memset(in, 0, sizeof(in));
 198
 199         MLX5_SET(ptys_reg, in, local_port, 1);
 200         MLX5_SET(ptys_reg, in, proto_mask, proto_mask);
 201         if (proto_mask == MLX5_PTYS_EN)
 202                 MLX5_SET(ptys_reg, in, eth_proto_admin, proto_admin);
 203         else
 204                 MLX5_SET(ptys_reg, in, ib_proto_admin, proto_admin);
 205
 206         return mlx5_core_access_reg(dev, in, sizeof(in), out,
 207                                     sizeof(out), MLX5_REG_PTYS, 0, 1);
 208 }
 209 EXPORT_SYMBOL_GPL(mlx5_set_port_proto);
 210
 211 int mlx5_set_port_admin_status(struct mlx5_core_dev *dev,
 212                                enum mlx5_port_status status)
 213 {
 214         u32 in[MLX5_ST_SZ_DW(paos_reg)];
 215         u32 out[MLX5_ST_SZ_DW(paos_reg)];
 216
 217         memset(in, 0, sizeof(in));
 218
 219         MLX5_SET(paos_reg, in, local_port, 1);
 220         MLX5_SET(paos_reg, in, admin_status, status);
 221         MLX5_SET(paos_reg, in, ase, 1);
 222
 223         return mlx5_core_access_reg(dev, in, sizeof(in), out,
 224                                     sizeof(out), MLX5_REG_PAOS, 0, 1);
 225 }
 226 EXPORT_SYMBOL_GPL(mlx5_set_port_admin_status);
 227
 228 int mlx5_query_port_admin_status(struct mlx5_core_dev *dev,
 229                                  enum mlx5_port_status *status)
 230 {
 231         u32 in[MLX5_ST_SZ_DW(paos_reg)];
 232         u32 out[MLX5_ST_SZ_DW(paos_reg)];
 233         int err;
 234
 235         memset(in, 0, sizeof(in));
 236
 237         MLX5_SET(paos_reg, in, local_port, 1);
 238
 239         err = mlx5_core_access_reg(dev, in, sizeof(in), out,
 240                                    sizeof(out), MLX5_REG_PAOS, 0, 0);
 241         if (err)
 242                 return err;
 243
 244         *status = MLX5_GET(paos_reg, out, admin_status);
 245         return 0;
 246 }
 247 EXPORT_SYMBOL_GPL(mlx5_query_port_admin_status);
 248
 249 static void mlx5_query_port_mtu(struct mlx5_core_dev *dev, int *admin_mtu,
 250                                 int *max_mtu, int *oper_mtu, u8 port)
 251 {
 252         u32 in[MLX5_ST_SZ_DW(pmtu_reg)];
 253         u32 out[MLX5_ST_SZ_DW(pmtu_reg)];
 254
 255         memset(in, 0, sizeof(in));
 256
 257         MLX5_SET(pmtu_reg, in, local_port, port);
 258
 259         mlx5_core_access_reg(dev, in, sizeof(in), out,
 260                              sizeof(out), MLX5_REG_PMTU, 0, 0);
 261
 262         if (max_mtu)
 263                 *max_mtu  = MLX5_GET(pmtu_reg, out, max_mtu);
 264         if (oper_mtu)
 265                 *oper_mtu = MLX5_GET(pmtu_reg, out, oper_mtu);
 266         if (admin_mtu)
 267                 *admin_mtu = MLX5_GET(pmtu_reg, out, admin_mtu);
 268 }
 269
 270 int mlx5_set_port_mtu(struct mlx5_core_dev *dev, int mtu, u8 port)
 271 {
 272         u32 in[MLX5_ST_SZ_DW(pmtu_reg)];
 273         u32 out[MLX5_ST_SZ_DW(pmtu_reg)];
 274
 275         memset(in, 0, sizeof(in));
 276
 277         MLX5_SET(pmtu_reg, in, admin_mtu, mtu);
 278         MLX5_SET(pmtu_reg, in, local_port, port);
 279
 280         return mlx5_core_access_reg(dev, in, sizeof(in), out,
 281                                    sizeof(out), MLX5_REG_PMTU, 0, 1);
 282 }
 283 EXPORT_SYMBOL_GPL(mlx5_set_port_mtu);
 284
 285 void mlx5_query_port_max_mtu(struct mlx5_core_dev *dev, int *max_mtu,
 286                              u8 port)
 287 {
 288         mlx5_query_port_mtu(dev, NULL, max_mtu, NULL, port);
 289 }
 290 EXPORT_SYMBOL_GPL(mlx5_query_port_max_mtu);
 291
 292 void mlx5_query_port_oper_mtu(struct mlx5_core_dev *dev, int *oper_mtu,
 293                               u8 port)
 294 {
 295         mlx5_query_port_mtu(dev, NULL, NULL, oper_mtu, port);
 296 }
 297 EXPORT_SYMBOL_GPL(mlx5_query_port_oper_mtu);
 298
 299 static int mlx5_query_port_pvlc(struct mlx5_core_dev *dev, u32 *pvlc,
 300                                 int pvlc_size,  u8 local_port)
 301 {
 302         u32 in[MLX5_ST_SZ_DW(pvlc_reg)];
 303
 304         memset(in, 0, sizeof(in));
 305         MLX5_SET(pvlc_reg, in, local_port, local_port);
 306
 307         return mlx5_core_access_reg(dev, in, sizeof(in), pvlc,
 308                                     pvlc_size, MLX5_REG_PVLC, 0, 0);
 309 }
 310
 311 int mlx5_query_port_vl_hw_cap(struct mlx5_core_dev *dev,
 312                               u8 *vl_hw_cap, u8 local_port)
 313 {
 314         u32 out[MLX5_ST_SZ_DW(pvlc_reg)];
 315         int err;
 316
 317         err = mlx5_query_port_pvlc(dev, out, sizeof(out), local_port);
 318         if (err)
 319                 return err;
 320
 321         *vl_hw_cap = MLX5_GET(pvlc_reg, out, vl_hw_cap);
 322
 323         return 0;
 324 }
 325 EXPORT_SYMBOL_GPL(mlx5_query_port_vl_hw_cap);
 326
 327 int mlx5_set_port_pause(struct mlx5_core_dev *dev, u32 rx_pause, u32 tx_pause)
 328 {
 329         u32 in[MLX5_ST_SZ_DW(pfcc_reg)];
 330         u32 out[MLX5_ST_SZ_DW(pfcc_reg)];
 331
 332         memset(in, 0, sizeof(in));
 333         MLX5_SET(pfcc_reg, in, local_port, 1);
 334         MLX5_SET(pfcc_reg, in, pptx, tx_pause);
 335         MLX5_SET(pfcc_reg, in, pprx, rx_pause);
 336
 337         return mlx5_core_access_reg(dev, in, sizeof(in), out,
 338                                     sizeof(out), MLX5_REG_PFCC, 0, 1);
 339 }
 340 EXPORT_SYMBOL_GPL(mlx5_set_port_pause);
 341
 342 int mlx5_query_port_pause(struct mlx5_core_dev *dev,
 343                           u32 *rx_pause, u32 *tx_pause)
 344 {
 345         u32 in[MLX5_ST_SZ_DW(pfcc_reg)];
 346         u32 out[MLX5_ST_SZ_DW(pfcc_reg)];
 347         int err;
 348
 349         memset(in, 0, sizeof(in));
 350         MLX5_SET(pfcc_reg, in, local_port, 1);
 351
 352         err = mlx5_core_access_reg(dev, in, sizeof(in), out,
 353                                    sizeof(out), MLX5_REG_PFCC, 0, 0);
 354         if (err)
 355                 return err;
 356
 357         if (rx_pause)
 358                 *rx_pause = MLX5_GET(pfcc_reg, out, pprx);
 359
 360         if (tx_pause)
 361                 *tx_pause = MLX5_GET(pfcc_reg, out, pptx);
 362
 363         return 0;
 364 }
 365 EXPORT_SYMBOL_GPL(mlx5_query_port_pause);